1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVIF_CL0002_H__
3 #define __NVIF_CL0002_H__
4
5 struct nv_dma_v0 {
6 __u8 version;
7 #define NV_DMA_V0_TARGET_VM 0x00
8 #define NV_DMA_V0_TARGET_VRAM 0x01
9 #define NV_DMA_V0_TARGET_PCI 0x02
10 #define NV_DMA_V0_TARGET_PCI_US 0x03
11 #define NV_DMA_V0_TARGET_AGP 0x04
12 __u8 target;
13 #define NV_DMA_V0_ACCESS_VM 0x00
14 #define NV_DMA_V0_ACCESS_RD 0x01
15 #define NV_DMA_V0_ACCESS_WR 0x02
16 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
17 __u8 access;
18 __u8 pad03[5];
19 __u64 start;
20 __u64 limit;
21 /* ... chipset-specific class data */
22 };
23
24 struct nv50_dma_v0 {
25 __u8 version;
26 #define NV50_DMA_V0_PRIV_VM 0x00
27 #define NV50_DMA_V0_PRIV_US 0x01
28 #define NV50_DMA_V0_PRIV__S 0x02
29 __u8 priv;
30 #define NV50_DMA_V0_PART_VM 0x00
31 #define NV50_DMA_V0_PART_256 0x01
32 #define NV50_DMA_V0_PART_1KB 0x02
33 __u8 part;
34 #define NV50_DMA_V0_COMP_NONE 0x00
35 #define NV50_DMA_V0_COMP_1 0x01
36 #define NV50_DMA_V0_COMP_2 0x02
37 #define NV50_DMA_V0_COMP_VM 0x03
38 __u8 comp;
39 #define NV50_DMA_V0_KIND_PITCH 0x00
40 #define NV50_DMA_V0_KIND_VM 0x7f
41 __u8 kind;
42 __u8 pad05[3];
43 };
44
45 struct gf100_dma_v0 {
46 __u8 version;
47 #define GF100_DMA_V0_PRIV_VM 0x00
48 #define GF100_DMA_V0_PRIV_US 0x01
49 #define GF100_DMA_V0_PRIV__S 0x02
50 __u8 priv;
51 #define GF100_DMA_V0_KIND_PITCH 0x00
52 #define GF100_DMA_V0_KIND_VM 0xff
53 __u8 kind;
54 __u8 pad03[5];
55 };
56
57 struct gf119_dma_v0 {
58 __u8 version;
59 #define GF119_DMA_V0_PAGE_LP 0x00
60 #define GF119_DMA_V0_PAGE_SP 0x01
61 __u8 page;
62 #define GF119_DMA_V0_KIND_PITCH 0x00
63 #define GF119_DMA_V0_KIND_VM 0xff
64 __u8 kind;
65 __u8 pad03[5];
66 };
67 #endif