arch/arm64/kernel/cpufeature.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
set_sys_caps_initialised
dump_cpu_hwcaps
register_cpu_hwcaps_dumper
search_cmp_ftr_reg
get_arm64_ftr_reg
arm64_ftr_set_value
arm64_ftr_safe_value
sort_ftr_regs
init_cpu_ftr_reg
init_cpu_hwcaps_indirect_list_from_array
init_cpu_hwcaps_indirect_list
init_cpu_features
update_cpu_ftr_reg
check_update_ftr_reg
update_cpu_features
read_sanitised_ftr_reg
__read_sysreg_by_encoding
feature_matches
has_cpuid_feature
has_useable_gicv3_cpuif
has_no_hw_prefetch
has_no_fpsimd
has_cache_idc
cpu_emulate_effective_ctr
has_cache_dic
has_useable_cnp
unmap_kernel_at_el0
kpti_install_ng_mappings
kpti_install_ng_mappings
parse_kpti
__cpu_enable_hw_dbm
cpu_has_broken_dbm
cpu_can_use_dbm
cpu_enable_hw_dbm
has_hw_dbm
runs_at_el2
cpu_copy_el2regs
cpu_has_fwb
ssbs_emulation_handler
cpu_enable_ssbs
cpu_enable_pan
cpu_clear_disr
cpu_enable_address_auth
early_enable_pseudo_nmi
can_use_gic_priorities
compat_has_neon
cap_set_elf_hwcap
cpus_have_elf_hwcap
setup_elf_hwcaps
update_cpu_capabilities
cpu_enable_non_boot_scope_capabilities
enable_cpu_capabilities
verify_local_cpu_caps
check_early_cpu_features
verify_local_elf_hwcaps
verify_sve_features
verify_local_cpu_capabilities
check_local_cpu_capabilities
setup_boot_cpu_capabilities
mark_const_caps_ready
this_cpu_has_cap
cpu_set_feature
cpu_have_feature
cpu_get_elf_hwcap
cpu_get_elf_hwcap2
setup_system_capabilities
setup_cpu_features
cpufeature_pan_not_uao
cpu_enable_cnp
is_emulated
emulate_id_reg
emulate_sys_reg
do_emulate_mrs
emulate_mrs
enable_mrs_emulation
cpu_show_meltdown
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Contains CPU feature definitions
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  */
   7 
   8 #define pr_fmt(fmt) "CPU features: " fmt
   9 
  10 #include <linux/bsearch.h>
  11 #include <linux/cpumask.h>
  12 #include <linux/crash_dump.h>
  13 #include <linux/sort.h>
  14 #include <linux/stop_machine.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/cpu.h>
  18 #include <asm/cpu.h>
  19 #include <asm/cpufeature.h>
  20 #include <asm/cpu_ops.h>
  21 #include <asm/fpsimd.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/processor.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/traps.h>
  26 #include <asm/virt.h>
  27 
  28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  29 static unsigned long elf_hwcap __read_mostly;
  30 
  31 #ifdef CONFIG_COMPAT
  32 #define COMPAT_ELF_HWCAP_DEFAULT        \
  33                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  34                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  35                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
  36                                  COMPAT_HWCAP_LPAE)
  37 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  38 unsigned int compat_elf_hwcap2 __read_mostly;
  39 #endif
  40 
  41 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  42 EXPORT_SYMBOL(cpu_hwcaps);
  43 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  44 
  45 /* Need also bit for ARM64_CB_PATCH */
  46 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  47 
  48 /*
  49  * Flag to indicate if we have computed the system wide
  50  * capabilities based on the boot time active CPUs. This
  51  * will be used to determine if a new booting CPU should
  52  * go through the verification process to make sure that it
  53  * supports the system capabilities, without using a hotplug
  54  * notifier.
  55  */
  56 static bool sys_caps_initialised;
  57 
  58 static inline void set_sys_caps_initialised(void)
  59 {
  60         sys_caps_initialised = true;
  61 }
  62 
  63 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  64 {
  65         /* file-wide pr_fmt adds "CPU features: " prefix */
  66         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  67         return 0;
  68 }
  69 
  70 static struct notifier_block cpu_hwcaps_notifier = {
  71         .notifier_call = dump_cpu_hwcaps
  72 };
  73 
  74 static int __init register_cpu_hwcaps_dumper(void)
  75 {
  76         atomic_notifier_chain_register(&panic_notifier_list,
  77                                        &cpu_hwcaps_notifier);
  78         return 0;
  79 }
  80 __initcall(register_cpu_hwcaps_dumper);
  81 
  82 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  83 EXPORT_SYMBOL(cpu_hwcap_keys);
  84 
  85 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  86         {                                               \
  87                 .sign = SIGNED,                         \
  88                 .visible = VISIBLE,                     \
  89                 .strict = STRICT,                       \
  90                 .type = TYPE,                           \
  91                 .shift = SHIFT,                         \
  92                 .width = WIDTH,                         \
  93                 .safe_val = SAFE_VAL,                   \
  94         }
  95 
  96 /* Define a feature with unsigned values */
  97 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  98         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
  99 
 100 /* Define a feature with a signed value */
 101 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 102         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 103 
 104 #define ARM64_FTR_END                                   \
 105         {                                               \
 106                 .width = 0,                             \
 107         }
 108 
 109 /* meta feature for alternatives */
 110 static bool __maybe_unused
 111 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 112 
 113 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 114 
 115 /*
 116  * NOTE: Any changes to the visibility of features should be kept in
 117  * sync with the documentation of the CPU feature register ABI.
 118  */
 119 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 120         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 121         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 122         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 123         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 124         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 125         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 132         ARM64_FTR_END,
 133 };
 134 
 135 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 139                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 141                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 145         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 146                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 147         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 148                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 149         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 150         ARM64_FTR_END,
 151 };
 152 
 153 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 154         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 155         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 156         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 157         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 158                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 161         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 162         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 163         /* Linux doesn't care about the EL3 */
 164         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 165         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 168         ARM64_FTR_END,
 169 };
 170 
 171 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 172         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 173         ARM64_FTR_END,
 174 };
 175 
 176 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 177         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 178                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 179         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 180                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 181         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 182                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 183         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 184                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 186                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 187         ARM64_FTR_END,
 188 };
 189 
 190 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 191         /*
 192          * We already refuse to boot CPUs that don't support our configured
 193          * page size, so we can only detect mismatches for a page size other
 194          * than the one we're currently using. Unfortunately, SoCs like this
 195          * exist in the wild so, even though we don't like it, we'll have to go
 196          * along with it and treat them as non-strict.
 197          */
 198         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 199         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 200         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 201 
 202         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 203         /* Linux shouldn't care about secure memory */
 204         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 205         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 206         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 207         /*
 208          * Differing PARange is fine as long as all peripherals and memory are mapped
 209          * within the minimum PARange of all CPUs
 210          */
 211         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 212         ARM64_FTR_END,
 213 };
 214 
 215 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 216         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 217         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 221         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 222         ARM64_FTR_END,
 223 };
 224 
 225 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 227         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 228         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 232         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 233         ARM64_FTR_END,
 234 };
 235 
 236 static const struct arm64_ftr_bits ftr_ctr[] = {
 237         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 239         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 240         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
 242         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 243         /*
 244          * Linux can handle differing I-cache policies. Userspace JITs will
 245          * make use of *minLine.
 246          * If we have differing I-cache policies, report it as the weakest - VIPT.
 247          */
 248         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 249         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 250         ARM64_FTR_END,
 251 };
 252 
 253 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 254         .name           = "SYS_CTR_EL0",
 255         .ftr_bits       = ftr_ctr
 256 };
 257 
 258 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 259         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 263         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 264         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 267         ARM64_FTR_END,
 268 };
 269 
 270 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 271         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 272         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 273         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 276         /*
 277          * We can instantiate multiple PMU instances with different levels
 278          * of support.
 279          */
 280         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 283         ARM64_FTR_END,
 284 };
 285 
 286 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 287         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 288         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 289         ARM64_FTR_END,
 290 };
 291 
 292 static const struct arm64_ftr_bits ftr_dczid[] = {
 293         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 294         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 295         ARM64_FTR_END,
 296 };
 297 
 298 
 299 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 302         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 305         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 306         ARM64_FTR_END,
 307 };
 308 
 309 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 310         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 311         ARM64_FTR_END,
 312 };
 313 
 314 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 319         ARM64_FTR_END,
 320 };
 321 
 322 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 323         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 324         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 326         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 327         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 328         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 330         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 331         ARM64_FTR_END,
 332 };
 333 
 334 static const struct arm64_ftr_bits ftr_zcr[] = {
 335         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 336                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 337         ARM64_FTR_END,
 338 };
 339 
 340 /*
 341  * Common ftr bits for a 32bit register with all hidden, strict
 342  * attributes, with 4bit feature fields and a default safe value of
 343  * 0. Covers the following 32bit registers:
 344  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 345  */
 346 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 347         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 351         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 352         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 353         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 354         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 355         ARM64_FTR_END,
 356 };
 357 
 358 /* Table for a single 32bit feature value */
 359 static const struct arm64_ftr_bits ftr_single32[] = {
 360         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 361         ARM64_FTR_END,
 362 };
 363 
 364 static const struct arm64_ftr_bits ftr_raz[] = {
 365         ARM64_FTR_END,
 366 };
 367 
 368 #define ARM64_FTR_REG(id, table) {              \
 369         .sys_id = id,                           \
 370         .reg =  &(struct arm64_ftr_reg){        \
 371                 .name = #id,                    \
 372                 .ftr_bits = &((table)[0]),      \
 373         }}
 374 
 375 static const struct __ftr_reg_entry {
 376         u32                     sys_id;
 377         struct arm64_ftr_reg    *reg;
 378 } arm64_ftr_regs[] = {
 379 
 380         /* Op1 = 0, CRn = 0, CRm = 1 */
 381         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 382         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 383         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 384         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 385         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 386         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 387         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 388 
 389         /* Op1 = 0, CRn = 0, CRm = 2 */
 390         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 391         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 392         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 393         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 394         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 395         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 396         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 397 
 398         /* Op1 = 0, CRn = 0, CRm = 3 */
 399         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 400         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 401         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 402 
 403         /* Op1 = 0, CRn = 0, CRm = 4 */
 404         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 405         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 406         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 407 
 408         /* Op1 = 0, CRn = 0, CRm = 5 */
 409         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 410         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 411 
 412         /* Op1 = 0, CRn = 0, CRm = 6 */
 413         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 414         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 415 
 416         /* Op1 = 0, CRn = 0, CRm = 7 */
 417         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 418         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 419         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 420 
 421         /* Op1 = 0, CRn = 1, CRm = 2 */
 422         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 423 
 424         /* Op1 = 3, CRn = 0, CRm = 0 */
 425         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 426         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 427 
 428         /* Op1 = 3, CRn = 14, CRm = 0 */
 429         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 430 };
 431 
 432 static int search_cmp_ftr_reg(const void *id, const void *regp)
 433 {
 434         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 435 }
 436 
 437 /*
 438  * get_arm64_ftr_reg - Lookup a feature register entry using its
 439  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 440  * ascending order of sys_id , we use binary search to find a matching
 441  * entry.
 442  *
 443  * returns - Upon success,  matching ftr_reg entry for id.
 444  *         - NULL on failure. It is upto the caller to decide
 445  *           the impact of a failure.
 446  */
 447 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 448 {
 449         const struct __ftr_reg_entry *ret;
 450 
 451         ret = bsearch((const void *)(unsigned long)sys_id,
 452                         arm64_ftr_regs,
 453                         ARRAY_SIZE(arm64_ftr_regs),
 454                         sizeof(arm64_ftr_regs[0]),
 455                         search_cmp_ftr_reg);
 456         if (ret)
 457                 return ret->reg;
 458         return NULL;
 459 }
 460 
 461 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 462                                s64 ftr_val)
 463 {
 464         u64 mask = arm64_ftr_mask(ftrp);
 465 
 466         reg &= ~mask;
 467         reg |= (ftr_val << ftrp->shift) & mask;
 468         return reg;
 469 }
 470 
 471 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 472                                 s64 cur)
 473 {
 474         s64 ret = 0;
 475 
 476         switch (ftrp->type) {
 477         case FTR_EXACT:
 478                 ret = ftrp->safe_val;
 479                 break;
 480         case FTR_LOWER_SAFE:
 481                 ret = new < cur ? new : cur;
 482                 break;
 483         case FTR_HIGHER_OR_ZERO_SAFE:
 484                 if (!cur || !new)
 485                         break;
 486                 /* Fallthrough */
 487         case FTR_HIGHER_SAFE:
 488                 ret = new > cur ? new : cur;
 489                 break;
 490         default:
 491                 BUG();
 492         }
 493 
 494         return ret;
 495 }
 496 
 497 static void __init sort_ftr_regs(void)
 498 {
 499         int i;
 500 
 501         /* Check that the array is sorted so that we can do the binary search */
 502         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 503                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 504 }
 505 
 506 /*
 507  * Initialise the CPU feature register from Boot CPU values.
 508  * Also initiliases the strict_mask for the register.
 509  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 510  * RES0 for the system-wide value, and must strictly match.
 511  */
 512 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 513 {
 514         u64 val = 0;
 515         u64 strict_mask = ~0x0ULL;
 516         u64 user_mask = 0;
 517         u64 valid_mask = 0;
 518 
 519         const struct arm64_ftr_bits *ftrp;
 520         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 521 
 522         BUG_ON(!reg);
 523 
 524         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 525                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 526                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 527 
 528                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 529 
 530                 valid_mask |= ftr_mask;
 531                 if (!ftrp->strict)
 532                         strict_mask &= ~ftr_mask;
 533                 if (ftrp->visible)
 534                         user_mask |= ftr_mask;
 535                 else
 536                         reg->user_val = arm64_ftr_set_value(ftrp,
 537                                                             reg->user_val,
 538                                                             ftrp->safe_val);
 539         }
 540 
 541         val &= valid_mask;
 542 
 543         reg->sys_val = val;
 544         reg->strict_mask = strict_mask;
 545         reg->user_mask = user_mask;
 546 }
 547 
 548 extern const struct arm64_cpu_capabilities arm64_errata[];
 549 static const struct arm64_cpu_capabilities arm64_features[];
 550 
 551 static void __init
 552 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 553 {
 554         for (; caps->matches; caps++) {
 555                 if (WARN(caps->capability >= ARM64_NCAPS,
 556                         "Invalid capability %d\n", caps->capability))
 557                         continue;
 558                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 559                         "Duplicate entry for capability %d\n",
 560                         caps->capability))
 561                         continue;
 562                 cpu_hwcaps_ptrs[caps->capability] = caps;
 563         }
 564 }
 565 
 566 static void __init init_cpu_hwcaps_indirect_list(void)
 567 {
 568         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 569         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 570 }
 571 
 572 static void __init setup_boot_cpu_capabilities(void);
 573 
 574 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 575 {
 576         /* Before we start using the tables, make sure it is sorted */
 577         sort_ftr_regs();
 578 
 579         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 580         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 581         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 582         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 583         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 584         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 585         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 586         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 587         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 588         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 589         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 590         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 591         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 592 
 593         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 594                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 595                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 596                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 597                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 598                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 599                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 600                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 601                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 602                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 603                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 604                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 605                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 606                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 607                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 608                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 609                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 610         }
 611 
 612         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 613                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 614                 sve_init_vq_map();
 615         }
 616 
 617         /*
 618          * Initialize the indirect array of CPU hwcaps capabilities pointers
 619          * before we handle the boot CPU below.
 620          */
 621         init_cpu_hwcaps_indirect_list();
 622 
 623         /*
 624          * Detect and enable early CPU capabilities based on the boot CPU,
 625          * after we have initialised the CPU feature infrastructure.
 626          */
 627         setup_boot_cpu_capabilities();
 628 }
 629 
 630 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 631 {
 632         const struct arm64_ftr_bits *ftrp;
 633 
 634         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 635                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 636                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 637 
 638                 if (ftr_cur == ftr_new)
 639                         continue;
 640                 /* Find a safe value */
 641                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 642                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 643         }
 644 
 645 }
 646 
 647 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 648 {
 649         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 650 
 651         BUG_ON(!regp);
 652         update_cpu_ftr_reg(regp, val);
 653         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 654                 return 0;
 655         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 656                         regp->name, boot, cpu, val);
 657         return 1;
 658 }
 659 
 660 /*
 661  * Update system wide CPU feature registers with the values from a
 662  * non-boot CPU. Also performs SANITY checks to make sure that there
 663  * aren't any insane variations from that of the boot CPU.
 664  */
 665 void update_cpu_features(int cpu,
 666                          struct cpuinfo_arm64 *info,
 667                          struct cpuinfo_arm64 *boot)
 668 {
 669         int taint = 0;
 670 
 671         /*
 672          * The kernel can handle differing I-cache policies, but otherwise
 673          * caches should look identical. Userspace JITs will make use of
 674          * *minLine.
 675          */
 676         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 677                                       info->reg_ctr, boot->reg_ctr);
 678 
 679         /*
 680          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 681          * could result in too much or too little memory being zeroed if a
 682          * process is preempted and migrated between CPUs.
 683          */
 684         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 685                                       info->reg_dczid, boot->reg_dczid);
 686 
 687         /* If different, timekeeping will be broken (especially with KVM) */
 688         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 689                                       info->reg_cntfrq, boot->reg_cntfrq);
 690 
 691         /*
 692          * The kernel uses self-hosted debug features and expects CPUs to
 693          * support identical debug features. We presently need CTX_CMPs, WRPs,
 694          * and BRPs to be identical.
 695          * ID_AA64DFR1 is currently RES0.
 696          */
 697         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 698                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 699         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 700                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 701         /*
 702          * Even in big.LITTLE, processors should be identical instruction-set
 703          * wise.
 704          */
 705         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 706                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 707         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 708                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 709 
 710         /*
 711          * Differing PARange support is fine as long as all peripherals and
 712          * memory are mapped within the minimum PARange of all CPUs.
 713          * Linux should not care about secure memory.
 714          */
 715         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 716                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 717         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 718                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 719         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 720                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 721 
 722         /*
 723          * EL3 is not our concern.
 724          */
 725         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 726                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 727         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 728                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 729 
 730         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 731                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 732 
 733         /*
 734          * If we have AArch32, we care about 32-bit features for compat.
 735          * If the system doesn't support AArch32, don't update them.
 736          */
 737         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 738                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 739 
 740                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 741                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 742                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 743                                         info->reg_id_isar0, boot->reg_id_isar0);
 744                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 745                                         info->reg_id_isar1, boot->reg_id_isar1);
 746                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 747                                         info->reg_id_isar2, boot->reg_id_isar2);
 748                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 749                                         info->reg_id_isar3, boot->reg_id_isar3);
 750                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 751                                         info->reg_id_isar4, boot->reg_id_isar4);
 752                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 753                                         info->reg_id_isar5, boot->reg_id_isar5);
 754 
 755                 /*
 756                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 757                  * ACTLR formats could differ across CPUs and therefore would have to
 758                  * be trapped for virtualization anyway.
 759                  */
 760                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 761                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 762                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 763                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 764                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 765                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 766                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 767                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 768                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 769                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 770                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 771                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 772                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 773                                         info->reg_mvfr0, boot->reg_mvfr0);
 774                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 775                                         info->reg_mvfr1, boot->reg_mvfr1);
 776                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 777                                         info->reg_mvfr2, boot->reg_mvfr2);
 778         }
 779 
 780         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 781                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 782                                         info->reg_zcr, boot->reg_zcr);
 783 
 784                 /* Probe vector lengths, unless we already gave up on SVE */
 785                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 786                     !sys_caps_initialised)
 787                         sve_update_vq_map();
 788         }
 789 
 790         /*
 791          * Mismatched CPU features are a recipe for disaster. Don't even
 792          * pretend to support them.
 793          */
 794         if (taint) {
 795                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 796                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 797         }
 798 }
 799 
 800 u64 read_sanitised_ftr_reg(u32 id)
 801 {
 802         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 803 
 804         /* We shouldn't get a request for an unsupported register */
 805         BUG_ON(!regp);
 806         return regp->sys_val;
 807 }
 808 
 809 #define read_sysreg_case(r)     \
 810         case r:         return read_sysreg_s(r)
 811 
 812 /*
 813  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 814  * Read the system register on the current CPU
 815  */
 816 static u64 __read_sysreg_by_encoding(u32 sys_id)
 817 {
 818         switch (sys_id) {
 819         read_sysreg_case(SYS_ID_PFR0_EL1);
 820         read_sysreg_case(SYS_ID_PFR1_EL1);
 821         read_sysreg_case(SYS_ID_DFR0_EL1);
 822         read_sysreg_case(SYS_ID_MMFR0_EL1);
 823         read_sysreg_case(SYS_ID_MMFR1_EL1);
 824         read_sysreg_case(SYS_ID_MMFR2_EL1);
 825         read_sysreg_case(SYS_ID_MMFR3_EL1);
 826         read_sysreg_case(SYS_ID_ISAR0_EL1);
 827         read_sysreg_case(SYS_ID_ISAR1_EL1);
 828         read_sysreg_case(SYS_ID_ISAR2_EL1);
 829         read_sysreg_case(SYS_ID_ISAR3_EL1);
 830         read_sysreg_case(SYS_ID_ISAR4_EL1);
 831         read_sysreg_case(SYS_ID_ISAR5_EL1);
 832         read_sysreg_case(SYS_MVFR0_EL1);
 833         read_sysreg_case(SYS_MVFR1_EL1);
 834         read_sysreg_case(SYS_MVFR2_EL1);
 835 
 836         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 837         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 838         read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
 839         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 840         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 841         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 842         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 843         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 844         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 845         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 846 
 847         read_sysreg_case(SYS_CNTFRQ_EL0);
 848         read_sysreg_case(SYS_CTR_EL0);
 849         read_sysreg_case(SYS_DCZID_EL0);
 850 
 851         default:
 852                 BUG();
 853                 return 0;
 854         }
 855 }
 856 
 857 #include <linux/irqchip/arm-gic-v3.h>
 858 
 859 static bool
 860 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 861 {
 862         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 863 
 864         return val >= entry->min_field_value;
 865 }
 866 
 867 static bool
 868 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 869 {
 870         u64 val;
 871 
 872         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 873         if (scope == SCOPE_SYSTEM)
 874                 val = read_sanitised_ftr_reg(entry->sys_reg);
 875         else
 876                 val = __read_sysreg_by_encoding(entry->sys_reg);
 877 
 878         return feature_matches(val, entry);
 879 }
 880 
 881 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 882 {
 883         bool has_sre;
 884 
 885         if (!has_cpuid_feature(entry, scope))
 886                 return false;
 887 
 888         has_sre = gic_enable_sre();
 889         if (!has_sre)
 890                 pr_warn_once("%s present but disabled by higher exception level\n",
 891                              entry->desc);
 892 
 893         return has_sre;
 894 }
 895 
 896 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 897 {
 898         u32 midr = read_cpuid_id();
 899 
 900         /* Cavium ThunderX pass 1.x and 2.x */
 901         return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
 902                 MIDR_CPU_VAR_REV(0, 0),
 903                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 904 }
 905 
 906 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 907 {
 908         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 909 
 910         return cpuid_feature_extract_signed_field(pfr0,
 911                                         ID_AA64PFR0_FP_SHIFT) < 0;
 912 }
 913 
 914 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 915                           int scope)
 916 {
 917         u64 ctr;
 918 
 919         if (scope == SCOPE_SYSTEM)
 920                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 921         else
 922                 ctr = read_cpuid_effective_cachetype();
 923 
 924         return ctr & BIT(CTR_IDC_SHIFT);
 925 }
 926 
 927 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 928 {
 929         /*
 930          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 931          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 932          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 933          * value.
 934          */
 935         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 936                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 937 }
 938 
 939 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 940                           int scope)
 941 {
 942         u64 ctr;
 943 
 944         if (scope == SCOPE_SYSTEM)
 945                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 946         else
 947                 ctr = read_cpuid_cachetype();
 948 
 949         return ctr & BIT(CTR_DIC_SHIFT);
 950 }
 951 
 952 static bool __maybe_unused
 953 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 954 {
 955         /*
 956          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 957          * may share TLB entries with a CPU stuck in the crashed
 958          * kernel.
 959          */
 960          if (is_kdump_kernel())
 961                 return false;
 962 
 963         return has_cpuid_feature(entry, scope);
 964 }
 965 
 966 static bool __meltdown_safe = true;
 967 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 968 
 969 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 970                                 int scope)
 971 {
 972         /* List of CPUs that are not vulnerable and don't need KPTI */
 973         static const struct midr_range kpti_safe_list[] = {
 974                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 975                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 976                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 977                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 978                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 979                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 980                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 981                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 982                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 983                 { /* sentinel */ }
 984         };
 985         char const *str = "kpti command line option";
 986         bool meltdown_safe;
 987 
 988         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 989 
 990         /* Defer to CPU feature registers */
 991         if (has_cpuid_feature(entry, scope))
 992                 meltdown_safe = true;
 993 
 994         if (!meltdown_safe)
 995                 __meltdown_safe = false;
 996 
 997         /*
 998          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 999          * ThunderX leads to apparent I-cache corruption of kernel text, which
1000          * ends as well as you might imagine. Don't even try.
1001          */
1002         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1003                 str = "ARM64_WORKAROUND_CAVIUM_27456";
1004                 __kpti_forced = -1;
1005         }
1006 
1007         /* Useful for KASLR robustness */
1008         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1009                 if (!__kpti_forced) {
1010                         str = "KASLR";
1011                         __kpti_forced = 1;
1012                 }
1013         }
1014 
1015         if (cpu_mitigations_off() && !__kpti_forced) {
1016                 str = "mitigations=off";
1017                 __kpti_forced = -1;
1018         }
1019 
1020         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1021                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1022                 return false;
1023         }
1024 
1025         /* Forced? */
1026         if (__kpti_forced) {
1027                 pr_info_once("kernel page table isolation forced %s by %s\n",
1028                              __kpti_forced > 0 ? "ON" : "OFF", str);
1029                 return __kpti_forced > 0;
1030         }
1031 
1032         return !meltdown_safe;
1033 }
1034 
1035 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1036 static void
1037 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1038 {
1039         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1040         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1041         kpti_remap_fn *remap_fn;
1042 
1043         static bool kpti_applied = false;
1044         int cpu = smp_processor_id();
1045 
1046         /*
1047          * We don't need to rewrite the page-tables if either we've done
1048          * it already or we have KASLR enabled and therefore have not
1049          * created any global mappings at all.
1050          */
1051         if (kpti_applied || kaslr_offset() > 0)
1052                 return;
1053 
1054         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1055 
1056         cpu_install_idmap();
1057         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1058         cpu_uninstall_idmap();
1059 
1060         if (!cpu)
1061                 kpti_applied = true;
1062 
1063         return;
1064 }
1065 #else
1066 static void
1067 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1068 {
1069 }
1070 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1071 
1072 static int __init parse_kpti(char *str)
1073 {
1074         bool enabled;
1075         int ret = strtobool(str, &enabled);
1076 
1077         if (ret)
1078                 return ret;
1079 
1080         __kpti_forced = enabled ? 1 : -1;
1081         return 0;
1082 }
1083 early_param("kpti", parse_kpti);
1084 
1085 #ifdef CONFIG_ARM64_HW_AFDBM
1086 static inline void __cpu_enable_hw_dbm(void)
1087 {
1088         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1089 
1090         write_sysreg(tcr, tcr_el1);
1091         isb();
1092 }
1093 
1094 static bool cpu_has_broken_dbm(void)
1095 {
1096         /* List of CPUs which have broken DBM support. */
1097         static const struct midr_range cpus[] = {
1098 #ifdef CONFIG_ARM64_ERRATUM_1024718
1099                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1100 #endif
1101                 {},
1102         };
1103 
1104         return is_midr_in_range_list(read_cpuid_id(), cpus);
1105 }
1106 
1107 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1108 {
1109         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1110                !cpu_has_broken_dbm();
1111 }
1112 
1113 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1114 {
1115         if (cpu_can_use_dbm(cap))
1116                 __cpu_enable_hw_dbm();
1117 }
1118 
1119 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1120                        int __unused)
1121 {
1122         static bool detected = false;
1123         /*
1124          * DBM is a non-conflicting feature. i.e, the kernel can safely
1125          * run a mix of CPUs with and without the feature. So, we
1126          * unconditionally enable the capability to allow any late CPU
1127          * to use the feature. We only enable the control bits on the
1128          * CPU, if it actually supports.
1129          *
1130          * We have to make sure we print the "feature" detection only
1131          * when at least one CPU actually uses it. So check if this CPU
1132          * can actually use it and print the message exactly once.
1133          *
1134          * This is safe as all CPUs (including secondary CPUs - due to the
1135          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1136          * goes through the "matches" check exactly once. Also if a CPU
1137          * matches the criteria, it is guaranteed that the CPU will turn
1138          * the DBM on, as the capability is unconditionally enabled.
1139          */
1140         if (!detected && cpu_can_use_dbm(cap)) {
1141                 detected = true;
1142                 pr_info("detected: Hardware dirty bit management\n");
1143         }
1144 
1145         return true;
1146 }
1147 
1148 #endif
1149 
1150 #ifdef CONFIG_ARM64_VHE
1151 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1152 {
1153         return is_kernel_in_hyp_mode();
1154 }
1155 
1156 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1157 {
1158         /*
1159          * Copy register values that aren't redirected by hardware.
1160          *
1161          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1162          * this value to tpidr_el2 before we patch the code. Once we've done
1163          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1164          * do anything here.
1165          */
1166         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1167                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1168 }
1169 #endif
1170 
1171 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1172 {
1173         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1174 
1175         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1176         WARN_ON(val & (7 << 27 | 7 << 21));
1177 }
1178 
1179 #ifdef CONFIG_ARM64_SSBD
1180 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1181 {
1182         if (user_mode(regs))
1183                 return 1;
1184 
1185         if (instr & BIT(PSTATE_Imm_shift))
1186                 regs->pstate |= PSR_SSBS_BIT;
1187         else
1188                 regs->pstate &= ~PSR_SSBS_BIT;
1189 
1190         arm64_skip_faulting_instruction(regs, 4);
1191         return 0;
1192 }
1193 
1194 static struct undef_hook ssbs_emulation_hook = {
1195         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1196         .instr_val      = 0xd500401f | PSTATE_SSBS,
1197         .fn             = ssbs_emulation_handler,
1198 };
1199 
1200 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1201 {
1202         static bool undef_hook_registered = false;
1203         static DEFINE_RAW_SPINLOCK(hook_lock);
1204 
1205         raw_spin_lock(&hook_lock);
1206         if (!undef_hook_registered) {
1207                 register_undef_hook(&ssbs_emulation_hook);
1208                 undef_hook_registered = true;
1209         }
1210         raw_spin_unlock(&hook_lock);
1211 
1212         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1213                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1214                 arm64_set_ssbd_mitigation(false);
1215         } else {
1216                 arm64_set_ssbd_mitigation(true);
1217         }
1218 }
1219 #endif /* CONFIG_ARM64_SSBD */
1220 
1221 #ifdef CONFIG_ARM64_PAN
1222 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1223 {
1224         /*
1225          * We modify PSTATE. This won't work from irq context as the PSTATE
1226          * is discarded once we return from the exception.
1227          */
1228         WARN_ON_ONCE(in_interrupt());
1229 
1230         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1231         asm(SET_PSTATE_PAN(1));
1232 }
1233 #endif /* CONFIG_ARM64_PAN */
1234 
1235 #ifdef CONFIG_ARM64_RAS_EXTN
1236 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1237 {
1238         /* Firmware may have left a deferred SError in this register. */
1239         write_sysreg_s(0, SYS_DISR_EL1);
1240 }
1241 #endif /* CONFIG_ARM64_RAS_EXTN */
1242 
1243 #ifdef CONFIG_ARM64_PTR_AUTH
1244 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1245 {
1246         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1247                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1248 }
1249 #endif /* CONFIG_ARM64_PTR_AUTH */
1250 
1251 #ifdef CONFIG_ARM64_PSEUDO_NMI
1252 static bool enable_pseudo_nmi;
1253 
1254 static int __init early_enable_pseudo_nmi(char *p)
1255 {
1256         return strtobool(p, &enable_pseudo_nmi);
1257 }
1258 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1259 
1260 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1261                                    int scope)
1262 {
1263         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1264 }
1265 #endif
1266 
1267 static const struct arm64_cpu_capabilities arm64_features[] = {
1268         {
1269                 .desc = "GIC system register CPU interface",
1270                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1271                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1272                 .matches = has_useable_gicv3_cpuif,
1273                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1274                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1275                 .sign = FTR_UNSIGNED,
1276                 .min_field_value = 1,
1277         },
1278 #ifdef CONFIG_ARM64_PAN
1279         {
1280                 .desc = "Privileged Access Never",
1281                 .capability = ARM64_HAS_PAN,
1282                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1283                 .matches = has_cpuid_feature,
1284                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1285                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1286                 .sign = FTR_UNSIGNED,
1287                 .min_field_value = 1,
1288                 .cpu_enable = cpu_enable_pan,
1289         },
1290 #endif /* CONFIG_ARM64_PAN */
1291 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1292         {
1293                 .desc = "LSE atomic instructions",
1294                 .capability = ARM64_HAS_LSE_ATOMICS,
1295                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1296                 .matches = has_cpuid_feature,
1297                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1298                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1299                 .sign = FTR_UNSIGNED,
1300                 .min_field_value = 2,
1301         },
1302 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1303         {
1304                 .desc = "Software prefetching using PRFM",
1305                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1306                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1307                 .matches = has_no_hw_prefetch,
1308         },
1309 #ifdef CONFIG_ARM64_UAO
1310         {
1311                 .desc = "User Access Override",
1312                 .capability = ARM64_HAS_UAO,
1313                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1314                 .matches = has_cpuid_feature,
1315                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1316                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1317                 .min_field_value = 1,
1318                 /*
1319                  * We rely on stop_machine() calling uao_thread_switch() to set
1320                  * UAO immediately after patching.
1321                  */
1322         },
1323 #endif /* CONFIG_ARM64_UAO */
1324 #ifdef CONFIG_ARM64_PAN
1325         {
1326                 .capability = ARM64_ALT_PAN_NOT_UAO,
1327                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1328                 .matches = cpufeature_pan_not_uao,
1329         },
1330 #endif /* CONFIG_ARM64_PAN */
1331 #ifdef CONFIG_ARM64_VHE
1332         {
1333                 .desc = "Virtualization Host Extensions",
1334                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1335                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1336                 .matches = runs_at_el2,
1337                 .cpu_enable = cpu_copy_el2regs,
1338         },
1339 #endif  /* CONFIG_ARM64_VHE */
1340         {
1341                 .desc = "32-bit EL0 Support",
1342                 .capability = ARM64_HAS_32BIT_EL0,
1343                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1344                 .matches = has_cpuid_feature,
1345                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1346                 .sign = FTR_UNSIGNED,
1347                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1348                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1349         },
1350         {
1351                 .desc = "Kernel page table isolation (KPTI)",
1352                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1353                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1354                 /*
1355                  * The ID feature fields below are used to indicate that
1356                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1357                  * more details.
1358                  */
1359                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1360                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1361                 .min_field_value = 1,
1362                 .matches = unmap_kernel_at_el0,
1363                 .cpu_enable = kpti_install_ng_mappings,
1364         },
1365         {
1366                 /* FP/SIMD is not implemented */
1367                 .capability = ARM64_HAS_NO_FPSIMD,
1368                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1369                 .min_field_value = 0,
1370                 .matches = has_no_fpsimd,
1371         },
1372 #ifdef CONFIG_ARM64_PMEM
1373         {
1374                 .desc = "Data cache clean to Point of Persistence",
1375                 .capability = ARM64_HAS_DCPOP,
1376                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1377                 .matches = has_cpuid_feature,
1378                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1379                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1380                 .min_field_value = 1,
1381         },
1382         {
1383                 .desc = "Data cache clean to Point of Deep Persistence",
1384                 .capability = ARM64_HAS_DCPODP,
1385                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1386                 .matches = has_cpuid_feature,
1387                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1388                 .sign = FTR_UNSIGNED,
1389                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1390                 .min_field_value = 2,
1391         },
1392 #endif
1393 #ifdef CONFIG_ARM64_SVE
1394         {
1395                 .desc = "Scalable Vector Extension",
1396                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1397                 .capability = ARM64_SVE,
1398                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1399                 .sign = FTR_UNSIGNED,
1400                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1401                 .min_field_value = ID_AA64PFR0_SVE,
1402                 .matches = has_cpuid_feature,
1403                 .cpu_enable = sve_kernel_enable,
1404         },
1405 #endif /* CONFIG_ARM64_SVE */
1406 #ifdef CONFIG_ARM64_RAS_EXTN
1407         {
1408                 .desc = "RAS Extension Support",
1409                 .capability = ARM64_HAS_RAS_EXTN,
1410                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1411                 .matches = has_cpuid_feature,
1412                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1413                 .sign = FTR_UNSIGNED,
1414                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1415                 .min_field_value = ID_AA64PFR0_RAS_V1,
1416                 .cpu_enable = cpu_clear_disr,
1417         },
1418 #endif /* CONFIG_ARM64_RAS_EXTN */
1419         {
1420                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1421                 .capability = ARM64_HAS_CACHE_IDC,
1422                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1423                 .matches = has_cache_idc,
1424                 .cpu_enable = cpu_emulate_effective_ctr,
1425         },
1426         {
1427                 .desc = "Instruction cache invalidation not required for I/D coherence",
1428                 .capability = ARM64_HAS_CACHE_DIC,
1429                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1430                 .matches = has_cache_dic,
1431         },
1432         {
1433                 .desc = "Stage-2 Force Write-Back",
1434                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1435                 .capability = ARM64_HAS_STAGE2_FWB,
1436                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1437                 .sign = FTR_UNSIGNED,
1438                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1439                 .min_field_value = 1,
1440                 .matches = has_cpuid_feature,
1441                 .cpu_enable = cpu_has_fwb,
1442         },
1443 #ifdef CONFIG_ARM64_HW_AFDBM
1444         {
1445                 /*
1446                  * Since we turn this on always, we don't want the user to
1447                  * think that the feature is available when it may not be.
1448                  * So hide the description.
1449                  *
1450                  * .desc = "Hardware pagetable Dirty Bit Management",
1451                  *
1452                  */
1453                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1454                 .capability = ARM64_HW_DBM,
1455                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1456                 .sign = FTR_UNSIGNED,
1457                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1458                 .min_field_value = 2,
1459                 .matches = has_hw_dbm,
1460                 .cpu_enable = cpu_enable_hw_dbm,
1461         },
1462 #endif
1463         {
1464                 .desc = "CRC32 instructions",
1465                 .capability = ARM64_HAS_CRC32,
1466                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1467                 .matches = has_cpuid_feature,
1468                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1469                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1470                 .min_field_value = 1,
1471         },
1472 #ifdef CONFIG_ARM64_SSBD
1473         {
1474                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1475                 .capability = ARM64_SSBS,
1476                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1477                 .matches = has_cpuid_feature,
1478                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1479                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1480                 .sign = FTR_UNSIGNED,
1481                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1482                 .cpu_enable = cpu_enable_ssbs,
1483         },
1484 #endif
1485 #ifdef CONFIG_ARM64_CNP
1486         {
1487                 .desc = "Common not Private translations",
1488                 .capability = ARM64_HAS_CNP,
1489                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1490                 .matches = has_useable_cnp,
1491                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1492                 .sign = FTR_UNSIGNED,
1493                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1494                 .min_field_value = 1,
1495                 .cpu_enable = cpu_enable_cnp,
1496         },
1497 #endif
1498         {
1499                 .desc = "Speculation barrier (SB)",
1500                 .capability = ARM64_HAS_SB,
1501                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1502                 .matches = has_cpuid_feature,
1503                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1504                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1505                 .sign = FTR_UNSIGNED,
1506                 .min_field_value = 1,
1507         },
1508 #ifdef CONFIG_ARM64_PTR_AUTH
1509         {
1510                 .desc = "Address authentication (architected algorithm)",
1511                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1512                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1513                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1514                 .sign = FTR_UNSIGNED,
1515                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1516                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1517                 .matches = has_cpuid_feature,
1518                 .cpu_enable = cpu_enable_address_auth,
1519         },
1520         {
1521                 .desc = "Address authentication (IMP DEF algorithm)",
1522                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1523                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1524                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1525                 .sign = FTR_UNSIGNED,
1526                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1527                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1528                 .matches = has_cpuid_feature,
1529                 .cpu_enable = cpu_enable_address_auth,
1530         },
1531         {
1532                 .desc = "Generic authentication (architected algorithm)",
1533                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1534                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1535                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1536                 .sign = FTR_UNSIGNED,
1537                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1538                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1539                 .matches = has_cpuid_feature,
1540         },
1541         {
1542                 .desc = "Generic authentication (IMP DEF algorithm)",
1543                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1544                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1545                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1546                 .sign = FTR_UNSIGNED,
1547                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1548                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1549                 .matches = has_cpuid_feature,
1550         },
1551 #endif /* CONFIG_ARM64_PTR_AUTH */
1552 #ifdef CONFIG_ARM64_PSEUDO_NMI
1553         {
1554                 /*
1555                  * Depends on having GICv3
1556                  */
1557                 .desc = "IRQ priority masking",
1558                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1559                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1560                 .matches = can_use_gic_priorities,
1561                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1562                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1563                 .sign = FTR_UNSIGNED,
1564                 .min_field_value = 1,
1565         },
1566 #endif
1567         {},
1568 };
1569 
1570 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1571                 .matches = has_cpuid_feature,                                   \
1572                 .sys_reg = reg,                                                 \
1573                 .field_pos = field,                                             \
1574                 .sign = s,                                                      \
1575                 .min_field_value = min_value,
1576 
1577 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1578                 .desc = name,                                                   \
1579                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1580                 .hwcap_type = cap_type,                                         \
1581                 .hwcap = cap,                                                   \
1582 
1583 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1584         {                                                                       \
1585                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1586                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1587         }
1588 
1589 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1590         {                                                                       \
1591                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1592                 .matches = cpucap_multi_entry_cap_matches,                      \
1593                 .match_list = list,                                             \
1594         }
1595 
1596 #define HWCAP_CAP_MATCH(match, cap_type, cap)                                   \
1597         {                                                                       \
1598                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1599                 .matches = match,                                               \
1600         }
1601 
1602 #ifdef CONFIG_ARM64_PTR_AUTH
1603 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1604         {
1605                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1606                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1607         },
1608         {
1609                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1610                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1611         },
1612         {},
1613 };
1614 
1615 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1616         {
1617                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1618                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1619         },
1620         {
1621                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1622                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1623         },
1624         {},
1625 };
1626 #endif
1627 
1628 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1629         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1630         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1631         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1632         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1633         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1634         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1635         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1636         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1637         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1638         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1639         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1640         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1641         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1642         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1643         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1644         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1645         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1646         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1647         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1648         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1649         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1650         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1651         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1652         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1653         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1654         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1655         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1656         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1657         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1658 #ifdef CONFIG_ARM64_SVE
1659         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1660         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1661         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1662         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1663         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1664         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1665         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1666 #endif
1667         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1668 #ifdef CONFIG_ARM64_PTR_AUTH
1669         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1670         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1671 #endif
1672         {},
1673 };
1674 
1675 #ifdef CONFIG_COMPAT
1676 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1677 {
1678         /*
1679          * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1680          * in line with that of arm32 as in vfp_init(). We make sure that the
1681          * check is future proof, by making sure value is non-zero.
1682          */
1683         u32 mvfr1;
1684 
1685         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1686         if (scope == SCOPE_SYSTEM)
1687                 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1688         else
1689                 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1690 
1691         return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1692                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1693                 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1694 }
1695 #endif
1696 
1697 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1698 #ifdef CONFIG_COMPAT
1699         HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1700         HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1701         /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1702         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1703         HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1704         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1705         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1706         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1707         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1708         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1709 #endif
1710         {},
1711 };
1712 
1713 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1714 {
1715         switch (cap->hwcap_type) {
1716         case CAP_HWCAP:
1717                 cpu_set_feature(cap->hwcap);
1718                 break;
1719 #ifdef CONFIG_COMPAT
1720         case CAP_COMPAT_HWCAP:
1721                 compat_elf_hwcap |= (u32)cap->hwcap;
1722                 break;
1723         case CAP_COMPAT_HWCAP2:
1724                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1725                 break;
1726 #endif
1727         default:
1728                 WARN_ON(1);
1729                 break;
1730         }
1731 }
1732 
1733 /* Check if we have a particular HWCAP enabled */
1734 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1735 {
1736         bool rc;
1737 
1738         switch (cap->hwcap_type) {
1739         case CAP_HWCAP:
1740                 rc = cpu_have_feature(cap->hwcap);
1741                 break;
1742 #ifdef CONFIG_COMPAT
1743         case CAP_COMPAT_HWCAP:
1744                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1745                 break;
1746         case CAP_COMPAT_HWCAP2:
1747                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1748                 break;
1749 #endif
1750         default:
1751                 WARN_ON(1);
1752                 rc = false;
1753         }
1754 
1755         return rc;
1756 }
1757 
1758 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1759 {
1760         /* We support emulation of accesses to CPU ID feature registers */
1761         cpu_set_named_feature(CPUID);
1762         for (; hwcaps->matches; hwcaps++)
1763                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1764                         cap_set_elf_hwcap(hwcaps);
1765 }
1766 
1767 static void update_cpu_capabilities(u16 scope_mask)
1768 {
1769         int i;
1770         const struct arm64_cpu_capabilities *caps;
1771 
1772         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1773         for (i = 0; i < ARM64_NCAPS; i++) {
1774                 caps = cpu_hwcaps_ptrs[i];
1775                 if (!caps || !(caps->type & scope_mask) ||
1776                     cpus_have_cap(caps->capability) ||
1777                     !caps->matches(caps, cpucap_default_scope(caps)))
1778                         continue;
1779 
1780                 if (caps->desc)
1781                         pr_info("detected: %s\n", caps->desc);
1782                 cpus_set_cap(caps->capability);
1783 
1784                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1785                         set_bit(caps->capability, boot_capabilities);
1786         }
1787 }
1788 
1789 /*
1790  * Enable all the available capabilities on this CPU. The capabilities
1791  * with BOOT_CPU scope are handled separately and hence skipped here.
1792  */
1793 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1794 {
1795         int i;
1796         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1797 
1798         for_each_available_cap(i) {
1799                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1800 
1801                 if (WARN_ON(!cap))
1802                         continue;
1803 
1804                 if (!(cap->type & non_boot_scope))
1805                         continue;
1806 
1807                 if (cap->cpu_enable)
1808                         cap->cpu_enable(cap);
1809         }
1810         return 0;
1811 }
1812 
1813 /*
1814  * Run through the enabled capabilities and enable() it on all active
1815  * CPUs
1816  */
1817 static void __init enable_cpu_capabilities(u16 scope_mask)
1818 {
1819         int i;
1820         const struct arm64_cpu_capabilities *caps;
1821         bool boot_scope;
1822 
1823         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1824         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1825 
1826         for (i = 0; i < ARM64_NCAPS; i++) {
1827                 unsigned int num;
1828 
1829                 caps = cpu_hwcaps_ptrs[i];
1830                 if (!caps || !(caps->type & scope_mask))
1831                         continue;
1832                 num = caps->capability;
1833                 if (!cpus_have_cap(num))
1834                         continue;
1835 
1836                 /* Ensure cpus_have_const_cap(num) works */
1837                 static_branch_enable(&cpu_hwcap_keys[num]);
1838 
1839                 if (boot_scope && caps->cpu_enable)
1840                         /*
1841                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1842                          * before any secondary CPU boots. Thus, each secondary
1843                          * will enable the capability as appropriate via
1844                          * check_local_cpu_capabilities(). The only exception is
1845                          * the boot CPU, for which the capability must be
1846                          * enabled here. This approach avoids costly
1847                          * stop_machine() calls for this case.
1848                          */
1849                         caps->cpu_enable(caps);
1850         }
1851 
1852         /*
1853          * For all non-boot scope capabilities, use stop_machine()
1854          * as it schedules the work allowing us to modify PSTATE,
1855          * instead of on_each_cpu() which uses an IPI, giving us a
1856          * PSTATE that disappears when we return.
1857          */
1858         if (!boot_scope)
1859                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1860                              NULL, cpu_online_mask);
1861 }
1862 
1863 /*
1864  * Run through the list of capabilities to check for conflicts.
1865  * If the system has already detected a capability, take necessary
1866  * action on this CPU.
1867  *
1868  * Returns "false" on conflicts.
1869  */
1870 static bool verify_local_cpu_caps(u16 scope_mask)
1871 {
1872         int i;
1873         bool cpu_has_cap, system_has_cap;
1874         const struct arm64_cpu_capabilities *caps;
1875 
1876         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1877 
1878         for (i = 0; i < ARM64_NCAPS; i++) {
1879                 caps = cpu_hwcaps_ptrs[i];
1880                 if (!caps || !(caps->type & scope_mask))
1881                         continue;
1882 
1883                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1884                 system_has_cap = cpus_have_cap(caps->capability);
1885 
1886                 if (system_has_cap) {
1887                         /*
1888                          * Check if the new CPU misses an advertised feature,
1889                          * which is not safe to miss.
1890                          */
1891                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1892                                 break;
1893                         /*
1894                          * We have to issue cpu_enable() irrespective of
1895                          * whether the CPU has it or not, as it is enabeld
1896                          * system wide. It is upto the call back to take
1897                          * appropriate action on this CPU.
1898                          */
1899                         if (caps->cpu_enable)
1900                                 caps->cpu_enable(caps);
1901                 } else {
1902                         /*
1903                          * Check if the CPU has this capability if it isn't
1904                          * safe to have when the system doesn't.
1905                          */
1906                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1907                                 break;
1908                 }
1909         }
1910 
1911         if (i < ARM64_NCAPS) {
1912                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1913                         smp_processor_id(), caps->capability,
1914                         caps->desc, system_has_cap, cpu_has_cap);
1915                 return false;
1916         }
1917 
1918         return true;
1919 }
1920 
1921 /*
1922  * Check for CPU features that are used in early boot
1923  * based on the Boot CPU value.
1924  */
1925 static void check_early_cpu_features(void)
1926 {
1927         verify_cpu_asid_bits();
1928         /*
1929          * Early features are used by the kernel already. If there
1930          * is a conflict, we cannot proceed further.
1931          */
1932         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1933                 cpu_panic_kernel();
1934 }
1935 
1936 static void
1937 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1938 {
1939 
1940         for (; caps->matches; caps++)
1941                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1942                         pr_crit("CPU%d: missing HWCAP: %s\n",
1943                                         smp_processor_id(), caps->desc);
1944                         cpu_die_early();
1945                 }
1946 }
1947 
1948 static void verify_sve_features(void)
1949 {
1950         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1951         u64 zcr = read_zcr_features();
1952 
1953         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1954         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1955 
1956         if (len < safe_len || sve_verify_vq_map()) {
1957                 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1958                         smp_processor_id());
1959                 cpu_die_early();
1960         }
1961 
1962         /* Add checks on other ZCR bits here if necessary */
1963 }
1964 
1965 
1966 /*
1967  * Run through the enabled system capabilities and enable() it on this CPU.
1968  * The capabilities were decided based on the available CPUs at the boot time.
1969  * Any new CPU should match the system wide status of the capability. If the
1970  * new CPU doesn't have a capability which the system now has enabled, we
1971  * cannot do anything to fix it up and could cause unexpected failures. So
1972  * we park the CPU.
1973  */
1974 static void verify_local_cpu_capabilities(void)
1975 {
1976         /*
1977          * The capabilities with SCOPE_BOOT_CPU are checked from
1978          * check_early_cpu_features(), as they need to be verified
1979          * on all secondary CPUs.
1980          */
1981         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1982                 cpu_die_early();
1983 
1984         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1985 
1986         if (system_supports_32bit_el0())
1987                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1988 
1989         if (system_supports_sve())
1990                 verify_sve_features();
1991 }
1992 
1993 void check_local_cpu_capabilities(void)
1994 {
1995         /*
1996          * All secondary CPUs should conform to the early CPU features
1997          * in use by the kernel based on boot CPU.
1998          */
1999         check_early_cpu_features();
2000 
2001         /*
2002          * If we haven't finalised the system capabilities, this CPU gets
2003          * a chance to update the errata work arounds and local features.
2004          * Otherwise, this CPU should verify that it has all the system
2005          * advertised capabilities.
2006          */
2007         if (!sys_caps_initialised)
2008                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2009         else
2010                 verify_local_cpu_capabilities();
2011 }
2012 
2013 static void __init setup_boot_cpu_capabilities(void)
2014 {
2015         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2016         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2017         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2018         enable_cpu_capabilities(SCOPE_BOOT_CPU);
2019 }
2020 
2021 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
2022 EXPORT_SYMBOL(arm64_const_caps_ready);
2023 
2024 static void __init mark_const_caps_ready(void)
2025 {
2026         static_branch_enable(&arm64_const_caps_ready);
2027 }
2028 
2029 bool this_cpu_has_cap(unsigned int n)
2030 {
2031         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2032                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2033 
2034                 if (cap)
2035                         return cap->matches(cap, SCOPE_LOCAL_CPU);
2036         }
2037 
2038         return false;
2039 }
2040 
2041 void cpu_set_feature(unsigned int num)
2042 {
2043         WARN_ON(num >= MAX_CPU_FEATURES);
2044         elf_hwcap |= BIT(num);
2045 }
2046 EXPORT_SYMBOL_GPL(cpu_set_feature);
2047 
2048 bool cpu_have_feature(unsigned int num)
2049 {
2050         WARN_ON(num >= MAX_CPU_FEATURES);
2051         return elf_hwcap & BIT(num);
2052 }
2053 EXPORT_SYMBOL_GPL(cpu_have_feature);
2054 
2055 unsigned long cpu_get_elf_hwcap(void)
2056 {
2057         /*
2058          * We currently only populate the first 32 bits of AT_HWCAP. Please
2059          * note that for userspace compatibility we guarantee that bits 62
2060          * and 63 will always be returned as 0.
2061          */
2062         return lower_32_bits(elf_hwcap);
2063 }
2064 
2065 unsigned long cpu_get_elf_hwcap2(void)
2066 {
2067         return upper_32_bits(elf_hwcap);
2068 }
2069 
2070 static void __init setup_system_capabilities(void)
2071 {
2072         /*
2073          * We have finalised the system-wide safe feature
2074          * registers, finalise the capabilities that depend
2075          * on it. Also enable all the available capabilities,
2076          * that are not enabled already.
2077          */
2078         update_cpu_capabilities(SCOPE_SYSTEM);
2079         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2080 }
2081 
2082 void __init setup_cpu_features(void)
2083 {
2084         u32 cwg;
2085 
2086         setup_system_capabilities();
2087         mark_const_caps_ready();
2088         setup_elf_hwcaps(arm64_elf_hwcaps);
2089 
2090         if (system_supports_32bit_el0())
2091                 setup_elf_hwcaps(compat_elf_hwcaps);
2092 
2093         if (system_uses_ttbr0_pan())
2094                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2095 
2096         sve_setup();
2097         minsigstksz_setup();
2098 
2099         /* Advertise that we have computed the system capabilities */
2100         set_sys_caps_initialised();
2101 
2102         /*
2103          * Check for sane CTR_EL0.CWG value.
2104          */
2105         cwg = cache_type_cwg();
2106         if (!cwg)
2107                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2108                         ARCH_DMA_MINALIGN);
2109 }
2110 
2111 static bool __maybe_unused
2112 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2113 {
2114         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2115 }
2116 
2117 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2118 {
2119         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2120 }
2121 
2122 /*
2123  * We emulate only the following system register space.
2124  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2125  * See Table C5-6 System instruction encodings for System register accesses,
2126  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2127  */
2128 static inline bool __attribute_const__ is_emulated(u32 id)
2129 {
2130         return (sys_reg_Op0(id) == 0x3 &&
2131                 sys_reg_CRn(id) == 0x0 &&
2132                 sys_reg_Op1(id) == 0x0 &&
2133                 (sys_reg_CRm(id) == 0 ||
2134                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2135 }
2136 
2137 /*
2138  * With CRm == 0, reg should be one of :
2139  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2140  */
2141 static inline int emulate_id_reg(u32 id, u64 *valp)
2142 {
2143         switch (id) {
2144         case SYS_MIDR_EL1:
2145                 *valp = read_cpuid_id();
2146                 break;
2147         case SYS_MPIDR_EL1:
2148                 *valp = SYS_MPIDR_SAFE_VAL;
2149                 break;
2150         case SYS_REVIDR_EL1:
2151                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2152                 *valp = 0;
2153                 break;
2154         default:
2155                 return -EINVAL;
2156         }
2157 
2158         return 0;
2159 }
2160 
2161 static int emulate_sys_reg(u32 id, u64 *valp)
2162 {
2163         struct arm64_ftr_reg *regp;
2164 
2165         if (!is_emulated(id))
2166                 return -EINVAL;
2167 
2168         if (sys_reg_CRm(id) == 0)
2169                 return emulate_id_reg(id, valp);
2170 
2171         regp = get_arm64_ftr_reg(id);
2172         if (regp)
2173                 *valp = arm64_ftr_reg_user_value(regp);
2174         else
2175                 /*
2176                  * The untracked registers are either IMPLEMENTATION DEFINED
2177                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2178                  */
2179                 *valp = 0;
2180         return 0;
2181 }
2182 
2183 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2184 {
2185         int rc;
2186         u64 val;
2187 
2188         rc = emulate_sys_reg(sys_reg, &val);
2189         if (!rc) {
2190                 pt_regs_write_reg(regs, rt, val);
2191                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2192         }
2193         return rc;
2194 }
2195 
2196 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2197 {
2198         u32 sys_reg, rt;
2199 
2200         /*
2201          * sys_reg values are defined as used in mrs/msr instruction.
2202          * shift the imm value to get the encoding.
2203          */
2204         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2205         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2206         return do_emulate_mrs(regs, sys_reg, rt);
2207 }
2208 
2209 static struct undef_hook mrs_hook = {
2210         .instr_mask = 0xfff00000,
2211         .instr_val  = 0xd5300000,
2212         .pstate_mask = PSR_AA32_MODE_MASK,
2213         .pstate_val = PSR_MODE_EL0t,
2214         .fn = emulate_mrs,
2215 };
2216 
2217 static int __init enable_mrs_emulation(void)
2218 {
2219         register_undef_hook(&mrs_hook);
2220         return 0;
2221 }
2222 
2223 core_initcall(enable_mrs_emulation);
2224 
2225 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2226                           char *buf)
2227 {
2228         if (__meltdown_safe)
2229                 return sprintf(buf, "Not affected\n");
2230 
2231         if (arm64_kernel_unmapped_at_el0())
2232                 return sprintf(buf, "Mitigation: PTI\n");
2233 
2234         return sprintf(buf, "Vulnerable\n");
2235 }
/* [<][>][^][v][top][bottom][index][help] */
root/arch/arm64/kernel/cpufeature.c

DEFINITIONS
