root/drivers/gpu/drm/nouveau/dispnv50/base507c.c

DEFINITIONS

1. base507c_update
2. base507c_image_clr
3. base507c_image_set
4. base507c_xlut_clr
5. base507c_xlut_set
6. base507c_ntfy_wait_begun
7. base507c_ntfy_clr
8. base507c_ntfy_set
9. base507c_ntfy_reset
10. base507c_sema_clr
11. base507c_sema_set
12. base507c_release
13. base507c_acquire
14. base507c_new_
15. base507c_new

   1 /*
   2  * Copyright 2018 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "base.h"
  23 
  24 #include <nvif/cl507c.h>
  25 #include <nvif/event.h>
  26 
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_fourcc.h>
  29 #include <drm/drm_plane_helper.h>
  30 
  31 #include "nouveau_bo.h"
  32 
  33 void
  34 base507c_update(struct nv50_wndw *wndw, u32 *interlock)
  35 {
  36         u32 *push;
  37         if ((push = evo_wait(&wndw->wndw, 2))) {
  38                 evo_mthd(push, 0x0080, 1);
  39                 evo_data(push, interlock[NV50_DISP_INTERLOCK_CORE]);
  40                 evo_kick(push, &wndw->wndw);
  41         }
  42 }
  43 
  44 void
  45 base507c_image_clr(struct nv50_wndw *wndw)
  46 {
  47         u32 *push;
  48         if ((push = evo_wait(&wndw->wndw, 4))) {
  49                 evo_mthd(push, 0x0084, 1);
  50                 evo_data(push, 0x00000000);
  51                 evo_mthd(push, 0x00c0, 1);
  52                 evo_data(push, 0x00000000);
  53                 evo_kick(push, &wndw->wndw);
  54         }
  55 }
  56 
  57 static void
  58 base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
  59 {
  60         u32 *push;
  61         if ((push = evo_wait(&wndw->wndw, 13))) {
  62                 evo_mthd(push, 0x0084, 1);
  63                 evo_data(push, asyw->image.mode << 8 |
  64                                asyw->image.interval << 4);
  65                 evo_mthd(push, 0x00c0, 1);
  66                 evo_data(push, asyw->image.handle[0]);
  67                 if (asyw->image.format == 0xca) {
  68                         evo_mthd(push, 0x0110, 2);
  69                         evo_data(push, 1);
  70                         evo_data(push, 0x6400);
  71                 } else {
  72                         evo_mthd(push, 0x0110, 2);
  73                         evo_data(push, 0);
  74                         evo_data(push, 0);
  75                 }
  76                 evo_mthd(push, 0x0800, 5);
  77                 evo_data(push, asyw->image.offset[0] >> 8);
  78                 evo_data(push, 0x00000000);
  79                 evo_data(push, asyw->image.h << 16 | asyw->image.w);
  80                 evo_data(push, asyw->image.layout << 20 |
  81                                (asyw->image.pitch[0] >> 8) << 8 |
  82                                asyw->image.blocks[0] << 8 |
  83                                asyw->image.blockh);
  84                 evo_data(push, asyw->image.kind << 16 |
  85                                asyw->image.format << 8);
  86                 evo_kick(push, &wndw->wndw);
  87         }
  88 }
  89 
  90 void
  91 base507c_xlut_clr(struct nv50_wndw *wndw)
  92 {
  93         u32 *push;
  94         if ((push = evo_wait(&wndw->wndw, 2))) {
  95                 evo_mthd(push, 0x00e0, 1);
  96                 evo_data(push, 0x00000000);
  97                 evo_kick(push, &wndw->wndw);
  98         }
  99 }
 100 
 101 void
 102 base507c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 103 {
 104         u32 *push;
 105         if ((push = evo_wait(&wndw->wndw, 2))) {
 106                 evo_mthd(push, 0x00e0, 1);
 107                 evo_data(push, 0x40000000);
 108                 evo_kick(push, &wndw->wndw);
 109         }
 110 }
 111 
 112 int
 113 base507c_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset,
 114                          struct nvif_device *device)
 115 {
 116         s64 time = nvif_msec(device, 2000ULL,
 117                 u32 data = nouveau_bo_rd32(bo, offset / 4);
 118                 if ((data & 0xc0000000) == 0x40000000)
 119                         break;
 120                 usleep_range(1, 2);
 121         );
 122         return time < 0 ? time : 0;
 123 }
 124 
 125 void
 126 base507c_ntfy_clr(struct nv50_wndw *wndw)
 127 {
 128         u32 *push;
 129         if ((push = evo_wait(&wndw->wndw, 2))) {
 130                 evo_mthd(push, 0x00a4, 1);
 131                 evo_data(push, 0x00000000);
 132                 evo_kick(push, &wndw->wndw);
 133         }
 134 }
 135 
 136 void
 137 base507c_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 138 {
 139         u32 *push;
 140         if ((push = evo_wait(&wndw->wndw, 3))) {
 141                 evo_mthd(push, 0x00a0, 2);
 142                 evo_data(push, asyw->ntfy.awaken << 30 | asyw->ntfy.offset);
 143                 evo_data(push, asyw->ntfy.handle);
 144                 evo_kick(push, &wndw->wndw);
 145         }
 146 }
 147 
 148 void
 149 base507c_ntfy_reset(struct nouveau_bo *bo, u32 offset)
 150 {
 151         nouveau_bo_wr32(bo, offset / 4, 0x00000000);
 152 }
 153 
 154 void
 155 base507c_sema_clr(struct nv50_wndw *wndw)
 156 {
 157         u32 *push;
 158         if ((push = evo_wait(&wndw->wndw, 2))) {
 159                 evo_mthd(push, 0x0094, 1);
 160                 evo_data(push, 0x00000000);
 161                 evo_kick(push, &wndw->wndw);
 162         }
 163 }
 164 
 165 void
 166 base507c_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 167 {
 168         u32 *push;
 169         if ((push = evo_wait(&wndw->wndw, 5))) {
 170                 evo_mthd(push, 0x0088, 4);
 171                 evo_data(push, asyw->sema.offset);
 172                 evo_data(push, asyw->sema.acquire);
 173                 evo_data(push, asyw->sema.release);
 174                 evo_data(push, asyw->sema.handle);
 175                 evo_kick(push, &wndw->wndw);
 176         }
 177 }
 178 
 179 void
 180 base507c_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
 181                  struct nv50_head_atom *asyh)
 182 {
 183         asyh->base.cpp = 0;
 184 }
 185 
 186 int
 187 base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
 188                  struct nv50_head_atom *asyh)
 189 {
 190         const struct drm_framebuffer *fb = asyw->state.fb;
 191         int ret;
 192 
 193         ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
 194                                                   DRM_PLANE_HELPER_NO_SCALING,
 195                                                   DRM_PLANE_HELPER_NO_SCALING,
 196                                                   false, true);
 197         if (ret)
 198                 return ret;
 199 
 200         if (!wndw->func->ilut) {
 201                 if ((asyh->base.cpp != 1) ^ (fb->format->cpp[0] != 1))
 202                         asyh->state.color_mgmt_changed = true;
 203         }
 204 
 205         asyh->base.depth = fb->format->depth;
 206         asyh->base.cpp = fb->format->cpp[0];
 207         asyh->base.x = asyw->state.src.x1 >> 16;
 208         asyh->base.y = asyw->state.src.y1 >> 16;
 209         asyh->base.w = asyw->state.fb->width;
 210         asyh->base.h = asyw->state.fb->height;
 211 
 212         /* Some newer formats, esp FP16 ones, don't have a
 213          * "depth". There's nothing that really makes sense there
 214          * either, so just set it to the implicit bit count.
 215          */
 216         if (!asyh->base.depth)
 217                 asyh->base.depth = asyh->base.cpp * 8;
 218 
 219         return 0;
 220 }
 221 
 222 const u32
 223 base507c_format[] = {
 224         DRM_FORMAT_C8,
 225         DRM_FORMAT_RGB565,
 226         DRM_FORMAT_XRGB1555,
 227         DRM_FORMAT_ARGB1555,
 228         DRM_FORMAT_XRGB8888,
 229         DRM_FORMAT_ARGB8888,
 230         DRM_FORMAT_XBGR2101010,
 231         DRM_FORMAT_ABGR2101010,
 232         DRM_FORMAT_XBGR8888,
 233         DRM_FORMAT_ABGR8888,
 234         DRM_FORMAT_XBGR16161616F,
 235         DRM_FORMAT_ABGR16161616F,
 236         0
 237 };
 238 
 239 static const struct nv50_wndw_func
 240 base507c = {
 241         .acquire = base507c_acquire,
 242         .release = base507c_release,
 243         .sema_set = base507c_sema_set,
 244         .sema_clr = base507c_sema_clr,
 245         .ntfy_reset = base507c_ntfy_reset,
 246         .ntfy_set = base507c_ntfy_set,
 247         .ntfy_clr = base507c_ntfy_clr,
 248         .ntfy_wait_begun = base507c_ntfy_wait_begun,
 249         .olut_core = 1,
 250         .xlut_set = base507c_xlut_set,
 251         .xlut_clr = base507c_xlut_clr,
 252         .image_set = base507c_image_set,
 253         .image_clr = base507c_image_clr,
 254         .update = base507c_update,
 255 };
 256 
 257 int
 258 base507c_new_(const struct nv50_wndw_func *func, const u32 *format,
 259               struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data,
 260               struct nv50_wndw **pwndw)
 261 {
 262         struct nv50_disp_base_channel_dma_v0 args = {
 263                 .head = head,
 264         };
 265         struct nv50_disp *disp = nv50_disp(drm->dev);
 266         struct nv50_wndw *wndw;
 267         int ret;
 268 
 269         ret = nv50_wndw_new_(func, drm->dev, DRM_PLANE_TYPE_PRIMARY,
 270                              "base", head, format, BIT(head),
 271                              NV50_DISP_INTERLOCK_BASE, interlock_data, &wndw);
 272         if (*pwndw = wndw, ret)
 273                 return ret;
 274 
 275         ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,
 276                                &oclass, head, &args, sizeof(args),
 277                                disp->sync->bo.offset, &wndw->wndw);
 278         if (ret) {
 279                 NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret);
 280                 return ret;
 281         }
 282 
 283         ret = nvif_notify_init(&wndw->wndw.base.user, wndw->notify.func,
 284                                false, NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
 285                                &(struct nvif_notify_uevent_req) {},
 286                                sizeof(struct nvif_notify_uevent_req),
 287                                sizeof(struct nvif_notify_uevent_rep),
 288                                &wndw->notify);
 289         if (ret)
 290                 return ret;
 291 
 292         wndw->ntfy = NV50_DISP_BASE_NTFY(wndw->id);
 293         wndw->sema = NV50_DISP_BASE_SEM0(wndw->id);
 294         wndw->data = 0x00000000;
 295         return 0;
 296 }
 297 
 298 int
 299 base507c_new(struct nouveau_drm *drm, int head, s32 oclass,
 300              struct nv50_wndw **pwndw)
 301 {
 302         return base507c_new_(&base507c, base507c_format, drm, head, oclass,
 303                              0x00000002 << (head * 8), pwndw);
 304 }