root/drivers/gpu/drm/i915/gt/intel_gt_types.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5 
   6 #ifndef __INTEL_GT_TYPES__
   7 #define __INTEL_GT_TYPES__
   8 
   9 #include <linux/ktime.h>
  10 #include <linux/list.h>
  11 #include <linux/mutex.h>
  12 #include <linux/notifier.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/types.h>
  15 
  16 #include "uc/intel_uc.h"
  17 
  18 #include "i915_vma.h"
  19 #include "intel_engine_types.h"
  20 #include "intel_reset_types.h"
  21 #include "intel_wakeref.h"
  22 
  23 struct drm_i915_private;
  24 struct i915_ggtt;
  25 struct intel_engine_cs;
  26 struct intel_uncore;
  27 
  28 struct intel_hangcheck {
  29         /* For hangcheck timer */
  30 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  31 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  32 
  33         struct delayed_work work;
  34 };
  35 
  36 struct intel_gt {
  37         struct drm_i915_private *i915;
  38         struct intel_uncore *uncore;
  39         struct i915_ggtt *ggtt;
  40 
  41         struct intel_uc uc;
  42 
  43         struct intel_gt_timelines {
  44                 spinlock_t lock; /* protects active_list */
  45                 struct list_head active_list;
  46 
  47                 /* Pack multiple timelines' seqnos into the same page */
  48                 spinlock_t hwsp_lock;
  49                 struct list_head hwsp_free_list;
  50         } timelines;
  51 
  52         struct intel_wakeref wakeref;
  53 
  54         struct list_head closed_vma;
  55         spinlock_t closed_lock; /* guards the list of closed_vma */
  56 
  57         struct intel_hangcheck hangcheck;
  58         struct intel_reset reset;
  59 
  60         /**
  61          * Is the GPU currently considered idle, or busy executing
  62          * userspace requests? Whilst idle, we allow runtime power
  63          * management to power down the hardware and display clocks.
  64          * In order to reduce the effect on performance, there
  65          * is a slight delay before we do so.
  66          */
  67         intel_wakeref_t awake;
  68 
  69         struct blocking_notifier_head pm_notifications;
  70 
  71         ktime_t last_init_time;
  72 
  73         struct i915_vma *scratch;
  74 
  75         spinlock_t irq_lock;
  76         u32 gt_imr;
  77         u32 pm_ier;
  78         u32 pm_imr;
  79 
  80         u32 pm_guc_events;
  81 
  82         struct intel_engine_cs *engine[I915_NUM_ENGINES];
  83         struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
  84                                             [MAX_ENGINE_INSTANCE + 1];
  85 };
  86 
  87 enum intel_gt_scratch_field {
  88         /* 8 bytes */
  89         INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
  90 
  91         /* 8 bytes */
  92         INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA = 128,
  93 
  94         /* 8 bytes */
  95         INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,
  96 
  97         /* 8 bytes */
  98         INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
  99 
 100 };
 101 
 102 #endif /* __INTEL_GT_TYPES_H__ */