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6 #ifndef _INTEL_GUC_REG_H_
7 #define _INTEL_GUC_REG_H_
8
9 #include <linux/compiler.h>
10 #include <linux/types.h>
11
12 #include "i915_reg.h"
13
14
15
16 #define GUC_STATUS _MMIO(0xc000)
17 #define GS_RESET_SHIFT 0
18 #define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT)
19 #define GS_BOOTROM_SHIFT 1
20 #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
21 #define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
22 #define GS_BOOTROM_JUMP_PASSED (0x76 << GS_BOOTROM_SHIFT)
23 #define GS_UKERNEL_SHIFT 8
24 #define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
25 #define GS_UKERNEL_LAPIC_DONE (0x30 << GS_UKERNEL_SHIFT)
26 #define GS_UKERNEL_DPC_ERROR (0x60 << GS_UKERNEL_SHIFT)
27 #define GS_UKERNEL_EXCEPTION (0x70 << GS_UKERNEL_SHIFT)
28 #define GS_UKERNEL_READY (0xF0 << GS_UKERNEL_SHIFT)
29 #define GS_MIA_SHIFT 16
30 #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
31 #define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT)
32 #define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT)
33 #define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT)
34 #define GS_AUTH_STATUS_SHIFT 30
35 #define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT)
36 #define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT)
37 #define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT)
38
39 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
40 #define SOFT_SCRATCH_COUNT 16
41
42 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
43 #define GEN11_SOFT_SCRATCH_COUNT 4
44
45 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
46 #define UOS_RSA_SCRATCH_COUNT 64
47
48 #define DMA_ADDR_0_LOW _MMIO(0xc300)
49 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
50 #define DMA_ADDR_1_LOW _MMIO(0xc308)
51 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
52 #define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
53 #define DMA_ADDRESS_SPACE_GTT (8 << 16)
54 #define DMA_COPY_SIZE _MMIO(0xc310)
55 #define DMA_CTRL _MMIO(0xc314)
56 #define HUC_UKERNEL (1<<9)
57 #define UOS_MOVE (1<<4)
58 #define START_DMA (1<<0)
59 #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
60 #define GUC_WOPCM_OFFSET_VALID (1<<0)
61 #define HUC_LOADING_AGENT_VCR (0<<1)
62 #define HUC_LOADING_AGENT_GUC (1<<1)
63 #define GUC_WOPCM_OFFSET_SHIFT 14
64 #define GUC_WOPCM_OFFSET_MASK (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
65 #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
66
67 #define HUC_STATUS2 _MMIO(0xD3B0)
68 #define HUC_FW_VERIFIED (1<<7)
69
70 #define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
71 #define HUC_LOAD_SUCCESSFUL (1 << 0)
72
73 #define GUC_WOPCM_SIZE _MMIO(0xc050)
74 #define GUC_WOPCM_SIZE_LOCKED (1<<0)
75 #define GUC_WOPCM_SIZE_SHIFT 12
76 #define GUC_WOPCM_SIZE_MASK (0xfffff << GUC_WOPCM_SIZE_SHIFT)
77
78 #define GEN8_GT_PM_CONFIG _MMIO(0x138140)
79 #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
80 #define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
81 #define GT_DOORBELL_ENABLE (1<<0)
82
83 #define GEN8_GTCR _MMIO(0x4274)
84 #define GEN8_GTCR_INVALIDATE (1<<0)
85
86 #define GUC_ARAT_C6DIS _MMIO(0xA178)
87
88 #define GUC_SHIM_CONTROL _MMIO(0xc064)
89 #define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
90 #define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
91 #define GUC_ENABLE_MIA_CACHING (1<<2)
92 #define GUC_GEN10_MSGCH_ENABLE (1<<4)
93 #define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9)
94 #define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
95 #define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
96 #define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
97
98 #define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
99 #define GUC_SEND_TRIGGER (1<<0)
100 #define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
101
102 #define GUC_NUM_DOORBELLS 256
103
104
105 struct guc_doorbell_info {
106 u32 db_status;
107 #define GUC_DOORBELL_DISABLED 0
108 #define GUC_DOORBELL_ENABLED 1
109
110 u32 cookie;
111 u32 reserved[14];
112 } __packed;
113
114 #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
115 #define GEN8_DRB_VALID (1<<0)
116 #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
117
118 #define DE_GUCRMR _MMIO(0x44054)
119
120 #define GUC_BCS_RCS_IER _MMIO(0xC550)
121 #define GUC_VCS2_VCS1_IER _MMIO(0xC554)
122 #define GUC_WD_VECS_IER _MMIO(0xC558)
123 #define GUC_PM_P24C_IER _MMIO(0xC55C)
124
125
126 #define GUC_INTR_GUC2HOST BIT(15)
127 #define GUC_INTR_EXEC_ERROR BIT(14)
128 #define GUC_INTR_DISPLAY_EVENT BIT(13)
129 #define GUC_INTR_SEM_SIG BIT(12)
130 #define GUC_INTR_IOMMU2GUC BIT(11)
131 #define GUC_INTR_DOORBELL_RANG BIT(10)
132 #define GUC_INTR_DMA_DONE BIT(9)
133 #define GUC_INTR_FATAL_ERROR BIT(8)
134 #define GUC_INTR_NOTIF_ERROR BIT(7)
135 #define GUC_INTR_SW_INT_6 BIT(6)
136 #define GUC_INTR_SW_INT_5 BIT(5)
137 #define GUC_INTR_SW_INT_4 BIT(4)
138 #define GUC_INTR_SW_INT_3 BIT(3)
139 #define GUC_INTR_SW_INT_2 BIT(2)
140 #define GUC_INTR_SW_INT_1 BIT(1)
141 #define GUC_INTR_SW_INT_0 BIT(0)
142
143 #endif