drivers/gpu/drm/i915/gt/intel_gpu

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   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright � 2003-2018 Intel Corporation
   5  */
   6 
   7 #ifndef _INTEL_GPU_COMMANDS_H_
   8 #define _INTEL_GPU_COMMANDS_H_
   9 
  10 /*
  11  * Target address alignments required for GPU access e.g.
  12  * MI_STORE_DWORD_IMM.
  13  */
  14 #define alignof_dword 4
  15 #define alignof_qword 8
  16 
  17 /*
  18  * Instruction field definitions used by the command parser
  19  */
  20 #define INSTR_CLIENT_SHIFT      29
  21 #define   INSTR_MI_CLIENT       0x0
  22 #define   INSTR_BC_CLIENT       0x2
  23 #define   INSTR_RC_CLIENT       0x3
  24 #define INSTR_SUBCLIENT_SHIFT   27
  25 #define INSTR_SUBCLIENT_MASK    0x18000000
  26 #define   INSTR_MEDIA_SUBCLIENT 0x2
  27 #define INSTR_26_TO_24_MASK     0x7000000
  28 #define   INSTR_26_TO_24_SHIFT  24
  29 
  30 /*
  31  * Memory interface instructions used by the kernel
  32  */
  33 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
  34 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
  35 #define  MI_GLOBAL_GTT    (1<<22)
  36 
  37 #define MI_NOOP                 MI_INSTR(0, 0)
  38 #define MI_USER_INTERRUPT       MI_INSTR(0x02, 0)
  39 #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
  40 #define   MI_WAIT_FOR_OVERLAY_FLIP      (1<<16)
  41 #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
  42 #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
  43 #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  44 #define MI_FLUSH                MI_INSTR(0x04, 0)
  45 #define   MI_READ_FLUSH         (1 << 0)
  46 #define   MI_EXE_FLUSH          (1 << 1)
  47 #define   MI_NO_WRITE_FLUSH     (1 << 2)
  48 #define   MI_SCENE_COUNT        (1 << 3) /* just increment scene count */
  49 #define   MI_END_SCENE          (1 << 4) /* flush binner and incr scene count */
  50 #define   MI_INVALIDATE_ISP     (1 << 5) /* invalidate indirect state pointers */
  51 #define MI_REPORT_HEAD          MI_INSTR(0x07, 0)
  52 #define MI_ARB_ON_OFF           MI_INSTR(0x08, 0)
  53 #define   MI_ARB_ENABLE                 (1<<0)
  54 #define   MI_ARB_DISABLE                (0<<0)
  55 #define MI_BATCH_BUFFER_END     MI_INSTR(0x0a, 0)
  56 #define MI_SUSPEND_FLUSH        MI_INSTR(0x0b, 0)
  57 #define   MI_SUSPEND_FLUSH_EN   (1<<0)
  58 #define MI_SET_APPID            MI_INSTR(0x0e, 0)
  59 #define MI_OVERLAY_FLIP         MI_INSTR(0x11, 0)
  60 #define   MI_OVERLAY_CONTINUE   (0x0<<21)
  61 #define   MI_OVERLAY_ON         (0x1<<21)
  62 #define   MI_OVERLAY_OFF        (0x2<<21)
  63 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
  64 #define MI_DISPLAY_FLIP         MI_INSTR(0x14, 2)
  65 #define MI_DISPLAY_FLIP_I915    MI_INSTR(0x14, 1)
  66 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
  67 /* IVB has funny definitions for which plane to flip. */
  68 #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
  69 #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
  70 #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
  71 #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
  72 #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
  73 #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
  74 /* SKL ones */
  75 #define   MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
  76 #define   MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
  77 #define   MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
  78 #define   MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
  79 #define   MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
  80 #define   MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
  81 #define   MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
  82 #define   MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
  83 #define   MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
  84 #define MI_SEMAPHORE_MBOX       MI_INSTR(0x16, 1) /* gen6, gen7 */
  85 #define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
  86 #define   MI_SEMAPHORE_UPDATE       (1<<21)
  87 #define   MI_SEMAPHORE_COMPARE      (1<<20)
  88 #define   MI_SEMAPHORE_REGISTER     (1<<18)
  89 #define   MI_SEMAPHORE_SYNC_VR      (0<<16) /* RCS  wait for VCS  (RVSYNC) */
  90 #define   MI_SEMAPHORE_SYNC_VER     (1<<16) /* RCS  wait for VECS (RVESYNC) */
  91 #define   MI_SEMAPHORE_SYNC_BR      (2<<16) /* RCS  wait for BCS  (RBSYNC) */
  92 #define   MI_SEMAPHORE_SYNC_BV      (0<<16) /* VCS  wait for BCS  (VBSYNC) */
  93 #define   MI_SEMAPHORE_SYNC_VEV     (1<<16) /* VCS  wait for VECS (VVESYNC) */
  94 #define   MI_SEMAPHORE_SYNC_RV      (2<<16) /* VCS  wait for RCS  (VRSYNC) */
  95 #define   MI_SEMAPHORE_SYNC_RB      (0<<16) /* BCS  wait for RCS  (BRSYNC) */
  96 #define   MI_SEMAPHORE_SYNC_VEB     (1<<16) /* BCS  wait for VECS (BVESYNC) */
  97 #define   MI_SEMAPHORE_SYNC_VB      (2<<16) /* BCS  wait for VCS  (BVSYNC) */
  98 #define   MI_SEMAPHORE_SYNC_BVE     (0<<16) /* VECS wait for BCS  (VEBSYNC) */
  99 #define   MI_SEMAPHORE_SYNC_VVE     (1<<16) /* VECS wait for VCS  (VEVSYNC) */
 100 #define   MI_SEMAPHORE_SYNC_RVE     (2<<16) /* VECS wait for RCS  (VERSYNC) */
 101 #define   MI_SEMAPHORE_SYNC_INVALID (3<<16)
 102 #define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
 103 #define MI_SET_CONTEXT          MI_INSTR(0x18, 0)
 104 #define   MI_MM_SPACE_GTT               (1<<8)
 105 #define   MI_MM_SPACE_PHYSICAL          (0<<8)
 106 #define   MI_SAVE_EXT_STATE_EN          (1<<3)
 107 #define   MI_RESTORE_EXT_STATE_EN       (1<<2)
 108 #define   MI_FORCE_RESTORE              (1<<1)
 109 #define   MI_RESTORE_INHIBIT            (1<<0)
 110 #define   HSW_MI_RS_SAVE_STATE_EN       (1<<3)
 111 #define   HSW_MI_RS_RESTORE_STATE_EN    (1<<2)
 112 #define MI_SEMAPHORE_SIGNAL     MI_INSTR(0x1b, 0) /* GEN8+ */
 113 #define   MI_SEMAPHORE_TARGET(engine)   ((engine)<<15)
 114 #define MI_SEMAPHORE_WAIT       MI_INSTR(0x1c, 2) /* GEN8+ */
 115 #define   MI_SEMAPHORE_POLL             (1 << 15)
 116 #define   MI_SEMAPHORE_SAD_GT_SDD       (0 << 12)
 117 #define   MI_SEMAPHORE_SAD_GTE_SDD      (1 << 12)
 118 #define   MI_SEMAPHORE_SAD_LT_SDD       (2 << 12)
 119 #define   MI_SEMAPHORE_SAD_LTE_SDD      (3 << 12)
 120 #define   MI_SEMAPHORE_SAD_EQ_SDD       (4 << 12)
 121 #define   MI_SEMAPHORE_SAD_NEQ_SDD      (5 << 12)
 122 #define MI_STORE_DWORD_IMM      MI_INSTR(0x20, 1)
 123 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
 124 #define   MI_MEM_VIRTUAL        (1 << 22) /* 945,g33,965 */
 125 #define   MI_USE_GGTT           (1 << 22) /* g4x+ */
 126 #define MI_STORE_DWORD_INDEX    MI_INSTR(0x21, 1)
 127 /*
 128  * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
 129  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
 130  *   simply ignores the register load under certain conditions.
 131  * - One can actually load arbitrary many arbitrary registers: Simply issue x
 132  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
 133  */
 134 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
 135 #define   MI_LRI_FORCE_POSTED           (1<<12)
 136 #define MI_STORE_REGISTER_MEM        MI_INSTR(0x24, 1)
 137 #define MI_STORE_REGISTER_MEM_GEN8   MI_INSTR(0x24, 2)
 138 #define   MI_SRM_LRM_GLOBAL_GTT         (1<<22)
 139 #define MI_FLUSH_DW             MI_INSTR(0x26, 1) /* for GEN6 */
 140 #define   MI_FLUSH_DW_STORE_INDEX       (1<<21)
 141 #define   MI_INVALIDATE_TLB             (1<<18)
 142 #define   MI_FLUSH_DW_OP_STOREDW        (1<<14)
 143 #define   MI_FLUSH_DW_OP_MASK           (3<<14)
 144 #define   MI_FLUSH_DW_NOTIFY            (1<<8)
 145 #define   MI_INVALIDATE_BSD             (1<<7)
 146 #define   MI_FLUSH_DW_USE_GTT           (1<<2)
 147 #define   MI_FLUSH_DW_USE_PPGTT         (0<<2)
 148 #define MI_LOAD_REGISTER_MEM       MI_INSTR(0x29, 1)
 149 #define MI_LOAD_REGISTER_MEM_GEN8  MI_INSTR(0x29, 2)
 150 #define MI_BATCH_BUFFER         MI_INSTR(0x30, 1)
 151 #define   MI_BATCH_NON_SECURE           (1)
 152 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
 153 #define   MI_BATCH_NON_SECURE_I965      (1<<8)
 154 #define   MI_BATCH_PPGTT_HSW            (1<<8)
 155 #define   MI_BATCH_NON_SECURE_HSW       (1<<13)
 156 #define MI_BATCH_BUFFER_START   MI_INSTR(0x31, 0)
 157 #define   MI_BATCH_GTT              (2<<6) /* aliased with (1<<7) on gen4 */
 158 #define MI_BATCH_BUFFER_START_GEN8      MI_INSTR(0x31, 1)
 159 #define   MI_BATCH_RESOURCE_STREAMER (1<<10)
 160 
 161 /*
 162  * 3D instructions used by the kernel
 163  */
 164 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
 165 
 166 #define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
 167 #define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
 168 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
 169 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 170 #define   SC_UPDATE_SCISSOR       (0x1<<1)
 171 #define   SC_ENABLE_MASK          (0x1<<0)
 172 #define   SC_ENABLE               (0x1<<0)
 173 #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
 174 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
 175 #define   SCI_YMIN_MASK      (0xffff<<16)
 176 #define   SCI_XMIN_MASK      (0xffff<<0)
 177 #define   SCI_YMAX_MASK      (0xffff<<16)
 178 #define   SCI_XMAX_MASK      (0xffff<<0)
 179 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 180 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
 181 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
 182 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
 183 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
 184 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
 185 #define GFX_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
 186 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
 187 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
 188 
 189 #define COLOR_BLT_CMD                   (2 << 29 | 0x40 << 22 | (5 - 2))
 190 #define XY_COLOR_BLT_CMD                (2 << 29 | 0x50 << 22)
 191 #define SRC_COPY_BLT_CMD                (2 << 29 | 0x43 << 22)
 192 #define GEN9_XY_FAST_COPY_BLT_CMD       (2 << 29 | 0x42 << 22)
 193 #define XY_SRC_COPY_BLT_CMD             (2 << 29 | 0x53 << 22)
 194 #define XY_MONO_SRC_COPY_IMM_BLT        (2 << 29 | 0x71 << 22 | 5)
 195 #define   BLT_WRITE_A                   (2<<20)
 196 #define   BLT_WRITE_RGB                 (1<<20)
 197 #define   BLT_WRITE_RGBA                (BLT_WRITE_RGB | BLT_WRITE_A)
 198 #define   BLT_DEPTH_8                   (0<<24)
 199 #define   BLT_DEPTH_16_565              (1<<24)
 200 #define   BLT_DEPTH_16_1555             (2<<24)
 201 #define   BLT_DEPTH_32                  (3<<24)
 202 #define   BLT_ROP_SRC_COPY              (0xcc<<16)
 203 #define   BLT_ROP_COLOR_COPY            (0xf0<<16)
 204 #define XY_SRC_COPY_BLT_SRC_TILED       (1<<15) /* 965+ only */
 205 #define XY_SRC_COPY_BLT_DST_TILED       (1<<11) /* 965+ only */
 206 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
 207 #define   ASYNC_FLIP                (1<<22)
 208 #define   DISPLAY_PLANE_A           (0<<20)
 209 #define   DISPLAY_PLANE_B           (1<<20)
 210 #define GFX_OP_PIPE_CONTROL(len)        ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
 211 #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE         (1<<29) /* gen11+ */
 212 #define   PIPE_CONTROL_TILE_CACHE_FLUSH                 (1<<28) /* gen11+ */
 213 #define   PIPE_CONTROL_FLUSH_L3                         (1<<27)
 214 #define   PIPE_CONTROL_GLOBAL_GTT_IVB                   (1<<24) /* gen7+ */
 215 #define   PIPE_CONTROL_MMIO_WRITE                       (1<<23)
 216 #define   PIPE_CONTROL_STORE_DATA_INDEX                 (1<<21)
 217 #define   PIPE_CONTROL_CS_STALL                         (1<<20)
 218 #define   PIPE_CONTROL_TLB_INVALIDATE                   (1<<18)
 219 #define   PIPE_CONTROL_MEDIA_STATE_CLEAR                (1<<16)
 220 #define   PIPE_CONTROL_QW_WRITE                         (1<<14)
 221 #define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
 222 #define   PIPE_CONTROL_DEPTH_STALL                      (1<<13)
 223 #define   PIPE_CONTROL_WRITE_FLUSH                      (1<<12)
 224 #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH        (1<<12) /* gen6+ */
 225 #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE     (1<<11) /* MBZ on ILK */
 226 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE         (1<<10) /* GM45+ only */
 227 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE           (1<<9)
 228 #define   PIPE_CONTROL_NOTIFY                           (1<<8)
 229 #define   PIPE_CONTROL_FLUSH_ENABLE                     (1<<7) /* gen7+ */
 230 #define   PIPE_CONTROL_DC_FLUSH_ENABLE                  (1<<5)
 231 #define   PIPE_CONTROL_VF_CACHE_INVALIDATE              (1<<4)
 232 #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE           (1<<3)
 233 #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE           (1<<2)
 234 #define   PIPE_CONTROL_STALL_AT_SCOREBOARD              (1<<1)
 235 #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH                (1<<0)
 236 #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
 237 
 238 /*
 239  * Commands used only by the command parser
 240  */
 241 #define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
 242 #define MI_ARB_CHECK            MI_INSTR(0x05, 0)
 243 #define MI_RS_CONTROL           MI_INSTR(0x06, 0)
 244 #define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
 245 #define MI_PREDICATE            MI_INSTR(0x0C, 0)
 246 #define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
 247 #define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
 248 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
 249 #define MI_URB_CLEAR            MI_INSTR(0x19, 0)
 250 #define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
 251 #define MI_CLFLUSH              MI_INSTR(0x27, 0)
 252 #define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
 253 #define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
 254 #define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
 255 #define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
 256 #define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
 257 #define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
 258 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
 259 
 260 #define PIPELINE_SELECT                ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
 261 #define GFX_OP_3DSTATE_VF_STATISTICS   ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
 262 #define MEDIA_VFE_STATE                ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
 263 #define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
 264 #define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
 265 #define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
 266 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
 267         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
 268 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
 269         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
 270 #define GFX_OP_3DSTATE_SO_DECL_LIST \
 271         ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
 272 
 273 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
 274         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
 275 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
 276         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
 277 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
 278         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
 279 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
 280         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
 281 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
 282         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
 283 
 284 #define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))
 285 
 286 #define COLOR_BLT     ((0x2<<29)|(0x40<<22))
 287 #define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
 288 
 289 #endif /* _INTEL_GPU_COMMANDS_H_ */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/i915/gt/intel_gpu_commands.h

INCLUDED FROM
