1
2
3
4
5
6 #ifndef __INTEL_PM_H__
7 #define __INTEL_PM_H__
8
9 #include <linux/types.h>
10
11 #include "i915_reg.h"
12
13 struct drm_device;
14 struct drm_i915_private;
15 struct i915_request;
16 struct intel_atomic_state;
17 struct intel_crtc;
18 struct intel_crtc_state;
19 struct intel_plane;
20 struct skl_ddb_allocation;
21 struct skl_ddb_entry;
22 struct skl_pipe_wm;
23 struct skl_wm_level;
24
25 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
26 void intel_suspend_hw(struct drm_i915_private *dev_priv);
27 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
28 void intel_update_watermarks(struct intel_crtc *crtc);
29 void intel_init_pm(struct drm_i915_private *dev_priv);
30 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
31 void intel_pm_setup(struct drm_i915_private *dev_priv);
32 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
33 void intel_gpu_ips_teardown(void);
34 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
35 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
36 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
37 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
38 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
39 bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915);
40 void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915);
41 void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915);
42 void gen6_rps_busy(struct drm_i915_private *dev_priv);
43 void gen6_rps_idle(struct drm_i915_private *dev_priv);
44 void gen6_rps_boost(struct i915_request *rq);
45 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
46 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
47 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
48 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
49 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
50 struct skl_ddb_entry *ddb_y,
51 struct skl_ddb_entry *ddb_uv);
52 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
53 struct skl_ddb_allocation *ddb );
54 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
55 struct skl_pipe_wm *out);
56 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
57 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
58 bool intel_can_enable_sagv(struct intel_atomic_state *state);
59 int intel_enable_sagv(struct drm_i915_private *dev_priv);
60 int intel_disable_sagv(struct drm_i915_private *dev_priv);
61 bool skl_wm_level_equals(const struct skl_wm_level *l1,
62 const struct skl_wm_level *l2);
63 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
64 const struct skl_ddb_entry *entries,
65 int num_entries, int ignore_idx);
66 void skl_write_plane_wm(struct intel_plane *plane,
67 const struct intel_crtc_state *crtc_state);
68 void skl_write_cursor_wm(struct intel_plane *plane,
69 const struct intel_crtc_state *crtc_state);
70 bool ilk_disable_lp_wm(struct drm_device *dev);
71 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
72 struct intel_crtc_state *cstate);
73 void intel_init_ipc(struct drm_i915_private *dev_priv);
74 void intel_enable_ipc(struct drm_i915_private *dev_priv);
75
76 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
77 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
78 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
79 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
80
81 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
82
83 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
84 unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
85 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
86 void i915_update_gfx_val(struct drm_i915_private *dev_priv);
87
88 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
89 int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
90 void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive);
91 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
92
93 #endif