drivers/gpu/drm/i915/gvt/mmio

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This source file includes following definitions.
load_render_mocs
restore_context_mmio_for_inhibit
restore_render_mocs_control_for_inhibit
restore_render_mocs_l3cc_for_inhibit
intel_vgpu_restore_inhibit_context
handle_tlb_pending_event
switch_mocs
is_inhibit_context
switch_mmio
intel_gvt_switch_mmio
intel_gvt_init_engine_mmio_context
   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eddie Dong <eddie.dong@intel.com>
  25  *    Kevin Tian <kevin.tian@intel.com>
  26  *
  27  * Contributors:
  28  *    Zhi Wang <zhi.a.wang@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  31  *    Tina Zhang <tina.zhang@intel.com>
  32  *    Bing Niu <bing.niu@intel.com>
  33  *
  34  */
  35 
  36 #include "i915_drv.h"
  37 #include "gt/intel_context.h"
  38 #include "gvt.h"
  39 #include "trace.h"
  40 
  41 #define GEN9_MOCS_SIZE          64
  42 
  43 /* Raw offset is appened to each line for convenience. */
  44 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
  45         {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
  46         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
  47         {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
  48         {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
  49         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
  50         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
  51         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
  52         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
  53         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
  54         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
  55         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
  56         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
  57         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
  58         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
  59         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
  60         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
  61         {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
  62         {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
  63         {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
  64         {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
  65         {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
  66         {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
  67 
  68         {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
  69         {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
  70         {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
  71         {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
  72         {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
  73         {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
  74 };
  75 
  76 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
  77         {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
  78         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
  79         {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
  80         {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
  81         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
  82         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
  83         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
  84         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
  85         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
  86         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
  87         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
  88         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
  89         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
  90         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
  91         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
  92         {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
  93         {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
  94         {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
  95         {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
  96         {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
  97         {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
  98         {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
  99 
 100         {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
 101         {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
 102         {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
 103         {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
 104         {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
 105         {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
 106         {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
 107         {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
 108         {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
 109         {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
 110         {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
 111         {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
 112         {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
 113         {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
 114         {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
 115         {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
 116         {RCS0, TRVADR, 0, true}, /* 0x4df0 */
 117         {RCS0, TRTTE, 0, true}, /* 0x4df4 */
 118         {RCS0, _MMIO(0x4dfc), 0, true},
 119 
 120         {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
 121         {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
 122         {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
 123         {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
 124         {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
 125 
 126         {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
 127 
 128         {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
 129 
 130         {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
 131         {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
 132         {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
 133         {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
 134 
 135         {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
 136         {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
 137         {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
 138 
 139         {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
 140         {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
 141         {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
 142         {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
 143 };
 144 
 145 static struct {
 146         bool initialized;
 147         u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
 148         u32 l3cc_table[GEN9_MOCS_SIZE / 2];
 149 } gen9_render_mocs;
 150 
 151 static u32 gen9_mocs_mmio_offset_list[] = {
 152         [RCS0]  = 0xc800,
 153         [VCS0]  = 0xc900,
 154         [VCS1]  = 0xca00,
 155         [BCS0]  = 0xcc00,
 156         [VECS0] = 0xcb00,
 157 };
 158 
 159 static void load_render_mocs(struct drm_i915_private *dev_priv)
 160 {
 161         struct intel_gvt *gvt = dev_priv->gvt;
 162         i915_reg_t offset;
 163         u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt;
 164         u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list;
 165         int ring_id, i;
 166 
 167         /* Platform doesn't have mocs mmios. */
 168         if (!regs)
 169                 return;
 170 
 171         for (ring_id = 0; ring_id < cnt; ring_id++) {
 172                 if (!HAS_ENGINE(dev_priv, ring_id))
 173                         continue;
 174                 offset.reg = regs[ring_id];
 175                 for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 176                         gen9_render_mocs.control_table[ring_id][i] =
 177                                 I915_READ_FW(offset);
 178                         offset.reg += 4;
 179                 }
 180         }
 181 
 182         offset.reg = 0xb020;
 183         for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
 184                 gen9_render_mocs.l3cc_table[i] =
 185                         I915_READ_FW(offset);
 186                 offset.reg += 4;
 187         }
 188         gen9_render_mocs.initialized = true;
 189 }
 190 
 191 static int
 192 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
 193                                  struct i915_request *req)
 194 {
 195         u32 *cs;
 196         int ret;
 197         struct engine_mmio *mmio;
 198         struct intel_gvt *gvt = vgpu->gvt;
 199         int ring_id = req->engine->id;
 200         int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
 201 
 202         if (count == 0)
 203                 return 0;
 204 
 205         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 206         if (ret)
 207                 return ret;
 208 
 209         cs = intel_ring_begin(req, count * 2 + 2);
 210         if (IS_ERR(cs))
 211                 return PTR_ERR(cs);
 212 
 213         *cs++ = MI_LOAD_REGISTER_IMM(count);
 214         for (mmio = gvt->engine_mmio_list.mmio;
 215              i915_mmio_reg_valid(mmio->reg); mmio++) {
 216                 if (mmio->ring_id != ring_id ||
 217                     !mmio->in_context)
 218                         continue;
 219 
 220                 *cs++ = i915_mmio_reg_offset(mmio->reg);
 221                 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) |
 222                                 (mmio->mask << 16);
 223                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 224                               *(cs-2), *(cs-1), vgpu->id, ring_id);
 225         }
 226 
 227         *cs++ = MI_NOOP;
 228         intel_ring_advance(req, cs);
 229 
 230         ret = req->engine->emit_flush(req, EMIT_BARRIER);
 231         if (ret)
 232                 return ret;
 233 
 234         return 0;
 235 }
 236 
 237 static int
 238 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
 239                                         struct i915_request *req)
 240 {
 241         unsigned int index;
 242         u32 *cs;
 243 
 244         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
 245         if (IS_ERR(cs))
 246                 return PTR_ERR(cs);
 247 
 248         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
 249 
 250         for (index = 0; index < GEN9_MOCS_SIZE; index++) {
 251                 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
 252                 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
 253                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 254                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
 255 
 256         }
 257 
 258         *cs++ = MI_NOOP;
 259         intel_ring_advance(req, cs);
 260 
 261         return 0;
 262 }
 263 
 264 static int
 265 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
 266                                      struct i915_request *req)
 267 {
 268         unsigned int index;
 269         u32 *cs;
 270 
 271         cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
 272         if (IS_ERR(cs))
 273                 return PTR_ERR(cs);
 274 
 275         *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
 276 
 277         for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
 278                 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
 279                 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
 280                 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
 281                               *(cs-2), *(cs-1), vgpu->id, req->engine->id);
 282 
 283         }
 284 
 285         *cs++ = MI_NOOP;
 286         intel_ring_advance(req, cs);
 287 
 288         return 0;
 289 }
 290 
 291 /*
 292  * Use lri command to initialize the mmio which is in context state image for
 293  * inhibit context, it contains tracked engine mmio, render_mocs and
 294  * render_mocs_l3cc.
 295  */
 296 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
 297                                        struct i915_request *req)
 298 {
 299         int ret;
 300         u32 *cs;
 301 
 302         cs = intel_ring_begin(req, 2);
 303         if (IS_ERR(cs))
 304                 return PTR_ERR(cs);
 305 
 306         *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
 307         *cs++ = MI_NOOP;
 308         intel_ring_advance(req, cs);
 309 
 310         ret = restore_context_mmio_for_inhibit(vgpu, req);
 311         if (ret)
 312                 goto out;
 313 
 314         /* no MOCS register in context except render engine */
 315         if (req->engine->id != RCS0)
 316                 goto out;
 317 
 318         ret = restore_render_mocs_control_for_inhibit(vgpu, req);
 319         if (ret)
 320                 goto out;
 321 
 322         ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
 323         if (ret)
 324                 goto out;
 325 
 326 out:
 327         cs = intel_ring_begin(req, 2);
 328         if (IS_ERR(cs))
 329                 return PTR_ERR(cs);
 330 
 331         *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
 332         *cs++ = MI_NOOP;
 333         intel_ring_advance(req, cs);
 334 
 335         return ret;
 336 }
 337 
 338 static u32 gen8_tlb_mmio_offset_list[] = {
 339         [RCS0]  = 0x4260,
 340         [VCS0]  = 0x4264,
 341         [VCS1]  = 0x4268,
 342         [BCS0]  = 0x426c,
 343         [VECS0] = 0x4270,
 344 };
 345 
 346 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
 347 {
 348         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 349         struct intel_uncore *uncore = &dev_priv->uncore;
 350         struct intel_vgpu_submission *s = &vgpu->submission;
 351         u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list;
 352         u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt;
 353         enum forcewake_domains fw;
 354         i915_reg_t reg;
 355 
 356         if (!regs)
 357                 return;
 358 
 359         if (WARN_ON(ring_id >= cnt))
 360                 return;
 361 
 362         if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
 363                 return;
 364 
 365         reg = _MMIO(regs[ring_id]);
 366 
 367         /* WaForceWakeRenderDuringMmioTLBInvalidate:skl
 368          * we need to put a forcewake when invalidating RCS TLB caches,
 369          * otherwise device can go to RC6 state and interrupt invalidation
 370          * process
 371          */
 372         fw = intel_uncore_forcewake_for_reg(uncore, reg,
 373                                             FW_REG_READ | FW_REG_WRITE);
 374         if (ring_id == RCS0 && INTEL_GEN(dev_priv) >= 9)
 375                 fw |= FORCEWAKE_RENDER;
 376 
 377         intel_uncore_forcewake_get(uncore, fw);
 378 
 379         intel_uncore_write_fw(uncore, reg, 0x1);
 380 
 381         if (wait_for_atomic((intel_uncore_read_fw(uncore, reg) == 0), 50))
 382                 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
 383         else
 384                 vgpu_vreg_t(vgpu, reg) = 0;
 385 
 386         intel_uncore_forcewake_put(uncore, fw);
 387 
 388         gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
 389 }
 390 
 391 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
 392                         int ring_id)
 393 {
 394         struct drm_i915_private *dev_priv;
 395         i915_reg_t offset, l3_offset;
 396         u32 old_v, new_v;
 397 
 398         u32 regs[] = {
 399                 [RCS0]  = 0xc800,
 400                 [VCS0]  = 0xc900,
 401                 [VCS1]  = 0xca00,
 402                 [BCS0]  = 0xcc00,
 403                 [VECS0] = 0xcb00,
 404         };
 405         int i;
 406 
 407         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 408         if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
 409                 return;
 410 
 411         if (ring_id == RCS0 && IS_GEN(dev_priv, 9))
 412                 return;
 413 
 414         if (!pre && !gen9_render_mocs.initialized)
 415                 load_render_mocs(dev_priv);
 416 
 417         offset.reg = regs[ring_id];
 418         for (i = 0; i < GEN9_MOCS_SIZE; i++) {
 419                 if (pre)
 420                         old_v = vgpu_vreg_t(pre, offset);
 421                 else
 422                         old_v = gen9_render_mocs.control_table[ring_id][i];
 423                 if (next)
 424                         new_v = vgpu_vreg_t(next, offset);
 425                 else
 426                         new_v = gen9_render_mocs.control_table[ring_id][i];
 427 
 428                 if (old_v != new_v)
 429                         I915_WRITE_FW(offset, new_v);
 430 
 431                 offset.reg += 4;
 432         }
 433 
 434         if (ring_id == RCS0) {
 435                 l3_offset.reg = 0xb020;
 436                 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
 437                         if (pre)
 438                                 old_v = vgpu_vreg_t(pre, l3_offset);
 439                         else
 440                                 old_v = gen9_render_mocs.l3cc_table[i];
 441                         if (next)
 442                                 new_v = vgpu_vreg_t(next, l3_offset);
 443                         else
 444                                 new_v = gen9_render_mocs.l3cc_table[i];
 445 
 446                         if (old_v != new_v)
 447                                 I915_WRITE_FW(l3_offset, new_v);
 448 
 449                         l3_offset.reg += 4;
 450                 }
 451         }
 452 }
 453 
 454 #define CTX_CONTEXT_CONTROL_VAL 0x03
 455 
 456 bool is_inhibit_context(struct intel_context *ce)
 457 {
 458         const u32 *reg_state = ce->lrc_reg_state;
 459         u32 inhibit_mask =
 460                 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
 461 
 462         return inhibit_mask ==
 463                 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
 464 }
 465 
 466 /* Switch ring mmio values (context). */
 467 static void switch_mmio(struct intel_vgpu *pre,
 468                         struct intel_vgpu *next,
 469                         int ring_id)
 470 {
 471         struct drm_i915_private *dev_priv;
 472         struct intel_vgpu_submission *s;
 473         struct engine_mmio *mmio;
 474         u32 old_v, new_v;
 475 
 476         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 477         if (INTEL_GEN(dev_priv) >= 9)
 478                 switch_mocs(pre, next, ring_id);
 479 
 480         for (mmio = dev_priv->gvt->engine_mmio_list.mmio;
 481              i915_mmio_reg_valid(mmio->reg); mmio++) {
 482                 if (mmio->ring_id != ring_id)
 483                         continue;
 484                 /*
 485                  * No need to do save or restore of the mmio which is in context
 486                  * state image on gen9, it's initialized by lri command and
 487                  * save or restore with context together.
 488                  */
 489                 if (IS_GEN(dev_priv, 9) && mmio->in_context)
 490                         continue;
 491 
 492                 // save
 493                 if (pre) {
 494                         vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg);
 495                         if (mmio->mask)
 496                                 vgpu_vreg_t(pre, mmio->reg) &=
 497                                                 ~(mmio->mask << 16);
 498                         old_v = vgpu_vreg_t(pre, mmio->reg);
 499                 } else
 500                         old_v = mmio->value = I915_READ_FW(mmio->reg);
 501 
 502                 // restore
 503                 if (next) {
 504                         s = &next->submission;
 505                         /*
 506                          * No need to restore the mmio which is in context state
 507                          * image if it's not inhibit context, it will restore
 508                          * itself.
 509                          */
 510                         if (mmio->in_context &&
 511                             !is_inhibit_context(s->shadow[ring_id]))
 512                                 continue;
 513 
 514                         if (mmio->mask)
 515                                 new_v = vgpu_vreg_t(next, mmio->reg) |
 516                                                         (mmio->mask << 16);
 517                         else
 518                                 new_v = vgpu_vreg_t(next, mmio->reg);
 519                 } else {
 520                         if (mmio->in_context)
 521                                 continue;
 522                         if (mmio->mask)
 523                                 new_v = mmio->value | (mmio->mask << 16);
 524                         else
 525                                 new_v = mmio->value;
 526                 }
 527 
 528                 I915_WRITE_FW(mmio->reg, new_v);
 529 
 530                 trace_render_mmio(pre ? pre->id : 0,
 531                                   next ? next->id : 0,
 532                                   "switch",
 533                                   i915_mmio_reg_offset(mmio->reg),
 534                                   old_v, new_v);
 535         }
 536 
 537         if (next)
 538                 handle_tlb_pending_event(next, ring_id);
 539 }
 540 
 541 /**
 542  * intel_gvt_switch_render_mmio - switch mmio context of specific engine
 543  * @pre: the last vGPU that own the engine
 544  * @next: the vGPU to switch to
 545  * @ring_id: specify the engine
 546  *
 547  * If pre is null indicates that host own the engine. If next is null
 548  * indicates that we are switching to host workload.
 549  */
 550 void intel_gvt_switch_mmio(struct intel_vgpu *pre,
 551                            struct intel_vgpu *next, int ring_id)
 552 {
 553         struct drm_i915_private *dev_priv;
 554 
 555         if (WARN_ON(!pre && !next))
 556                 return;
 557 
 558         gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
 559                        pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
 560 
 561         dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
 562 
 563         /**
 564          * We are using raw mmio access wrapper to improve the
 565          * performace for batch mmio read/write, so we need
 566          * handle forcewake mannually.
 567          */
 568         intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 569         switch_mmio(pre, next, ring_id);
 570         intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 571 }
 572 
 573 /**
 574  * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
 575  * @gvt: GVT device
 576  *
 577  */
 578 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
 579 {
 580         struct engine_mmio *mmio;
 581 
 582         if (INTEL_GEN(gvt->dev_priv) >= 9) {
 583                 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
 584                 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
 585                 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
 586                 gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list;
 587                 gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list);
 588         } else {
 589                 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
 590                 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
 591                 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
 592         }
 593 
 594         for (mmio = gvt->engine_mmio_list.mmio;
 595              i915_mmio_reg_valid(mmio->reg); mmio++) {
 596                 if (mmio->in_context) {
 597                         gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++;
 598                         intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
 599                 }
 600         }
 601 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/i915/gvt/mmio_context.c

DEFINITIONS
