drivers/gpu/drm/i915/gvt/display.c

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
get_edp_pipe
edp_pipe_is_enabled
pipe_is_enabled
emulate_monitor_status_change
clean_virtual_dp_monitor
setup_virtual_dp_monitor
intel_gvt_check_vblank_emulation
emulate_vblank_on_pipe
emulate_vblank
intel_gvt_emulate_vblank
intel_vgpu_emulate_hotplug
intel_vgpu_clean_display
intel_vgpu_init_display
intel_vgpu_reset_display
   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  26  *
  27  * Contributors:
  28  *    Terrence Xu <terrence.xu@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Bing Niu <bing.niu@intel.com>
  31  *    Zhi Wang <zhi.a.wang@intel.com>
  32  *
  33  */
  34 
  35 #include "i915_drv.h"
  36 #include "gvt.h"
  37 
  38 static int get_edp_pipe(struct intel_vgpu *vgpu)
  39 {
  40         u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
  41         int pipe = -1;
  42 
  43         switch (data & TRANS_DDI_EDP_INPUT_MASK) {
  44         case TRANS_DDI_EDP_INPUT_A_ON:
  45         case TRANS_DDI_EDP_INPUT_A_ONOFF:
  46                 pipe = PIPE_A;
  47                 break;
  48         case TRANS_DDI_EDP_INPUT_B_ONOFF:
  49                 pipe = PIPE_B;
  50                 break;
  51         case TRANS_DDI_EDP_INPUT_C_ONOFF:
  52                 pipe = PIPE_C;
  53                 break;
  54         }
  55         return pipe;
  56 }
  57 
  58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
  59 {
  60         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
  61 
  62         if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
  63                 return 0;
  64 
  65         if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
  66                 return 0;
  67         return 1;
  68 }
  69 
  70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
  71 {
  72         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
  73 
  74         if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
  75                 return -EINVAL;
  76 
  77         if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
  78                 return 1;
  79 
  80         if (edp_pipe_is_enabled(vgpu) &&
  81                         get_edp_pipe(vgpu) == pipe)
  82                 return 1;
  83         return 0;
  84 }
  85 
  86 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
  87         {
  88 /* EDID with 1024x768 as its resolution */
  89                 /*Header*/
  90                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
  91                 /* Vendor & Product Identification */
  92                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
  93                 /* Version & Revision */
  94                 0x01, 0x04,
  95                 /* Basic Display Parameters & Features */
  96                 0xa5, 0x34, 0x20, 0x78, 0x23,
  97                 /* Color Characteristics */
  98                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
  99                 /* Established Timings: maximum resolution is 1024x768 */
 100                 0x21, 0x08, 0x00,
 101                 /* Standard Timings. All invalid */
 102                 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
 103                 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
 104                 /* 18 Byte Data Blocks 1: invalid */
 105                 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
 106                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
 107                 /* 18 Byte Data Blocks 2: invalid */
 108                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
 109                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 110                 /* 18 Byte Data Blocks 3: invalid */
 111                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
 112                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
 113                 /* 18 Byte Data Blocks 4: invalid */
 114                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
 115                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
 116                 /* Extension Block Count */
 117                 0x00,
 118                 /* Checksum */
 119                 0xef,
 120         },
 121         {
 122 /* EDID with 1920x1200 as its resolution */
 123                 /*Header*/
 124                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
 125                 /* Vendor & Product Identification */
 126                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
 127                 /* Version & Revision */
 128                 0x01, 0x04,
 129                 /* Basic Display Parameters & Features */
 130                 0xa5, 0x34, 0x20, 0x78, 0x23,
 131                 /* Color Characteristics */
 132                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
 133                 /* Established Timings: maximum resolution is 1024x768 */
 134                 0x21, 0x08, 0x00,
 135                 /*
 136                  * Standard Timings.
 137                  * below new resolutions can be supported:
 138                  * 1920x1080, 1280x720, 1280x960, 1280x1024,
 139                  * 1440x900, 1600x1200, 1680x1050
 140                  */
 141                 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
 142                 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
 143                 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
 144                 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
 145                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
 146                 /* 18 Byte Data Blocks 2: invalid */
 147                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
 148                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 149                 /* 18 Byte Data Blocks 3: invalid */
 150                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
 151                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
 152                 /* 18 Byte Data Blocks 4: invalid */
 153                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
 154                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
 155                 /* Extension Block Count */
 156                 0x00,
 157                 /* Checksum */
 158                 0x45,
 159         },
 160 };
 161 
 162 #define DPCD_HEADER_SIZE        0xb
 163 
 164 /* let the virtual display supports DP1.2 */
 165 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
 166         0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 167 };
 168 
 169 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 170 {
 171         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 172         int pipe;
 173 
 174         if (IS_BROXTON(dev_priv)) {
 175                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
 176                         BXT_DE_PORT_HP_DDIB |
 177                         BXT_DE_PORT_HP_DDIC);
 178 
 179                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 180                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 181                                 BXT_DE_PORT_HP_DDIA;
 182                 }
 183 
 184                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 185                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 186                                 BXT_DE_PORT_HP_DDIB;
 187                 }
 188 
 189                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 190                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 191                                 BXT_DE_PORT_HP_DDIC;
 192                 }
 193 
 194                 return;
 195         }
 196 
 197         vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
 198                         SDE_PORTC_HOTPLUG_CPT |
 199                         SDE_PORTD_HOTPLUG_CPT);
 200 
 201         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
 202             IS_COFFEELAKE(dev_priv)) {
 203                 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
 204                                 SDE_PORTE_HOTPLUG_SPT);
 205                 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
 206                                 SKL_FUSE_DOWNLOAD_STATUS |
 207                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
 208                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
 209                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
 210                 /*
 211                  * Only 1 PIPE enabled in current vGPU display and PIPE_A is
 212                  *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
 213                  *   TRANSCODER_A can be enabled. PORT_x depends on the input of
 214                  *   setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
 215                  *   so we fixed to DPLL0 here.
 216                  * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
 217                  */
 218                 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
 219                         DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
 220                 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
 221                         DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
 222                 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
 223                         LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
 224                 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
 225                 /*
 226                  * Golden M/N are calculated based on:
 227                  *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
 228                  *   DP link clk 1620 MHz and non-constant_n.
 229                  * TODO: calculate DP link symbol clk and stream clk m/n.
 230                  */
 231                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
 232                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
 233                 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
 234                 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
 235                 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 236         }
 237 
 238         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 239                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
 240                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
 241                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 242                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
 243                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 244                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
 245                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
 246                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 247                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 248                         TRANS_DDI_PORT_MASK);
 249                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 250                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
 251                         (PORT_B << TRANS_DDI_PORT_SHIFT) |
 252                         TRANS_DDI_FUNC_ENABLE);
 253                 if (IS_BROADWELL(dev_priv)) {
 254                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
 255                                 ~PORT_CLK_SEL_MASK;
 256                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
 257                                 PORT_CLK_SEL_LCPLL_810;
 258                 }
 259                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
 260                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
 261                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
 262         }
 263 
 264         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 265                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
 266                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
 267                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 268                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
 269                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 270                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
 271                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
 272                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 273                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 274                         TRANS_DDI_PORT_MASK);
 275                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 276                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
 277                         (PORT_C << TRANS_DDI_PORT_SHIFT) |
 278                         TRANS_DDI_FUNC_ENABLE);
 279                 if (IS_BROADWELL(dev_priv)) {
 280                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
 281                                 ~PORT_CLK_SEL_MASK;
 282                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
 283                                 PORT_CLK_SEL_LCPLL_810;
 284                 }
 285                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
 286                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
 287                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
 288         }
 289 
 290         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
 291                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
 292                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
 293                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 294                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
 295                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 296                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
 297                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
 298                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 299                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 300                         TRANS_DDI_PORT_MASK);
 301                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 302                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
 303                         (PORT_D << TRANS_DDI_PORT_SHIFT) |
 304                         TRANS_DDI_FUNC_ENABLE);
 305                 if (IS_BROADWELL(dev_priv)) {
 306                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
 307                                 ~PORT_CLK_SEL_MASK;
 308                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
 309                                 PORT_CLK_SEL_LCPLL_810;
 310                 }
 311                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
 312                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
 313                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
 314         }
 315 
 316         if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
 317              IS_COFFEELAKE(dev_priv)) &&
 318                         intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
 319                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
 320         }
 321 
 322         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 323                 if (IS_BROADWELL(dev_priv))
 324                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 325                                 GEN8_PORT_DP_A_HOTPLUG;
 326                 else
 327                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
 328 
 329                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
 330         }
 331 
 332         /* Clear host CRT status, so guest couldn't detect this host CRT. */
 333         if (IS_BROADWELL(dev_priv))
 334                 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
 335 
 336         /* Disable Primary/Sprite/Cursor plane */
 337         for_each_pipe(dev_priv, pipe) {
 338                 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
 339                 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
 340                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
 341                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
 342         }
 343 
 344         vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
 345 }
 346 
 347 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
 348 {
 349         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 350 
 351         kfree(port->edid);
 352         port->edid = NULL;
 353 
 354         kfree(port->dpcd);
 355         port->dpcd = NULL;
 356 }
 357 
 358 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
 359                                     int type, unsigned int resolution)
 360 {
 361         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 362 
 363         if (WARN_ON(resolution >= GVT_EDID_NUM))
 364                 return -EINVAL;
 365 
 366         port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
 367         if (!port->edid)
 368                 return -ENOMEM;
 369 
 370         port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
 371         if (!port->dpcd) {
 372                 kfree(port->edid);
 373                 return -ENOMEM;
 374         }
 375 
 376         memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
 377                         EDID_SIZE);
 378         port->edid->data_valid = true;
 379 
 380         memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
 381         port->dpcd->data_valid = true;
 382         port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
 383         port->type = type;
 384         port->id = resolution;
 385 
 386         emulate_monitor_status_change(vgpu);
 387 
 388         return 0;
 389 }
 390 
 391 /**
 392  * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
 393  * be turned on/off when a virtual pipe is enabled/disabled.
 394  * @gvt: a GVT device
 395  *
 396  * This function is used to turn on/off vblank timer according to currently
 397  * enabled/disabled virtual pipes.
 398  *
 399  */
 400 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
 401 {
 402         struct intel_gvt_irq *irq = &gvt->irq;
 403         struct intel_vgpu *vgpu;
 404         int pipe, id;
 405         int found = false;
 406 
 407         mutex_lock(&gvt->lock);
 408         for_each_active_vgpu(gvt, vgpu, id) {
 409                 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
 410                         if (pipe_is_enabled(vgpu, pipe)) {
 411                                 found = true;
 412                                 break;
 413                         }
 414                 }
 415                 if (found)
 416                         break;
 417         }
 418 
 419         /* all the pipes are disabled */
 420         if (!found)
 421                 hrtimer_cancel(&irq->vblank_timer.timer);
 422         else
 423                 hrtimer_start(&irq->vblank_timer.timer,
 424                         ktime_add_ns(ktime_get(), irq->vblank_timer.period),
 425                         HRTIMER_MODE_ABS);
 426         mutex_unlock(&gvt->lock);
 427 }
 428 
 429 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
 430 {
 431         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 432         struct intel_vgpu_irq *irq = &vgpu->irq;
 433         int vblank_event[] = {
 434                 [PIPE_A] = PIPE_A_VBLANK,
 435                 [PIPE_B] = PIPE_B_VBLANK,
 436                 [PIPE_C] = PIPE_C_VBLANK,
 437         };
 438         int event;
 439 
 440         if (pipe < PIPE_A || pipe > PIPE_C)
 441                 return;
 442 
 443         for_each_set_bit(event, irq->flip_done_event[pipe],
 444                         INTEL_GVT_EVENT_MAX) {
 445                 clear_bit(event, irq->flip_done_event[pipe]);
 446                 if (!pipe_is_enabled(vgpu, pipe))
 447                         continue;
 448 
 449                 intel_vgpu_trigger_virtual_event(vgpu, event);
 450         }
 451 
 452         if (pipe_is_enabled(vgpu, pipe)) {
 453                 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
 454                 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
 455         }
 456 }
 457 
 458 static void emulate_vblank(struct intel_vgpu *vgpu)
 459 {
 460         int pipe;
 461 
 462         mutex_lock(&vgpu->vgpu_lock);
 463         for_each_pipe(vgpu->gvt->dev_priv, pipe)
 464                 emulate_vblank_on_pipe(vgpu, pipe);
 465         mutex_unlock(&vgpu->vgpu_lock);
 466 }
 467 
 468 /**
 469  * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
 470  * @gvt: a GVT device
 471  *
 472  * This function is used to trigger vblank interrupts for vGPUs on GVT device
 473  *
 474  */
 475 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
 476 {
 477         struct intel_vgpu *vgpu;
 478         int id;
 479 
 480         mutex_lock(&gvt->lock);
 481         for_each_active_vgpu(gvt, vgpu, id)
 482                 emulate_vblank(vgpu);
 483         mutex_unlock(&gvt->lock);
 484 }
 485 
 486 /**
 487  * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
 488  * @vgpu: a vGPU
 489  * @connected: link state
 490  *
 491  * This function is used to trigger hotplug interrupt for vGPU
 492  *
 493  */
 494 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
 495 {
 496         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 497 
 498         /* TODO: add more platforms support */
 499         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
 500                 IS_COFFEELAKE(dev_priv)) {
 501                 if (connected) {
 502                         vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
 503                                 SFUSE_STRAP_DDID_DETECTED;
 504                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
 505                 } else {
 506                         vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
 507                                 ~SFUSE_STRAP_DDID_DETECTED;
 508                         vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
 509                 }
 510                 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
 511                 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 512                                 PORTD_HOTPLUG_STATUS_MASK;
 513                 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
 514         }
 515 }
 516 
 517 /**
 518  * intel_vgpu_clean_display - clean vGPU virtual display emulation
 519  * @vgpu: a vGPU
 520  *
 521  * This function is used to clean vGPU virtual display emulation stuffs
 522  *
 523  */
 524 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
 525 {
 526         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 527 
 528         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
 529             IS_COFFEELAKE(dev_priv))
 530                 clean_virtual_dp_monitor(vgpu, PORT_D);
 531         else
 532                 clean_virtual_dp_monitor(vgpu, PORT_B);
 533 }
 534 
 535 /**
 536  * intel_vgpu_init_display- initialize vGPU virtual display emulation
 537  * @vgpu: a vGPU
 538  * @resolution: resolution index for intel_vgpu_edid
 539  *
 540  * This function is used to initialize vGPU virtual display emulation stuffs
 541  *
 542  * Returns:
 543  * Zero on success, negative error code if failed.
 544  *
 545  */
 546 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
 547 {
 548         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 549 
 550         intel_vgpu_init_i2c_edid(vgpu);
 551 
 552         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
 553             IS_COFFEELAKE(dev_priv))
 554                 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
 555                                                 resolution);
 556         else
 557                 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
 558                                                 resolution);
 559 }
 560 
 561 /**
 562  * intel_vgpu_reset_display- reset vGPU virtual display emulation
 563  * @vgpu: a vGPU
 564  *
 565  * This function is used to reset vGPU virtual display emulation stuffs
 566  *
 567  */
 568 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
 569 {
 570         emulate_monitor_status_change(vgpu);
 571 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/i915/gvt/display.c

DEFINITIONS
