drivers/gpu/drm/i915/display/intel_display

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This source file includes following definitions.
intel_display_power_put_async
intel_display_power_put
intel_display_power_put_async
   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5 
   6 #ifndef __INTEL_DISPLAY_POWER_H__
   7 #define __INTEL_DISPLAY_POWER_H__
   8 
   9 #include "intel_display.h"
  10 #include "intel_runtime_pm.h"
  11 #include "i915_reg.h"
  12 
  13 struct drm_i915_private;
  14 struct intel_encoder;
  15 
  16 enum intel_display_power_domain {
  17         POWER_DOMAIN_DISPLAY_CORE,
  18         POWER_DOMAIN_PIPE_A,
  19         POWER_DOMAIN_PIPE_B,
  20         POWER_DOMAIN_PIPE_C,
  21         POWER_DOMAIN_PIPE_D,
  22         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
  23         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
  24         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
  25         POWER_DOMAIN_PIPE_D_PANEL_FITTER,
  26         POWER_DOMAIN_TRANSCODER_A,
  27         POWER_DOMAIN_TRANSCODER_B,
  28         POWER_DOMAIN_TRANSCODER_C,
  29         POWER_DOMAIN_TRANSCODER_D,
  30         POWER_DOMAIN_TRANSCODER_EDP,
  31         /* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
  32         POWER_DOMAIN_TRANSCODER_VDSC_PW2,
  33         POWER_DOMAIN_TRANSCODER_DSI_A,
  34         POWER_DOMAIN_TRANSCODER_DSI_C,
  35         POWER_DOMAIN_PORT_DDI_A_LANES,
  36         POWER_DOMAIN_PORT_DDI_B_LANES,
  37         POWER_DOMAIN_PORT_DDI_C_LANES,
  38         POWER_DOMAIN_PORT_DDI_D_LANES,
  39         POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
  40         POWER_DOMAIN_PORT_DDI_E_LANES,
  41         POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
  42         POWER_DOMAIN_PORT_DDI_F_LANES,
  43         POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
  44         POWER_DOMAIN_PORT_DDI_TC4_LANES,
  45         POWER_DOMAIN_PORT_DDI_TC5_LANES,
  46         POWER_DOMAIN_PORT_DDI_TC6_LANES,
  47         POWER_DOMAIN_PORT_DDI_A_IO,
  48         POWER_DOMAIN_PORT_DDI_B_IO,
  49         POWER_DOMAIN_PORT_DDI_C_IO,
  50         POWER_DOMAIN_PORT_DDI_D_IO,
  51         POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
  52         POWER_DOMAIN_PORT_DDI_E_IO,
  53         POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
  54         POWER_DOMAIN_PORT_DDI_F_IO,
  55         POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
  56         POWER_DOMAIN_PORT_DDI_G_IO,
  57         POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
  58         POWER_DOMAIN_PORT_DDI_H_IO,
  59         POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
  60         POWER_DOMAIN_PORT_DDI_I_IO,
  61         POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
  62         POWER_DOMAIN_PORT_DSI,
  63         POWER_DOMAIN_PORT_CRT,
  64         POWER_DOMAIN_PORT_OTHER,
  65         POWER_DOMAIN_VGA,
  66         POWER_DOMAIN_AUDIO,
  67         POWER_DOMAIN_AUX_A,
  68         POWER_DOMAIN_AUX_B,
  69         POWER_DOMAIN_AUX_C,
  70         POWER_DOMAIN_AUX_D,
  71         POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
  72         POWER_DOMAIN_AUX_E,
  73         POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
  74         POWER_DOMAIN_AUX_F,
  75         POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
  76         POWER_DOMAIN_AUX_TC4,
  77         POWER_DOMAIN_AUX_TC5,
  78         POWER_DOMAIN_AUX_TC6,
  79         POWER_DOMAIN_AUX_IO_A,
  80         POWER_DOMAIN_AUX_TBT1,
  81         POWER_DOMAIN_AUX_TBT2,
  82         POWER_DOMAIN_AUX_TBT3,
  83         POWER_DOMAIN_AUX_TBT4,
  84         POWER_DOMAIN_AUX_TBT5,
  85         POWER_DOMAIN_AUX_TBT6,
  86         POWER_DOMAIN_GMBUS,
  87         POWER_DOMAIN_MODESET,
  88         POWER_DOMAIN_GT_IRQ,
  89         POWER_DOMAIN_DPLL_DC_OFF,
  90         POWER_DOMAIN_INIT,
  91 
  92         POWER_DOMAIN_NUM,
  93 };
  94 
  95 /*
  96  * i915_power_well_id:
  97  *
  98  * IDs used to look up power wells. Power wells accessed directly bypassing
  99  * the power domains framework must be assigned a unique ID. The rest of power
 100  * wells must be assigned DISP_PW_ID_NONE.
 101  */
 102 enum i915_power_well_id {
 103         DISP_PW_ID_NONE,
 104 
 105         VLV_DISP_PW_DISP2D,
 106         BXT_DISP_PW_DPIO_CMN_A,
 107         VLV_DISP_PW_DPIO_CMN_BC,
 108         GLK_DISP_PW_DPIO_CMN_C,
 109         CHV_DISP_PW_DPIO_CMN_D,
 110         HSW_DISP_PW_GLOBAL,
 111         SKL_DISP_PW_MISC_IO,
 112         SKL_DISP_PW_1,
 113         SKL_DISP_PW_2,
 114 };
 115 
 116 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 117 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 118                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 119 #define POWER_DOMAIN_TRANSCODER(tran) \
 120         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 121          (tran) + POWER_DOMAIN_TRANSCODER_A)
 122 
 123 struct i915_power_well;
 124 
 125 struct i915_power_well_ops {
 126         /*
 127          * Synchronize the well's hw state to match the current sw state, for
 128          * example enable/disable it based on the current refcount. Called
 129          * during driver init and resume time, possibly after first calling
 130          * the enable/disable handlers.
 131          */
 132         void (*sync_hw)(struct drm_i915_private *dev_priv,
 133                         struct i915_power_well *power_well);
 134         /*
 135          * Enable the well and resources that depend on it (for example
 136          * interrupts located on the well). Called after the 0->1 refcount
 137          * transition.
 138          */
 139         void (*enable)(struct drm_i915_private *dev_priv,
 140                        struct i915_power_well *power_well);
 141         /*
 142          * Disable the well and resources that depend on it. Called after
 143          * the 1->0 refcount transition.
 144          */
 145         void (*disable)(struct drm_i915_private *dev_priv,
 146                         struct i915_power_well *power_well);
 147         /* Returns the hw enabled state. */
 148         bool (*is_enabled)(struct drm_i915_private *dev_priv,
 149                            struct i915_power_well *power_well);
 150 };
 151 
 152 struct i915_power_well_regs {
 153         i915_reg_t bios;
 154         i915_reg_t driver;
 155         i915_reg_t kvmr;
 156         i915_reg_t debug;
 157 };
 158 
 159 /* Power well structure for haswell */
 160 struct i915_power_well_desc {
 161         const char *name;
 162         bool always_on;
 163         u64 domains;
 164         /* unique identifier for this power well */
 165         enum i915_power_well_id id;
 166         /*
 167          * Arbitraty data associated with this power well. Platform and power
 168          * well specific.
 169          */
 170         union {
 171                 struct {
 172                         /*
 173                          * request/status flag index in the PUNIT power well
 174                          * control/status registers.
 175                          */
 176                         u8 idx;
 177                 } vlv;
 178                 struct {
 179                         enum dpio_phy phy;
 180                 } bxt;
 181                 struct {
 182                         const struct i915_power_well_regs *regs;
 183                         /*
 184                          * request/status flag index in the power well
 185                          * constrol/status registers.
 186                          */
 187                         u8 idx;
 188                         /* Mask of pipes whose IRQ logic is backed by the pw */
 189                         u8 irq_pipe_mask;
 190                         /* The pw is backing the VGA functionality */
 191                         bool has_vga:1;
 192                         bool has_fuses:1;
 193                         /*
 194                          * The pw is for an ICL+ TypeC PHY port in
 195                          * Thunderbolt mode.
 196                          */
 197                         bool is_tc_tbt:1;
 198                 } hsw;
 199         };
 200         const struct i915_power_well_ops *ops;
 201 };
 202 
 203 struct i915_power_well {
 204         const struct i915_power_well_desc *desc;
 205         /* power well enable/disable usage count */
 206         int count;
 207         /* cached hw enabled state */
 208         bool hw_enabled;
 209 };
 210 
 211 struct i915_power_domains {
 212         /*
 213          * Power wells needed for initialization at driver init and suspend
 214          * time are on. They are kept on until after the first modeset.
 215          */
 216         bool initializing;
 217         bool display_core_suspended;
 218         int power_well_count;
 219 
 220         intel_wakeref_t wakeref;
 221 
 222         struct mutex lock;
 223         int domain_use_count[POWER_DOMAIN_NUM];
 224 
 225         struct delayed_work async_put_work;
 226         intel_wakeref_t async_put_wakeref;
 227         u64 async_put_domains[2];
 228 
 229         struct i915_power_well *power_wells;
 230 };
 231 
 232 #define for_each_power_domain(domain, mask)                             \
 233         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 234                 for_each_if(BIT_ULL(domain) & (mask))
 235 
 236 #define for_each_power_well(__dev_priv, __power_well)                           \
 237         for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
 238              (__power_well) - (__dev_priv)->power_domains.power_wells < \
 239                 (__dev_priv)->power_domains.power_well_count;           \
 240              (__power_well)++)
 241 
 242 #define for_each_power_well_reverse(__dev_priv, __power_well)                   \
 243         for ((__power_well) = (__dev_priv)->power_domains.power_wells +         \
 244                               (__dev_priv)->power_domains.power_well_count - 1; \
 245              (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;     \
 246              (__power_well)--)
 247 
 248 #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)     \
 249         for_each_power_well(__dev_priv, __power_well)                           \
 250                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 251 
 252 #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
 253         for_each_power_well_reverse(__dev_priv, __power_well)                   \
 254                 for_each_if((__power_well)->desc->domains & (__domain_mask))
 255 
 256 int intel_power_domains_init(struct drm_i915_private *dev_priv);
 257 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 258 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 259 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
 260 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 261 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 262 void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
 263                                  enum i915_drm_suspend_mode);
 264 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
 265 
 266 void intel_display_power_suspend_late(struct drm_i915_private *i915);
 267 void intel_display_power_resume_early(struct drm_i915_private *i915);
 268 void intel_display_power_suspend(struct drm_i915_private *i915);
 269 void intel_display_power_resume(struct drm_i915_private *i915);
 270 
 271 const char *
 272 intel_display_power_domain_str(struct drm_i915_private *i915,
 273                                enum intel_display_power_domain domain);
 274 
 275 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 276                                     enum intel_display_power_domain domain);
 277 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 278                                       enum intel_display_power_domain domain);
 279 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 280                                         enum intel_display_power_domain domain);
 281 intel_wakeref_t
 282 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 283                                    enum intel_display_power_domain domain);
 284 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 285                                        enum intel_display_power_domain domain);
 286 void __intel_display_power_put_async(struct drm_i915_private *i915,
 287                                      enum intel_display_power_domain domain,
 288                                      intel_wakeref_t wakeref);
 289 void intel_display_power_flush_work(struct drm_i915_private *i915);
 290 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 291 void intel_display_power_put(struct drm_i915_private *dev_priv,
 292                              enum intel_display_power_domain domain,
 293                              intel_wakeref_t wakeref);
 294 static inline void
 295 intel_display_power_put_async(struct drm_i915_private *i915,
 296                               enum intel_display_power_domain domain,
 297                               intel_wakeref_t wakeref)
 298 {
 299         __intel_display_power_put_async(i915, domain, wakeref);
 300 }
 301 #else
 302 static inline void
 303 intel_display_power_put(struct drm_i915_private *i915,
 304                         enum intel_display_power_domain domain,
 305                         intel_wakeref_t wakeref)
 306 {
 307         intel_display_power_put_unchecked(i915, domain);
 308 }
 309 
 310 static inline void
 311 intel_display_power_put_async(struct drm_i915_private *i915,
 312                               enum intel_display_power_domain domain,
 313                               intel_wakeref_t wakeref)
 314 {
 315         __intel_display_power_put_async(i915, domain, -1);
 316 }
 317 #endif
 318 
 319 #define with_intel_display_power(i915, domain, wf) \
 320         for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
 321              intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
 322 
 323 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
 324                             u8 req_slices);
 325 
 326 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
 327                              bool override, unsigned int mask);
 328 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
 329                           enum dpio_channel ch, bool override);
 330 
 331 #endif /* __INTEL_DISPLAY_POWER_H__ */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/i915/display/intel_display_power.h

INCLUDED FROM

DEFINITIONS
