root/drivers/gpu/drm/i915/display/intel_display_types.h

INCLUDED FROM

DEFINITIONS

1. vlv_dport_to_channel
2. vlv_dport_to_phy
3. vlv_pipe_to_channel
4. intel_get_crtc_for_pipe
5. intel_get_crtc_for_plane
6. intel_attached_encoder
7. intel_encoder_is_dig_port
8. enc_to_dig_port
9. conn_to_dig_port
10. enc_to_mst
11. enc_to_intel_dp
12. intel_encoder_is_dp
13. enc_to_intel_lspcon
14. dp_to_dig_port
15. dp_to_lspcon
16. dp_to_i915
17. hdmi_to_dig_port
18. intel_atomic_get_plane_state
19. intel_atomic_get_old_plane_state
20. intel_atomic_get_new_plane_state
21. intel_atomic_get_old_crtc_state
22. intel_atomic_get_new_crtc_state
23. intel_crtc_has_type
24. intel_crtc_has_dp_encoder
25. intel_wait_for_vblank
26. intel_wait_for_vblank_if_active
27. intel_plane_ggtt_offset

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 
  26 #ifndef __INTEL_DISPLAY_TYPES_H__
  27 #define __INTEL_DISPLAY_TYPES_H__
  28 
  29 #include <linux/async.h>
  30 #include <linux/i2c.h>
  31 #include <linux/sched/clock.h>
  32 
  33 #include <drm/drm_atomic.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_dp_dual_mode_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_encoder.h>
  38 #include <drm/drm_fb_helper.h>
  39 #include <drm/drm_probe_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_vblank.h>
  42 #include <drm/i915_drm.h>
  43 #include <drm/i915_mei_hdcp_interface.h>
  44 #include <media/cec-notifier.h>
  45 
  46 #include "i915_drv.h"
  47 
  48 struct drm_printer;
  49 
  50 /*
  51  * Display related stuff
  52  */
  53 
  54 /* these are outputs from the chip - integrated only
  55    external chips are via DVO or SDVO output */
  56 enum intel_output_type {
  57         INTEL_OUTPUT_UNUSED = 0,
  58         INTEL_OUTPUT_ANALOG = 1,
  59         INTEL_OUTPUT_DVO = 2,
  60         INTEL_OUTPUT_SDVO = 3,
  61         INTEL_OUTPUT_LVDS = 4,
  62         INTEL_OUTPUT_TVOUT = 5,
  63         INTEL_OUTPUT_HDMI = 6,
  64         INTEL_OUTPUT_DP = 7,
  65         INTEL_OUTPUT_EDP = 8,
  66         INTEL_OUTPUT_DSI = 9,
  67         INTEL_OUTPUT_DDI = 10,
  68         INTEL_OUTPUT_DP_MST = 11,
  69 };
  70 
  71 enum hdmi_force_audio {
  72         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
  73         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
  74         HDMI_AUDIO_AUTO,                /* trust EDID */
  75         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
  76 };
  77 
  78 /* "Broadcast RGB" property */
  79 enum intel_broadcast_rgb {
  80         INTEL_BROADCAST_RGB_AUTO,
  81         INTEL_BROADCAST_RGB_FULL,
  82         INTEL_BROADCAST_RGB_LIMITED,
  83 };
  84 
  85 struct intel_framebuffer {
  86         struct drm_framebuffer base;
  87         struct intel_frontbuffer *frontbuffer;
  88         struct intel_rotation_info rot_info;
  89 
  90         /* for each plane in the normal GTT view */
  91         struct {
  92                 unsigned int x, y;
  93         } normal[2];
  94         /* for each plane in the rotated GTT view */
  95         struct {
  96                 unsigned int x, y;
  97                 unsigned int pitch; /* pixels */
  98         } rotated[2];
  99 };
 100 
 101 struct intel_fbdev {
 102         struct drm_fb_helper helper;
 103         struct intel_framebuffer *fb;
 104         struct i915_vma *vma;
 105         unsigned long vma_flags;
 106         async_cookie_t cookie;
 107         int preferred_bpp;
 108 
 109         /* Whether or not fbdev hpd processing is temporarily suspended */
 110         bool hpd_suspended : 1;
 111         /* Set when a hotplug was received while HPD processing was
 112          * suspended
 113          */
 114         bool hpd_waiting : 1;
 115 
 116         /* Protects hpd_suspended */
 117         struct mutex hpd_lock;
 118 };
 119 
 120 enum intel_hotplug_state {
 121         INTEL_HOTPLUG_UNCHANGED,
 122         INTEL_HOTPLUG_CHANGED,
 123         INTEL_HOTPLUG_RETRY,
 124 };
 125 
 126 struct intel_encoder {
 127         struct drm_encoder base;
 128 
 129         enum intel_output_type type;
 130         enum port port;
 131         unsigned int cloneable;
 132         enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
 133                                             struct intel_connector *connector,
 134                                             bool irq_received);
 135         enum intel_output_type (*compute_output_type)(struct intel_encoder *,
 136                                                       struct intel_crtc_state *,
 137                                                       struct drm_connector_state *);
 138         int (*compute_config)(struct intel_encoder *,
 139                               struct intel_crtc_state *,
 140                               struct drm_connector_state *);
 141         void (*update_prepare)(struct intel_atomic_state *,
 142                                struct intel_encoder *,
 143                                struct intel_crtc *);
 144         void (*pre_pll_enable)(struct intel_encoder *,
 145                                const struct intel_crtc_state *,
 146                                const struct drm_connector_state *);
 147         void (*pre_enable)(struct intel_encoder *,
 148                            const struct intel_crtc_state *,
 149                            const struct drm_connector_state *);
 150         void (*enable)(struct intel_encoder *,
 151                        const struct intel_crtc_state *,
 152                        const struct drm_connector_state *);
 153         void (*update_complete)(struct intel_atomic_state *,
 154                                 struct intel_encoder *,
 155                                 struct intel_crtc *);
 156         void (*disable)(struct intel_encoder *,
 157                         const struct intel_crtc_state *,
 158                         const struct drm_connector_state *);
 159         void (*post_disable)(struct intel_encoder *,
 160                              const struct intel_crtc_state *,
 161                              const struct drm_connector_state *);
 162         void (*post_pll_disable)(struct intel_encoder *,
 163                                  const struct intel_crtc_state *,
 164                                  const struct drm_connector_state *);
 165         void (*update_pipe)(struct intel_encoder *,
 166                             const struct intel_crtc_state *,
 167                             const struct drm_connector_state *);
 168         /* Read out the current hw state of this connector, returning true if
 169          * the encoder is active. If the encoder is enabled it also set the pipe
 170          * it is connected to in the pipe parameter. */
 171         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 172         /* Reconstructs the equivalent mode flags for the current hardware
 173          * state. This must be called _after_ display->get_pipe_config has
 174          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 175          * be set correctly before calling this function. */
 176         void (*get_config)(struct intel_encoder *,
 177                            struct intel_crtc_state *pipe_config);
 178         /*
 179          * Acquires the power domains needed for an active encoder during
 180          * hardware state readout.
 181          */
 182         void (*get_power_domains)(struct intel_encoder *encoder,
 183                                   struct intel_crtc_state *crtc_state);
 184         /*
 185          * Called during system suspend after all pending requests for the
 186          * encoder are flushed (for example for DP AUX transactions) and
 187          * device interrupts are disabled.
 188          */
 189         void (*suspend)(struct intel_encoder *);
 190         int crtc_mask;
 191         enum hpd_pin hpd_pin;
 192         enum intel_display_power_domain power_domain;
 193         /* for communication with audio component; protected by av_mutex */
 194         const struct drm_connector *audio_connector;
 195 };
 196 
 197 struct intel_panel {
 198         struct drm_display_mode *fixed_mode;
 199         struct drm_display_mode *downclock_mode;
 200 
 201         /* backlight */
 202         struct {
 203                 bool present;
 204                 u32 level;
 205                 u32 min;
 206                 u32 max;
 207                 bool enabled;
 208                 bool combination_mode;  /* gen 2/4 only */
 209                 bool active_low_pwm;
 210                 bool alternate_pwm_increment;   /* lpt+ */
 211 
 212                 /* PWM chip */
 213                 bool util_pin_active_low;       /* bxt+ */
 214                 u8 controller;          /* bxt+ only */
 215                 struct pwm_device *pwm;
 216 
 217                 struct backlight_device *device;
 218 
 219                 /* Connector and platform specific backlight functions */
 220                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 221                 u32 (*get)(struct intel_connector *connector);
 222                 void (*set)(const struct drm_connector_state *conn_state, u32 level);
 223                 void (*disable)(const struct drm_connector_state *conn_state);
 224                 void (*enable)(const struct intel_crtc_state *crtc_state,
 225                                const struct drm_connector_state *conn_state);
 226                 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
 227                 void (*power)(struct intel_connector *, bool enable);
 228         } backlight;
 229 };
 230 
 231 struct intel_digital_port;
 232 
 233 enum check_link_response {
 234         HDCP_LINK_PROTECTED     = 0,
 235         HDCP_TOPOLOGY_CHANGE,
 236         HDCP_LINK_INTEGRITY_FAILURE,
 237         HDCP_REAUTH_REQUEST
 238 };
 239 
 240 /*
 241  * This structure serves as a translation layer between the generic HDCP code
 242  * and the bus-specific code. What that means is that HDCP over HDMI differs
 243  * from HDCP over DP, so to account for these differences, we need to
 244  * communicate with the receiver through this shim.
 245  *
 246  * For completeness, the 2 buses differ in the following ways:
 247  *      - DP AUX vs. DDC
 248  *              HDCP registers on the receiver are set via DP AUX for DP, and
 249  *              they are set via DDC for HDMI.
 250  *      - Receiver register offsets
 251  *              The offsets of the registers are different for DP vs. HDMI
 252  *      - Receiver register masks/offsets
 253  *              For instance, the ready bit for the KSV fifo is in a different
 254  *              place on DP vs HDMI
 255  *      - Receiver register names
 256  *              Seriously. In the DP spec, the 16-bit register containing
 257  *              downstream information is called BINFO, on HDMI it's called
 258  *              BSTATUS. To confuse matters further, DP has a BSTATUS register
 259  *              with a completely different definition.
 260  *      - KSV FIFO
 261  *              On HDMI, the ksv fifo is read all at once, whereas on DP it must
 262  *              be read 3 keys at a time
 263  *      - Aksv output
 264  *              Since Aksv is hidden in hardware, there's different procedures
 265  *              to send it over DP AUX vs DDC
 266  */
 267 struct intel_hdcp_shim {
 268         /* Outputs the transmitter's An and Aksv values to the receiver. */
 269         int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
 270 
 271         /* Reads the receiver's key selection vector */
 272         int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
 273 
 274         /*
 275          * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
 276          * definitions are the same in the respective specs, but the names are
 277          * different. Call it BSTATUS since that's the name the HDMI spec
 278          * uses and it was there first.
 279          */
 280         int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
 281                             u8 *bstatus);
 282 
 283         /* Determines whether a repeater is present downstream */
 284         int (*repeater_present)(struct intel_digital_port *intel_dig_port,
 285                                 bool *repeater_present);
 286 
 287         /* Reads the receiver's Ri' value */
 288         int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
 289 
 290         /* Determines if the receiver's KSV FIFO is ready for consumption */
 291         int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
 292                               bool *ksv_ready);
 293 
 294         /* Reads the ksv fifo for num_downstream devices */
 295         int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
 296                              int num_downstream, u8 *ksv_fifo);
 297 
 298         /* Reads a 32-bit part of V' from the receiver */
 299         int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
 300                                  int i, u32 *part);
 301 
 302         /* Enables HDCP signalling on the port */
 303         int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
 304                                  bool enable);
 305 
 306         /* Ensures the link is still protected */
 307         bool (*check_link)(struct intel_digital_port *intel_dig_port);
 308 
 309         /* Detects panel's hdcp capability. This is optional for HDMI. */
 310         int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
 311                             bool *hdcp_capable);
 312 
 313         /* HDCP adaptation(DP/HDMI) required on the port */
 314         enum hdcp_wired_protocol protocol;
 315 
 316         /* Detects whether sink is HDCP2.2 capable */
 317         int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
 318                                 bool *capable);
 319 
 320         /* Write HDCP2.2 messages */
 321         int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
 322                              void *buf, size_t size);
 323 
 324         /* Read HDCP2.2 messages */
 325         int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
 326                             u8 msg_id, void *buf, size_t size);
 327 
 328         /*
 329          * Implementation of DP HDCP2.2 Errata for the communication of stream
 330          * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
 331          * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
 332          */
 333         int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
 334                                   bool is_repeater, u8 type);
 335 
 336         /* HDCP2.2 Link Integrity Check */
 337         int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
 338 };
 339 
 340 struct intel_hdcp {
 341         const struct intel_hdcp_shim *shim;
 342         /* Mutex for hdcp state of the connector */
 343         struct mutex mutex;
 344         u64 value;
 345         struct delayed_work check_work;
 346         struct work_struct prop_work;
 347 
 348         /* HDCP1.4 Encryption status */
 349         bool hdcp_encrypted;
 350 
 351         /* HDCP2.2 related definitions */
 352         /* Flag indicates whether this connector supports HDCP2.2 or not. */
 353         bool hdcp2_supported;
 354 
 355         /* HDCP2.2 Encryption status */
 356         bool hdcp2_encrypted;
 357 
 358         /*
 359          * Content Stream Type defined by content owner. TYPE0(0x0) content can
 360          * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
 361          * content can flow only through a link protected by HDCP2.2.
 362          */
 363         u8 content_type;
 364         struct hdcp_port_data port_data;
 365 
 366         bool is_paired;
 367         bool is_repeater;
 368 
 369         /*
 370          * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
 371          * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
 372          * When it rolls over re-auth has to be triggered.
 373          */
 374         u32 seq_num_v;
 375 
 376         /*
 377          * Count of RepeaterAuth_Stream_Manage msg propagated.
 378          * Initialized to 0 on AKE_INIT. Incremented after every successful
 379          * transmission of RepeaterAuth_Stream_Manage message. When it rolls
 380          * over re-Auth has to be triggered.
 381          */
 382         u32 seq_num_m;
 383 
 384         /*
 385          * Work queue to signal the CP_IRQ. Used for the waiters to read the
 386          * available information from HDCP DP sink.
 387          */
 388         wait_queue_head_t cp_irq_queue;
 389         atomic_t cp_irq_count;
 390         int cp_irq_count_cached;
 391 };
 392 
 393 struct intel_connector {
 394         struct drm_connector base;
 395         /*
 396          * The fixed encoder this connector is connected to.
 397          */
 398         struct intel_encoder *encoder;
 399 
 400         /* ACPI device id for ACPI and driver cooperation */
 401         u32 acpi_device_id;
 402 
 403         /* Reads out the current hw, returning true if the connector is enabled
 404          * and active (i.e. dpms ON state). */
 405         bool (*get_hw_state)(struct intel_connector *);
 406 
 407         /* Panel info for eDP and LVDS */
 408         struct intel_panel panel;
 409 
 410         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 411         struct edid *edid;
 412         struct edid *detect_edid;
 413 
 414         /* since POLL and HPD connectors may use the same HPD line keep the native
 415            state of connector->polled in case hotplug storm detection changes it */
 416         u8 polled;
 417 
 418         void *port; /* store this opaque as its illegal to dereference it */
 419 
 420         struct intel_dp *mst_port;
 421 
 422         /* Work struct to schedule a uevent on link train failure */
 423         struct work_struct modeset_retry_work;
 424 
 425         struct intel_hdcp hdcp;
 426 };
 427 
 428 struct intel_digital_connector_state {
 429         struct drm_connector_state base;
 430 
 431         enum hdmi_force_audio force_audio;
 432         int broadcast_rgb;
 433 };
 434 
 435 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 436 
 437 struct dpll {
 438         /* given values */
 439         int n;
 440         int m1, m2;
 441         int p1, p2;
 442         /* derived values */
 443         int     dot;
 444         int     vco;
 445         int     m;
 446         int     p;
 447 };
 448 
 449 struct intel_atomic_state {
 450         struct drm_atomic_state base;
 451 
 452         intel_wakeref_t wakeref;
 453 
 454         struct {
 455                 /*
 456                  * Logical state of cdclk (used for all scaling, watermark,
 457                  * etc. calculations and checks). This is computed as if all
 458                  * enabled crtcs were active.
 459                  */
 460                 struct intel_cdclk_state logical;
 461 
 462                 /*
 463                  * Actual state of cdclk, can be different from the logical
 464                  * state only when all crtc's are DPMS off.
 465                  */
 466                 struct intel_cdclk_state actual;
 467 
 468                 int force_min_cdclk;
 469                 bool force_min_cdclk_changed;
 470                 /* pipe to which cd2x update is synchronized */
 471                 enum pipe pipe;
 472         } cdclk;
 473 
 474         bool dpll_set, modeset;
 475 
 476         /*
 477          * Does this transaction change the pipes that are active?  This mask
 478          * tracks which CRTC's have changed their active state at the end of
 479          * the transaction (not counting the temporary disable during modesets).
 480          * This mask should only be non-zero when intel_state->modeset is true,
 481          * but the converse is not necessarily true; simply changing a mode may
 482          * not flip the final active status of any CRTC's
 483          */
 484         unsigned int active_pipe_changes;
 485 
 486         unsigned int active_crtcs;
 487         /* minimum acceptable cdclk for each pipe */
 488         int min_cdclk[I915_MAX_PIPES];
 489         /* minimum acceptable voltage level for each pipe */
 490         u8 min_voltage_level[I915_MAX_PIPES];
 491 
 492         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 493 
 494         /*
 495          * Current watermarks can't be trusted during hardware readout, so
 496          * don't bother calculating intermediate watermarks.
 497          */
 498         bool skip_intermediate_wm;
 499 
 500         bool rps_interactive;
 501 
 502         /* Gen9+ only */
 503         struct skl_ddb_values wm_results;
 504 
 505         struct i915_sw_fence commit_ready;
 506 
 507         struct llist_node freed;
 508 };
 509 
 510 struct intel_plane_state {
 511         struct drm_plane_state base;
 512         struct i915_ggtt_view view;
 513         struct i915_vma *vma;
 514         unsigned long flags;
 515 #define PLANE_HAS_FENCE BIT(0)
 516 
 517         struct {
 518                 u32 offset;
 519                 /*
 520                  * Plane stride in:
 521                  * bytes for 0/180 degree rotation
 522                  * pixels for 90/270 degree rotation
 523                  */
 524                 u32 stride;
 525                 int x, y;
 526         } color_plane[2];
 527 
 528         /* plane control register */
 529         u32 ctl;
 530 
 531         /* plane color control register */
 532         u32 color_ctl;
 533 
 534         /*
 535          * scaler_id
 536          *    = -1 : not using a scaler
 537          *    >=  0 : using a scalers
 538          *
 539          * plane requiring a scaler:
 540          *   - During check_plane, its bit is set in
 541          *     crtc_state->scaler_state.scaler_users by calling helper function
 542          *     update_scaler_plane.
 543          *   - scaler_id indicates the scaler it got assigned.
 544          *
 545          * plane doesn't require a scaler:
 546          *   - this can happen when scaling is no more required or plane simply
 547          *     got disabled.
 548          *   - During check_plane, corresponding bit is reset in
 549          *     crtc_state->scaler_state.scaler_users by calling helper function
 550          *     update_scaler_plane.
 551          */
 552         int scaler_id;
 553 
 554         /*
 555          * linked_plane:
 556          *
 557          * ICL planar formats require 2 planes that are updated as pairs.
 558          * This member is used to make sure the other plane is also updated
 559          * when required, and for update_slave() to find the correct
 560          * plane_state to pass as argument.
 561          */
 562         struct intel_plane *linked_plane;
 563 
 564         /*
 565          * slave:
 566          * If set don't update use the linked plane's state for updating
 567          * this plane during atomic commit with the update_slave() callback.
 568          *
 569          * It's also used by the watermark code to ignore wm calculations on
 570          * this plane. They're calculated by the linked plane's wm code.
 571          */
 572         u32 slave;
 573 
 574         struct drm_intel_sprite_colorkey ckey;
 575 };
 576 
 577 struct intel_initial_plane_config {
 578         struct intel_framebuffer *fb;
 579         unsigned int tiling;
 580         int size;
 581         u32 base;
 582         u8 rotation;
 583 };
 584 
 585 struct intel_scaler {
 586         int in_use;
 587         u32 mode;
 588 };
 589 
 590 struct intel_crtc_scaler_state {
 591 #define SKL_NUM_SCALERS 2
 592         struct intel_scaler scalers[SKL_NUM_SCALERS];
 593 
 594         /*
 595          * scaler_users: keeps track of users requesting scalers on this crtc.
 596          *
 597          *     If a bit is set, a user is using a scaler.
 598          *     Here user can be a plane or crtc as defined below:
 599          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 600          *       bit 31    - crtc
 601          *
 602          * Instead of creating a new index to cover planes and crtc, using
 603          * existing drm_plane_index for planes which is well less than 31
 604          * planes and bit 31 for crtc. This should be fine to cover all
 605          * our platforms.
 606          *
 607          * intel_atomic_setup_scalers will setup available scalers to users
 608          * requesting scalers. It will gracefully fail if request exceeds
 609          * avilability.
 610          */
 611 #define SKL_CRTC_INDEX 31
 612         unsigned scaler_users;
 613 
 614         /* scaler used by crtc for panel fitting purpose */
 615         int scaler_id;
 616 };
 617 
 618 /* drm_mode->private_flags */
 619 #define I915_MODE_FLAG_INHERITED (1<<0)
 620 /* Flag to get scanline using frame time stamps */
 621 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
 622 /* Flag to use the scanline counter instead of the pixel counter */
 623 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
 624 
 625 struct intel_pipe_wm {
 626         struct intel_wm_level wm[5];
 627         u32 linetime;
 628         bool fbc_wm_enabled;
 629         bool pipe_enabled;
 630         bool sprites_enabled;
 631         bool sprites_scaled;
 632 };
 633 
 634 struct skl_plane_wm {
 635         struct skl_wm_level wm[8];
 636         struct skl_wm_level uv_wm[8];
 637         struct skl_wm_level trans_wm;
 638         bool is_planar;
 639 };
 640 
 641 struct skl_pipe_wm {
 642         struct skl_plane_wm planes[I915_MAX_PLANES];
 643         u32 linetime;
 644 };
 645 
 646 enum vlv_wm_level {
 647         VLV_WM_LEVEL_PM2,
 648         VLV_WM_LEVEL_PM5,
 649         VLV_WM_LEVEL_DDR_DVFS,
 650         NUM_VLV_WM_LEVELS,
 651 };
 652 
 653 struct vlv_wm_state {
 654         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 655         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 656         u8 num_levels;
 657         bool cxsr;
 658 };
 659 
 660 struct vlv_fifo_state {
 661         u16 plane[I915_MAX_PLANES];
 662 };
 663 
 664 enum g4x_wm_level {
 665         G4X_WM_LEVEL_NORMAL,
 666         G4X_WM_LEVEL_SR,
 667         G4X_WM_LEVEL_HPLL,
 668         NUM_G4X_WM_LEVELS,
 669 };
 670 
 671 struct g4x_wm_state {
 672         struct g4x_pipe_wm wm;
 673         struct g4x_sr_wm sr;
 674         struct g4x_sr_wm hpll;
 675         bool cxsr;
 676         bool hpll_en;
 677         bool fbc_en;
 678 };
 679 
 680 struct intel_crtc_wm_state {
 681         union {
 682                 struct {
 683                         /*
 684                          * Intermediate watermarks; these can be
 685                          * programmed immediately since they satisfy
 686                          * both the current configuration we're
 687                          * switching away from and the new
 688                          * configuration we're switching to.
 689                          */
 690                         struct intel_pipe_wm intermediate;
 691 
 692                         /*
 693                          * Optimal watermarks, programmed post-vblank
 694                          * when this state is committed.
 695                          */
 696                         struct intel_pipe_wm optimal;
 697                 } ilk;
 698 
 699                 struct {
 700                         /* gen9+ only needs 1-step wm programming */
 701                         struct skl_pipe_wm optimal;
 702                         struct skl_ddb_entry ddb;
 703                         struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
 704                         struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
 705                 } skl;
 706 
 707                 struct {
 708                         /* "raw" watermarks (not inverted) */
 709                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 710                         /* intermediate watermarks (inverted) */
 711                         struct vlv_wm_state intermediate;
 712                         /* optimal watermarks (inverted) */
 713                         struct vlv_wm_state optimal;
 714                         /* display FIFO split */
 715                         struct vlv_fifo_state fifo_state;
 716                 } vlv;
 717 
 718                 struct {
 719                         /* "raw" watermarks */
 720                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 721                         /* intermediate watermarks */
 722                         struct g4x_wm_state intermediate;
 723                         /* optimal watermarks */
 724                         struct g4x_wm_state optimal;
 725                 } g4x;
 726         };
 727 
 728         /*
 729          * Platforms with two-step watermark programming will need to
 730          * update watermark programming post-vblank to switch from the
 731          * safe intermediate watermarks to the optimal final
 732          * watermarks.
 733          */
 734         bool need_postvbl_update;
 735 };
 736 
 737 enum intel_output_format {
 738         INTEL_OUTPUT_FORMAT_INVALID,
 739         INTEL_OUTPUT_FORMAT_RGB,
 740         INTEL_OUTPUT_FORMAT_YCBCR420,
 741         INTEL_OUTPUT_FORMAT_YCBCR444,
 742 };
 743 
 744 struct intel_crtc_state {
 745         struct drm_crtc_state base;
 746 
 747         /**
 748          * quirks - bitfield with hw state readout quirks
 749          *
 750          * For various reasons the hw state readout code might not be able to
 751          * completely faithfully read out the current state. These cases are
 752          * tracked with quirk flags so that fastboot and state checker can act
 753          * accordingly.
 754          */
 755 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 756         unsigned long quirks;
 757 
 758         unsigned fb_bits; /* framebuffers to flip */
 759         bool update_pipe; /* can a fast modeset be performed? */
 760         bool disable_cxsr;
 761         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 762         bool fb_changed; /* fb on any of the planes is changed */
 763         bool fifo_changed; /* FIFO split is changed */
 764         bool preload_luts;
 765 
 766         /* Pipe source size (ie. panel fitter input size)
 767          * All planes will be positioned inside this space,
 768          * and get clipped at the edges. */
 769         int pipe_src_w, pipe_src_h;
 770 
 771         /*
 772          * Pipe pixel rate, adjusted for
 773          * panel fitter/pipe scaler downscaling.
 774          */
 775         unsigned int pixel_rate;
 776 
 777         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 778          * between pch encoders and cpu encoders. */
 779         bool has_pch_encoder;
 780 
 781         /* Are we sending infoframes on the attached port */
 782         bool has_infoframe;
 783 
 784         /* CPU Transcoder for the pipe. Currently this can only differ from the
 785          * pipe on Haswell and later (where we have a special eDP transcoder)
 786          * and Broxton (where we have special DSI transcoders). */
 787         enum transcoder cpu_transcoder;
 788 
 789         /*
 790          * Use reduced/limited/broadcast rbg range, compressing from the full
 791          * range fed into the crtcs.
 792          */
 793         bool limited_color_range;
 794 
 795         /* Bitmask of encoder types (enum intel_output_type)
 796          * driven by the pipe.
 797          */
 798         unsigned int output_types;
 799 
 800         /* Whether we should send NULL infoframes. Required for audio. */
 801         bool has_hdmi_sink;
 802 
 803         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 804          * has_dp_encoder is set. */
 805         bool has_audio;
 806 
 807         /*
 808          * Enable dithering, used when the selected pipe bpp doesn't match the
 809          * plane bpp.
 810          */
 811         bool dither;
 812 
 813         /*
 814          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 815          * compliance video pattern tests.
 816          * Disable dither only if it is a compliance test request for
 817          * 18bpp.
 818          */
 819         bool dither_force_disable;
 820 
 821         /* Controls for the clock computation, to override various stages. */
 822         bool clock_set;
 823 
 824         /* SDVO TV has a bunch of special case. To make multifunction encoders
 825          * work correctly, we need to track this at runtime.*/
 826         bool sdvo_tv_clock;
 827 
 828         /*
 829          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 830          * required. This is set in the 2nd loop of calling encoder's
 831          * ->compute_config if the first pick doesn't work out.
 832          */
 833         bool bw_constrained;
 834 
 835         /* Settings for the intel dpll used on pretty much everything but
 836          * haswell. */
 837         struct dpll dpll;
 838 
 839         /* Selected dpll when shared or NULL. */
 840         struct intel_shared_dpll *shared_dpll;
 841 
 842         /* Actual register state of the dpll, for shared dpll cross-checking. */
 843         struct intel_dpll_hw_state dpll_hw_state;
 844 
 845         /*
 846          * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
 847          * setting shared_dpll and dpll_hw_state to one of these reserved ones.
 848          */
 849         struct icl_port_dpll {
 850                 struct intel_shared_dpll *pll;
 851                 struct intel_dpll_hw_state hw_state;
 852         } icl_port_dplls[ICL_PORT_DPLL_COUNT];
 853 
 854         /* DSI PLL registers */
 855         struct {
 856                 u32 ctrl, div;
 857         } dsi_pll;
 858 
 859         int pipe_bpp;
 860         struct intel_link_m_n dp_m_n;
 861 
 862         /* m2_n2 for eDP downclock */
 863         struct intel_link_m_n dp_m2_n2;
 864         bool has_drrs;
 865 
 866         bool has_psr;
 867         bool has_psr2;
 868 
 869         /*
 870          * Frequence the dpll for the port should run at. Differs from the
 871          * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
 872          * already multiplied by pixel_multiplier.
 873          */
 874         int port_clock;
 875 
 876         /* Used by SDVO (and if we ever fix it, HDMI). */
 877         unsigned pixel_multiplier;
 878 
 879         u8 lane_count;
 880 
 881         /*
 882          * Used by platforms having DP/HDMI PHY with programmable lane
 883          * latency optimization.
 884          */
 885         u8 lane_lat_optim_mask;
 886 
 887         /* minimum acceptable voltage level */
 888         u8 min_voltage_level;
 889 
 890         /* Panel fitter controls for gen2-gen4 + VLV */
 891         struct {
 892                 u32 control;
 893                 u32 pgm_ratios;
 894                 u32 lvds_border_bits;
 895         } gmch_pfit;
 896 
 897         /* Panel fitter placement and size for Ironlake+ */
 898         struct {
 899                 u32 pos;
 900                 u32 size;
 901                 bool enabled;
 902                 bool force_thru;
 903         } pch_pfit;
 904 
 905         /* FDI configuration, only valid if has_pch_encoder is set. */
 906         int fdi_lanes;
 907         struct intel_link_m_n fdi_m_n;
 908 
 909         bool ips_enabled;
 910 
 911         bool crc_enabled;
 912 
 913         bool enable_fbc;
 914 
 915         bool double_wide;
 916 
 917         int pbn;
 918 
 919         struct intel_crtc_scaler_state scaler_state;
 920 
 921         /* w/a for waiting 2 vblanks during crtc enable */
 922         enum pipe hsw_workaround_pipe;
 923 
 924         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 925         bool disable_lp_wm;
 926 
 927         struct intel_crtc_wm_state wm;
 928 
 929         u32 data_rate[I915_MAX_PLANES];
 930 
 931         /* Gamma mode programmed on the pipe */
 932         u32 gamma_mode;
 933 
 934         union {
 935                 /* CSC mode programmed on the pipe */
 936                 u32 csc_mode;
 937 
 938                 /* CHV CGM mode */
 939                 u32 cgm_mode;
 940         };
 941 
 942         /* bitmask of visible planes (enum plane_id) */
 943         u8 active_planes;
 944         u8 nv12_planes;
 945         u8 c8_planes;
 946 
 947         /* bitmask of planes that will be updated during the commit */
 948         u8 update_planes;
 949 
 950         struct {
 951                 u32 enable;
 952                 u32 gcp;
 953                 union hdmi_infoframe avi;
 954                 union hdmi_infoframe spd;
 955                 union hdmi_infoframe hdmi;
 956                 union hdmi_infoframe drm;
 957         } infoframes;
 958 
 959         /* HDMI scrambling status */
 960         bool hdmi_scrambling;
 961 
 962         /* HDMI High TMDS char rate ratio */
 963         bool hdmi_high_tmds_clock_ratio;
 964 
 965         /* Output format RGB/YCBCR etc */
 966         enum intel_output_format output_format;
 967 
 968         /* Output down scaling is done in LSPCON device */
 969         bool lspcon_downsampling;
 970 
 971         /* enable pipe gamma? */
 972         bool gamma_enable;
 973 
 974         /* enable pipe csc? */
 975         bool csc_enable;
 976 
 977         /* Display Stream compression state */
 978         struct {
 979                 bool compression_enable;
 980                 bool dsc_split;
 981                 u16 compressed_bpp;
 982                 u8 slice_count;
 983         } dsc_params;
 984         struct drm_dsc_config dp_dsc_cfg;
 985 
 986         /* Forward Error correction State */
 987         bool fec_enable;
 988 };
 989 
 990 struct intel_crtc {
 991         struct drm_crtc base;
 992         enum pipe pipe;
 993         /*
 994          * Whether the crtc and the connected output pipeline is active. Implies
 995          * that crtc->enabled is set, i.e. the current mode configuration has
 996          * some outputs connected to this crtc.
 997          */
 998         bool active;
 999         u8 plane_ids_mask;
1000         unsigned long long enabled_power_domains;
1001         struct intel_overlay *overlay;
1002 
1003         struct intel_crtc_state *config;
1004 
1005         /* Access to these should be protected by dev_priv->irq_lock. */
1006         bool cpu_fifo_underrun_disabled;
1007         bool pch_fifo_underrun_disabled;
1008 
1009         /* per-pipe watermark state */
1010         struct {
1011                 /* watermarks currently being used  */
1012                 union {
1013                         struct intel_pipe_wm ilk;
1014                         struct vlv_wm_state vlv;
1015                         struct g4x_wm_state g4x;
1016                 } active;
1017         } wm;
1018 
1019         int scanline_offset;
1020 
1021         struct {
1022                 unsigned start_vbl_count;
1023                 ktime_t start_vbl_time;
1024                 int min_vbl, max_vbl;
1025                 int scanline_start;
1026         } debug;
1027 
1028         /* scalers available on this crtc */
1029         int num_scalers;
1030 };
1031 
1032 struct intel_plane {
1033         struct drm_plane base;
1034         enum i9xx_plane_id i9xx_plane;
1035         enum plane_id id;
1036         enum pipe pipe;
1037         bool has_fbc;
1038         bool has_ccs;
1039         u32 frontbuffer_bit;
1040 
1041         struct {
1042                 u32 base, cntl, size;
1043         } cursor;
1044 
1045         /*
1046          * NOTE: Do not place new plane state fields here (e.g., when adding
1047          * new plane properties).  New runtime state should now be placed in
1048          * the intel_plane_state structure and accessed via plane_state.
1049          */
1050 
1051         unsigned int (*max_stride)(struct intel_plane *plane,
1052                                    u32 pixel_format, u64 modifier,
1053                                    unsigned int rotation);
1054         void (*update_plane)(struct intel_plane *plane,
1055                              const struct intel_crtc_state *crtc_state,
1056                              const struct intel_plane_state *plane_state);
1057         void (*update_slave)(struct intel_plane *plane,
1058                              const struct intel_crtc_state *crtc_state,
1059                              const struct intel_plane_state *plane_state);
1060         void (*disable_plane)(struct intel_plane *plane,
1061                               const struct intel_crtc_state *crtc_state);
1062         bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1063         int (*check_plane)(struct intel_crtc_state *crtc_state,
1064                            struct intel_plane_state *plane_state);
1065 };
1066 
1067 struct intel_watermark_params {
1068         u16 fifo_size;
1069         u16 max_wm;
1070         u8 default_wm;
1071         u8 guard_size;
1072         u8 cacheline_size;
1073 };
1074 
1075 struct cxsr_latency {
1076         bool is_desktop : 1;
1077         bool is_ddr3 : 1;
1078         u16 fsb_freq;
1079         u16 mem_freq;
1080         u16 display_sr;
1081         u16 display_hpll_disable;
1082         u16 cursor_sr;
1083         u16 cursor_hpll_disable;
1084 };
1085 
1086 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1087 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1088 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1089 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1090 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1091 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1092 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1093 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1094 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1095 
1096 struct intel_hdmi {
1097         i915_reg_t hdmi_reg;
1098         int ddc_bus;
1099         struct {
1100                 enum drm_dp_dual_mode_type type;
1101                 int max_tmds_clock;
1102         } dp_dual_mode;
1103         bool has_hdmi_sink;
1104         bool has_audio;
1105         struct intel_connector *attached_connector;
1106         struct cec_notifier *cec_notifier;
1107 };
1108 
1109 struct intel_dp_mst_encoder;
1110 #define DP_MAX_DOWNSTREAM_PORTS         0x10
1111 
1112 /*
1113  * enum link_m_n_set:
1114  *      When platform provides two set of M_N registers for dp, we can
1115  *      program them and switch between them incase of DRRS.
1116  *      But When only one such register is provided, we have to program the
1117  *      required divider value on that registers itself based on the DRRS state.
1118  *
1119  * M1_N1        : Program dp_m_n on M1_N1 registers
1120  *                        dp_m2_n2 on M2_N2 registers (If supported)
1121  *
1122  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
1123  *                        M2_N2 registers are not supported
1124  */
1125 
1126 enum link_m_n_set {
1127         /* Sets the m1_n1 and m2_n2 */
1128         M1_N1 = 0,
1129         M2_N2
1130 };
1131 
1132 struct intel_dp_compliance_data {
1133         unsigned long edid;
1134         u8 video_pattern;
1135         u16 hdisplay, vdisplay;
1136         u8 bpc;
1137 };
1138 
1139 struct intel_dp_compliance {
1140         unsigned long test_type;
1141         struct intel_dp_compliance_data test_data;
1142         bool test_active;
1143         int test_link_rate;
1144         u8 test_lane_count;
1145 };
1146 
1147 struct intel_dp {
1148         i915_reg_t output_reg;
1149         u32 DP;
1150         int link_rate;
1151         u8 lane_count;
1152         u8 sink_count;
1153         bool link_mst;
1154         bool link_trained;
1155         bool has_audio;
1156         bool reset_link_params;
1157         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1158         u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1159         u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1160         u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1161         u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1162         u8 fec_capable;
1163         /* source rates */
1164         int num_source_rates;
1165         const int *source_rates;
1166         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1167         int num_sink_rates;
1168         int sink_rates[DP_MAX_SUPPORTED_RATES];
1169         bool use_rate_select;
1170         /* intersection of source and sink rates */
1171         int num_common_rates;
1172         int common_rates[DP_MAX_SUPPORTED_RATES];
1173         /* Max lane count for the current link */
1174         int max_link_lane_count;
1175         /* Max rate for the current link */
1176         int max_link_rate;
1177         /* sink or branch descriptor */
1178         struct drm_dp_desc desc;
1179         struct drm_dp_aux aux;
1180         u8 train_set[4];
1181         int panel_power_up_delay;
1182         int panel_power_down_delay;
1183         int panel_power_cycle_delay;
1184         int backlight_on_delay;
1185         int backlight_off_delay;
1186         struct delayed_work panel_vdd_work;
1187         bool want_panel_vdd;
1188         unsigned long last_power_on;
1189         unsigned long last_backlight_off;
1190         ktime_t panel_power_off_time;
1191 
1192         struct notifier_block edp_notifier;
1193 
1194         /*
1195          * Pipe whose power sequencer is currently locked into
1196          * this port. Only relevant on VLV/CHV.
1197          */
1198         enum pipe pps_pipe;
1199         /*
1200          * Pipe currently driving the port. Used for preventing
1201          * the use of the PPS for any pipe currentrly driving
1202          * external DP as that will mess things up on VLV.
1203          */
1204         enum pipe active_pipe;
1205         /*
1206          * Set if the sequencer may be reset due to a power transition,
1207          * requiring a reinitialization. Only relevant on BXT.
1208          */
1209         bool pps_reset;
1210         struct edp_power_seq pps_delays;
1211 
1212         bool can_mst; /* this port supports mst */
1213         bool is_mst;
1214         int active_mst_links;
1215         /* connector directly attached - won't be use for modeset in mst world */
1216         struct intel_connector *attached_connector;
1217 
1218         /* mst connector list */
1219         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1220         struct drm_dp_mst_topology_mgr mst_mgr;
1221 
1222         u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1223         /*
1224          * This function returns the value we have to program the AUX_CTL
1225          * register with to kick off an AUX transaction.
1226          */
1227         u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1228                                 u32 aux_clock_divider);
1229 
1230         i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1231         i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1232 
1233         /* This is called before a link training is starterd */
1234         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1235 
1236         /* Displayport compliance testing */
1237         struct intel_dp_compliance compliance;
1238 
1239         /* Display stream compression testing */
1240         bool force_dsc_en;
1241 };
1242 
1243 enum lspcon_vendor {
1244         LSPCON_VENDOR_MCA,
1245         LSPCON_VENDOR_PARADE
1246 };
1247 
1248 struct intel_lspcon {
1249         bool active;
1250         enum drm_lspcon_mode mode;
1251         enum lspcon_vendor vendor;
1252 };
1253 
1254 struct intel_digital_port {
1255         struct intel_encoder base;
1256         u32 saved_port_bits;
1257         struct intel_dp dp;
1258         struct intel_hdmi hdmi;
1259         struct intel_lspcon lspcon;
1260         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1261         bool release_cl2_override;
1262         u8 max_lanes;
1263         /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1264         enum aux_ch aux_ch;
1265         enum intel_display_power_domain ddi_io_power_domain;
1266         struct mutex tc_lock;   /* protects the TypeC port mode */
1267         intel_wakeref_t tc_lock_wakeref;
1268         int tc_link_refcount;
1269         bool tc_legacy_port:1;
1270         char tc_port_name[8];
1271         enum tc_port_mode tc_mode;
1272         enum phy_fia tc_phy_fia;
1273 
1274         void (*write_infoframe)(struct intel_encoder *encoder,
1275                                 const struct intel_crtc_state *crtc_state,
1276                                 unsigned int type,
1277                                 const void *frame, ssize_t len);
1278         void (*read_infoframe)(struct intel_encoder *encoder,
1279                                const struct intel_crtc_state *crtc_state,
1280                                unsigned int type,
1281                                void *frame, ssize_t len);
1282         void (*set_infoframes)(struct intel_encoder *encoder,
1283                                bool enable,
1284                                const struct intel_crtc_state *crtc_state,
1285                                const struct drm_connector_state *conn_state);
1286         u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1287                                   const struct intel_crtc_state *pipe_config);
1288 };
1289 
1290 struct intel_dp_mst_encoder {
1291         struct intel_encoder base;
1292         enum pipe pipe;
1293         struct intel_digital_port *primary;
1294         struct intel_connector *connector;
1295 };
1296 
1297 static inline enum dpio_channel
1298 vlv_dport_to_channel(struct intel_digital_port *dport)
1299 {
1300         switch (dport->base.port) {
1301         case PORT_B:
1302         case PORT_D:
1303                 return DPIO_CH0;
1304         case PORT_C:
1305                 return DPIO_CH1;
1306         default:
1307                 BUG();
1308         }
1309 }
1310 
1311 static inline enum dpio_phy
1312 vlv_dport_to_phy(struct intel_digital_port *dport)
1313 {
1314         switch (dport->base.port) {
1315         case PORT_B:
1316         case PORT_C:
1317                 return DPIO_PHY0;
1318         case PORT_D:
1319                 return DPIO_PHY1;
1320         default:
1321                 BUG();
1322         }
1323 }
1324 
1325 static inline enum dpio_channel
1326 vlv_pipe_to_channel(enum pipe pipe)
1327 {
1328         switch (pipe) {
1329         case PIPE_A:
1330         case PIPE_C:
1331                 return DPIO_CH0;
1332         case PIPE_B:
1333                 return DPIO_CH1;
1334         default:
1335                 BUG();
1336         }
1337 }
1338 
1339 static inline struct intel_crtc *
1340 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1341 {
1342         return dev_priv->pipe_to_crtc_mapping[pipe];
1343 }
1344 
1345 static inline struct intel_crtc *
1346 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1347 {
1348         return dev_priv->plane_to_crtc_mapping[plane];
1349 }
1350 
1351 struct intel_load_detect_pipe {
1352         struct drm_atomic_state *restore_state;
1353 };
1354 
1355 static inline struct intel_encoder *
1356 intel_attached_encoder(struct drm_connector *connector)
1357 {
1358         return to_intel_connector(connector)->encoder;
1359 }
1360 
1361 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1362 {
1363         switch (encoder->type) {
1364         case INTEL_OUTPUT_DDI:
1365         case INTEL_OUTPUT_DP:
1366         case INTEL_OUTPUT_EDP:
1367         case INTEL_OUTPUT_HDMI:
1368                 return true;
1369         default:
1370                 return false;
1371         }
1372 }
1373 
1374 static inline struct intel_digital_port *
1375 enc_to_dig_port(struct drm_encoder *encoder)
1376 {
1377         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1378 
1379         if (intel_encoder_is_dig_port(intel_encoder))
1380                 return container_of(encoder, struct intel_digital_port,
1381                                     base.base);
1382         else
1383                 return NULL;
1384 }
1385 
1386 static inline struct intel_digital_port *
1387 conn_to_dig_port(struct intel_connector *connector)
1388 {
1389         return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1390 }
1391 
1392 static inline struct intel_dp_mst_encoder *
1393 enc_to_mst(struct drm_encoder *encoder)
1394 {
1395         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1396 }
1397 
1398 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1399 {
1400         return &enc_to_dig_port(encoder)->dp;
1401 }
1402 
1403 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1404 {
1405         switch (encoder->type) {
1406         case INTEL_OUTPUT_DP:
1407         case INTEL_OUTPUT_EDP:
1408                 return true;
1409         case INTEL_OUTPUT_DDI:
1410                 /* Skip pure HDMI/DVI DDI encoders */
1411                 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1412         default:
1413                 return false;
1414         }
1415 }
1416 
1417 static inline struct intel_lspcon *
1418 enc_to_intel_lspcon(struct drm_encoder *encoder)
1419 {
1420         return &enc_to_dig_port(encoder)->lspcon;
1421 }
1422 
1423 static inline struct intel_digital_port *
1424 dp_to_dig_port(struct intel_dp *intel_dp)
1425 {
1426         return container_of(intel_dp, struct intel_digital_port, dp);
1427 }
1428 
1429 static inline struct intel_lspcon *
1430 dp_to_lspcon(struct intel_dp *intel_dp)
1431 {
1432         return &dp_to_dig_port(intel_dp)->lspcon;
1433 }
1434 
1435 static inline struct drm_i915_private *
1436 dp_to_i915(struct intel_dp *intel_dp)
1437 {
1438         return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1439 }
1440 
1441 static inline struct intel_digital_port *
1442 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1443 {
1444         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1445 }
1446 
1447 static inline struct intel_plane_state *
1448 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1449                                  struct intel_plane *plane)
1450 {
1451         struct drm_plane_state *ret =
1452                 drm_atomic_get_plane_state(&state->base, &plane->base);
1453 
1454         if (IS_ERR(ret))
1455                 return ERR_CAST(ret);
1456 
1457         return to_intel_plane_state(ret);
1458 }
1459 
1460 static inline struct intel_plane_state *
1461 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1462                                  struct intel_plane *plane)
1463 {
1464         return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1465                                                                    &plane->base));
1466 }
1467 
1468 static inline struct intel_plane_state *
1469 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1470                                  struct intel_plane *plane)
1471 {
1472         return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1473                                                                    &plane->base));
1474 }
1475 
1476 static inline struct intel_crtc_state *
1477 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1478                                 struct intel_crtc *crtc)
1479 {
1480         return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1481                                                                  &crtc->base));
1482 }
1483 
1484 static inline struct intel_crtc_state *
1485 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1486                                 struct intel_crtc *crtc)
1487 {
1488         return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1489                                                                  &crtc->base));
1490 }
1491 
1492 /* intel_display.c */
1493 static inline bool
1494 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1495                     enum intel_output_type type)
1496 {
1497         return crtc_state->output_types & (1 << type);
1498 }
1499 static inline bool
1500 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1501 {
1502         return crtc_state->output_types &
1503                 ((1 << INTEL_OUTPUT_DP) |
1504                  (1 << INTEL_OUTPUT_DP_MST) |
1505                  (1 << INTEL_OUTPUT_EDP));
1506 }
1507 static inline void
1508 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1509 {
1510         drm_wait_one_vblank(&dev_priv->drm, pipe);
1511 }
1512 static inline void
1513 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1514 {
1515         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1516 
1517         if (crtc->active)
1518                 intel_wait_for_vblank(dev_priv, pipe);
1519 }
1520 
1521 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1522 {
1523         return i915_ggtt_offset(state->vma);
1524 }
1525 
1526 #endif /*  __INTEL_DISPLAY_TYPES_H__ */