drivers/gpu/drm/i915/display/intel_dsi

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This source file includes following definitions.
intel_dsi_seq_port_to_port
mipi_exec_send_packet
mipi_exec_delay
vlv_exec_gpio
chv_exec_gpio
bxt_exec_gpio
icl_exec_gpio
mipi_exec_gpio
mipi_exec_i2c
mipi_exec_spi
mipi_exec_pmic
sequence_name
intel_dsi_vbt_exec_sequence
intel_dsi_msleep
intel_dsi_log_params
intel_dsi_vbt_init
   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Shobhit Kumar <shobhit.kumar@intel.com>
  24  *
  25  */
  26 
  27 #include <linux/gpio/consumer.h>
  28 #include <linux/mfd/intel_soc_pmic.h>
  29 #include <linux/slab.h>
  30 
  31 #include <asm/intel-mid.h>
  32 #include <asm/unaligned.h>
  33 
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/i915_drm.h>
  37 
  38 #include <video/mipi_display.h>
  39 
  40 #include "i915_drv.h"
  41 #include "intel_display_types.h"
  42 #include "intel_dsi.h"
  43 #include "intel_sideband.h"
  44 
  45 #define MIPI_TRANSFER_MODE_SHIFT        0
  46 #define MIPI_VIRTUAL_CHANNEL_SHIFT      1
  47 #define MIPI_PORT_SHIFT                 3
  48 
  49 /* base offsets for gpio pads */
  50 #define VLV_GPIO_NC_0_HV_DDI0_HPD       0x4130
  51 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA   0x4120
  52 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL   0x4110
  53 #define VLV_GPIO_NC_3_PANEL0_VDDEN      0x4140
  54 #define VLV_GPIO_NC_4_PANEL0_BKLTEN     0x4150
  55 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL    0x4160
  56 #define VLV_GPIO_NC_6_HV_DDI1_HPD       0x4180
  57 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA   0x4190
  58 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL   0x4170
  59 #define VLV_GPIO_NC_9_PANEL1_VDDEN      0x4100
  60 #define VLV_GPIO_NC_10_PANEL1_BKLTEN    0x40E0
  61 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL   0x40F0
  62 
  63 #define VLV_GPIO_PCONF0(base_offset)    (base_offset)
  64 #define VLV_GPIO_PAD_VAL(base_offset)   ((base_offset) + 8)
  65 
  66 struct gpio_map {
  67         u16 base_offset;
  68         bool init;
  69 };
  70 
  71 static struct gpio_map vlv_gpio_table[] = {
  72         { VLV_GPIO_NC_0_HV_DDI0_HPD },
  73         { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA },
  74         { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL },
  75         { VLV_GPIO_NC_3_PANEL0_VDDEN },
  76         { VLV_GPIO_NC_4_PANEL0_BKLTEN },
  77         { VLV_GPIO_NC_5_PANEL0_BKLTCTL },
  78         { VLV_GPIO_NC_6_HV_DDI1_HPD },
  79         { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA },
  80         { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL },
  81         { VLV_GPIO_NC_9_PANEL1_VDDEN },
  82         { VLV_GPIO_NC_10_PANEL1_BKLTEN },
  83         { VLV_GPIO_NC_11_PANEL1_BKLTCTL },
  84 };
  85 
  86 #define CHV_GPIO_IDX_START_N            0
  87 #define CHV_GPIO_IDX_START_E            73
  88 #define CHV_GPIO_IDX_START_SW           100
  89 #define CHV_GPIO_IDX_START_SE           198
  90 
  91 #define CHV_VBT_MAX_PINS_PER_FMLY       15
  92 
  93 #define CHV_GPIO_PAD_CFG0(f, i)         (0x4400 + (f) * 0x400 + (i) * 8)
  94 #define  CHV_GPIO_GPIOEN                (1 << 15)
  95 #define  CHV_GPIO_GPIOCFG_GPIO          (0 << 8)
  96 #define  CHV_GPIO_GPIOCFG_GPO           (1 << 8)
  97 #define  CHV_GPIO_GPIOCFG_GPI           (2 << 8)
  98 #define  CHV_GPIO_GPIOCFG_HIZ           (3 << 8)
  99 #define  CHV_GPIO_GPIOTXSTATE(state)    ((!!(state)) << 1)
 100 
 101 #define CHV_GPIO_PAD_CFG1(f, i)         (0x4400 + (f) * 0x400 + (i) * 8 + 4)
 102 #define  CHV_GPIO_CFGLOCK               (1 << 31)
 103 
 104 /* ICL DSI Display GPIO Pins */
 105 #define  ICL_GPIO_DDSP_HPD_A            0
 106 #define  ICL_GPIO_L_VDDEN_1             1
 107 #define  ICL_GPIO_L_BKLTEN_1            2
 108 #define  ICL_GPIO_DDPA_CTRLCLK_1        3
 109 #define  ICL_GPIO_DDPA_CTRLDATA_1       4
 110 #define  ICL_GPIO_DDSP_HPD_B            5
 111 #define  ICL_GPIO_L_VDDEN_2             6
 112 #define  ICL_GPIO_L_BKLTEN_2            7
 113 #define  ICL_GPIO_DDPA_CTRLCLK_2        8
 114 #define  ICL_GPIO_DDPA_CTRLDATA_2       9
 115 
 116 static inline enum port intel_dsi_seq_port_to_port(u8 port)
 117 {
 118         return port ? PORT_C : PORT_A;
 119 }
 120 
 121 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
 122                                        const u8 *data)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 125         struct mipi_dsi_device *dsi_device;
 126         u8 type, flags, seq_port;
 127         u16 len;
 128         enum port port;
 129 
 130         DRM_DEBUG_KMS("\n");
 131 
 132         flags = *data++;
 133         type = *data++;
 134 
 135         len = *((u16 *) data);
 136         data += 2;
 137 
 138         seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
 139 
 140         /* For DSI single link on Port A & C, the seq_port value which is
 141          * parsed from Sequence Block#53 of VBT has been set to 0
 142          * Now, read/write of packets for the DSI single link on Port A and
 143          * Port C will based on the DVO port from VBT block 2.
 144          */
 145         if (intel_dsi->ports == (1 << PORT_C))
 146                 port = PORT_C;
 147         else
 148                 port = intel_dsi_seq_port_to_port(seq_port);
 149 
 150         dsi_device = intel_dsi->dsi_hosts[port]->device;
 151         if (!dsi_device) {
 152                 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
 153                 goto out;
 154         }
 155 
 156         if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
 157                 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
 158         else
 159                 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
 160 
 161         dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
 162 
 163         switch (type) {
 164         case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 165                 mipi_dsi_generic_write(dsi_device, NULL, 0);
 166                 break;
 167         case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 168                 mipi_dsi_generic_write(dsi_device, data, 1);
 169                 break;
 170         case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 171                 mipi_dsi_generic_write(dsi_device, data, 2);
 172                 break;
 173         case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
 174         case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
 175         case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
 176                 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
 177                 break;
 178         case MIPI_DSI_GENERIC_LONG_WRITE:
 179                 mipi_dsi_generic_write(dsi_device, data, len);
 180                 break;
 181         case MIPI_DSI_DCS_SHORT_WRITE:
 182                 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
 183                 break;
 184         case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 185                 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
 186                 break;
 187         case MIPI_DSI_DCS_READ:
 188                 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
 189                 break;
 190         case MIPI_DSI_DCS_LONG_WRITE:
 191                 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
 192                 break;
 193         }
 194 
 195         if (INTEL_GEN(dev_priv) < 11)
 196                 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 197 
 198 out:
 199         data += len;
 200 
 201         return data;
 202 }
 203 
 204 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
 205 {
 206         u32 delay = *((const u32 *) data);
 207 
 208         DRM_DEBUG_KMS("\n");
 209 
 210         usleep_range(delay, delay + 10);
 211         data += 4;
 212 
 213         return data;
 214 }
 215 
 216 static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
 217                           u8 gpio_source, u8 gpio_index, bool value)
 218 {
 219         struct gpio_map *map;
 220         u16 pconf0, padval;
 221         u32 tmp;
 222         u8 port;
 223 
 224         if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) {
 225                 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index);
 226                 return;
 227         }
 228 
 229         map = &vlv_gpio_table[gpio_index];
 230 
 231         if (dev_priv->vbt.dsi.seq_version >= 3) {
 232                 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
 233                 port = IOSF_PORT_GPIO_NC;
 234         } else {
 235                 if (gpio_source == 0) {
 236                         port = IOSF_PORT_GPIO_NC;
 237                 } else if (gpio_source == 1) {
 238                         DRM_DEBUG_KMS("SC gpio not supported\n");
 239                         return;
 240                 } else {
 241                         DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
 242                         return;
 243                 }
 244         }
 245 
 246         pconf0 = VLV_GPIO_PCONF0(map->base_offset);
 247         padval = VLV_GPIO_PAD_VAL(map->base_offset);
 248 
 249         vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 250         if (!map->init) {
 251                 /* FIXME: remove constant below */
 252                 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
 253                 map->init = true;
 254         }
 255 
 256         tmp = 0x4 | value;
 257         vlv_iosf_sb_write(dev_priv, port, padval, tmp);
 258         vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 259 }
 260 
 261 static void chv_exec_gpio(struct drm_i915_private *dev_priv,
 262                           u8 gpio_source, u8 gpio_index, bool value)
 263 {
 264         u16 cfg0, cfg1;
 265         u16 family_num;
 266         u8 port;
 267 
 268         if (dev_priv->vbt.dsi.seq_version >= 3) {
 269                 if (gpio_index >= CHV_GPIO_IDX_START_SE) {
 270                         /* XXX: it's unclear whether 255->57 is part of SE. */
 271                         gpio_index -= CHV_GPIO_IDX_START_SE;
 272                         port = CHV_IOSF_PORT_GPIO_SE;
 273                 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) {
 274                         gpio_index -= CHV_GPIO_IDX_START_SW;
 275                         port = CHV_IOSF_PORT_GPIO_SW;
 276                 } else if (gpio_index >= CHV_GPIO_IDX_START_E) {
 277                         gpio_index -= CHV_GPIO_IDX_START_E;
 278                         port = CHV_IOSF_PORT_GPIO_E;
 279                 } else {
 280                         port = CHV_IOSF_PORT_GPIO_N;
 281                 }
 282         } else {
 283                 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
 284                 if (gpio_source != 0) {
 285                         DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source);
 286                         return;
 287                 }
 288 
 289                 if (gpio_index >= CHV_GPIO_IDX_START_E) {
 290                         DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n",
 291                                       gpio_index);
 292                         return;
 293                 }
 294 
 295                 port = CHV_IOSF_PORT_GPIO_N;
 296         }
 297 
 298         family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY;
 299         gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY;
 300 
 301         cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
 302         cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
 303 
 304         vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 305         vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
 306         vlv_iosf_sb_write(dev_priv, port, cfg0,
 307                           CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
 308                           CHV_GPIO_GPIOTXSTATE(value));
 309         vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
 310 }
 311 
 312 static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
 313                           u8 gpio_source, u8 gpio_index, bool value)
 314 {
 315         /* XXX: this table is a quick ugly hack. */
 316         static struct gpio_desc *bxt_gpio_table[U8_MAX + 1];
 317         struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
 318 
 319         if (!gpio_desc) {
 320                 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
 321                                                  NULL, gpio_index,
 322                                                  value ? GPIOD_OUT_LOW :
 323                                                  GPIOD_OUT_HIGH);
 324 
 325                 if (IS_ERR_OR_NULL(gpio_desc)) {
 326                         DRM_ERROR("GPIO index %u request failed (%ld)\n",
 327                                   gpio_index, PTR_ERR(gpio_desc));
 328                         return;
 329                 }
 330 
 331                 bxt_gpio_table[gpio_index] = gpio_desc;
 332         }
 333 
 334         gpiod_set_value(gpio_desc, value);
 335 }
 336 
 337 static void icl_exec_gpio(struct drm_i915_private *dev_priv,
 338                           u8 gpio_source, u8 gpio_index, bool value)
 339 {
 340         DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n");
 341 }
 342 
 343 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
 344 {
 345         struct drm_device *dev = intel_dsi->base.base.dev;
 346         struct drm_i915_private *dev_priv = to_i915(dev);
 347         u8 gpio_source, gpio_index = 0, gpio_number;
 348         bool value;
 349 
 350         DRM_DEBUG_KMS("\n");
 351 
 352         if (dev_priv->vbt.dsi.seq_version >= 3)
 353                 gpio_index = *data++;
 354 
 355         gpio_number = *data++;
 356 
 357         /* gpio source in sequence v2 only */
 358         if (dev_priv->vbt.dsi.seq_version == 2)
 359                 gpio_source = (*data >> 1) & 3;
 360         else
 361                 gpio_source = 0;
 362 
 363         /* pull up/down */
 364         value = *data++ & 1;
 365 
 366         if (INTEL_GEN(dev_priv) >= 11)
 367                 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 368         else if (IS_VALLEYVIEW(dev_priv))
 369                 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 370         else if (IS_CHERRYVIEW(dev_priv))
 371                 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
 372         else
 373                 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
 374 
 375         return data;
 376 }
 377 
 378 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
 379 {
 380         DRM_DEBUG_KMS("Skipping I2C element execution\n");
 381 
 382         return data + *(data + 6) + 7;
 383 }
 384 
 385 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
 386 {
 387         DRM_DEBUG_KMS("Skipping SPI element execution\n");
 388 
 389         return data + *(data + 5) + 6;
 390 }
 391 
 392 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
 393 {
 394 #ifdef CONFIG_PMIC_OPREGION
 395         u32 value, mask, reg_address;
 396         u16 i2c_address;
 397         int ret;
 398 
 399         /* byte 0 aka PMIC Flag is reserved */
 400         i2c_address     = get_unaligned_le16(data + 1);
 401         reg_address     = get_unaligned_le32(data + 3);
 402         value           = get_unaligned_le32(data + 7);
 403         mask            = get_unaligned_le32(data + 11);
 404 
 405         ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
 406                                                         reg_address,
 407                                                         value, mask);
 408         if (ret)
 409                 DRM_ERROR("%s failed, error: %d\n", __func__, ret);
 410 #else
 411         DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n");
 412 #endif
 413 
 414         return data + 15;
 415 }
 416 
 417 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
 418                                         const u8 *data);
 419 static const fn_mipi_elem_exec exec_elem[] = {
 420         [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
 421         [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
 422         [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
 423         [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
 424         [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
 425         [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
 426 };
 427 
 428 /*
 429  * MIPI Sequence from VBT #53 parsing logic
 430  * We have already separated each seqence during bios parsing
 431  * Following is generic execution function for any sequence
 432  */
 433 
 434 static const char * const seq_name[] = {
 435         [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
 436         [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
 437         [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
 438         [MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
 439         [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
 440         [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
 441         [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
 442         [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
 443         [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
 444         [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
 445         [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
 446 };
 447 
 448 static const char *sequence_name(enum mipi_seq seq_id)
 449 {
 450         if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id])
 451                 return seq_name[seq_id];
 452         else
 453                 return "(unknown)";
 454 }
 455 
 456 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
 457                                  enum mipi_seq seq_id)
 458 {
 459         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 460         const u8 *data;
 461         fn_mipi_elem_exec mipi_elem_exec;
 462 
 463         if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence)))
 464                 return;
 465 
 466         data = dev_priv->vbt.dsi.sequence[seq_id];
 467         if (!data)
 468                 return;
 469 
 470         WARN_ON(*data != seq_id);
 471 
 472         DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n",
 473                       seq_id, sequence_name(seq_id));
 474 
 475         /* Skip Sequence Byte. */
 476         data++;
 477 
 478         /* Skip Size of Sequence. */
 479         if (dev_priv->vbt.dsi.seq_version >= 3)
 480                 data += 4;
 481 
 482         while (1) {
 483                 u8 operation_byte = *data++;
 484                 u8 operation_size = 0;
 485 
 486                 if (operation_byte == MIPI_SEQ_ELEM_END)
 487                         break;
 488 
 489                 if (operation_byte < ARRAY_SIZE(exec_elem))
 490                         mipi_elem_exec = exec_elem[operation_byte];
 491                 else
 492                         mipi_elem_exec = NULL;
 493 
 494                 /* Size of Operation. */
 495                 if (dev_priv->vbt.dsi.seq_version >= 3)
 496                         operation_size = *data++;
 497 
 498                 if (mipi_elem_exec) {
 499                         const u8 *next = data + operation_size;
 500 
 501                         data = mipi_elem_exec(intel_dsi, data);
 502 
 503                         /* Consistency check if we have size. */
 504                         if (operation_size && data != next) {
 505                                 DRM_ERROR("Inconsistent operation size\n");
 506                                 return;
 507                         }
 508                 } else if (operation_size) {
 509                         /* We have size, skip. */
 510                         DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n",
 511                                       operation_byte);
 512                         data += operation_size;
 513                 } else {
 514                         /* No size, can't skip without parsing. */
 515                         DRM_ERROR("Unsupported MIPI operation byte %u\n",
 516                                   operation_byte);
 517                         return;
 518                 }
 519         }
 520 }
 521 
 522 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
 523 {
 524         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 525 
 526         /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
 527         if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
 528                 return;
 529 
 530         msleep(msec);
 531 }
 532 
 533 void intel_dsi_log_params(struct intel_dsi *intel_dsi)
 534 {
 535         DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk);
 536         DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap);
 537         DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count);
 538         DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
 539         DRM_DEBUG_KMS("Video mode format %s\n",
 540                       intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
 541                       "non-burst with sync pulse" :
 542                       intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
 543                       "non-burst with sync events" :
 544                       intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
 545                       "burst" : "<unknown>");
 546         DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio);
 547         DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val);
 548         DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt));
 549         DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop));
 550         DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video");
 551         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 552                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n");
 553         else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT)
 554                 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n");
 555         else
 556                 DRM_DEBUG_KMS("Dual link: NONE\n");
 557         DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format);
 558         DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div);
 559         DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout);
 560         DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val);
 561         DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count);
 562         DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count);
 563         DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk);
 564         DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer);
 565         DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count);
 566         DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count);
 567         DRM_DEBUG_KMS("BTA %s\n",
 568                         enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)));
 569 }
 570 
 571 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 572 {
 573         struct drm_device *dev = intel_dsi->base.base.dev;
 574         struct drm_i915_private *dev_priv = to_i915(dev);
 575         struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
 576         struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
 577         struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
 578         u16 burst_mode_ratio;
 579         enum port port;
 580 
 581         DRM_DEBUG_KMS("\n");
 582 
 583         intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
 584         intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
 585         intel_dsi->lane_count = mipi_config->lane_cnt + 1;
 586         intel_dsi->pixel_format =
 587                         pixel_format_from_register_bits(
 588                                 mipi_config->videomode_color_format << 7);
 589 
 590         intel_dsi->dual_link = mipi_config->dual_link;
 591         intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
 592         intel_dsi->operation_mode = mipi_config->is_cmd_mode;
 593         intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
 594         intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
 595         intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
 596         intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
 597         intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
 598         intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
 599         intel_dsi->init_count = mipi_config->master_init_timer;
 600         intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 601         intel_dsi->video_frmt_cfg_bits =
 602                 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
 603         intel_dsi->bgr_enabled = mipi_config->rgb_flip;
 604 
 605         /* Starting point, adjusted depending on dual link and burst mode */
 606         intel_dsi->pclk = mode->clock;
 607 
 608         /* In dual link mode each port needs half of pixel clock */
 609         if (intel_dsi->dual_link) {
 610                 intel_dsi->pclk /= 2;
 611 
 612                 /* we can enable pixel_overlap if needed by panel. In this
 613                  * case we need to increase the pixelclock for extra pixels
 614                  */
 615                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 616                         intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000);
 617                 }
 618         }
 619 
 620         /* Burst Mode Ratio
 621          * Target ddr frequency from VBT / non burst ddr freq
 622          * multiply by 100 to preserve remainder
 623          */
 624         if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 625                 if (mipi_config->target_burst_mode_freq) {
 626                         u32 bitrate = intel_dsi_bitrate(intel_dsi);
 627 
 628                         /*
 629                          * Sometimes the VBT contains a slightly lower clock,
 630                          * then the bitrate we have calculated, in this case
 631                          * just replace it with the calculated bitrate.
 632                          */
 633                         if (mipi_config->target_burst_mode_freq < bitrate &&
 634                             intel_fuzzy_clock_check(
 635                                         mipi_config->target_burst_mode_freq,
 636                                         bitrate))
 637                                 mipi_config->target_burst_mode_freq = bitrate;
 638 
 639                         if (mipi_config->target_burst_mode_freq < bitrate) {
 640                                 DRM_ERROR("Burst mode freq is less than computed\n");
 641                                 return false;
 642                         }
 643 
 644                         burst_mode_ratio = DIV_ROUND_UP(
 645                                 mipi_config->target_burst_mode_freq * 100,
 646                                 bitrate);
 647 
 648                         intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100);
 649                 } else {
 650                         DRM_ERROR("Burst mode target is not set\n");
 651                         return false;
 652                 }
 653         } else
 654                 burst_mode_ratio = 100;
 655 
 656         intel_dsi->burst_mode_ratio = burst_mode_ratio;
 657 
 658         /* delays in VBT are in unit of 100us, so need to convert
 659          * here in ms
 660          * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
 661         intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
 662         intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
 663         intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
 664         intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
 665         intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
 666 
 667         /* a regular driver would get the device in probe */
 668         for_each_dsi_port(port, intel_dsi->ports) {
 669                 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
 670         }
 671 
 672         return true;
 673 }
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/gpu/drm/i915/display/intel_dsi_vbt.c

DEFINITIONS
