This source file includes following definitions.
- bxt_get_phy_list
- bxt_get_phy_info
- bxt_port_to_phy_channel
- bxt_ddi_phy_set_signal_level
- bxt_ddi_phy_is_enabled
- bxt_get_grc
- bxt_phy_wait_grc_done
- _bxt_ddi_phy_init
- bxt_ddi_phy_uninit
- bxt_ddi_phy_init
- __printf
- bxt_ddi_phy_verify_state
- bxt_ddi_phy_calc_lane_lat_optim_mask
- bxt_ddi_phy_set_lane_optim_mask
- bxt_ddi_phy_get_lane_lat_optim_mask
- chv_set_phy_signal_level
- chv_data_lane_soft_reset
- chv_phy_pre_pll_enable
- chv_phy_pre_encoder_enable
- chv_phy_release_cl2_override
- chv_phy_post_pll_disable
- vlv_set_phy_signal_level
- vlv_phy_pre_pll_enable
- vlv_phy_pre_encoder_enable
- vlv_phy_reset_lanes
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24 #include "display/intel_dp.h"
25
26 #include "intel_display_types.h"
27 #include "intel_dpio_phy.h"
28 #include "intel_sideband.h"
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123
124 struct bxt_ddi_phy_info {
125
126
127
128 bool dual_channel;
129
130
131
132
133
134
135 enum dpio_phy rcomp_phy;
136
137
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139
140
141 int reset_delay;
142
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146
147 u32 pwron_mask;
148
149
150
151
152 struct {
153
154
155
156 enum port port;
157 } channel[2];
158 };
159
160 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
161 [DPIO_PHY0] = {
162 .dual_channel = true,
163 .rcomp_phy = DPIO_PHY1,
164 .pwron_mask = BIT(0),
165
166 .channel = {
167 [DPIO_CH0] = { .port = PORT_B },
168 [DPIO_CH1] = { .port = PORT_C },
169 }
170 },
171 [DPIO_PHY1] = {
172 .dual_channel = false,
173 .rcomp_phy = -1,
174 .pwron_mask = BIT(1),
175
176 .channel = {
177 [DPIO_CH0] = { .port = PORT_A },
178 }
179 },
180 };
181
182 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
183 [DPIO_PHY0] = {
184 .dual_channel = false,
185 .rcomp_phy = DPIO_PHY1,
186 .pwron_mask = BIT(0),
187 .reset_delay = 20,
188
189 .channel = {
190 [DPIO_CH0] = { .port = PORT_B },
191 }
192 },
193 [DPIO_PHY1] = {
194 .dual_channel = false,
195 .rcomp_phy = -1,
196 .pwron_mask = BIT(3),
197 .reset_delay = 20,
198
199 .channel = {
200 [DPIO_CH0] = { .port = PORT_A },
201 }
202 },
203 [DPIO_PHY2] = {
204 .dual_channel = false,
205 .rcomp_phy = DPIO_PHY1,
206 .pwron_mask = BIT(1),
207 .reset_delay = 20,
208
209 .channel = {
210 [DPIO_CH0] = { .port = PORT_C },
211 }
212 },
213 };
214
215 static const struct bxt_ddi_phy_info *
216 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
217 {
218 if (IS_GEMINILAKE(dev_priv)) {
219 *count = ARRAY_SIZE(glk_ddi_phy_info);
220 return glk_ddi_phy_info;
221 } else {
222 *count = ARRAY_SIZE(bxt_ddi_phy_info);
223 return bxt_ddi_phy_info;
224 }
225 }
226
227 static const struct bxt_ddi_phy_info *
228 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
229 {
230 int count;
231 const struct bxt_ddi_phy_info *phy_list =
232 bxt_get_phy_list(dev_priv, &count);
233
234 return &phy_list[phy];
235 }
236
237 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
238 enum dpio_phy *phy, enum dpio_channel *ch)
239 {
240 const struct bxt_ddi_phy_info *phy_info, *phys;
241 int i, count;
242
243 phys = bxt_get_phy_list(dev_priv, &count);
244
245 for (i = 0; i < count; i++) {
246 phy_info = &phys[i];
247
248 if (port == phy_info->channel[DPIO_CH0].port) {
249 *phy = i;
250 *ch = DPIO_CH0;
251 return;
252 }
253
254 if (phy_info->dual_channel &&
255 port == phy_info->channel[DPIO_CH1].port) {
256 *phy = i;
257 *ch = DPIO_CH1;
258 return;
259 }
260 }
261
262 WARN(1, "PHY not found for PORT %c", port_name(port));
263 *phy = DPIO_PHY0;
264 *ch = DPIO_CH0;
265 }
266
267 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
268 enum port port, u32 margin, u32 scale,
269 u32 enable, u32 deemphasis)
270 {
271 u32 val;
272 enum dpio_phy phy;
273 enum dpio_channel ch;
274
275 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
276
277
278
279
280
281 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
282 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
283 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
284
285 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
286 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
287 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
288 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
289
290 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
291 val &= ~SCALE_DCOMP_METHOD;
292 if (enable)
293 val |= SCALE_DCOMP_METHOD;
294
295 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
296 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
297
298 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
299
300 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
301 val &= ~DE_EMPHASIS;
302 val |= deemphasis << DEEMPH_SHIFT;
303 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
304
305 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
306 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
307 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
308 }
309
310 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
311 enum dpio_phy phy)
312 {
313 const struct bxt_ddi_phy_info *phy_info;
314
315 phy_info = bxt_get_phy_info(dev_priv, phy);
316
317 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
318 return false;
319
320 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
321 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
322 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
323 phy);
324
325 return false;
326 }
327
328 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
329 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
330 phy);
331
332 return false;
333 }
334
335 return true;
336 }
337
338 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
339 {
340 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
341
342 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
343 }
344
345 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
346 enum dpio_phy phy)
347 {
348 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
349 GRC_DONE, 10))
350 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
351 }
352
353 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
354 enum dpio_phy phy)
355 {
356 const struct bxt_ddi_phy_info *phy_info;
357 u32 val;
358
359 phy_info = bxt_get_phy_info(dev_priv, phy);
360
361 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
362
363 if (phy_info->rcomp_phy != -1)
364 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
365
366 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
367 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
368 "won't reprogram it\n", phy);
369 return;
370 }
371
372 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
373 "force reprogramming it\n", phy);
374 }
375
376 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
377 val |= phy_info->pwron_mask;
378 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
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386
387
388 if (intel_wait_for_register_fw(&dev_priv->uncore,
389 BXT_PORT_CL1CM_DW0(phy),
390 PHY_RESERVED | PHY_POWER_GOOD,
391 PHY_POWER_GOOD,
392 1))
393 DRM_ERROR("timeout during PHY%d power on\n", phy);
394
395
396 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
397 val &= ~IREF0RC_OFFSET_MASK;
398 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
399 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
400
401 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
402 val &= ~IREF1RC_OFFSET_MASK;
403 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
404 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
405
406
407 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
408 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
409 SUS_CLK_CONFIG;
410 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
411
412 if (phy_info->dual_channel) {
413 val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
414 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
415 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
416 }
417
418 if (phy_info->rcomp_phy != -1) {
419 u32 grc_code;
420
421 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
422
423
424
425
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427
428 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
429 phy_info->rcomp_phy);
430 grc_code = val << GRC_CODE_FAST_SHIFT |
431 val << GRC_CODE_SLOW_SHIFT |
432 val;
433 I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
434
435 val = I915_READ(BXT_PORT_REF_DW8(phy));
436 val |= GRC_DIS | GRC_RDY_OVRD;
437 I915_WRITE(BXT_PORT_REF_DW8(phy), val);
438 }
439
440 if (phy_info->reset_delay)
441 udelay(phy_info->reset_delay);
442
443 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
444 val |= COMMON_RESET_DIS;
445 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
446 }
447
448 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
449 {
450 const struct bxt_ddi_phy_info *phy_info;
451 u32 val;
452
453 phy_info = bxt_get_phy_info(dev_priv, phy);
454
455 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
456 val &= ~COMMON_RESET_DIS;
457 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
458
459 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
460 val &= ~phy_info->pwron_mask;
461 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
462 }
463
464 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
465 {
466 const struct bxt_ddi_phy_info *phy_info =
467 bxt_get_phy_info(dev_priv, phy);
468 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
469 bool was_enabled;
470
471 lockdep_assert_held(&dev_priv->power_domains.lock);
472
473 was_enabled = true;
474 if (rcomp_phy != -1)
475 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
476
477
478
479
480
481 if (!was_enabled)
482 _bxt_ddi_phy_init(dev_priv, rcomp_phy);
483
484 _bxt_ddi_phy_init(dev_priv, phy);
485
486 if (!was_enabled)
487 bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
488 }
489
490 static bool __printf(6, 7)
491 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
492 i915_reg_t reg, u32 mask, u32 expected,
493 const char *reg_fmt, ...)
494 {
495 struct va_format vaf;
496 va_list args;
497 u32 val;
498
499 val = I915_READ(reg);
500 if ((val & mask) == expected)
501 return true;
502
503 va_start(args, reg_fmt);
504 vaf.fmt = reg_fmt;
505 vaf.va = &args;
506
507 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
508 "current %08x, expected %08x (mask %08x)\n",
509 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
510 mask);
511
512 va_end(args);
513
514 return false;
515 }
516
517 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
518 enum dpio_phy phy)
519 {
520 const struct bxt_ddi_phy_info *phy_info;
521 u32 mask;
522 bool ok;
523
524 phy_info = bxt_get_phy_info(dev_priv, phy);
525
526 #define _CHK(reg, mask, exp, fmt, ...) \
527 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
528 ## __VA_ARGS__)
529
530 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
531 return false;
532
533 ok = true;
534
535
536 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
537 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
538 "BXT_PORT_CL1CM_DW9(%d)", phy);
539 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
540 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
541 "BXT_PORT_CL1CM_DW10(%d)", phy);
542
543
544 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
545 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
546 "BXT_PORT_CL1CM_DW28(%d)", phy);
547
548 if (phy_info->dual_channel)
549 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
550 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
551 "BXT_PORT_CL2CM_DW6(%d)", phy);
552
553 if (phy_info->rcomp_phy != -1) {
554 u32 grc_code = dev_priv->bxt_phy_grc;
555
556 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
557 grc_code << GRC_CODE_SLOW_SHIFT |
558 grc_code;
559 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
560 GRC_CODE_NOM_MASK;
561 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
562 "BXT_PORT_REF_DW6(%d)", phy);
563
564 mask = GRC_DIS | GRC_RDY_OVRD;
565 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
566 "BXT_PORT_REF_DW8(%d)", phy);
567 }
568
569 return ok;
570 #undef _CHK
571 }
572
573 u8
574 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
575 {
576 switch (lane_count) {
577 case 1:
578 return 0;
579 case 2:
580 return BIT(2) | BIT(0);
581 case 4:
582 return BIT(3) | BIT(2) | BIT(0);
583 default:
584 MISSING_CASE(lane_count);
585
586 return 0;
587 }
588 }
589
590 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
591 u8 lane_lat_optim_mask)
592 {
593 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
594 enum port port = encoder->port;
595 enum dpio_phy phy;
596 enum dpio_channel ch;
597 int lane;
598
599 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
600
601 for (lane = 0; lane < 4; lane++) {
602 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
603
604
605
606
607
608 val &= ~LATENCY_OPTIM;
609 if (lane_lat_optim_mask & BIT(lane))
610 val |= LATENCY_OPTIM;
611
612 I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
613 }
614 }
615
616 u8
617 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
618 {
619 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
620 enum port port = encoder->port;
621 enum dpio_phy phy;
622 enum dpio_channel ch;
623 int lane;
624 u8 mask;
625
626 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
627
628 mask = 0;
629 for (lane = 0; lane < 4; lane++) {
630 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
631
632 if (val & LATENCY_OPTIM)
633 mask |= BIT(lane);
634 }
635
636 return mask;
637 }
638
639
640 void chv_set_phy_signal_level(struct intel_encoder *encoder,
641 u32 deemph_reg_value, u32 margin_reg_value,
642 bool uniq_trans_scale)
643 {
644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
645 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
646 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
647 enum dpio_channel ch = vlv_dport_to_channel(dport);
648 enum pipe pipe = intel_crtc->pipe;
649 u32 val;
650 int i;
651
652 vlv_dpio_get(dev_priv);
653
654
655 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
656 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
657 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
658 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
659 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
660
661 if (intel_crtc->config->lane_count > 2) {
662 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
663 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
664 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
665 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
666 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
667 }
668
669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
670 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
671 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
672 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
673
674 if (intel_crtc->config->lane_count > 2) {
675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
676 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
677 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
678 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
679 }
680
681
682 for (i = 0; i < intel_crtc->config->lane_count; i++) {
683 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
684 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
685 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
686 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
687 }
688
689
690 for (i = 0; i < intel_crtc->config->lane_count; i++) {
691 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
692
693 val &= ~DPIO_SWING_MARGIN000_MASK;
694 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
695
696
697
698
699
700
701 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
702 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
703
704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
705 }
706
707
708
709
710
711
712
713 for (i = 0; i < intel_crtc->config->lane_count; i++) {
714 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
715 if (uniq_trans_scale)
716 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
717 else
718 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
719 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
720 }
721
722
723 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
724 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
725 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
726
727 if (intel_crtc->config->lane_count > 2) {
728 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
729 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
730 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
731 }
732
733 vlv_dpio_put(dev_priv);
734 }
735
736 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
737 const struct intel_crtc_state *crtc_state,
738 bool reset)
739 {
740 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
741 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
742 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
743 enum pipe pipe = crtc->pipe;
744 u32 val;
745
746 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
747 if (reset)
748 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
749 else
750 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
751 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
752
753 if (crtc_state->lane_count > 2) {
754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
755 if (reset)
756 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
757 else
758 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
759 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
760 }
761
762 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
763 val |= CHV_PCS_REQ_SOFTRESET_EN;
764 if (reset)
765 val &= ~DPIO_PCS_CLK_SOFT_RESET;
766 else
767 val |= DPIO_PCS_CLK_SOFT_RESET;
768 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
769
770 if (crtc_state->lane_count > 2) {
771 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
772 val |= CHV_PCS_REQ_SOFTRESET_EN;
773 if (reset)
774 val &= ~DPIO_PCS_CLK_SOFT_RESET;
775 else
776 val |= DPIO_PCS_CLK_SOFT_RESET;
777 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
778 }
779 }
780
781 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
782 const struct intel_crtc_state *crtc_state)
783 {
784 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
785 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
786 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
787 enum dpio_channel ch = vlv_dport_to_channel(dport);
788 enum pipe pipe = crtc->pipe;
789 unsigned int lane_mask =
790 intel_dp_unused_lane_mask(crtc_state->lane_count);
791 u32 val;
792
793
794
795
796
797 if (ch == DPIO_CH0 && pipe == PIPE_B)
798 dport->release_cl2_override =
799 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
800
801 chv_phy_powergate_lanes(encoder, true, lane_mask);
802
803 vlv_dpio_get(dev_priv);
804
805
806 chv_data_lane_soft_reset(encoder, crtc_state, true);
807
808
809 if (pipe != PIPE_B) {
810 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
811 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
812 if (ch == DPIO_CH0)
813 val |= CHV_BUFLEFTENA1_FORCE;
814 if (ch == DPIO_CH1)
815 val |= CHV_BUFRIGHTENA1_FORCE;
816 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
817 } else {
818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
819 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
820 if (ch == DPIO_CH0)
821 val |= CHV_BUFLEFTENA2_FORCE;
822 if (ch == DPIO_CH1)
823 val |= CHV_BUFRIGHTENA2_FORCE;
824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
825 }
826
827
828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
829 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
830 if (pipe != PIPE_B)
831 val &= ~CHV_PCS_USEDCLKCHANNEL;
832 else
833 val |= CHV_PCS_USEDCLKCHANNEL;
834 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
835
836 if (crtc_state->lane_count > 2) {
837 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
838 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
839 if (pipe != PIPE_B)
840 val &= ~CHV_PCS_USEDCLKCHANNEL;
841 else
842 val |= CHV_PCS_USEDCLKCHANNEL;
843 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
844 }
845
846
847
848
849
850
851 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
852 if (pipe != PIPE_B)
853 val &= ~CHV_CMN_USEDCLKCHANNEL;
854 else
855 val |= CHV_CMN_USEDCLKCHANNEL;
856 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
857
858 vlv_dpio_put(dev_priv);
859 }
860
861 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
862 const struct intel_crtc_state *crtc_state)
863 {
864 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
865 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
866 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
868 enum dpio_channel ch = vlv_dport_to_channel(dport);
869 enum pipe pipe = crtc->pipe;
870 int data, i, stagger;
871 u32 val;
872
873 vlv_dpio_get(dev_priv);
874
875
876 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
877 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
878 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
879
880 if (crtc_state->lane_count > 2) {
881 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
882 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
883 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
884 }
885
886
887 for (i = 0; i < crtc_state->lane_count; i++) {
888
889 if (crtc_state->lane_count == 1)
890 data = 0x0;
891 else
892 data = (i == 1) ? 0x0 : 0x1;
893 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
894 data << DPIO_UPAR_SHIFT);
895 }
896
897
898 if (crtc_state->port_clock > 270000)
899 stagger = 0x18;
900 else if (crtc_state->port_clock > 135000)
901 stagger = 0xd;
902 else if (crtc_state->port_clock > 67500)
903 stagger = 0x7;
904 else if (crtc_state->port_clock > 33750)
905 stagger = 0x4;
906 else
907 stagger = 0x2;
908
909 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
910 val |= DPIO_TX2_STAGGER_MASK(0x1f);
911 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
912
913 if (crtc_state->lane_count > 2) {
914 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
915 val |= DPIO_TX2_STAGGER_MASK(0x1f);
916 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
917 }
918
919 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
920 DPIO_LANESTAGGER_STRAP(stagger) |
921 DPIO_LANESTAGGER_STRAP_OVRD |
922 DPIO_TX1_STAGGER_MASK(0x1f) |
923 DPIO_TX1_STAGGER_MULT(6) |
924 DPIO_TX2_STAGGER_MULT(0));
925
926 if (crtc_state->lane_count > 2) {
927 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
928 DPIO_LANESTAGGER_STRAP(stagger) |
929 DPIO_LANESTAGGER_STRAP_OVRD |
930 DPIO_TX1_STAGGER_MASK(0x1f) |
931 DPIO_TX1_STAGGER_MULT(7) |
932 DPIO_TX2_STAGGER_MULT(5));
933 }
934
935
936 chv_data_lane_soft_reset(encoder, crtc_state, false);
937
938 vlv_dpio_put(dev_priv);
939 }
940
941 void chv_phy_release_cl2_override(struct intel_encoder *encoder)
942 {
943 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
944 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
945
946 if (dport->release_cl2_override) {
947 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
948 dport->release_cl2_override = false;
949 }
950 }
951
952 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
953 const struct intel_crtc_state *old_crtc_state)
954 {
955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
956 enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
957 u32 val;
958
959 vlv_dpio_get(dev_priv);
960
961
962 if (pipe != PIPE_B) {
963 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
964 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
965 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
966 } else {
967 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
968 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
969 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
970 }
971
972 vlv_dpio_put(dev_priv);
973
974
975
976
977
978
979
980
981
982
983 chv_phy_powergate_lanes(encoder, false, 0x0);
984 }
985
986 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
987 u32 demph_reg_value, u32 preemph_reg_value,
988 u32 uniqtranscale_reg_value, u32 tx3_demph)
989 {
990 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
991 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
992 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
993 enum dpio_channel port = vlv_dport_to_channel(dport);
994 enum pipe pipe = intel_crtc->pipe;
995
996 vlv_dpio_get(dev_priv);
997
998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
1000 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
1001 uniqtranscale_reg_value);
1002 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
1003
1004 if (tx3_demph)
1005 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
1006
1007 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1008 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
1009 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1010
1011 vlv_dpio_put(dev_priv);
1012 }
1013
1014 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1015 const struct intel_crtc_state *crtc_state)
1016 {
1017 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1018 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1019 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1020 enum dpio_channel port = vlv_dport_to_channel(dport);
1021 enum pipe pipe = crtc->pipe;
1022
1023
1024 vlv_dpio_get(dev_priv);
1025
1026 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1027 DPIO_PCS_TX_LANE2_RESET |
1028 DPIO_PCS_TX_LANE1_RESET);
1029 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1030 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1031 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1032 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1033 DPIO_PCS_CLK_SOFT_RESET);
1034
1035
1036 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1037 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1038 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1039
1040 vlv_dpio_put(dev_priv);
1041 }
1042
1043 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1044 const struct intel_crtc_state *crtc_state)
1045 {
1046 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1047 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1048 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1049 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1050 enum dpio_channel port = vlv_dport_to_channel(dport);
1051 enum pipe pipe = crtc->pipe;
1052 u32 val;
1053
1054 vlv_dpio_get(dev_priv);
1055
1056
1057 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1058 val = 0;
1059 if (pipe)
1060 val |= (1<<21);
1061 else
1062 val &= ~(1<<21);
1063 val |= 0x001000c4;
1064 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1065
1066
1067 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1068 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1069
1070 vlv_dpio_put(dev_priv);
1071 }
1072
1073 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1074 const struct intel_crtc_state *old_crtc_state)
1075 {
1076 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1078 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1079 enum dpio_channel port = vlv_dport_to_channel(dport);
1080 enum pipe pipe = crtc->pipe;
1081
1082 vlv_dpio_get(dev_priv);
1083 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1084 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1085 vlv_dpio_put(dev_priv);
1086 }