This source file includes following definitions.
- get_gmbus_pin
- intel_gmbus_is_valid_pin
- to_intel_gmbus
- intel_gmbus_reset
- pnv_gmbus_clock_gating
- pch_gmbus_clock_gating
- bxt_gmbus_clock_gating
- get_reserved
- get_clock
- get_data
- set_clock
- set_data
- intel_gpio_pre_xfer
- intel_gpio_post_xfer
- intel_gpio_setup
- gmbus_wait
- gmbus_wait_idle
- gmbus_max_xfer_size
- gmbus_xfer_read_chunk
- gmbus_xfer_read
- gmbus_xfer_write_chunk
- gmbus_xfer_write
- gmbus_is_index_xfer
- gmbus_index_xfer
- do_gmbus_xfer
- gmbus_xfer
- intel_gmbus_output_aksv
- gmbus_func
- gmbus_lock_bus
- gmbus_trylock_bus
- gmbus_unlock_bus
- intel_gmbus_setup
- intel_gmbus_get_adapter
- intel_gmbus_set_speed
- intel_gmbus_force_bit
- intel_gmbus_is_forced_bit
- intel_gmbus_teardown
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 #include <linux/export.h>
31 #include <linux/i2c-algo-bit.h>
32 #include <linux/i2c.h>
33
34 #include <drm/drm_hdcp.h>
35 #include <drm/i915_drm.h>
36
37 #include "i915_drv.h"
38 #include "intel_display_types.h"
39 #include "intel_gmbus.h"
40
41 struct gmbus_pin {
42 const char *name;
43 enum i915_gpio gpio;
44 };
45
46
47 static const struct gmbus_pin gmbus_pins[] = {
48 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
49 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
50 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
51 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
52 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
53 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
54 };
55
56 static const struct gmbus_pin gmbus_pins_bdw[] = {
57 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
58 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
59 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
60 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
61 };
62
63 static const struct gmbus_pin gmbus_pins_skl[] = {
64 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
65 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
66 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
67 };
68
69 static const struct gmbus_pin gmbus_pins_bxt[] = {
70 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
71 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
72 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
73 };
74
75 static const struct gmbus_pin gmbus_pins_cnp[] = {
76 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
77 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
78 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
79 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
80 };
81
82 static const struct gmbus_pin gmbus_pins_icp[] = {
83 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
84 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
85 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
86 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
87 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
88 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
89 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
90 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
91 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
92 };
93
94
95 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
96 unsigned int pin)
97 {
98 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
99 return &gmbus_pins_icp[pin];
100 else if (HAS_PCH_CNP(dev_priv))
101 return &gmbus_pins_cnp[pin];
102 else if (IS_GEN9_LP(dev_priv))
103 return &gmbus_pins_bxt[pin];
104 else if (IS_GEN9_BC(dev_priv))
105 return &gmbus_pins_skl[pin];
106 else if (IS_BROADWELL(dev_priv))
107 return &gmbus_pins_bdw[pin];
108 else
109 return &gmbus_pins[pin];
110 }
111
112 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
113 unsigned int pin)
114 {
115 unsigned int size;
116
117 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
118 size = ARRAY_SIZE(gmbus_pins_icp);
119 else if (HAS_PCH_CNP(dev_priv))
120 size = ARRAY_SIZE(gmbus_pins_cnp);
121 else if (IS_GEN9_LP(dev_priv))
122 size = ARRAY_SIZE(gmbus_pins_bxt);
123 else if (IS_GEN9_BC(dev_priv))
124 size = ARRAY_SIZE(gmbus_pins_skl);
125 else if (IS_BROADWELL(dev_priv))
126 size = ARRAY_SIZE(gmbus_pins_bdw);
127 else
128 size = ARRAY_SIZE(gmbus_pins);
129
130 return pin < size && get_gmbus_pin(dev_priv, pin)->name;
131 }
132
133
134
135 #define I2C_RISEFALL_TIME 10
136
137 static inline struct intel_gmbus *
138 to_intel_gmbus(struct i2c_adapter *i2c)
139 {
140 return container_of(i2c, struct intel_gmbus, adapter);
141 }
142
143 void
144 intel_gmbus_reset(struct drm_i915_private *dev_priv)
145 {
146 I915_WRITE(GMBUS0, 0);
147 I915_WRITE(GMBUS4, 0);
148 }
149
150 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
151 bool enable)
152 {
153 u32 val;
154
155
156 val = I915_READ(DSPCLK_GATE_D);
157 if (!enable)
158 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
159 else
160 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
161 I915_WRITE(DSPCLK_GATE_D, val);
162 }
163
164 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
165 bool enable)
166 {
167 u32 val;
168
169 val = I915_READ(SOUTH_DSPCLK_GATE_D);
170 if (!enable)
171 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
172 else
173 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
174 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
175 }
176
177 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
178 bool enable)
179 {
180 u32 val;
181
182 val = I915_READ(GEN9_CLKGATE_DIS_4);
183 if (!enable)
184 val |= BXT_GMBUS_GATING_DIS;
185 else
186 val &= ~BXT_GMBUS_GATING_DIS;
187 I915_WRITE(GEN9_CLKGATE_DIS_4, val);
188 }
189
190 static u32 get_reserved(struct intel_gmbus *bus)
191 {
192 struct drm_i915_private *i915 = bus->dev_priv;
193 struct intel_uncore *uncore = &i915->uncore;
194 u32 reserved = 0;
195
196
197 if (!IS_I830(i915) && !IS_I845G(i915))
198 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) &
199 (GPIO_DATA_PULLUP_DISABLE |
200 GPIO_CLOCK_PULLUP_DISABLE);
201
202 return reserved;
203 }
204
205 static int get_clock(void *data)
206 {
207 struct intel_gmbus *bus = data;
208 struct intel_uncore *uncore = &bus->dev_priv->uncore;
209 u32 reserved = get_reserved(bus);
210
211 intel_uncore_write_notrace(uncore,
212 bus->gpio_reg,
213 reserved | GPIO_CLOCK_DIR_MASK);
214 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
215
216 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
217 GPIO_CLOCK_VAL_IN) != 0;
218 }
219
220 static int get_data(void *data)
221 {
222 struct intel_gmbus *bus = data;
223 struct intel_uncore *uncore = &bus->dev_priv->uncore;
224 u32 reserved = get_reserved(bus);
225
226 intel_uncore_write_notrace(uncore,
227 bus->gpio_reg,
228 reserved | GPIO_DATA_DIR_MASK);
229 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved);
230
231 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) &
232 GPIO_DATA_VAL_IN) != 0;
233 }
234
235 static void set_clock(void *data, int state_high)
236 {
237 struct intel_gmbus *bus = data;
238 struct intel_uncore *uncore = &bus->dev_priv->uncore;
239 u32 reserved = get_reserved(bus);
240 u32 clock_bits;
241
242 if (state_high)
243 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
244 else
245 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
246 GPIO_CLOCK_VAL_MASK;
247
248 intel_uncore_write_notrace(uncore,
249 bus->gpio_reg,
250 reserved | clock_bits);
251 intel_uncore_posting_read(uncore, bus->gpio_reg);
252 }
253
254 static void set_data(void *data, int state_high)
255 {
256 struct intel_gmbus *bus = data;
257 struct intel_uncore *uncore = &bus->dev_priv->uncore;
258 u32 reserved = get_reserved(bus);
259 u32 data_bits;
260
261 if (state_high)
262 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
263 else
264 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
265 GPIO_DATA_VAL_MASK;
266
267 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits);
268 intel_uncore_posting_read(uncore, bus->gpio_reg);
269 }
270
271 static int
272 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
273 {
274 struct intel_gmbus *bus = container_of(adapter,
275 struct intel_gmbus,
276 adapter);
277 struct drm_i915_private *dev_priv = bus->dev_priv;
278
279 intel_gmbus_reset(dev_priv);
280
281 if (IS_PINEVIEW(dev_priv))
282 pnv_gmbus_clock_gating(dev_priv, false);
283
284 set_data(bus, 1);
285 set_clock(bus, 1);
286 udelay(I2C_RISEFALL_TIME);
287 return 0;
288 }
289
290 static void
291 intel_gpio_post_xfer(struct i2c_adapter *adapter)
292 {
293 struct intel_gmbus *bus = container_of(adapter,
294 struct intel_gmbus,
295 adapter);
296 struct drm_i915_private *dev_priv = bus->dev_priv;
297
298 set_data(bus, 1);
299 set_clock(bus, 1);
300
301 if (IS_PINEVIEW(dev_priv))
302 pnv_gmbus_clock_gating(dev_priv, true);
303 }
304
305 static void
306 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
307 {
308 struct drm_i915_private *dev_priv = bus->dev_priv;
309 struct i2c_algo_bit_data *algo;
310
311 algo = &bus->bit_algo;
312
313 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
314 bus->adapter.algo_data = algo;
315 algo->setsda = set_data;
316 algo->setscl = set_clock;
317 algo->getsda = get_data;
318 algo->getscl = get_clock;
319 algo->pre_xfer = intel_gpio_pre_xfer;
320 algo->post_xfer = intel_gpio_post_xfer;
321 algo->udelay = I2C_RISEFALL_TIME;
322 algo->timeout = usecs_to_jiffies(2200);
323 algo->data = bus;
324 }
325
326 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
327 {
328 DEFINE_WAIT(wait);
329 u32 gmbus2;
330 int ret;
331
332
333
334
335
336 if (!HAS_GMBUS_IRQ(dev_priv))
337 irq_en = 0;
338
339 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
340 I915_WRITE_FW(GMBUS4, irq_en);
341
342 status |= GMBUS_SATOER;
343 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
344 if (ret)
345 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
346
347 I915_WRITE_FW(GMBUS4, 0);
348 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
349
350 if (gmbus2 & GMBUS_SATOER)
351 return -ENXIO;
352
353 return ret;
354 }
355
356 static int
357 gmbus_wait_idle(struct drm_i915_private *dev_priv)
358 {
359 DEFINE_WAIT(wait);
360 u32 irq_enable;
361 int ret;
362
363
364 irq_enable = 0;
365 if (HAS_GMBUS_IRQ(dev_priv))
366 irq_enable = GMBUS_IDLE_EN;
367
368 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
369 I915_WRITE_FW(GMBUS4, irq_enable);
370
371 ret = intel_wait_for_register_fw(&dev_priv->uncore,
372 GMBUS2, GMBUS_ACTIVE, 0,
373 10);
374
375 I915_WRITE_FW(GMBUS4, 0);
376 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
377
378 return ret;
379 }
380
381 static inline
382 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
383 {
384 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
385 GMBUS_BYTE_COUNT_MAX;
386 }
387
388 static int
389 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
390 unsigned short addr, u8 *buf, unsigned int len,
391 u32 gmbus0_reg, u32 gmbus1_index)
392 {
393 unsigned int size = len;
394 bool burst_read = len > gmbus_max_xfer_size(dev_priv);
395 bool extra_byte_added = false;
396
397 if (burst_read) {
398
399
400
401
402 if (len == 512) {
403 extra_byte_added = true;
404 len++;
405 }
406 size = len % 256 + 256;
407 I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
408 }
409
410 I915_WRITE_FW(GMBUS1,
411 gmbus1_index |
412 GMBUS_CYCLE_WAIT |
413 (size << GMBUS_BYTE_COUNT_SHIFT) |
414 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
415 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
416 while (len) {
417 int ret;
418 u32 val, loop = 0;
419
420 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
421 if (ret)
422 return ret;
423
424 val = I915_READ_FW(GMBUS3);
425 do {
426 if (extra_byte_added && len == 1)
427 break;
428
429 *buf++ = val & 0xff;
430 val >>= 8;
431 } while (--len && ++loop < 4);
432
433 if (burst_read && len == size - 4)
434
435 I915_WRITE_FW(GMBUS0, gmbus0_reg);
436 }
437
438 return 0;
439 }
440
441
442
443
444
445
446
447
448
449 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
450
451 static int
452 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
453 u32 gmbus0_reg, u32 gmbus1_index)
454 {
455 u8 *buf = msg->buf;
456 unsigned int rx_size = msg->len;
457 unsigned int len;
458 int ret;
459
460 do {
461 if (HAS_GMBUS_BURST_READ(dev_priv))
462 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
463 else
464 len = min(rx_size, gmbus_max_xfer_size(dev_priv));
465
466 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
467 gmbus0_reg, gmbus1_index);
468 if (ret)
469 return ret;
470
471 rx_size -= len;
472 buf += len;
473 } while (rx_size != 0);
474
475 return 0;
476 }
477
478 static int
479 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
480 unsigned short addr, u8 *buf, unsigned int len,
481 u32 gmbus1_index)
482 {
483 unsigned int chunk_size = len;
484 u32 val, loop;
485
486 val = loop = 0;
487 while (len && loop < 4) {
488 val |= *buf++ << (8 * loop++);
489 len -= 1;
490 }
491
492 I915_WRITE_FW(GMBUS3, val);
493 I915_WRITE_FW(GMBUS1,
494 gmbus1_index | GMBUS_CYCLE_WAIT |
495 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
496 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
497 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
498 while (len) {
499 int ret;
500
501 val = loop = 0;
502 do {
503 val |= *buf++ << (8 * loop);
504 } while (--len && ++loop < 4);
505
506 I915_WRITE_FW(GMBUS3, val);
507
508 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
509 if (ret)
510 return ret;
511 }
512
513 return 0;
514 }
515
516 static int
517 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
518 u32 gmbus1_index)
519 {
520 u8 *buf = msg->buf;
521 unsigned int tx_size = msg->len;
522 unsigned int len;
523 int ret;
524
525 do {
526 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
527
528 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
529 gmbus1_index);
530 if (ret)
531 return ret;
532
533 buf += len;
534 tx_size -= len;
535 } while (tx_size != 0);
536
537 return 0;
538 }
539
540
541
542
543
544 static bool
545 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
546 {
547 return (i + 1 < num &&
548 msgs[i].addr == msgs[i + 1].addr &&
549 !(msgs[i].flags & I2C_M_RD) &&
550 (msgs[i].len == 1 || msgs[i].len == 2) &&
551 msgs[i + 1].len > 0);
552 }
553
554 static int
555 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
556 u32 gmbus0_reg)
557 {
558 u32 gmbus1_index = 0;
559 u32 gmbus5 = 0;
560 int ret;
561
562 if (msgs[0].len == 2)
563 gmbus5 = GMBUS_2BYTE_INDEX_EN |
564 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
565 if (msgs[0].len == 1)
566 gmbus1_index = GMBUS_CYCLE_INDEX |
567 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
568
569
570 if (gmbus5)
571 I915_WRITE_FW(GMBUS5, gmbus5);
572
573 if (msgs[1].flags & I2C_M_RD)
574 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
575 gmbus1_index);
576 else
577 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
578
579
580 if (gmbus5)
581 I915_WRITE_FW(GMBUS5, 0);
582
583 return ret;
584 }
585
586 static int
587 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
588 u32 gmbus0_source)
589 {
590 struct intel_gmbus *bus = container_of(adapter,
591 struct intel_gmbus,
592 adapter);
593 struct drm_i915_private *dev_priv = bus->dev_priv;
594 int i = 0, inc, try = 0;
595 int ret = 0;
596
597
598 if (IS_GEN9_LP(dev_priv))
599 bxt_gmbus_clock_gating(dev_priv, false);
600 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
601 pch_gmbus_clock_gating(dev_priv, false);
602
603 retry:
604 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
605
606 for (; i < num; i += inc) {
607 inc = 1;
608 if (gmbus_is_index_xfer(msgs, i, num)) {
609 ret = gmbus_index_xfer(dev_priv, &msgs[i],
610 gmbus0_source | bus->reg0);
611 inc = 2;
612 } else if (msgs[i].flags & I2C_M_RD) {
613 ret = gmbus_xfer_read(dev_priv, &msgs[i],
614 gmbus0_source | bus->reg0, 0);
615 } else {
616 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
617 }
618
619 if (!ret)
620 ret = gmbus_wait(dev_priv,
621 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
622 if (ret == -ETIMEDOUT)
623 goto timeout;
624 else if (ret)
625 goto clear_err;
626 }
627
628
629
630
631
632 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
633
634
635
636
637
638 if (gmbus_wait_idle(dev_priv)) {
639 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
640 adapter->name);
641 ret = -ETIMEDOUT;
642 }
643 I915_WRITE_FW(GMBUS0, 0);
644 ret = ret ?: i;
645 goto out;
646
647 clear_err:
648
649
650
651
652
653
654
655
656
657
658
659
660
661 ret = -ENXIO;
662 if (gmbus_wait_idle(dev_priv)) {
663 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
664 adapter->name);
665 ret = -ETIMEDOUT;
666 }
667
668
669
670
671
672 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
673 I915_WRITE_FW(GMBUS1, 0);
674 I915_WRITE_FW(GMBUS0, 0);
675
676 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
677 adapter->name, msgs[i].addr,
678 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
679
680
681
682
683
684
685
686 if (ret == -ENXIO && i == 0 && try++ == 0) {
687 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
688 adapter->name);
689 goto retry;
690 }
691
692 goto out;
693
694 timeout:
695 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
696 bus->adapter.name, bus->reg0 & 0xff);
697 I915_WRITE_FW(GMBUS0, 0);
698
699
700
701
702
703 ret = -EAGAIN;
704
705 out:
706
707 if (IS_GEN9_LP(dev_priv))
708 bxt_gmbus_clock_gating(dev_priv, true);
709 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv))
710 pch_gmbus_clock_gating(dev_priv, true);
711
712 return ret;
713 }
714
715 static int
716 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
717 {
718 struct intel_gmbus *bus =
719 container_of(adapter, struct intel_gmbus, adapter);
720 struct drm_i915_private *dev_priv = bus->dev_priv;
721 intel_wakeref_t wakeref;
722 int ret;
723
724 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
725
726 if (bus->force_bit) {
727 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
728 if (ret < 0)
729 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
730 } else {
731 ret = do_gmbus_xfer(adapter, msgs, num, 0);
732 if (ret == -EAGAIN)
733 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
734 }
735
736 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
737
738 return ret;
739 }
740
741 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
742 {
743 struct intel_gmbus *bus =
744 container_of(adapter, struct intel_gmbus, adapter);
745 struct drm_i915_private *dev_priv = bus->dev_priv;
746 u8 cmd = DRM_HDCP_DDC_AKSV;
747 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
748 struct i2c_msg msgs[] = {
749 {
750 .addr = DRM_HDCP_DDC_ADDR,
751 .flags = 0,
752 .len = sizeof(cmd),
753 .buf = &cmd,
754 },
755 {
756 .addr = DRM_HDCP_DDC_ADDR,
757 .flags = 0,
758 .len = sizeof(buf),
759 .buf = buf,
760 }
761 };
762 intel_wakeref_t wakeref;
763 int ret;
764
765 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
766 mutex_lock(&dev_priv->gmbus_mutex);
767
768
769
770
771
772
773 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
774
775 mutex_unlock(&dev_priv->gmbus_mutex);
776 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
777
778 return ret;
779 }
780
781 static u32 gmbus_func(struct i2c_adapter *adapter)
782 {
783 return i2c_bit_algo.functionality(adapter) &
784 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
785
786 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
787 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
788 }
789
790 static const struct i2c_algorithm gmbus_algorithm = {
791 .master_xfer = gmbus_xfer,
792 .functionality = gmbus_func
793 };
794
795 static void gmbus_lock_bus(struct i2c_adapter *adapter,
796 unsigned int flags)
797 {
798 struct intel_gmbus *bus = to_intel_gmbus(adapter);
799 struct drm_i915_private *dev_priv = bus->dev_priv;
800
801 mutex_lock(&dev_priv->gmbus_mutex);
802 }
803
804 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
805 unsigned int flags)
806 {
807 struct intel_gmbus *bus = to_intel_gmbus(adapter);
808 struct drm_i915_private *dev_priv = bus->dev_priv;
809
810 return mutex_trylock(&dev_priv->gmbus_mutex);
811 }
812
813 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
814 unsigned int flags)
815 {
816 struct intel_gmbus *bus = to_intel_gmbus(adapter);
817 struct drm_i915_private *dev_priv = bus->dev_priv;
818
819 mutex_unlock(&dev_priv->gmbus_mutex);
820 }
821
822 static const struct i2c_lock_operations gmbus_lock_ops = {
823 .lock_bus = gmbus_lock_bus,
824 .trylock_bus = gmbus_trylock_bus,
825 .unlock_bus = gmbus_unlock_bus,
826 };
827
828
829
830
831
832 int intel_gmbus_setup(struct drm_i915_private *dev_priv)
833 {
834 struct pci_dev *pdev = dev_priv->drm.pdev;
835 struct intel_gmbus *bus;
836 unsigned int pin;
837 int ret;
838
839 if (!HAS_DISPLAY(dev_priv))
840 return 0;
841
842 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
843 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
844 else if (!HAS_GMCH(dev_priv))
845
846
847
848
849 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
850
851 mutex_init(&dev_priv->gmbus_mutex);
852 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
853
854 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
855 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
856 continue;
857
858 bus = &dev_priv->gmbus[pin];
859
860 bus->adapter.owner = THIS_MODULE;
861 bus->adapter.class = I2C_CLASS_DDC;
862 snprintf(bus->adapter.name,
863 sizeof(bus->adapter.name),
864 "i915 gmbus %s",
865 get_gmbus_pin(dev_priv, pin)->name);
866
867 bus->adapter.dev.parent = &pdev->dev;
868 bus->dev_priv = dev_priv;
869
870 bus->adapter.algo = &gmbus_algorithm;
871 bus->adapter.lock_ops = &gmbus_lock_ops;
872
873
874
875
876
877 bus->adapter.retries = 1;
878
879
880 bus->reg0 = pin | GMBUS_RATE_100KHZ;
881
882
883 if (IS_I830(dev_priv))
884 bus->force_bit = 1;
885
886 intel_gpio_setup(bus, pin);
887
888 ret = i2c_add_adapter(&bus->adapter);
889 if (ret)
890 goto err;
891 }
892
893 intel_gmbus_reset(dev_priv);
894
895 return 0;
896
897 err:
898 while (pin--) {
899 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
900 continue;
901
902 bus = &dev_priv->gmbus[pin];
903 i2c_del_adapter(&bus->adapter);
904 }
905 return ret;
906 }
907
908 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
909 unsigned int pin)
910 {
911 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
912 return NULL;
913
914 return &dev_priv->gmbus[pin].adapter;
915 }
916
917 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
918 {
919 struct intel_gmbus *bus = to_intel_gmbus(adapter);
920
921 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
922 }
923
924 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
925 {
926 struct intel_gmbus *bus = to_intel_gmbus(adapter);
927 struct drm_i915_private *dev_priv = bus->dev_priv;
928
929 mutex_lock(&dev_priv->gmbus_mutex);
930
931 bus->force_bit += force_bit ? 1 : -1;
932 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
933 force_bit ? "en" : "dis", adapter->name,
934 bus->force_bit);
935
936 mutex_unlock(&dev_priv->gmbus_mutex);
937 }
938
939 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
940 {
941 struct intel_gmbus *bus = to_intel_gmbus(adapter);
942
943 return bus->force_bit;
944 }
945
946 void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
947 {
948 struct intel_gmbus *bus;
949 unsigned int pin;
950
951 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
952 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
953 continue;
954
955 bus = &dev_priv->gmbus[pin];
956 i2c_del_adapter(&bus->adapter);
957 }
958 }