This source file includes following definitions.
- to_powergate
- tegra_pmc_readl
- tegra_pmc_writel
- tegra_pmc_scratch_readl
- tegra_pmc_scratch_writel
- tegra_powergate_state
- tegra_powergate_is_valid
- tegra_powergate_is_available
- tegra_powergate_lookup
- tegra_powergate_set
- __tegra_powergate_remove_clamping
- tegra_powergate_disable_clocks
- tegra_powergate_enable_clocks
- tegra210_clk_handle_mbist_war
- tegra_powergate_power_up
- tegra_powergate_power_down
- tegra_genpd_power_on
- tegra_genpd_power_off
- tegra_powergate_power_on
- tegra_powergate_power_off
- tegra_powergate_is_powered
- tegra_powergate_remove_clamping
- tegra_powergate_sequence_power_up
- tegra_get_cpu_powergate_id
- tegra_pmc_cpu_is_powered
- tegra_pmc_cpu_power_on
- tegra_pmc_cpu_remove_clamping
- tegra_pmc_restart_notify
- powergate_show
- tegra_powergate_debugfs_init
- tegra_powergate_of_get_clks
- tegra_powergate_of_get_resets
- tegra_powergate_add
- tegra_powergate_init
- tegra_powergate_remove
- tegra_powergate_remove_all
- tegra_io_pad_find
- tegra_io_pad_get_dpd_register_bit
- tegra_io_pad_prepare
- tegra_io_pad_poll
- tegra_io_pad_unprepare
- tegra_io_pad_power_enable
- tegra_io_pad_power_disable
- tegra_io_pad_is_powered
- tegra_io_pad_set_voltage
- tegra_io_pad_get_voltage
- tegra_io_rail_power_on
- tegra_io_rail_power_off
- tegra_pmc_get_suspend_mode
- tegra_pmc_set_suspend_mode
- tegra_pmc_enter_suspend_mode
- tegra_pmc_parse_dt
- tegra_pmc_init
- tegra_pmc_init_tsense_reset
- tegra_io_pad_pinctrl_get_groups_count
- tegra_io_pad_pinctrl_get_group_name
- tegra_io_pad_pinctrl_get_group_pins
- tegra_io_pad_pinconf_get
- tegra_io_pad_pinconf_set
- tegra_pmc_pinctrl_init
- reset_reason_show
- reset_level_show
- tegra_pmc_reset_sysfs_init
- tegra_pmc_irq_translate
- tegra_pmc_irq_alloc
- tegra_pmc_irq_set_wake
- tegra_pmc_irq_set_type
- tegra_pmc_irq_init
- tegra_pmc_probe
- tegra_pmc_suspend
- tegra_pmc_resume
- tegra20_pmc_init
- tegra20_pmc_setup_irq_polarity
- tegra186_pmc_setup_irq_polarity
- tegra_pmc_detect_tz_only
- tegra_pmc_early_init
1
2
3
4
5
6
7
8
9
10
11
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk/tegra.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/of_address.h>
28 #include <linux/of_clk.h>
29 #include <linux/of.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinconf.h>
34 #include <linux/pinctrl/pinctrl.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
49 #include <dt-bindings/gpio/tegra186-gpio.h>
50 #include <dt-bindings/gpio/tegra194-gpio.h>
51
52 #define PMC_CNTRL 0x0
53 #define PMC_CNTRL_INTR_POLARITY BIT(17)
54 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16)
55 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15)
56 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14)
57 #define PMC_CNTRL_SYSCLK_OE BIT(11)
58 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10)
59 #define PMC_CNTRL_MAIN_RST BIT(4)
60
61 #define DPD_SAMPLE 0x020
62 #define DPD_SAMPLE_ENABLE BIT(0)
63 #define DPD_SAMPLE_DISABLE (0 << 0)
64
65 #define PWRGATE_TOGGLE 0x30
66 #define PWRGATE_TOGGLE_START BIT(8)
67
68 #define REMOVE_CLAMPING 0x34
69
70 #define PWRGATE_STATUS 0x38
71
72 #define PMC_IMPL_E_33V_PWR 0x40
73
74 #define PMC_PWR_DET 0x48
75
76 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
77 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
78 #define PMC_SCRATCH0_MODE_RCM BIT(1)
79 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
80 PMC_SCRATCH0_MODE_BOOTLOADER | \
81 PMC_SCRATCH0_MODE_RCM)
82
83 #define PMC_CPUPWRGOOD_TIMER 0xc8
84 #define PMC_CPUPWROFF_TIMER 0xcc
85
86 #define PMC_PWR_DET_VALUE 0xe4
87
88 #define PMC_SCRATCH41 0x140
89
90 #define PMC_SENSOR_CTRL 0x1b0
91 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
92 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
93
94 #define PMC_RST_STATUS_POR 0
95 #define PMC_RST_STATUS_WATCHDOG 1
96 #define PMC_RST_STATUS_SENSOR 2
97 #define PMC_RST_STATUS_SW_MAIN 3
98 #define PMC_RST_STATUS_LP0 4
99 #define PMC_RST_STATUS_AOTAG 5
100
101 #define IO_DPD_REQ 0x1b8
102 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
103 #define IO_DPD_REQ_CODE_OFF (1U << 30)
104 #define IO_DPD_REQ_CODE_ON (2U << 30)
105 #define IO_DPD_REQ_CODE_MASK (3U << 30)
106
107 #define IO_DPD_STATUS 0x1bc
108 #define IO_DPD2_REQ 0x1c0
109 #define IO_DPD2_STATUS 0x1c4
110 #define SEL_DPD_TIM 0x1c8
111
112 #define PMC_SCRATCH54 0x258
113 #define PMC_SCRATCH54_DATA_SHIFT 8
114 #define PMC_SCRATCH54_ADDR_SHIFT 0
115
116 #define PMC_SCRATCH55 0x25c
117 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
118 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
119 #define PMC_SCRATCH55_PINMUX_SHIFT 24
120 #define PMC_SCRATCH55_16BITOP BIT(15)
121 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
122 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
123
124 #define GPU_RG_CNTRL 0x2d4
125
126
127 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
128 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
129 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
130 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
131 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
132 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
133 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
134 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
135 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
136
137 #define WAKE_AOWAKE_CTRL 0x4f4
138 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
139
140
141 #define TEGRA_SMC_PMC 0xc2fffe00
142 #define TEGRA_SMC_PMC_READ 0xaa
143 #define TEGRA_SMC_PMC_WRITE 0xbb
144
145 struct tegra_powergate {
146 struct generic_pm_domain genpd;
147 struct tegra_pmc *pmc;
148 unsigned int id;
149 struct clk **clks;
150 unsigned int num_clks;
151 struct reset_control *reset;
152 };
153
154 struct tegra_io_pad_soc {
155 enum tegra_io_pad id;
156 unsigned int dpd;
157 unsigned int voltage;
158 const char *name;
159 };
160
161 struct tegra_pmc_regs {
162 unsigned int scratch0;
163 unsigned int dpd_req;
164 unsigned int dpd_status;
165 unsigned int dpd2_req;
166 unsigned int dpd2_status;
167 unsigned int rst_status;
168 unsigned int rst_source_shift;
169 unsigned int rst_source_mask;
170 unsigned int rst_level_shift;
171 unsigned int rst_level_mask;
172 };
173
174 struct tegra_wake_event {
175 const char *name;
176 unsigned int id;
177 unsigned int irq;
178 struct {
179 unsigned int instance;
180 unsigned int pin;
181 } gpio;
182 };
183
184 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
185 { \
186 .name = _name, \
187 .id = _id, \
188 .irq = _irq, \
189 .gpio = { \
190 .instance = UINT_MAX, \
191 .pin = UINT_MAX, \
192 }, \
193 }
194
195 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
196 { \
197 .name = _name, \
198 .id = _id, \
199 .irq = 0, \
200 .gpio = { \
201 .instance = _instance, \
202 .pin = _pin, \
203 }, \
204 }
205
206 struct tegra_pmc_soc {
207 unsigned int num_powergates;
208 const char *const *powergates;
209 unsigned int num_cpu_powergates;
210 const u8 *cpu_powergates;
211
212 bool has_tsense_reset;
213 bool has_gpu_clamps;
214 bool needs_mbist_war;
215 bool has_impl_33v_pwr;
216 bool maybe_tz_only;
217
218 const struct tegra_io_pad_soc *io_pads;
219 unsigned int num_io_pads;
220
221 const struct pinctrl_pin_desc *pin_descs;
222 unsigned int num_pin_descs;
223
224 const struct tegra_pmc_regs *regs;
225 void (*init)(struct tegra_pmc *pmc);
226 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
227 struct device_node *np,
228 bool invert);
229
230 const char * const *reset_sources;
231 unsigned int num_reset_sources;
232 const char * const *reset_levels;
233 unsigned int num_reset_levels;
234
235
236
237
238
239
240 const struct tegra_wake_event *wake_events;
241 unsigned int num_wake_events;
242 };
243
244 static const char * const tegra186_reset_sources[] = {
245 "SYS_RESET",
246 "AOWDT",
247 "MCCPLEXWDT",
248 "BPMPWDT",
249 "SCEWDT",
250 "SPEWDT",
251 "APEWDT",
252 "BCCPLEXWDT",
253 "SENSOR",
254 "AOTAG",
255 "VFSENSOR",
256 "SWREST",
257 "SC7",
258 "HSM",
259 "CORESIGHT"
260 };
261
262 static const char * const tegra186_reset_levels[] = {
263 "L0", "L1", "L2", "WARM"
264 };
265
266 static const char * const tegra30_reset_sources[] = {
267 "POWER_ON_RESET",
268 "WATCHDOG",
269 "SENSOR",
270 "SW_MAIN",
271 "LP0"
272 };
273
274 static const char * const tegra210_reset_sources[] = {
275 "POWER_ON_RESET",
276 "WATCHDOG",
277 "SENSOR",
278 "SW_MAIN",
279 "LP0",
280 "AOTAG"
281 };
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313 struct tegra_pmc {
314 struct device *dev;
315 void __iomem *base;
316 void __iomem *wake;
317 void __iomem *aotag;
318 void __iomem *scratch;
319 struct clk *clk;
320 struct dentry *debugfs;
321
322 const struct tegra_pmc_soc *soc;
323 bool tz_only;
324
325 unsigned long rate;
326
327 enum tegra_suspend_mode suspend_mode;
328 u32 cpu_good_time;
329 u32 cpu_off_time;
330 u32 core_osc_time;
331 u32 core_pmu_time;
332 u32 core_off_time;
333 bool corereq_high;
334 bool sysclkreq_high;
335 bool combined_req;
336 bool cpu_pwr_good_en;
337 u32 lp0_vec_phys;
338 u32 lp0_vec_size;
339 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
340
341 struct mutex powergates_lock;
342
343 struct pinctrl_dev *pctl_dev;
344
345 struct irq_domain *domain;
346 struct irq_chip irq;
347 };
348
349 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
350 .base = NULL,
351 .suspend_mode = TEGRA_SUSPEND_NONE,
352 };
353
354 static inline struct tegra_powergate *
355 to_powergate(struct generic_pm_domain *domain)
356 {
357 return container_of(domain, struct tegra_powergate, genpd);
358 }
359
360 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
361 {
362 struct arm_smccc_res res;
363
364 if (pmc->tz_only) {
365 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
366 0, 0, 0, &res);
367 if (res.a0) {
368 if (pmc->dev)
369 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
370 __func__, res.a0);
371 else
372 pr_warn("%s(): SMC failed: %lu\n", __func__,
373 res.a0);
374 }
375
376 return res.a1;
377 }
378
379 return readl(pmc->base + offset);
380 }
381
382 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
383 unsigned long offset)
384 {
385 struct arm_smccc_res res;
386
387 if (pmc->tz_only) {
388 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
389 value, 0, 0, 0, 0, &res);
390 if (res.a0) {
391 if (pmc->dev)
392 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
393 __func__, res.a0);
394 else
395 pr_warn("%s(): SMC failed: %lu\n", __func__,
396 res.a0);
397 }
398 } else {
399 writel(value, pmc->base + offset);
400 }
401 }
402
403 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
404 {
405 if (pmc->tz_only)
406 return tegra_pmc_readl(pmc, offset);
407
408 return readl(pmc->scratch + offset);
409 }
410
411 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
412 unsigned long offset)
413 {
414 if (pmc->tz_only)
415 tegra_pmc_writel(pmc, value, offset);
416 else
417 writel(value, pmc->scratch + offset);
418 }
419
420
421
422
423
424
425 static inline bool tegra_powergate_state(int id)
426 {
427 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
428 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
429 else
430 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
431 }
432
433 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
434 {
435 return (pmc->soc && pmc->soc->powergates[id]);
436 }
437
438 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
439 {
440 return test_bit(id, pmc->powergates_available);
441 }
442
443 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
444 {
445 unsigned int i;
446
447 if (!pmc || !pmc->soc || !name)
448 return -EINVAL;
449
450 for (i = 0; i < pmc->soc->num_powergates; i++) {
451 if (!tegra_powergate_is_valid(pmc, i))
452 continue;
453
454 if (!strcmp(name, pmc->soc->powergates[i]))
455 return i;
456 }
457
458 return -ENODEV;
459 }
460
461
462
463
464
465
466
467 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
468 bool new_state)
469 {
470 bool status;
471 int err;
472
473 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
474 return -EINVAL;
475
476 mutex_lock(&pmc->powergates_lock);
477
478 if (tegra_powergate_state(id) == new_state) {
479 mutex_unlock(&pmc->powergates_lock);
480 return 0;
481 }
482
483 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
484
485 err = readx_poll_timeout(tegra_powergate_state, id, status,
486 status == new_state, 10, 100000);
487
488 mutex_unlock(&pmc->powergates_lock);
489
490 return err;
491 }
492
493 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
494 unsigned int id)
495 {
496 u32 mask;
497
498 mutex_lock(&pmc->powergates_lock);
499
500
501
502
503
504 if (id == TEGRA_POWERGATE_3D) {
505 if (pmc->soc->has_gpu_clamps) {
506 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
507 goto out;
508 }
509 }
510
511
512
513
514
515 if (id == TEGRA_POWERGATE_VDEC)
516 mask = (1 << TEGRA_POWERGATE_PCIE);
517 else if (id == TEGRA_POWERGATE_PCIE)
518 mask = (1 << TEGRA_POWERGATE_VDEC);
519 else
520 mask = (1 << id);
521
522 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
523
524 out:
525 mutex_unlock(&pmc->powergates_lock);
526
527 return 0;
528 }
529
530 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
531 {
532 unsigned int i;
533
534 for (i = 0; i < pg->num_clks; i++)
535 clk_disable_unprepare(pg->clks[i]);
536 }
537
538 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
539 {
540 unsigned int i;
541 int err;
542
543 for (i = 0; i < pg->num_clks; i++) {
544 err = clk_prepare_enable(pg->clks[i]);
545 if (err)
546 goto out;
547 }
548
549 return 0;
550
551 out:
552 while (i--)
553 clk_disable_unprepare(pg->clks[i]);
554
555 return err;
556 }
557
558 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
559 {
560 return 0;
561 }
562
563 static int tegra_powergate_power_up(struct tegra_powergate *pg,
564 bool disable_clocks)
565 {
566 int err;
567
568 err = reset_control_assert(pg->reset);
569 if (err)
570 return err;
571
572 usleep_range(10, 20);
573
574 err = tegra_powergate_set(pg->pmc, pg->id, true);
575 if (err < 0)
576 return err;
577
578 usleep_range(10, 20);
579
580 err = tegra_powergate_enable_clocks(pg);
581 if (err)
582 goto disable_clks;
583
584 usleep_range(10, 20);
585
586 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
587 if (err)
588 goto disable_clks;
589
590 usleep_range(10, 20);
591
592 err = reset_control_deassert(pg->reset);
593 if (err)
594 goto powergate_off;
595
596 usleep_range(10, 20);
597
598 if (pg->pmc->soc->needs_mbist_war)
599 err = tegra210_clk_handle_mbist_war(pg->id);
600 if (err)
601 goto disable_clks;
602
603 if (disable_clocks)
604 tegra_powergate_disable_clocks(pg);
605
606 return 0;
607
608 disable_clks:
609 tegra_powergate_disable_clocks(pg);
610 usleep_range(10, 20);
611
612 powergate_off:
613 tegra_powergate_set(pg->pmc, pg->id, false);
614
615 return err;
616 }
617
618 static int tegra_powergate_power_down(struct tegra_powergate *pg)
619 {
620 int err;
621
622 err = tegra_powergate_enable_clocks(pg);
623 if (err)
624 return err;
625
626 usleep_range(10, 20);
627
628 err = reset_control_assert(pg->reset);
629 if (err)
630 goto disable_clks;
631
632 usleep_range(10, 20);
633
634 tegra_powergate_disable_clocks(pg);
635
636 usleep_range(10, 20);
637
638 err = tegra_powergate_set(pg->pmc, pg->id, false);
639 if (err)
640 goto assert_resets;
641
642 return 0;
643
644 assert_resets:
645 tegra_powergate_enable_clocks(pg);
646 usleep_range(10, 20);
647 reset_control_deassert(pg->reset);
648 usleep_range(10, 20);
649
650 disable_clks:
651 tegra_powergate_disable_clocks(pg);
652
653 return err;
654 }
655
656 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
657 {
658 struct tegra_powergate *pg = to_powergate(domain);
659 struct device *dev = pg->pmc->dev;
660 int err;
661
662 err = tegra_powergate_power_up(pg, true);
663 if (err) {
664 dev_err(dev, "failed to turn on PM domain %s: %d\n",
665 pg->genpd.name, err);
666 goto out;
667 }
668
669 reset_control_release(pg->reset);
670
671 out:
672 return err;
673 }
674
675 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
676 {
677 struct tegra_powergate *pg = to_powergate(domain);
678 struct device *dev = pg->pmc->dev;
679 int err;
680
681 err = reset_control_acquire(pg->reset);
682 if (err < 0) {
683 pr_err("failed to acquire resets: %d\n", err);
684 return err;
685 }
686
687 err = tegra_powergate_power_down(pg);
688 if (err) {
689 dev_err(dev, "failed to turn off PM domain %s: %d\n",
690 pg->genpd.name, err);
691 reset_control_release(pg->reset);
692 }
693
694 return err;
695 }
696
697
698
699
700
701 int tegra_powergate_power_on(unsigned int id)
702 {
703 if (!tegra_powergate_is_available(pmc, id))
704 return -EINVAL;
705
706 return tegra_powergate_set(pmc, id, true);
707 }
708 EXPORT_SYMBOL(tegra_powergate_power_on);
709
710
711
712
713
714 int tegra_powergate_power_off(unsigned int id)
715 {
716 if (!tegra_powergate_is_available(pmc, id))
717 return -EINVAL;
718
719 return tegra_powergate_set(pmc, id, false);
720 }
721 EXPORT_SYMBOL(tegra_powergate_power_off);
722
723
724
725
726
727
728 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
729 {
730 if (!tegra_powergate_is_valid(pmc, id))
731 return -EINVAL;
732
733 return tegra_powergate_state(id);
734 }
735
736
737
738
739
740 int tegra_powergate_remove_clamping(unsigned int id)
741 {
742 if (!tegra_powergate_is_available(pmc, id))
743 return -EINVAL;
744
745 return __tegra_powergate_remove_clamping(pmc, id);
746 }
747 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
748
749
750
751
752
753
754
755
756
757 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
758 struct reset_control *rst)
759 {
760 struct tegra_powergate *pg;
761 int err;
762
763 if (!tegra_powergate_is_available(pmc, id))
764 return -EINVAL;
765
766 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
767 if (!pg)
768 return -ENOMEM;
769
770 pg->id = id;
771 pg->clks = &clk;
772 pg->num_clks = 1;
773 pg->reset = rst;
774 pg->pmc = pmc;
775
776 err = tegra_powergate_power_up(pg, false);
777 if (err)
778 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
779 err);
780
781 kfree(pg);
782
783 return err;
784 }
785 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
786
787
788
789
790
791
792
793
794
795 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
796 unsigned int cpuid)
797 {
798 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
799 return pmc->soc->cpu_powergates[cpuid];
800
801 return -EINVAL;
802 }
803
804
805
806
807
808 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
809 {
810 int id;
811
812 id = tegra_get_cpu_powergate_id(pmc, cpuid);
813 if (id < 0)
814 return false;
815
816 return tegra_powergate_is_powered(pmc, id);
817 }
818
819
820
821
822
823 int tegra_pmc_cpu_power_on(unsigned int cpuid)
824 {
825 int id;
826
827 id = tegra_get_cpu_powergate_id(pmc, cpuid);
828 if (id < 0)
829 return id;
830
831 return tegra_powergate_set(pmc, id, true);
832 }
833
834
835
836
837
838 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
839 {
840 int id;
841
842 id = tegra_get_cpu_powergate_id(pmc, cpuid);
843 if (id < 0)
844 return id;
845
846 return tegra_powergate_remove_clamping(id);
847 }
848
849 static int tegra_pmc_restart_notify(struct notifier_block *this,
850 unsigned long action, void *data)
851 {
852 const char *cmd = data;
853 u32 value;
854
855 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
856 value &= ~PMC_SCRATCH0_MODE_MASK;
857
858 if (cmd) {
859 if (strcmp(cmd, "recovery") == 0)
860 value |= PMC_SCRATCH0_MODE_RECOVERY;
861
862 if (strcmp(cmd, "bootloader") == 0)
863 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
864
865 if (strcmp(cmd, "forced-recovery") == 0)
866 value |= PMC_SCRATCH0_MODE_RCM;
867 }
868
869 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
870
871
872 value = tegra_pmc_readl(pmc, PMC_CNTRL);
873 value |= PMC_CNTRL_MAIN_RST;
874 tegra_pmc_writel(pmc, value, PMC_CNTRL);
875
876 return NOTIFY_DONE;
877 }
878
879 static struct notifier_block tegra_pmc_restart_handler = {
880 .notifier_call = tegra_pmc_restart_notify,
881 .priority = 128,
882 };
883
884 static int powergate_show(struct seq_file *s, void *data)
885 {
886 unsigned int i;
887 int status;
888
889 seq_printf(s, " powergate powered\n");
890 seq_printf(s, "------------------\n");
891
892 for (i = 0; i < pmc->soc->num_powergates; i++) {
893 status = tegra_powergate_is_powered(pmc, i);
894 if (status < 0)
895 continue;
896
897 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
898 status ? "yes" : "no");
899 }
900
901 return 0;
902 }
903
904 DEFINE_SHOW_ATTRIBUTE(powergate);
905
906 static int tegra_powergate_debugfs_init(void)
907 {
908 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
909 &powergate_fops);
910 if (!pmc->debugfs)
911 return -ENOMEM;
912
913 return 0;
914 }
915
916 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
917 struct device_node *np)
918 {
919 struct clk *clk;
920 unsigned int i, count;
921 int err;
922
923 count = of_clk_get_parent_count(np);
924 if (count == 0)
925 return -ENODEV;
926
927 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
928 if (!pg->clks)
929 return -ENOMEM;
930
931 for (i = 0; i < count; i++) {
932 pg->clks[i] = of_clk_get(np, i);
933 if (IS_ERR(pg->clks[i])) {
934 err = PTR_ERR(pg->clks[i]);
935 goto err;
936 }
937 }
938
939 pg->num_clks = count;
940
941 return 0;
942
943 err:
944 while (i--)
945 clk_put(pg->clks[i]);
946
947 kfree(pg->clks);
948
949 return err;
950 }
951
952 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
953 struct device_node *np, bool off)
954 {
955 struct device *dev = pg->pmc->dev;
956 int err;
957
958 pg->reset = of_reset_control_array_get_exclusive_released(np);
959 if (IS_ERR(pg->reset)) {
960 err = PTR_ERR(pg->reset);
961 dev_err(dev, "failed to get device resets: %d\n", err);
962 return err;
963 }
964
965 err = reset_control_acquire(pg->reset);
966 if (err < 0) {
967 pr_err("failed to acquire resets: %d\n", err);
968 goto out;
969 }
970
971 if (off) {
972 err = reset_control_assert(pg->reset);
973 } else {
974 err = reset_control_deassert(pg->reset);
975 if (err < 0)
976 goto out;
977
978 reset_control_release(pg->reset);
979 }
980
981 out:
982 if (err) {
983 reset_control_release(pg->reset);
984 reset_control_put(pg->reset);
985 }
986
987 return err;
988 }
989
990 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
991 {
992 struct device *dev = pmc->dev;
993 struct tegra_powergate *pg;
994 int id, err = 0;
995 bool off;
996
997 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
998 if (!pg)
999 return -ENOMEM;
1000
1001 id = tegra_powergate_lookup(pmc, np->name);
1002 if (id < 0) {
1003 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1004 err = -ENODEV;
1005 goto free_mem;
1006 }
1007
1008
1009
1010
1011
1012 clear_bit(id, pmc->powergates_available);
1013
1014 pg->id = id;
1015 pg->genpd.name = np->name;
1016 pg->genpd.power_off = tegra_genpd_power_off;
1017 pg->genpd.power_on = tegra_genpd_power_on;
1018 pg->pmc = pmc;
1019
1020 off = !tegra_powergate_is_powered(pmc, pg->id);
1021
1022 err = tegra_powergate_of_get_clks(pg, np);
1023 if (err < 0) {
1024 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1025 goto set_available;
1026 }
1027
1028 err = tegra_powergate_of_get_resets(pg, np, off);
1029 if (err < 0) {
1030 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1031 goto remove_clks;
1032 }
1033
1034 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1035 if (off)
1036 WARN_ON(tegra_powergate_power_up(pg, true));
1037
1038 goto remove_resets;
1039 }
1040
1041 err = pm_genpd_init(&pg->genpd, NULL, off);
1042 if (err < 0) {
1043 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1044 err);
1045 goto remove_resets;
1046 }
1047
1048 err = of_genpd_add_provider_simple(np, &pg->genpd);
1049 if (err < 0) {
1050 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1051 np, err);
1052 goto remove_genpd;
1053 }
1054
1055 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1056
1057 return 0;
1058
1059 remove_genpd:
1060 pm_genpd_remove(&pg->genpd);
1061
1062 remove_resets:
1063 reset_control_put(pg->reset);
1064
1065 remove_clks:
1066 while (pg->num_clks--)
1067 clk_put(pg->clks[pg->num_clks]);
1068
1069 kfree(pg->clks);
1070
1071 set_available:
1072 set_bit(id, pmc->powergates_available);
1073
1074 free_mem:
1075 kfree(pg);
1076
1077 return err;
1078 }
1079
1080 static int tegra_powergate_init(struct tegra_pmc *pmc,
1081 struct device_node *parent)
1082 {
1083 struct device_node *np, *child;
1084 int err = 0;
1085
1086 np = of_get_child_by_name(parent, "powergates");
1087 if (!np)
1088 return 0;
1089
1090 for_each_child_of_node(np, child) {
1091 err = tegra_powergate_add(pmc, child);
1092 if (err < 0) {
1093 of_node_put(child);
1094 break;
1095 }
1096 }
1097
1098 of_node_put(np);
1099
1100 return err;
1101 }
1102
1103 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1104 {
1105 struct tegra_powergate *pg = to_powergate(genpd);
1106
1107 reset_control_put(pg->reset);
1108
1109 while (pg->num_clks--)
1110 clk_put(pg->clks[pg->num_clks]);
1111
1112 kfree(pg->clks);
1113
1114 set_bit(pg->id, pmc->powergates_available);
1115
1116 kfree(pg);
1117 }
1118
1119 static void tegra_powergate_remove_all(struct device_node *parent)
1120 {
1121 struct generic_pm_domain *genpd;
1122 struct device_node *np, *child;
1123
1124 np = of_get_child_by_name(parent, "powergates");
1125 if (!np)
1126 return;
1127
1128 for_each_child_of_node(np, child) {
1129 of_genpd_del_provider(child);
1130
1131 genpd = of_genpd_remove_last(child);
1132 if (IS_ERR(genpd))
1133 continue;
1134
1135 tegra_powergate_remove(genpd);
1136 }
1137
1138 of_node_put(np);
1139 }
1140
1141 static const struct tegra_io_pad_soc *
1142 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1143 {
1144 unsigned int i;
1145
1146 for (i = 0; i < pmc->soc->num_io_pads; i++)
1147 if (pmc->soc->io_pads[i].id == id)
1148 return &pmc->soc->io_pads[i];
1149
1150 return NULL;
1151 }
1152
1153 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1154 enum tegra_io_pad id,
1155 unsigned long *request,
1156 unsigned long *status,
1157 u32 *mask)
1158 {
1159 const struct tegra_io_pad_soc *pad;
1160
1161 pad = tegra_io_pad_find(pmc, id);
1162 if (!pad) {
1163 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1164 return -ENOENT;
1165 }
1166
1167 if (pad->dpd == UINT_MAX)
1168 return -ENOTSUPP;
1169
1170 *mask = BIT(pad->dpd % 32);
1171
1172 if (pad->dpd < 32) {
1173 *status = pmc->soc->regs->dpd_status;
1174 *request = pmc->soc->regs->dpd_req;
1175 } else {
1176 *status = pmc->soc->regs->dpd2_status;
1177 *request = pmc->soc->regs->dpd2_req;
1178 }
1179
1180 return 0;
1181 }
1182
1183 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1184 unsigned long *request, unsigned long *status,
1185 u32 *mask)
1186 {
1187 unsigned long rate, value;
1188 int err;
1189
1190 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1191 if (err)
1192 return err;
1193
1194 if (pmc->clk) {
1195 rate = clk_get_rate(pmc->clk);
1196 if (!rate) {
1197 dev_err(pmc->dev, "failed to get clock rate\n");
1198 return -ENODEV;
1199 }
1200
1201 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1202
1203
1204 value = DIV_ROUND_UP(1000000000, rate);
1205 value = DIV_ROUND_UP(200, value);
1206 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1207 }
1208
1209 return 0;
1210 }
1211
1212 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1213 u32 mask, u32 val, unsigned long timeout)
1214 {
1215 u32 value;
1216
1217 timeout = jiffies + msecs_to_jiffies(timeout);
1218
1219 while (time_after(timeout, jiffies)) {
1220 value = tegra_pmc_readl(pmc, offset);
1221 if ((value & mask) == val)
1222 return 0;
1223
1224 usleep_range(250, 1000);
1225 }
1226
1227 return -ETIMEDOUT;
1228 }
1229
1230 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1231 {
1232 if (pmc->clk)
1233 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1234 }
1235
1236
1237
1238
1239
1240
1241
1242 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1243 {
1244 unsigned long request, status;
1245 u32 mask;
1246 int err;
1247
1248 mutex_lock(&pmc->powergates_lock);
1249
1250 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1251 if (err < 0) {
1252 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1253 goto unlock;
1254 }
1255
1256 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1257
1258 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1259 if (err < 0) {
1260 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1261 goto unlock;
1262 }
1263
1264 tegra_io_pad_unprepare(pmc);
1265
1266 unlock:
1267 mutex_unlock(&pmc->powergates_lock);
1268 return err;
1269 }
1270 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1271
1272
1273
1274
1275
1276
1277
1278 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1279 {
1280 unsigned long request, status;
1281 u32 mask;
1282 int err;
1283
1284 mutex_lock(&pmc->powergates_lock);
1285
1286 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1287 if (err < 0) {
1288 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1289 goto unlock;
1290 }
1291
1292 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1293
1294 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1295 if (err < 0) {
1296 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1297 goto unlock;
1298 }
1299
1300 tegra_io_pad_unprepare(pmc);
1301
1302 unlock:
1303 mutex_unlock(&pmc->powergates_lock);
1304 return err;
1305 }
1306 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1307
1308 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1309 {
1310 unsigned long request, status;
1311 u32 mask, value;
1312 int err;
1313
1314 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1315 &mask);
1316 if (err)
1317 return err;
1318
1319 value = tegra_pmc_readl(pmc, status);
1320
1321 return !(value & mask);
1322 }
1323
1324 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1325 int voltage)
1326 {
1327 const struct tegra_io_pad_soc *pad;
1328 u32 value;
1329
1330 pad = tegra_io_pad_find(pmc, id);
1331 if (!pad)
1332 return -ENOENT;
1333
1334 if (pad->voltage == UINT_MAX)
1335 return -ENOTSUPP;
1336
1337 mutex_lock(&pmc->powergates_lock);
1338
1339 if (pmc->soc->has_impl_33v_pwr) {
1340 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1341
1342 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1343 value &= ~BIT(pad->voltage);
1344 else
1345 value |= BIT(pad->voltage);
1346
1347 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1348 } else {
1349
1350 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1351 value |= BIT(pad->voltage);
1352 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1353
1354
1355 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1356
1357 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1358 value &= ~BIT(pad->voltage);
1359 else
1360 value |= BIT(pad->voltage);
1361
1362 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1363 }
1364
1365 mutex_unlock(&pmc->powergates_lock);
1366
1367 usleep_range(100, 250);
1368
1369 return 0;
1370 }
1371
1372 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1373 {
1374 const struct tegra_io_pad_soc *pad;
1375 u32 value;
1376
1377 pad = tegra_io_pad_find(pmc, id);
1378 if (!pad)
1379 return -ENOENT;
1380
1381 if (pad->voltage == UINT_MAX)
1382 return -ENOTSUPP;
1383
1384 if (pmc->soc->has_impl_33v_pwr)
1385 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1386 else
1387 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1388
1389 if ((value & BIT(pad->voltage)) == 0)
1390 return TEGRA_IO_PAD_VOLTAGE_1V8;
1391
1392 return TEGRA_IO_PAD_VOLTAGE_3V3;
1393 }
1394
1395
1396
1397
1398
1399
1400
1401 int tegra_io_rail_power_on(unsigned int id)
1402 {
1403 return tegra_io_pad_power_enable(id);
1404 }
1405 EXPORT_SYMBOL(tegra_io_rail_power_on);
1406
1407
1408
1409
1410
1411
1412
1413 int tegra_io_rail_power_off(unsigned int id)
1414 {
1415 return tegra_io_pad_power_disable(id);
1416 }
1417 EXPORT_SYMBOL(tegra_io_rail_power_off);
1418
1419 #ifdef CONFIG_PM_SLEEP
1420 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1421 {
1422 return pmc->suspend_mode;
1423 }
1424
1425 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1426 {
1427 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1428 return;
1429
1430 pmc->suspend_mode = mode;
1431 }
1432
1433 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1434 {
1435 unsigned long long rate = 0;
1436 u32 value;
1437
1438 switch (mode) {
1439 case TEGRA_SUSPEND_LP1:
1440 rate = 32768;
1441 break;
1442
1443 case TEGRA_SUSPEND_LP2:
1444 rate = clk_get_rate(pmc->clk);
1445 break;
1446
1447 default:
1448 break;
1449 }
1450
1451 if (WARN_ON_ONCE(rate == 0))
1452 rate = 100000000;
1453
1454 if (rate != pmc->rate) {
1455 u64 ticks;
1456
1457 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1458 do_div(ticks, USEC_PER_SEC);
1459 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1460
1461 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1462 do_div(ticks, USEC_PER_SEC);
1463 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1464
1465 wmb();
1466
1467 pmc->rate = rate;
1468 }
1469
1470 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1471 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1472 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1473 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1474 }
1475 #endif
1476
1477 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1478 {
1479 u32 value, values[2];
1480
1481 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1482 } else {
1483 switch (value) {
1484 case 0:
1485 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1486 break;
1487
1488 case 1:
1489 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1490 break;
1491
1492 case 2:
1493 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1494 break;
1495
1496 default:
1497 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1498 break;
1499 }
1500 }
1501
1502 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1503
1504 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1505 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1506
1507 pmc->cpu_good_time = value;
1508
1509 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1510 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1511
1512 pmc->cpu_off_time = value;
1513
1514 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1515 values, ARRAY_SIZE(values)))
1516 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1517
1518 pmc->core_osc_time = values[0];
1519 pmc->core_pmu_time = values[1];
1520
1521 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1522 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1523
1524 pmc->core_off_time = value;
1525
1526 pmc->corereq_high = of_property_read_bool(np,
1527 "nvidia,core-power-req-active-high");
1528
1529 pmc->sysclkreq_high = of_property_read_bool(np,
1530 "nvidia,sys-clock-req-active-high");
1531
1532 pmc->combined_req = of_property_read_bool(np,
1533 "nvidia,combined-power-req");
1534
1535 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1536 "nvidia,cpu-pwr-good-en");
1537
1538 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1539 ARRAY_SIZE(values)))
1540 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1541 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1542
1543 pmc->lp0_vec_phys = values[0];
1544 pmc->lp0_vec_size = values[1];
1545
1546 return 0;
1547 }
1548
1549 static void tegra_pmc_init(struct tegra_pmc *pmc)
1550 {
1551 if (pmc->soc->init)
1552 pmc->soc->init(pmc);
1553 }
1554
1555 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1556 {
1557 static const char disabled[] = "emergency thermal reset disabled";
1558 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1559 struct device *dev = pmc->dev;
1560 struct device_node *np;
1561 u32 value, checksum;
1562
1563 if (!pmc->soc->has_tsense_reset)
1564 return;
1565
1566 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1567 if (!np) {
1568 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1569 return;
1570 }
1571
1572 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1573 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1574 goto out;
1575 }
1576
1577 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1578 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1579 goto out;
1580 }
1581
1582 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1583 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1584 goto out;
1585 }
1586
1587 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1588 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1589 goto out;
1590 }
1591
1592 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1593 pinmux = 0;
1594
1595 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1596 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1597 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1598
1599 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1600 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1601 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1602
1603 value = PMC_SCRATCH55_RESET_TEGRA;
1604 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1605 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1606 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1607
1608
1609
1610
1611
1612 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1613 + ((value >> 24) & 0xff);
1614 checksum &= 0xff;
1615 checksum = 0x100 - checksum;
1616
1617 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1618
1619 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1620
1621 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1622 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1623 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1624
1625 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1626
1627 out:
1628 of_node_put(np);
1629 }
1630
1631 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1632 {
1633 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1634
1635 return pmc->soc->num_io_pads;
1636 }
1637
1638 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1639 unsigned int group)
1640 {
1641 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1642
1643 return pmc->soc->io_pads[group].name;
1644 }
1645
1646 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1647 unsigned int group,
1648 const unsigned int **pins,
1649 unsigned int *num_pins)
1650 {
1651 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1652
1653 *pins = &pmc->soc->io_pads[group].id;
1654 *num_pins = 1;
1655
1656 return 0;
1657 }
1658
1659 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1660 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1661 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1662 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1663 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1664 .dt_free_map = pinconf_generic_dt_free_map,
1665 };
1666
1667 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1668 unsigned int pin, unsigned long *config)
1669 {
1670 enum pin_config_param param = pinconf_to_config_param(*config);
1671 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1672 const struct tegra_io_pad_soc *pad;
1673 int ret;
1674 u32 arg;
1675
1676 pad = tegra_io_pad_find(pmc, pin);
1677 if (!pad)
1678 return -EINVAL;
1679
1680 switch (param) {
1681 case PIN_CONFIG_POWER_SOURCE:
1682 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1683 if (ret < 0)
1684 return ret;
1685
1686 arg = ret;
1687 break;
1688
1689 case PIN_CONFIG_LOW_POWER_MODE:
1690 ret = tegra_io_pad_is_powered(pmc, pad->id);
1691 if (ret < 0)
1692 return ret;
1693
1694 arg = !ret;
1695 break;
1696
1697 default:
1698 return -EINVAL;
1699 }
1700
1701 *config = pinconf_to_config_packed(param, arg);
1702
1703 return 0;
1704 }
1705
1706 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1707 unsigned int pin, unsigned long *configs,
1708 unsigned int num_configs)
1709 {
1710 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1711 const struct tegra_io_pad_soc *pad;
1712 enum pin_config_param param;
1713 unsigned int i;
1714 int err;
1715 u32 arg;
1716
1717 pad = tegra_io_pad_find(pmc, pin);
1718 if (!pad)
1719 return -EINVAL;
1720
1721 for (i = 0; i < num_configs; ++i) {
1722 param = pinconf_to_config_param(configs[i]);
1723 arg = pinconf_to_config_argument(configs[i]);
1724
1725 switch (param) {
1726 case PIN_CONFIG_LOW_POWER_MODE:
1727 if (arg)
1728 err = tegra_io_pad_power_disable(pad->id);
1729 else
1730 err = tegra_io_pad_power_enable(pad->id);
1731 if (err)
1732 return err;
1733 break;
1734 case PIN_CONFIG_POWER_SOURCE:
1735 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1736 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1737 return -EINVAL;
1738 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1739 if (err)
1740 return err;
1741 break;
1742 default:
1743 return -EINVAL;
1744 }
1745 }
1746
1747 return 0;
1748 }
1749
1750 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1751 .pin_config_get = tegra_io_pad_pinconf_get,
1752 .pin_config_set = tegra_io_pad_pinconf_set,
1753 .is_generic = true,
1754 };
1755
1756 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1757 .pctlops = &tegra_io_pad_pinctrl_ops,
1758 .confops = &tegra_io_pad_pinconf_ops,
1759 };
1760
1761 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1762 {
1763 int err;
1764
1765 if (!pmc->soc->num_pin_descs)
1766 return 0;
1767
1768 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1769 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1770 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1771
1772 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1773 pmc);
1774 if (IS_ERR(pmc->pctl_dev)) {
1775 err = PTR_ERR(pmc->pctl_dev);
1776 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1777 err);
1778 return err;
1779 }
1780
1781 return 0;
1782 }
1783
1784 static ssize_t reset_reason_show(struct device *dev,
1785 struct device_attribute *attr, char *buf)
1786 {
1787 u32 value;
1788
1789 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1790 value &= pmc->soc->regs->rst_source_mask;
1791 value >>= pmc->soc->regs->rst_source_shift;
1792
1793 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1794 return sprintf(buf, "%s\n", "UNKNOWN");
1795
1796 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1797 }
1798
1799 static DEVICE_ATTR_RO(reset_reason);
1800
1801 static ssize_t reset_level_show(struct device *dev,
1802 struct device_attribute *attr, char *buf)
1803 {
1804 u32 value;
1805
1806 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1807 value &= pmc->soc->regs->rst_level_mask;
1808 value >>= pmc->soc->regs->rst_level_shift;
1809
1810 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1811 return sprintf(buf, "%s\n", "UNKNOWN");
1812
1813 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1814 }
1815
1816 static DEVICE_ATTR_RO(reset_level);
1817
1818 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1819 {
1820 struct device *dev = pmc->dev;
1821 int err = 0;
1822
1823 if (pmc->soc->reset_sources) {
1824 err = device_create_file(dev, &dev_attr_reset_reason);
1825 if (err < 0)
1826 dev_warn(dev,
1827 "failed to create attr \"reset_reason\": %d\n",
1828 err);
1829 }
1830
1831 if (pmc->soc->reset_levels) {
1832 err = device_create_file(dev, &dev_attr_reset_level);
1833 if (err < 0)
1834 dev_warn(dev,
1835 "failed to create attr \"reset_level\": %d\n",
1836 err);
1837 }
1838 }
1839
1840 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1841 struct irq_fwspec *fwspec,
1842 unsigned long *hwirq,
1843 unsigned int *type)
1844 {
1845 if (WARN_ON(fwspec->param_count < 2))
1846 return -EINVAL;
1847
1848 *hwirq = fwspec->param[0];
1849 *type = fwspec->param[1];
1850
1851 return 0;
1852 }
1853
1854 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1855 unsigned int num_irqs, void *data)
1856 {
1857 struct tegra_pmc *pmc = domain->host_data;
1858 const struct tegra_pmc_soc *soc = pmc->soc;
1859 struct irq_fwspec *fwspec = data;
1860 unsigned int i;
1861 int err = 0;
1862
1863 if (WARN_ON(num_irqs > 1))
1864 return -EINVAL;
1865
1866 for (i = 0; i < soc->num_wake_events; i++) {
1867 const struct tegra_wake_event *event = &soc->wake_events[i];
1868
1869 if (fwspec->param_count == 2) {
1870 struct irq_fwspec spec;
1871
1872 if (event->id != fwspec->param[0])
1873 continue;
1874
1875 err = irq_domain_set_hwirq_and_chip(domain, virq,
1876 event->id,
1877 &pmc->irq, pmc);
1878 if (err < 0)
1879 break;
1880
1881 spec.fwnode = &pmc->dev->of_node->fwnode;
1882 spec.param_count = 3;
1883 spec.param[0] = GIC_SPI;
1884 spec.param[1] = event->irq;
1885 spec.param[2] = fwspec->param[1];
1886
1887 err = irq_domain_alloc_irqs_parent(domain, virq,
1888 num_irqs, &spec);
1889
1890 break;
1891 }
1892
1893 if (fwspec->param_count == 3) {
1894 if (event->gpio.instance != fwspec->param[0] ||
1895 event->gpio.pin != fwspec->param[1])
1896 continue;
1897
1898 err = irq_domain_set_hwirq_and_chip(domain, virq,
1899 event->id,
1900 &pmc->irq, pmc);
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911 if (domain->parent)
1912 irq_domain_set_hwirq_and_chip(domain->parent,
1913 virq, 0, NULL,
1914 NULL);
1915
1916 break;
1917 }
1918 }
1919
1920
1921
1922
1923
1924
1925 if (i == soc->num_wake_events) {
1926 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX,
1927 &pmc->irq, pmc);
1928
1929
1930
1931
1932
1933
1934
1935
1936 if (domain->parent)
1937 irq_domain_set_hwirq_and_chip(domain->parent, virq, 0,
1938 NULL, NULL);
1939 }
1940
1941 return err;
1942 }
1943
1944 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
1945 .translate = tegra_pmc_irq_translate,
1946 .alloc = tegra_pmc_irq_alloc,
1947 };
1948
1949 static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
1950 {
1951 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1952 unsigned int offset, bit;
1953 u32 value;
1954
1955
1956 if (WARN_ON(data->hwirq == ULONG_MAX))
1957 return 0;
1958
1959 offset = data->hwirq / 32;
1960 bit = data->hwirq % 32;
1961
1962
1963 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
1964
1965
1966 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1967
1968 if (!on)
1969 value &= ~(1 << bit);
1970 else
1971 value |= 1 << bit;
1972
1973 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1974
1975
1976 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
1977
1978 return 0;
1979 }
1980
1981 static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type)
1982 {
1983 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1984 u32 value;
1985
1986
1987 if (data->hwirq == ULONG_MAX)
1988 return 0;
1989
1990 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
1991
1992 switch (type) {
1993 case IRQ_TYPE_EDGE_RISING:
1994 case IRQ_TYPE_LEVEL_HIGH:
1995 value |= WAKE_AOWAKE_CNTRL_LEVEL;
1996 break;
1997
1998 case IRQ_TYPE_EDGE_FALLING:
1999 case IRQ_TYPE_LEVEL_LOW:
2000 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2001 break;
2002
2003 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2004 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2005 break;
2006
2007 default:
2008 return -EINVAL;
2009 }
2010
2011 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2012
2013 return 0;
2014 }
2015
2016 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2017 {
2018 struct irq_domain *parent = NULL;
2019 struct device_node *np;
2020
2021 np = of_irq_find_parent(pmc->dev->of_node);
2022 if (np) {
2023 parent = irq_find_host(np);
2024 of_node_put(np);
2025 }
2026
2027 if (!parent)
2028 return 0;
2029
2030 pmc->irq.name = dev_name(pmc->dev);
2031 pmc->irq.irq_mask = irq_chip_mask_parent;
2032 pmc->irq.irq_unmask = irq_chip_unmask_parent;
2033 pmc->irq.irq_eoi = irq_chip_eoi_parent;
2034 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;
2035 pmc->irq.irq_set_type = tegra_pmc_irq_set_type;
2036 pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake;
2037
2038 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2039 &tegra_pmc_irq_domain_ops, pmc);
2040 if (!pmc->domain) {
2041 dev_err(pmc->dev, "failed to allocate domain\n");
2042 return -ENOMEM;
2043 }
2044
2045 return 0;
2046 }
2047
2048 static int tegra_pmc_probe(struct platform_device *pdev)
2049 {
2050 void __iomem *base;
2051 struct resource *res;
2052 int err;
2053
2054
2055
2056
2057
2058
2059 if (WARN_ON(!pmc->base || !pmc->soc))
2060 return -ENODEV;
2061
2062 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2063 if (err < 0)
2064 return err;
2065
2066
2067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2068 base = devm_ioremap_resource(&pdev->dev, res);
2069 if (IS_ERR(base))
2070 return PTR_ERR(base);
2071
2072 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2073 if (res) {
2074 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2075 if (IS_ERR(pmc->wake))
2076 return PTR_ERR(pmc->wake);
2077 } else {
2078 pmc->wake = base;
2079 }
2080
2081 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2082 if (res) {
2083 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2084 if (IS_ERR(pmc->aotag))
2085 return PTR_ERR(pmc->aotag);
2086 } else {
2087 pmc->aotag = base;
2088 }
2089
2090 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2091 if (res) {
2092 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2093 if (IS_ERR(pmc->scratch))
2094 return PTR_ERR(pmc->scratch);
2095 } else {
2096 pmc->scratch = base;
2097 }
2098
2099 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2100 if (IS_ERR(pmc->clk)) {
2101 err = PTR_ERR(pmc->clk);
2102
2103 if (err != -ENOENT) {
2104 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2105 return err;
2106 }
2107
2108 pmc->clk = NULL;
2109 }
2110
2111 pmc->dev = &pdev->dev;
2112
2113 tegra_pmc_init(pmc);
2114
2115 tegra_pmc_init_tsense_reset(pmc);
2116
2117 tegra_pmc_reset_sysfs_init(pmc);
2118
2119 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2120 err = tegra_powergate_debugfs_init();
2121 if (err < 0)
2122 goto cleanup_sysfs;
2123 }
2124
2125 err = register_restart_handler(&tegra_pmc_restart_handler);
2126 if (err) {
2127 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2128 err);
2129 goto cleanup_debugfs;
2130 }
2131
2132 err = tegra_pmc_pinctrl_init(pmc);
2133 if (err)
2134 goto cleanup_restart_handler;
2135
2136 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2137 if (err < 0)
2138 goto cleanup_powergates;
2139
2140 err = tegra_pmc_irq_init(pmc);
2141 if (err < 0)
2142 goto cleanup_powergates;
2143
2144 mutex_lock(&pmc->powergates_lock);
2145 iounmap(pmc->base);
2146 pmc->base = base;
2147 mutex_unlock(&pmc->powergates_lock);
2148
2149 platform_set_drvdata(pdev, pmc);
2150
2151 return 0;
2152
2153 cleanup_powergates:
2154 tegra_powergate_remove_all(pdev->dev.of_node);
2155 cleanup_restart_handler:
2156 unregister_restart_handler(&tegra_pmc_restart_handler);
2157 cleanup_debugfs:
2158 debugfs_remove(pmc->debugfs);
2159 cleanup_sysfs:
2160 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2161 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2162 return err;
2163 }
2164
2165 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2166 static int tegra_pmc_suspend(struct device *dev)
2167 {
2168 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2169
2170 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2171
2172 return 0;
2173 }
2174
2175 static int tegra_pmc_resume(struct device *dev)
2176 {
2177 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2178
2179 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2180
2181 return 0;
2182 }
2183
2184 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2185
2186 #endif
2187
2188 static const char * const tegra20_powergates[] = {
2189 [TEGRA_POWERGATE_CPU] = "cpu",
2190 [TEGRA_POWERGATE_3D] = "3d",
2191 [TEGRA_POWERGATE_VENC] = "venc",
2192 [TEGRA_POWERGATE_VDEC] = "vdec",
2193 [TEGRA_POWERGATE_PCIE] = "pcie",
2194 [TEGRA_POWERGATE_L2] = "l2",
2195 [TEGRA_POWERGATE_MPE] = "mpe",
2196 };
2197
2198 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2199 .scratch0 = 0x50,
2200 .dpd_req = 0x1b8,
2201 .dpd_status = 0x1bc,
2202 .dpd2_req = 0x1c0,
2203 .dpd2_status = 0x1c4,
2204 .rst_status = 0x1b4,
2205 .rst_source_shift = 0x0,
2206 .rst_source_mask = 0x7,
2207 .rst_level_shift = 0x0,
2208 .rst_level_mask = 0x0,
2209 };
2210
2211 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2212 {
2213 u32 value;
2214
2215
2216 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2217 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2218 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2219
2220 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2221
2222 if (pmc->sysclkreq_high)
2223 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2224 else
2225 value |= PMC_CNTRL_SYSCLK_POLARITY;
2226
2227
2228 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2229
2230
2231 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2232 value |= PMC_CNTRL_SYSCLK_OE;
2233 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2234 }
2235
2236 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2237 struct device_node *np,
2238 bool invert)
2239 {
2240 u32 value;
2241
2242 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2243
2244 if (invert)
2245 value |= PMC_CNTRL_INTR_POLARITY;
2246 else
2247 value &= ~PMC_CNTRL_INTR_POLARITY;
2248
2249 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2250 }
2251
2252 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2253 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2254 .powergates = tegra20_powergates,
2255 .num_cpu_powergates = 0,
2256 .cpu_powergates = NULL,
2257 .has_tsense_reset = false,
2258 .has_gpu_clamps = false,
2259 .needs_mbist_war = false,
2260 .has_impl_33v_pwr = false,
2261 .maybe_tz_only = false,
2262 .num_io_pads = 0,
2263 .io_pads = NULL,
2264 .num_pin_descs = 0,
2265 .pin_descs = NULL,
2266 .regs = &tegra20_pmc_regs,
2267 .init = tegra20_pmc_init,
2268 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2269 .reset_sources = NULL,
2270 .num_reset_sources = 0,
2271 .reset_levels = NULL,
2272 .num_reset_levels = 0,
2273 };
2274
2275 static const char * const tegra30_powergates[] = {
2276 [TEGRA_POWERGATE_CPU] = "cpu0",
2277 [TEGRA_POWERGATE_3D] = "3d0",
2278 [TEGRA_POWERGATE_VENC] = "venc",
2279 [TEGRA_POWERGATE_VDEC] = "vdec",
2280 [TEGRA_POWERGATE_PCIE] = "pcie",
2281 [TEGRA_POWERGATE_L2] = "l2",
2282 [TEGRA_POWERGATE_MPE] = "mpe",
2283 [TEGRA_POWERGATE_HEG] = "heg",
2284 [TEGRA_POWERGATE_SATA] = "sata",
2285 [TEGRA_POWERGATE_CPU1] = "cpu1",
2286 [TEGRA_POWERGATE_CPU2] = "cpu2",
2287 [TEGRA_POWERGATE_CPU3] = "cpu3",
2288 [TEGRA_POWERGATE_CELP] = "celp",
2289 [TEGRA_POWERGATE_3D1] = "3d1",
2290 };
2291
2292 static const u8 tegra30_cpu_powergates[] = {
2293 TEGRA_POWERGATE_CPU,
2294 TEGRA_POWERGATE_CPU1,
2295 TEGRA_POWERGATE_CPU2,
2296 TEGRA_POWERGATE_CPU3,
2297 };
2298
2299 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2300 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2301 .powergates = tegra30_powergates,
2302 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2303 .cpu_powergates = tegra30_cpu_powergates,
2304 .has_tsense_reset = true,
2305 .has_gpu_clamps = false,
2306 .needs_mbist_war = false,
2307 .has_impl_33v_pwr = false,
2308 .maybe_tz_only = false,
2309 .num_io_pads = 0,
2310 .io_pads = NULL,
2311 .num_pin_descs = 0,
2312 .pin_descs = NULL,
2313 .regs = &tegra20_pmc_regs,
2314 .init = tegra20_pmc_init,
2315 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2316 .reset_sources = tegra30_reset_sources,
2317 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2318 .reset_levels = NULL,
2319 .num_reset_levels = 0,
2320 };
2321
2322 static const char * const tegra114_powergates[] = {
2323 [TEGRA_POWERGATE_CPU] = "crail",
2324 [TEGRA_POWERGATE_3D] = "3d",
2325 [TEGRA_POWERGATE_VENC] = "venc",
2326 [TEGRA_POWERGATE_VDEC] = "vdec",
2327 [TEGRA_POWERGATE_MPE] = "mpe",
2328 [TEGRA_POWERGATE_HEG] = "heg",
2329 [TEGRA_POWERGATE_CPU1] = "cpu1",
2330 [TEGRA_POWERGATE_CPU2] = "cpu2",
2331 [TEGRA_POWERGATE_CPU3] = "cpu3",
2332 [TEGRA_POWERGATE_CELP] = "celp",
2333 [TEGRA_POWERGATE_CPU0] = "cpu0",
2334 [TEGRA_POWERGATE_C0NC] = "c0nc",
2335 [TEGRA_POWERGATE_C1NC] = "c1nc",
2336 [TEGRA_POWERGATE_DIS] = "dis",
2337 [TEGRA_POWERGATE_DISB] = "disb",
2338 [TEGRA_POWERGATE_XUSBA] = "xusba",
2339 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2340 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2341 };
2342
2343 static const u8 tegra114_cpu_powergates[] = {
2344 TEGRA_POWERGATE_CPU0,
2345 TEGRA_POWERGATE_CPU1,
2346 TEGRA_POWERGATE_CPU2,
2347 TEGRA_POWERGATE_CPU3,
2348 };
2349
2350 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2351 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2352 .powergates = tegra114_powergates,
2353 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2354 .cpu_powergates = tegra114_cpu_powergates,
2355 .has_tsense_reset = true,
2356 .has_gpu_clamps = false,
2357 .needs_mbist_war = false,
2358 .has_impl_33v_pwr = false,
2359 .maybe_tz_only = false,
2360 .num_io_pads = 0,
2361 .io_pads = NULL,
2362 .num_pin_descs = 0,
2363 .pin_descs = NULL,
2364 .regs = &tegra20_pmc_regs,
2365 .init = tegra20_pmc_init,
2366 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2367 .reset_sources = tegra30_reset_sources,
2368 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2369 .reset_levels = NULL,
2370 .num_reset_levels = 0,
2371 };
2372
2373 static const char * const tegra124_powergates[] = {
2374 [TEGRA_POWERGATE_CPU] = "crail",
2375 [TEGRA_POWERGATE_3D] = "3d",
2376 [TEGRA_POWERGATE_VENC] = "venc",
2377 [TEGRA_POWERGATE_PCIE] = "pcie",
2378 [TEGRA_POWERGATE_VDEC] = "vdec",
2379 [TEGRA_POWERGATE_MPE] = "mpe",
2380 [TEGRA_POWERGATE_HEG] = "heg",
2381 [TEGRA_POWERGATE_SATA] = "sata",
2382 [TEGRA_POWERGATE_CPU1] = "cpu1",
2383 [TEGRA_POWERGATE_CPU2] = "cpu2",
2384 [TEGRA_POWERGATE_CPU3] = "cpu3",
2385 [TEGRA_POWERGATE_CELP] = "celp",
2386 [TEGRA_POWERGATE_CPU0] = "cpu0",
2387 [TEGRA_POWERGATE_C0NC] = "c0nc",
2388 [TEGRA_POWERGATE_C1NC] = "c1nc",
2389 [TEGRA_POWERGATE_SOR] = "sor",
2390 [TEGRA_POWERGATE_DIS] = "dis",
2391 [TEGRA_POWERGATE_DISB] = "disb",
2392 [TEGRA_POWERGATE_XUSBA] = "xusba",
2393 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2394 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2395 [TEGRA_POWERGATE_VIC] = "vic",
2396 [TEGRA_POWERGATE_IRAM] = "iram",
2397 };
2398
2399 static const u8 tegra124_cpu_powergates[] = {
2400 TEGRA_POWERGATE_CPU0,
2401 TEGRA_POWERGATE_CPU1,
2402 TEGRA_POWERGATE_CPU2,
2403 TEGRA_POWERGATE_CPU3,
2404 };
2405
2406 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2407 ((struct tegra_io_pad_soc) { \
2408 .id = (_id), \
2409 .dpd = (_dpd), \
2410 .voltage = (_voltage), \
2411 .name = (_name), \
2412 })
2413
2414 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2415 ((struct pinctrl_pin_desc) { \
2416 .number = (_id), \
2417 .name = (_name) \
2418 })
2419
2420 #define TEGRA124_IO_PAD_TABLE(_pad) \
2421 \
2422 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2423 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2424 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2425 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2426 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2427 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2428 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2429 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2430 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2431 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2432 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2433 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2434 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2435 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2436 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2437 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2438 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2439 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2440 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2441 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2442 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2443 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2444 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2445 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2446 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2447 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2448 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2449 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2450 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2451 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2452
2453 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2454 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2455 };
2456
2457 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2458 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2459 };
2460
2461 static const struct tegra_pmc_soc tegra124_pmc_soc = {
2462 .num_powergates = ARRAY_SIZE(tegra124_powergates),
2463 .powergates = tegra124_powergates,
2464 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
2465 .cpu_powergates = tegra124_cpu_powergates,
2466 .has_tsense_reset = true,
2467 .has_gpu_clamps = true,
2468 .needs_mbist_war = false,
2469 .has_impl_33v_pwr = false,
2470 .maybe_tz_only = false,
2471 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
2472 .io_pads = tegra124_io_pads,
2473 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
2474 .pin_descs = tegra124_pin_descs,
2475 .regs = &tegra20_pmc_regs,
2476 .init = tegra20_pmc_init,
2477 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2478 .reset_sources = tegra30_reset_sources,
2479 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2480 .reset_levels = NULL,
2481 .num_reset_levels = 0,
2482 };
2483
2484 static const char * const tegra210_powergates[] = {
2485 [TEGRA_POWERGATE_CPU] = "crail",
2486 [TEGRA_POWERGATE_3D] = "3d",
2487 [TEGRA_POWERGATE_VENC] = "venc",
2488 [TEGRA_POWERGATE_PCIE] = "pcie",
2489 [TEGRA_POWERGATE_MPE] = "mpe",
2490 [TEGRA_POWERGATE_SATA] = "sata",
2491 [TEGRA_POWERGATE_CPU1] = "cpu1",
2492 [TEGRA_POWERGATE_CPU2] = "cpu2",
2493 [TEGRA_POWERGATE_CPU3] = "cpu3",
2494 [TEGRA_POWERGATE_CPU0] = "cpu0",
2495 [TEGRA_POWERGATE_C0NC] = "c0nc",
2496 [TEGRA_POWERGATE_SOR] = "sor",
2497 [TEGRA_POWERGATE_DIS] = "dis",
2498 [TEGRA_POWERGATE_DISB] = "disb",
2499 [TEGRA_POWERGATE_XUSBA] = "xusba",
2500 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2501 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2502 [TEGRA_POWERGATE_VIC] = "vic",
2503 [TEGRA_POWERGATE_IRAM] = "iram",
2504 [TEGRA_POWERGATE_NVDEC] = "nvdec",
2505 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
2506 [TEGRA_POWERGATE_AUD] = "aud",
2507 [TEGRA_POWERGATE_DFD] = "dfd",
2508 [TEGRA_POWERGATE_VE2] = "ve2",
2509 };
2510
2511 static const u8 tegra210_cpu_powergates[] = {
2512 TEGRA_POWERGATE_CPU0,
2513 TEGRA_POWERGATE_CPU1,
2514 TEGRA_POWERGATE_CPU2,
2515 TEGRA_POWERGATE_CPU3,
2516 };
2517
2518 #define TEGRA210_IO_PAD_TABLE(_pad) \
2519 \
2520 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
2521 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
2522 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
2523 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2524 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2525 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
2526 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
2527 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
2528 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
2529 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
2530 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
2531 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
2532 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
2533 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2534 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2535 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2536 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2537 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
2538 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
2539 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
2540 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2541 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2542 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2543 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2544 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2545 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2546 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2547 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
2548 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
2549 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
2550 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
2551 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
2552 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
2553 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2554 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2555 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2556 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
2557 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
2558
2559 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
2560 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
2561 };
2562
2563 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
2564 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2565 };
2566
2567 static const struct tegra_pmc_soc tegra210_pmc_soc = {
2568 .num_powergates = ARRAY_SIZE(tegra210_powergates),
2569 .powergates = tegra210_powergates,
2570 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
2571 .cpu_powergates = tegra210_cpu_powergates,
2572 .has_tsense_reset = true,
2573 .has_gpu_clamps = true,
2574 .needs_mbist_war = true,
2575 .has_impl_33v_pwr = false,
2576 .maybe_tz_only = true,
2577 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
2578 .io_pads = tegra210_io_pads,
2579 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
2580 .pin_descs = tegra210_pin_descs,
2581 .regs = &tegra20_pmc_regs,
2582 .init = tegra20_pmc_init,
2583 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2584 .reset_sources = tegra210_reset_sources,
2585 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
2586 .reset_levels = NULL,
2587 .num_reset_levels = 0,
2588 };
2589
2590 #define TEGRA186_IO_PAD_TABLE(_pad) \
2591 \
2592 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2593 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2594 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2595 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2596 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
2597 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
2598 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2599 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
2600 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2601 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2602 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2603 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
2604 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2605 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2606 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2607 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
2608 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
2609 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
2610 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2611 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
2612 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
2613 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
2614 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
2615 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
2616 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
2617 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
2618 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
2619 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
2620 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
2621 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
2622 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
2623 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
2624 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
2625 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
2626 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
2627 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
2628 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
2629 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
2630
2631 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
2632 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
2633 };
2634
2635 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
2636 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2637 };
2638
2639 static const struct tegra_pmc_regs tegra186_pmc_regs = {
2640 .scratch0 = 0x2000,
2641 .dpd_req = 0x74,
2642 .dpd_status = 0x78,
2643 .dpd2_req = 0x7c,
2644 .dpd2_status = 0x80,
2645 .rst_status = 0x70,
2646 .rst_source_shift = 0x2,
2647 .rst_source_mask = 0x3C,
2648 .rst_level_shift = 0x0,
2649 .rst_level_mask = 0x3,
2650 };
2651
2652 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2653 struct device_node *np,
2654 bool invert)
2655 {
2656 struct resource regs;
2657 void __iomem *wake;
2658 u32 value;
2659 int index;
2660
2661 index = of_property_match_string(np, "reg-names", "wake");
2662 if (index < 0) {
2663 dev_err(pmc->dev, "failed to find PMC wake registers\n");
2664 return;
2665 }
2666
2667 of_address_to_resource(np, index, ®s);
2668
2669 wake = ioremap_nocache(regs.start, resource_size(®s));
2670 if (!wake) {
2671 dev_err(pmc->dev, "failed to map PMC wake registers\n");
2672 return;
2673 }
2674
2675 value = readl(wake + WAKE_AOWAKE_CTRL);
2676
2677 if (invert)
2678 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
2679 else
2680 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
2681
2682 writel(value, wake + WAKE_AOWAKE_CTRL);
2683
2684 iounmap(wake);
2685 }
2686
2687 static const struct tegra_wake_event tegra186_wake_events[] = {
2688 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
2689 TEGRA_WAKE_IRQ("rtc", 73, 10),
2690 };
2691
2692 static const struct tegra_pmc_soc tegra186_pmc_soc = {
2693 .num_powergates = 0,
2694 .powergates = NULL,
2695 .num_cpu_powergates = 0,
2696 .cpu_powergates = NULL,
2697 .has_tsense_reset = false,
2698 .has_gpu_clamps = false,
2699 .needs_mbist_war = false,
2700 .has_impl_33v_pwr = true,
2701 .maybe_tz_only = false,
2702 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
2703 .io_pads = tegra186_io_pads,
2704 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
2705 .pin_descs = tegra186_pin_descs,
2706 .regs = &tegra186_pmc_regs,
2707 .init = NULL,
2708 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2709 .reset_sources = tegra186_reset_sources,
2710 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
2711 .reset_levels = tegra186_reset_levels,
2712 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
2713 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
2714 .wake_events = tegra186_wake_events,
2715 };
2716
2717 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
2718 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
2719 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
2720 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
2721 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
2722 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
2723 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
2724 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
2725 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX },
2726 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX },
2727 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX },
2728 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX },
2729 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX },
2730 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
2731 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX },
2732 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX },
2733 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
2734 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX },
2735 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX },
2736 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX },
2737 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX },
2738 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX },
2739 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX },
2740 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX },
2741 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
2742 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX },
2743 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX },
2744 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
2745 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
2746 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
2747 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX },
2748 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX },
2749 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX },
2750 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
2751 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX },
2752 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
2753 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
2754 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
2755 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
2756 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
2757 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
2758 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX },
2759 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX },
2760 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
2761 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
2762 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
2763 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
2764 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
2765 };
2766
2767 static const struct tegra_wake_event tegra194_wake_events[] = {
2768 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
2769 TEGRA_WAKE_IRQ("rtc", 73, 10),
2770 };
2771
2772 static const struct tegra_pmc_soc tegra194_pmc_soc = {
2773 .num_powergates = 0,
2774 .powergates = NULL,
2775 .num_cpu_powergates = 0,
2776 .cpu_powergates = NULL,
2777 .has_tsense_reset = false,
2778 .has_gpu_clamps = false,
2779 .needs_mbist_war = false,
2780 .has_impl_33v_pwr = false,
2781 .maybe_tz_only = false,
2782 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
2783 .io_pads = tegra194_io_pads,
2784 .regs = &tegra186_pmc_regs,
2785 .init = NULL,
2786 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2787 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
2788 .wake_events = tegra194_wake_events,
2789 };
2790
2791 static const struct of_device_id tegra_pmc_match[] = {
2792 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
2793 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
2794 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
2795 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
2796 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
2797 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
2798 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
2799 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
2800 { }
2801 };
2802
2803 static struct platform_driver tegra_pmc_driver = {
2804 .driver = {
2805 .name = "tegra-pmc",
2806 .suppress_bind_attrs = true,
2807 .of_match_table = tegra_pmc_match,
2808 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2809 .pm = &tegra_pmc_pm_ops,
2810 #endif
2811 },
2812 .probe = tegra_pmc_probe,
2813 };
2814 builtin_platform_driver(tegra_pmc_driver);
2815
2816 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
2817 {
2818 u32 value, saved;
2819
2820 saved = readl(pmc->base + pmc->soc->regs->scratch0);
2821 value = saved ^ 0xffffffff;
2822
2823 if (value == 0xffffffff)
2824 value = 0xdeadbeef;
2825
2826
2827 writel(value, pmc->base + pmc->soc->regs->scratch0);
2828 value = readl(pmc->base + pmc->soc->regs->scratch0);
2829
2830
2831 if (value == 0) {
2832 pr_info("access to PMC is restricted to TZ\n");
2833 return true;
2834 }
2835
2836
2837 writel(saved, pmc->base + pmc->soc->regs->scratch0);
2838
2839 return false;
2840 }
2841
2842
2843
2844
2845
2846 static int __init tegra_pmc_early_init(void)
2847 {
2848 const struct of_device_id *match;
2849 struct device_node *np;
2850 struct resource regs;
2851 unsigned int i;
2852 bool invert;
2853
2854 mutex_init(&pmc->powergates_lock);
2855
2856 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
2857 if (!np) {
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
2869 pr_warn("DT node not found, powergating disabled\n");
2870
2871 regs.start = 0x7000e400;
2872 regs.end = 0x7000e7ff;
2873 regs.flags = IORESOURCE_MEM;
2874
2875 pr_warn("Using memory region %pR\n", ®s);
2876 } else {
2877
2878
2879
2880
2881 return 0;
2882 }
2883 } else {
2884
2885
2886
2887
2888 if (of_address_to_resource(np, 0, ®s) < 0) {
2889 pr_err("failed to get PMC registers\n");
2890 of_node_put(np);
2891 return -ENXIO;
2892 }
2893 }
2894
2895 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
2896 if (!pmc->base) {
2897 pr_err("failed to map PMC registers\n");
2898 of_node_put(np);
2899 return -ENXIO;
2900 }
2901
2902 if (np) {
2903 pmc->soc = match->data;
2904
2905 if (pmc->soc->maybe_tz_only)
2906 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
2907
2908
2909 for (i = 0; i < pmc->soc->num_powergates; i++)
2910 if (pmc->soc->powergates[i])
2911 set_bit(i, pmc->powergates_available);
2912
2913
2914
2915
2916
2917 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
2918
2919 pmc->soc->setup_irq_polarity(pmc, np, invert);
2920
2921 of_node_put(np);
2922 }
2923
2924 return 0;
2925 }
2926 early_initcall(tegra_pmc_early_init);