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12 #ifndef _POWERPC_SYSDEV_QE_IC_H
13 #define _POWERPC_SYSDEV_QE_IC_H
14
15 #include <soc/fsl/qe/qe_ic.h>
16
17 #define NR_QE_IC_INTS 64
18
19
20 #define QEIC_CICR 0x00
21 #define QEIC_CIVEC 0x04
22 #define QEIC_CRIPNR 0x08
23 #define QEIC_CIPNR 0x0c
24 #define QEIC_CIPXCC 0x10
25 #define QEIC_CIPYCC 0x14
26 #define QEIC_CIPWCC 0x18
27 #define QEIC_CIPZCC 0x1c
28 #define QEIC_CIMR 0x20
29 #define QEIC_CRIMR 0x24
30 #define QEIC_CICNR 0x28
31 #define QEIC_CIPRTA 0x30
32 #define QEIC_CIPRTB 0x34
33 #define QEIC_CRICR 0x3c
34 #define QEIC_CHIVEC 0x60
35
36
37 #define CIPCC_SHIFT_PRI0 29
38 #define CIPCC_SHIFT_PRI1 26
39 #define CIPCC_SHIFT_PRI2 23
40 #define CIPCC_SHIFT_PRI3 20
41 #define CIPCC_SHIFT_PRI4 13
42 #define CIPCC_SHIFT_PRI5 10
43 #define CIPCC_SHIFT_PRI6 7
44 #define CIPCC_SHIFT_PRI7 4
45
46
47 #define CICR_GWCC 0x00040000
48 #define CICR_GXCC 0x00020000
49 #define CICR_GYCC 0x00010000
50 #define CICR_GZCC 0x00080000
51 #define CICR_GRTA 0x00200000
52 #define CICR_GRTB 0x00400000
53 #define CICR_HPIT_SHIFT 8
54 #define CICR_HPIT_MASK 0x00000300
55 #define CICR_HP_SHIFT 24
56 #define CICR_HP_MASK 0x3f000000
57
58
59 #define CICNR_WCC1T_SHIFT 20
60 #define CICNR_ZCC1T_SHIFT 28
61 #define CICNR_YCC1T_SHIFT 12
62 #define CICNR_XCC1T_SHIFT 4
63
64
65 #define CRICR_RTA1T_SHIFT 20
66 #define CRICR_RTB1T_SHIFT 28
67
68
69 #define SIGNAL_MASK 3
70 #define SIGNAL_HIGH 2
71 #define SIGNAL_LOW 0
72
73 struct qe_ic {
74
75 volatile u32 __iomem *regs;
76
77
78 struct irq_domain *irqhost;
79
80
81 struct irq_chip hc_irq;
82
83
84 unsigned int virq_high;
85 unsigned int virq_low;
86 };
87
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90
91 struct qe_ic_info {
92 u32 mask;
93 u32 mask_reg;
94 u8 pri_code;
95
96 u32 pri_reg;
97 };
98
99 #endif