root/drivers/video/fbdev/arkfb.c

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DEFINITIONS

This source file includes following definitions.
  1. arkfb_settile
  2. arkfb_tilecursor
  3. expand_color
  4. arkfb_iplan_imageblit
  5. arkfb_iplan_fillrect
  6. expand_pixel
  7. arkfb_cfb4_imageblit
  8. arkfb_imageblit
  9. arkfb_fillrect
  10. dac_read_reg
  11. dac_read_regs
  12. dac_write_reg
  13. dac_write_regs
  14. dac_set_mode
  15. dac_set_freq
  16. dac_release
  17. ics5342_set_mode
  18. ics5342_set_freq
  19. ics5342_release
  20. ics5342_init
  21. ark_dac_read_regs
  22. ark_dac_write_regs
  23. ark_set_pixclock
  24. arkfb_open
  25. arkfb_release
  26. arkfb_check_var
  27. arkfb_set_par
  28. arkfb_setcolreg
  29. arkfb_blank
  30. arkfb_pan_display
  31. ark_pci_probe
  32. ark_pci_remove
  33. ark_pci_suspend
  34. ark_pci_resume
  35. arkfb_cleanup
  36. arkfb_init

   1 /*
   2  *  linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
   3  *  with ICS 5342 dac (it is easy to add support for different dacs).
   4  *
   5  *  Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org>
   6  *
   7  *  This file is subject to the terms and conditions of the GNU General Public
   8  *  License.  See the file COPYING in the main directory of this archive for
   9  *  more details.
  10  *
  11  *  Code is based on s3fb
  12  */
  13 
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/string.h>
  18 #include <linux/mm.h>
  19 #include <linux/tty.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/fb.h>
  23 #include <linux/svga.h>
  24 #include <linux/init.h>
  25 #include <linux/pci.h>
  26 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
  27 #include <video/vga.h>
  28 
  29 struct arkfb_info {
  30         int mclk_freq;
  31         int wc_cookie;
  32 
  33         struct dac_info *dac;
  34         struct vgastate state;
  35         struct mutex open_lock;
  36         unsigned int ref_count;
  37         u32 pseudo_palette[16];
  38 };
  39 
  40 
  41 /* ------------------------------------------------------------------------- */
  42 
  43 
  44 static const struct svga_fb_format arkfb_formats[] = {
  45         { 0,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,
  46                 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4,   FB_VISUAL_PSEUDOCOLOR, 8, 8},
  47         { 4,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,
  48                 FB_TYPE_PACKED_PIXELS, 0,               FB_VISUAL_PSEUDOCOLOR, 8, 16},
  49         { 4,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 1,
  50                 FB_TYPE_INTERLEAVED_PLANES, 1,          FB_VISUAL_PSEUDOCOLOR, 8, 16},
  51         { 8,  {0, 6, 0},  {0, 6, 0},  {0, 6, 0}, {0, 0, 0}, 0,
  52                 FB_TYPE_PACKED_PIXELS, 0,               FB_VISUAL_PSEUDOCOLOR, 8, 8},
  53         {16,  {10, 5, 0}, {5, 5, 0},  {0, 5, 0}, {0, 0, 0}, 0,
  54                 FB_TYPE_PACKED_PIXELS, 0,               FB_VISUAL_TRUECOLOR, 4, 4},
  55         {16,  {11, 5, 0}, {5, 6, 0},  {0, 5, 0}, {0, 0, 0}, 0,
  56                 FB_TYPE_PACKED_PIXELS, 0,               FB_VISUAL_TRUECOLOR, 4, 4},
  57         {24,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,
  58                 FB_TYPE_PACKED_PIXELS, 0,               FB_VISUAL_TRUECOLOR, 8, 8},
  59         {32,  {16, 8, 0}, {8, 8, 0},  {0, 8, 0}, {0, 0, 0}, 0,
  60                 FB_TYPE_PACKED_PIXELS, 0,               FB_VISUAL_TRUECOLOR, 2, 2},
  61         SVGA_FORMAT_END
  62 };
  63 
  64 
  65 /* CRT timing register sets */
  66 
  67 static const struct vga_regset ark_h_total_regs[]        = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
  68 static const struct vga_regset ark_h_display_regs[]      = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
  69 static const struct vga_regset ark_h_blank_start_regs[]  = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
  70 static const struct vga_regset ark_h_blank_end_regs[]    = {{0x03, 0, 4}, {0x05, 7, 7   }, VGA_REGSET_END};
  71 static const struct vga_regset ark_h_sync_start_regs[]   = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
  72 static const struct vga_regset ark_h_sync_end_regs[]     = {{0x05, 0, 4}, VGA_REGSET_END};
  73 
  74 static const struct vga_regset ark_v_total_regs[]        = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
  75 static const struct vga_regset ark_v_display_regs[]      = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
  76 static const struct vga_regset ark_v_blank_start_regs[]  = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
  77 // const struct vga_regset ark_v_blank_end_regs[]    = {{0x16, 0, 6}, VGA_REGSET_END};
  78 static const struct vga_regset ark_v_blank_end_regs[]    = {{0x16, 0, 7}, VGA_REGSET_END};
  79 static const struct vga_regset ark_v_sync_start_regs[]   = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
  80 static const struct vga_regset ark_v_sync_end_regs[]     = {{0x11, 0, 3}, VGA_REGSET_END};
  81 
  82 static const struct vga_regset ark_line_compare_regs[]   = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
  83 static const struct vga_regset ark_start_address_regs[]  = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
  84 static const struct vga_regset ark_offset_regs[]         = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
  85 
  86 static const struct svga_timing_regs ark_timing_regs     = {
  87         ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
  88         ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
  89         ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
  90         ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
  91 };
  92 
  93 
  94 /* ------------------------------------------------------------------------- */
  95 
  96 
  97 /* Module parameters */
  98 
  99 static char *mode_option = "640x480-8@60";
 100 
 101 MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>");
 102 MODULE_LICENSE("GPL");
 103 MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
 104 
 105 module_param(mode_option, charp, 0444);
 106 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
 107 module_param_named(mode, mode_option, charp, 0444);
 108 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
 109 
 110 static int threshold = 4;
 111 
 112 module_param(threshold, int, 0644);
 113 MODULE_PARM_DESC(threshold, "FIFO threshold");
 114 
 115 
 116 /* ------------------------------------------------------------------------- */
 117 
 118 
 119 static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
 120 {
 121         const u8 *font = map->data;
 122         u8 __iomem *fb = (u8 __iomem *)info->screen_base;
 123         int i, c;
 124 
 125         if ((map->width != 8) || (map->height != 16) ||
 126             (map->depth != 1) || (map->length != 256)) {
 127                 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
 128                        map->width, map->height, map->depth, map->length);
 129                 return;
 130         }
 131 
 132         fb += 2;
 133         for (c = 0; c < map->length; c++) {
 134                 for (i = 0; i < map->height; i++) {
 135                         fb_writeb(font[i], &fb[i * 4]);
 136                         fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
 137                 }
 138                 fb += 128;
 139 
 140                 if ((c % 8) == 7)
 141                         fb += 128*8;
 142 
 143                 font += map->height;
 144         }
 145 }
 146 
 147 static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
 148 {
 149         struct arkfb_info *par = info->par;
 150 
 151         svga_tilecursor(par->state.vgabase, info, cursor);
 152 }
 153 
 154 static struct fb_tile_ops arkfb_tile_ops = {
 155         .fb_settile     = arkfb_settile,
 156         .fb_tilecopy    = svga_tilecopy,
 157         .fb_tilefill    = svga_tilefill,
 158         .fb_tileblit    = svga_tileblit,
 159         .fb_tilecursor  = arkfb_tilecursor,
 160         .fb_get_tilemax = svga_get_tilemax,
 161 };
 162 
 163 
 164 /* ------------------------------------------------------------------------- */
 165 
 166 
 167 /* image data is MSB-first, fb structure is MSB-first too */
 168 static inline u32 expand_color(u32 c)
 169 {
 170         return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
 171 }
 172 
 173 /* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
 174 static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
 175 {
 176         u32 fg = expand_color(image->fg_color);
 177         u32 bg = expand_color(image->bg_color);
 178         const u8 *src1, *src;
 179         u8 __iomem *dst1;
 180         u32 __iomem *dst;
 181         u32 val;
 182         int x, y;
 183 
 184         src1 = image->data;
 185         dst1 = info->screen_base + (image->dy * info->fix.line_length)
 186                  + ((image->dx / 8) * 4);
 187 
 188         for (y = 0; y < image->height; y++) {
 189                 src = src1;
 190                 dst = (u32 __iomem *) dst1;
 191                 for (x = 0; x < image->width; x += 8) {
 192                         val = *(src++) * 0x01010101;
 193                         val = (val & fg) | (~val & bg);
 194                         fb_writel(val, dst++);
 195                 }
 196                 src1 += image->width / 8;
 197                 dst1 += info->fix.line_length;
 198         }
 199 
 200 }
 201 
 202 /* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
 203 static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 204 {
 205         u32 fg = expand_color(rect->color);
 206         u8 __iomem *dst1;
 207         u32 __iomem *dst;
 208         int x, y;
 209 
 210         dst1 = info->screen_base + (rect->dy * info->fix.line_length)
 211                  + ((rect->dx / 8) * 4);
 212 
 213         for (y = 0; y < rect->height; y++) {
 214                 dst = (u32 __iomem *) dst1;
 215                 for (x = 0; x < rect->width; x += 8) {
 216                         fb_writel(fg, dst++);
 217                 }
 218                 dst1 += info->fix.line_length;
 219         }
 220 
 221 }
 222 
 223 
 224 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
 225 static inline u32 expand_pixel(u32 c)
 226 {
 227         return (((c &  1) << 24) | ((c &  2) << 27) | ((c &  4) << 14) | ((c &   8) << 17) |
 228                 ((c & 16) <<  4) | ((c & 32) <<  7) | ((c & 64) >>  6) | ((c & 128) >>  3)) * 0xF;
 229 }
 230 
 231 /* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
 232 static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
 233 {
 234         u32 fg = image->fg_color * 0x11111111;
 235         u32 bg = image->bg_color * 0x11111111;
 236         const u8 *src1, *src;
 237         u8 __iomem *dst1;
 238         u32 __iomem *dst;
 239         u32 val;
 240         int x, y;
 241 
 242         src1 = image->data;
 243         dst1 = info->screen_base + (image->dy * info->fix.line_length)
 244                  + ((image->dx / 8) * 4);
 245 
 246         for (y = 0; y < image->height; y++) {
 247                 src = src1;
 248                 dst = (u32 __iomem *) dst1;
 249                 for (x = 0; x < image->width; x += 8) {
 250                         val = expand_pixel(*(src++));
 251                         val = (val & fg) | (~val & bg);
 252                         fb_writel(val, dst++);
 253                 }
 254                 src1 += image->width / 8;
 255                 dst1 += info->fix.line_length;
 256         }
 257 
 258 }
 259 
 260 static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
 261 {
 262         if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
 263             && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
 264                 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
 265                         arkfb_iplan_imageblit(info, image);
 266                 else
 267                         arkfb_cfb4_imageblit(info, image);
 268         } else
 269                 cfb_imageblit(info, image);
 270 }
 271 
 272 static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 273 {
 274         if ((info->var.bits_per_pixel == 4)
 275             && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
 276             && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
 277                 arkfb_iplan_fillrect(info, rect);
 278          else
 279                 cfb_fillrect(info, rect);
 280 }
 281 
 282 
 283 /* ------------------------------------------------------------------------- */
 284 
 285 
 286 enum
 287 {
 288         DAC_PSEUDO8_8,
 289         DAC_RGB1555_8,
 290         DAC_RGB0565_8,
 291         DAC_RGB0888_8,
 292         DAC_RGB8888_8,
 293         DAC_PSEUDO8_16,
 294         DAC_RGB1555_16,
 295         DAC_RGB0565_16,
 296         DAC_RGB0888_16,
 297         DAC_RGB8888_16,
 298         DAC_MAX
 299 };
 300 
 301 struct dac_ops {
 302         int (*dac_get_mode)(struct dac_info *info);
 303         int (*dac_set_mode)(struct dac_info *info, int mode);
 304         int (*dac_get_freq)(struct dac_info *info, int channel);
 305         int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
 306         void (*dac_release)(struct dac_info *info);
 307 };
 308 
 309 typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
 310 typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
 311 
 312 struct dac_info
 313 {
 314         struct dac_ops *dacops;
 315         dac_read_regs_t dac_read_regs;
 316         dac_write_regs_t dac_write_regs;
 317         void *data;
 318 };
 319 
 320 
 321 static inline u8 dac_read_reg(struct dac_info *info, u8 reg)
 322 {
 323         u8 code[2] = {reg, 0};
 324         info->dac_read_regs(info->data, code, 1);
 325         return code[1];
 326 }
 327 
 328 static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
 329 {
 330         info->dac_read_regs(info->data, code, count);
 331 }
 332 
 333 static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
 334 {
 335         u8 code[2] = {reg, val};
 336         info->dac_write_regs(info->data, code, 1);
 337 }
 338 
 339 static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
 340 {
 341         info->dac_write_regs(info->data, code, count);
 342 }
 343 
 344 static inline int dac_set_mode(struct dac_info *info, int mode)
 345 {
 346         return info->dacops->dac_set_mode(info, mode);
 347 }
 348 
 349 static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
 350 {
 351         return info->dacops->dac_set_freq(info, channel, freq);
 352 }
 353 
 354 static inline void dac_release(struct dac_info *info)
 355 {
 356         info->dacops->dac_release(info);
 357 }
 358 
 359 
 360 /* ------------------------------------------------------------------------- */
 361 
 362 
 363 /* ICS5342 DAC */
 364 
 365 struct ics5342_info
 366 {
 367         struct dac_info dac;
 368         u8 mode;
 369 };
 370 
 371 #define DAC_PAR(info) ((struct ics5342_info *) info)
 372 
 373 /* LSB is set to distinguish unused slots */
 374 static const u8 ics5342_mode_table[DAC_MAX] = {
 375         [DAC_PSEUDO8_8]  = 0x01, [DAC_RGB1555_8]  = 0x21, [DAC_RGB0565_8]  = 0x61,
 376         [DAC_RGB0888_8]  = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
 377         [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
 378 };
 379 
 380 static int ics5342_set_mode(struct dac_info *info, int mode)
 381 {
 382         u8 code;
 383 
 384         if (mode >= DAC_MAX)
 385                 return -EINVAL;
 386 
 387         code = ics5342_mode_table[mode];
 388 
 389         if (! code)
 390                 return -EINVAL;
 391 
 392         dac_write_reg(info, 6, code & 0xF0);
 393         DAC_PAR(info)->mode = mode;
 394 
 395         return 0;
 396 }
 397 
 398 static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
 399         60000, 250000, 14318};
 400 
 401 /* pd4 - allow only posdivider 4 (r=2) */
 402 static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
 403         60000, 335000, 14318};
 404 
 405 /* 270 MHz should be upper bound for VCO clock according to specs,
 406    but that is too restrictive in pd4 case */
 407 
 408 static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
 409 {
 410         u16 m, n, r;
 411 
 412         /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
 413         int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
 414                                   ? &ics5342_pll_pd4 : &ics5342_pll,
 415                                   freq, &m, &n, &r, 0);
 416 
 417         if (rv < 0) {
 418                 return -EINVAL;
 419         } else {
 420                 u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
 421                 dac_write_regs(info, code, 3);
 422                 return 0;
 423         }
 424 }
 425 
 426 static void ics5342_release(struct dac_info *info)
 427 {
 428         ics5342_set_mode(info, DAC_PSEUDO8_8);
 429         kfree(info);
 430 }
 431 
 432 static struct dac_ops ics5342_ops = {
 433         .dac_set_mode   = ics5342_set_mode,
 434         .dac_set_freq   = ics5342_set_freq,
 435         .dac_release    = ics5342_release
 436 };
 437 
 438 
 439 static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
 440 {
 441         struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
 442 
 443         if (! info)
 444                 return NULL;
 445 
 446         info->dacops = &ics5342_ops;
 447         info->dac_read_regs = drr;
 448         info->dac_write_regs = dwr;
 449         info->data = data;
 450         DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
 451         return info;
 452 }
 453 
 454 
 455 /* ------------------------------------------------------------------------- */
 456 
 457 
 458 static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
 459 
 460 static void ark_dac_read_regs(void *data, u8 *code, int count)
 461 {
 462         struct fb_info *info = data;
 463         struct arkfb_info *par;
 464         u8 regval;
 465 
 466         par = info->par;
 467         regval = vga_rseq(par->state.vgabase, 0x1C);
 468         while (count != 0)
 469         {
 470                 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
 471                 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
 472                 count--;
 473                 code += 2;
 474         }
 475 
 476         vga_wseq(par->state.vgabase, 0x1C, regval);
 477 }
 478 
 479 static void ark_dac_write_regs(void *data, u8 *code, int count)
 480 {
 481         struct fb_info *info = data;
 482         struct arkfb_info *par;
 483         u8 regval;
 484 
 485         par = info->par;
 486         regval = vga_rseq(par->state.vgabase, 0x1C);
 487         while (count != 0)
 488         {
 489                 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
 490                 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
 491                 count--;
 492                 code += 2;
 493         }
 494 
 495         vga_wseq(par->state.vgabase, 0x1C, regval);
 496 }
 497 
 498 
 499 static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
 500 {
 501         struct arkfb_info *par = info->par;
 502         u8 regval;
 503 
 504         int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
 505         if (rv < 0) {
 506                 fb_err(info, "cannot set requested pixclock, keeping old value\n");
 507                 return;
 508         }
 509 
 510         /* Set VGA misc register  */
 511         regval = vga_r(par->state.vgabase, VGA_MIS_R);
 512         vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
 513 }
 514 
 515 
 516 /* Open framebuffer */
 517 
 518 static int arkfb_open(struct fb_info *info, int user)
 519 {
 520         struct arkfb_info *par = info->par;
 521 
 522         mutex_lock(&(par->open_lock));
 523         if (par->ref_count == 0) {
 524                 void __iomem *vgabase = par->state.vgabase;
 525 
 526                 memset(&(par->state), 0, sizeof(struct vgastate));
 527                 par->state.vgabase = vgabase;
 528                 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
 529                 par->state.num_crtc = 0x60;
 530                 par->state.num_seq = 0x30;
 531                 save_vga(&(par->state));
 532         }
 533 
 534         par->ref_count++;
 535         mutex_unlock(&(par->open_lock));
 536 
 537         return 0;
 538 }
 539 
 540 /* Close framebuffer */
 541 
 542 static int arkfb_release(struct fb_info *info, int user)
 543 {
 544         struct arkfb_info *par = info->par;
 545 
 546         mutex_lock(&(par->open_lock));
 547         if (par->ref_count == 0) {
 548                 mutex_unlock(&(par->open_lock));
 549                 return -EINVAL;
 550         }
 551 
 552         if (par->ref_count == 1) {
 553                 restore_vga(&(par->state));
 554                 dac_set_mode(par->dac, DAC_PSEUDO8_8);
 555         }
 556 
 557         par->ref_count--;
 558         mutex_unlock(&(par->open_lock));
 559 
 560         return 0;
 561 }
 562 
 563 /* Validate passed in var */
 564 
 565 static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 566 {
 567         int rv, mem, step;
 568 
 569         /* Find appropriate format */
 570         rv = svga_match_format (arkfb_formats, var, NULL);
 571         if (rv < 0)
 572         {
 573                 fb_err(info, "unsupported mode requested\n");
 574                 return rv;
 575         }
 576 
 577         /* Do not allow to have real resoulution larger than virtual */
 578         if (var->xres > var->xres_virtual)
 579                 var->xres_virtual = var->xres;
 580 
 581         if (var->yres > var->yres_virtual)
 582                 var->yres_virtual = var->yres;
 583 
 584         /* Round up xres_virtual to have proper alignment of lines */
 585         step = arkfb_formats[rv].xresstep - 1;
 586         var->xres_virtual = (var->xres_virtual+step) & ~step;
 587 
 588 
 589         /* Check whether have enough memory */
 590         mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
 591         if (mem > info->screen_size)
 592         {
 593                 fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n",
 594                        mem >> 10, (unsigned int) (info->screen_size >> 10));
 595                 return -EINVAL;
 596         }
 597 
 598         rv = svga_check_timings (&ark_timing_regs, var, info->node);
 599         if (rv < 0)
 600         {
 601                 fb_err(info, "invalid timings requested\n");
 602                 return rv;
 603         }
 604 
 605         /* Interlaced mode is broken */
 606         if (var->vmode & FB_VMODE_INTERLACED)
 607                 return -EINVAL;
 608 
 609         return 0;
 610 }
 611 
 612 /* Set video mode from par */
 613 
 614 static int arkfb_set_par(struct fb_info *info)
 615 {
 616         struct arkfb_info *par = info->par;
 617         u32 value, mode, hmul, hdiv, offset_value, screen_size;
 618         u32 bpp = info->var.bits_per_pixel;
 619         u8 regval;
 620 
 621         if (bpp != 0) {
 622                 info->fix.ypanstep = 1;
 623                 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
 624 
 625                 info->flags &= ~FBINFO_MISC_TILEBLITTING;
 626                 info->tileops = NULL;
 627 
 628                 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
 629                 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
 630                 info->pixmap.blit_y = ~(u32)0;
 631 
 632                 offset_value = (info->var.xres_virtual * bpp) / 64;
 633                 screen_size = info->var.yres_virtual * info->fix.line_length;
 634         } else {
 635                 info->fix.ypanstep = 16;
 636                 info->fix.line_length = 0;
 637 
 638                 info->flags |= FBINFO_MISC_TILEBLITTING;
 639                 info->tileops = &arkfb_tile_ops;
 640 
 641                 /* supports 8x16 tiles only */
 642                 info->pixmap.blit_x = 1 << (8 - 1);
 643                 info->pixmap.blit_y = 1 << (16 - 1);
 644 
 645                 offset_value = info->var.xres_virtual / 16;
 646                 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
 647         }
 648 
 649         info->var.xoffset = 0;
 650         info->var.yoffset = 0;
 651         info->var.activate = FB_ACTIVATE_NOW;
 652 
 653         /* Unlock registers */
 654         svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
 655 
 656         /* Blank screen and turn off sync */
 657         svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
 658         svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
 659 
 660         /* Set default values */
 661         svga_set_default_gfx_regs(par->state.vgabase);
 662         svga_set_default_atc_regs(par->state.vgabase);
 663         svga_set_default_seq_regs(par->state.vgabase);
 664         svga_set_default_crt_regs(par->state.vgabase);
 665         svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
 666         svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
 667 
 668         /* ARK specific initialization */
 669         svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
 670         svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
 671 
 672         vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
 673         vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
 674         vga_wseq(par->state.vgabase, 0x15, 0);
 675         vga_wseq(par->state.vgabase, 0x16, 0);
 676 
 677         /* Set the FIFO threshold register */
 678         /* It is fascinating way to store 5-bit value in 8-bit register */
 679         regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
 680         vga_wseq(par->state.vgabase, 0x18, regval);
 681 
 682         /* Set the offset register */
 683         fb_dbg(info, "offset register       : %d\n", offset_value);
 684         svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
 685 
 686         /* fix for hi-res textmode */
 687         svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
 688 
 689         if (info->var.vmode & FB_VMODE_DOUBLE)
 690                 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
 691         else
 692                 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
 693 
 694         if (info->var.vmode & FB_VMODE_INTERLACED)
 695                 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
 696         else
 697                 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
 698 
 699         hmul = 1;
 700         hdiv = 1;
 701         mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
 702 
 703         /* Set mode-specific register values */
 704         switch (mode) {
 705         case 0:
 706                 fb_dbg(info, "text mode\n");
 707                 svga_set_textmode_vga_regs(par->state.vgabase);
 708 
 709                 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
 710                 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
 711                 dac_set_mode(par->dac, DAC_PSEUDO8_8);
 712 
 713                 break;
 714         case 1:
 715                 fb_dbg(info, "4 bit pseudocolor\n");
 716                 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
 717 
 718                 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
 719                 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
 720                 dac_set_mode(par->dac, DAC_PSEUDO8_8);
 721                 break;
 722         case 2:
 723                 fb_dbg(info, "4 bit pseudocolor, planar\n");
 724 
 725                 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
 726                 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
 727                 dac_set_mode(par->dac, DAC_PSEUDO8_8);
 728                 break;
 729         case 3:
 730                 fb_dbg(info, "8 bit pseudocolor\n");
 731 
 732                 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
 733 
 734                 if (info->var.pixclock > 20000) {
 735                         fb_dbg(info, "not using multiplex\n");
 736                         svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
 737                         dac_set_mode(par->dac, DAC_PSEUDO8_8);
 738                 } else {
 739                         fb_dbg(info, "using multiplex\n");
 740                         svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
 741                         dac_set_mode(par->dac, DAC_PSEUDO8_16);
 742                         hdiv = 2;
 743                 }
 744                 break;
 745         case 4:
 746                 fb_dbg(info, "5/5/5 truecolor\n");
 747 
 748                 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
 749                 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
 750                 dac_set_mode(par->dac, DAC_RGB1555_16);
 751                 break;
 752         case 5:
 753                 fb_dbg(info, "5/6/5 truecolor\n");
 754 
 755                 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
 756                 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
 757                 dac_set_mode(par->dac, DAC_RGB0565_16);
 758                 break;
 759         case 6:
 760                 fb_dbg(info, "8/8/8 truecolor\n");
 761 
 762                 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
 763                 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
 764                 dac_set_mode(par->dac, DAC_RGB0888_16);
 765                 hmul = 3;
 766                 hdiv = 2;
 767                 break;
 768         case 7:
 769                 fb_dbg(info, "8/8/8/8 truecolor\n");
 770 
 771                 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
 772                 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
 773                 dac_set_mode(par->dac, DAC_RGB8888_16);
 774                 hmul = 2;
 775                 break;
 776         default:
 777                 fb_err(info, "unsupported mode - bug\n");
 778                 return -EINVAL;
 779         }
 780 
 781         ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul);
 782         svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
 783                          (info->var.vmode & FB_VMODE_DOUBLE)     ? 2 : 1,
 784                          (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
 785                           hmul, info->node);
 786 
 787         /* Set interlaced mode start/end register */
 788         value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
 789         value = ((value * hmul / hdiv) / 8) - 5;
 790         vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
 791 
 792         memset_io(info->screen_base, 0x00, screen_size);
 793         /* Device and screen back on */
 794         svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
 795         svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
 796 
 797         return 0;
 798 }
 799 
 800 /* Set a colour register */
 801 
 802 static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 803                                 u_int transp, struct fb_info *fb)
 804 {
 805         switch (fb->var.bits_per_pixel) {
 806         case 0:
 807         case 4:
 808                 if (regno >= 16)
 809                         return -EINVAL;
 810 
 811                 if ((fb->var.bits_per_pixel == 4) &&
 812                     (fb->var.nonstd == 0)) {
 813                         outb(0xF0, VGA_PEL_MSK);
 814                         outb(regno*16, VGA_PEL_IW);
 815                 } else {
 816                         outb(0x0F, VGA_PEL_MSK);
 817                         outb(regno, VGA_PEL_IW);
 818                 }
 819                 outb(red >> 10, VGA_PEL_D);
 820                 outb(green >> 10, VGA_PEL_D);
 821                 outb(blue >> 10, VGA_PEL_D);
 822                 break;
 823         case 8:
 824                 if (regno >= 256)
 825                         return -EINVAL;
 826 
 827                 outb(0xFF, VGA_PEL_MSK);
 828                 outb(regno, VGA_PEL_IW);
 829                 outb(red >> 10, VGA_PEL_D);
 830                 outb(green >> 10, VGA_PEL_D);
 831                 outb(blue >> 10, VGA_PEL_D);
 832                 break;
 833         case 16:
 834                 if (regno >= 16)
 835                         return 0;
 836 
 837                 if (fb->var.green.length == 5)
 838                         ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
 839                                 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
 840                 else if (fb->var.green.length == 6)
 841                         ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
 842                                 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
 843                 else
 844                         return -EINVAL;
 845                 break;
 846         case 24:
 847         case 32:
 848                 if (regno >= 16)
 849                         return 0;
 850 
 851                 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
 852                         (green & 0xFF00) | ((blue & 0xFF00) >> 8);
 853                 break;
 854         default:
 855                 return -EINVAL;
 856         }
 857 
 858         return 0;
 859 }
 860 
 861 /* Set the display blanking state */
 862 
 863 static int arkfb_blank(int blank_mode, struct fb_info *info)
 864 {
 865         struct arkfb_info *par = info->par;
 866 
 867         switch (blank_mode) {
 868         case FB_BLANK_UNBLANK:
 869                 fb_dbg(info, "unblank\n");
 870                 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
 871                 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
 872                 break;
 873         case FB_BLANK_NORMAL:
 874                 fb_dbg(info, "blank\n");
 875                 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
 876                 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
 877                 break;
 878         case FB_BLANK_POWERDOWN:
 879         case FB_BLANK_HSYNC_SUSPEND:
 880         case FB_BLANK_VSYNC_SUSPEND:
 881                 fb_dbg(info, "sync down\n");
 882                 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
 883                 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
 884                 break;
 885         }
 886         return 0;
 887 }
 888 
 889 
 890 /* Pan the display */
 891 
 892 static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 893 {
 894         struct arkfb_info *par = info->par;
 895         unsigned int offset;
 896 
 897         /* Calculate the offset */
 898         if (info->var.bits_per_pixel == 0) {
 899                 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
 900                        + (var->xoffset / 2);
 901                 offset = offset >> 2;
 902         } else {
 903                 offset = (var->yoffset * info->fix.line_length) +
 904                          (var->xoffset * info->var.bits_per_pixel / 8);
 905                 offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3);
 906         }
 907 
 908         /* Set the offset */
 909         svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
 910 
 911         return 0;
 912 }
 913 
 914 
 915 /* ------------------------------------------------------------------------- */
 916 
 917 
 918 /* Frame buffer operations */
 919 
 920 static struct fb_ops arkfb_ops = {
 921         .owner          = THIS_MODULE,
 922         .fb_open        = arkfb_open,
 923         .fb_release     = arkfb_release,
 924         .fb_check_var   = arkfb_check_var,
 925         .fb_set_par     = arkfb_set_par,
 926         .fb_setcolreg   = arkfb_setcolreg,
 927         .fb_blank       = arkfb_blank,
 928         .fb_pan_display = arkfb_pan_display,
 929         .fb_fillrect    = arkfb_fillrect,
 930         .fb_copyarea    = cfb_copyarea,
 931         .fb_imageblit   = arkfb_imageblit,
 932         .fb_get_caps    = svga_get_caps,
 933 };
 934 
 935 
 936 /* ------------------------------------------------------------------------- */
 937 
 938 
 939 /* PCI probe */
 940 static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 941 {
 942         struct pci_bus_region bus_reg;
 943         struct resource vga_res;
 944         struct fb_info *info;
 945         struct arkfb_info *par;
 946         int rc;
 947         u8 regval;
 948 
 949         /* Ignore secondary VGA device because there is no VGA arbitration */
 950         if (! svga_primary_device(dev)) {
 951                 dev_info(&(dev->dev), "ignoring secondary device\n");
 952                 return -ENODEV;
 953         }
 954 
 955         /* Allocate and fill driver data structure */
 956         info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
 957         if (!info)
 958                 return -ENOMEM;
 959 
 960         par = info->par;
 961         mutex_init(&par->open_lock);
 962 
 963         info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
 964         info->fbops = &arkfb_ops;
 965 
 966         /* Prepare PCI device */
 967         rc = pci_enable_device(dev);
 968         if (rc < 0) {
 969                 dev_err(info->device, "cannot enable PCI device\n");
 970                 goto err_enable_device;
 971         }
 972 
 973         rc = pci_request_regions(dev, "arkfb");
 974         if (rc < 0) {
 975                 dev_err(info->device, "cannot reserve framebuffer region\n");
 976                 goto err_request_regions;
 977         }
 978 
 979         par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
 980         if (! par->dac) {
 981                 rc = -ENOMEM;
 982                 dev_err(info->device, "RAMDAC initialization failed\n");
 983                 goto err_dac;
 984         }
 985 
 986         info->fix.smem_start = pci_resource_start(dev, 0);
 987         info->fix.smem_len = pci_resource_len(dev, 0);
 988 
 989         /* Map physical IO memory address into kernel space */
 990         info->screen_base = pci_iomap_wc(dev, 0, 0);
 991         if (! info->screen_base) {
 992                 rc = -ENOMEM;
 993                 dev_err(info->device, "iomap for framebuffer failed\n");
 994                 goto err_iomap;
 995         }
 996 
 997         bus_reg.start = 0;
 998         bus_reg.end = 64 * 1024;
 999 
1000         vga_res.flags = IORESOURCE_IO;
1001 
1002         pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1003 
1004         par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1005 
1006         /* FIXME get memsize */
1007         regval = vga_rseq(par->state.vgabase, 0x10);
1008         info->screen_size = (1 << (regval >> 6)) << 20;
1009         info->fix.smem_len = info->screen_size;
1010 
1011         strcpy(info->fix.id, "ARK 2000PV");
1012         info->fix.mmio_start = 0;
1013         info->fix.mmio_len = 0;
1014         info->fix.type = FB_TYPE_PACKED_PIXELS;
1015         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1016         info->fix.ypanstep = 0;
1017         info->fix.accel = FB_ACCEL_NONE;
1018         info->pseudo_palette = (void*) (par->pseudo_palette);
1019 
1020         /* Prepare startup mode */
1021         rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
1022         if (! ((rc == 1) || (rc == 2))) {
1023                 rc = -EINVAL;
1024                 dev_err(info->device, "mode %s not found\n", mode_option);
1025                 goto err_find_mode;
1026         }
1027 
1028         rc = fb_alloc_cmap(&info->cmap, 256, 0);
1029         if (rc < 0) {
1030                 dev_err(info->device, "cannot allocate colormap\n");
1031                 goto err_alloc_cmap;
1032         }
1033 
1034         rc = register_framebuffer(info);
1035         if (rc < 0) {
1036                 dev_err(info->device, "cannot register framebuffer\n");
1037                 goto err_reg_fb;
1038         }
1039 
1040         fb_info(info, "%s on %s, %d MB RAM\n",
1041                 info->fix.id, pci_name(dev), info->fix.smem_len >> 20);
1042 
1043         /* Record a reference to the driver data */
1044         pci_set_drvdata(dev, info);
1045         par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1046                                           info->fix.smem_len);
1047         return 0;
1048 
1049         /* Error handling */
1050 err_reg_fb:
1051         fb_dealloc_cmap(&info->cmap);
1052 err_alloc_cmap:
1053 err_find_mode:
1054         pci_iounmap(dev, info->screen_base);
1055 err_iomap:
1056         dac_release(par->dac);
1057 err_dac:
1058         pci_release_regions(dev);
1059 err_request_regions:
1060 /*      pci_disable_device(dev); */
1061 err_enable_device:
1062         framebuffer_release(info);
1063         return rc;
1064 }
1065 
1066 /* PCI remove */
1067 
1068 static void ark_pci_remove(struct pci_dev *dev)
1069 {
1070         struct fb_info *info = pci_get_drvdata(dev);
1071 
1072         if (info) {
1073                 struct arkfb_info *par = info->par;
1074                 arch_phys_wc_del(par->wc_cookie);
1075                 dac_release(par->dac);
1076                 unregister_framebuffer(info);
1077                 fb_dealloc_cmap(&info->cmap);
1078 
1079                 pci_iounmap(dev, info->screen_base);
1080                 pci_release_regions(dev);
1081 /*              pci_disable_device(dev); */
1082 
1083                 framebuffer_release(info);
1084         }
1085 }
1086 
1087 
1088 #ifdef CONFIG_PM
1089 /* PCI suspend */
1090 
1091 static int ark_pci_suspend (struct pci_dev* dev, pm_message_t state)
1092 {
1093         struct fb_info *info = pci_get_drvdata(dev);
1094         struct arkfb_info *par = info->par;
1095 
1096         dev_info(info->device, "suspend\n");
1097 
1098         console_lock();
1099         mutex_lock(&(par->open_lock));
1100 
1101         if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
1102                 mutex_unlock(&(par->open_lock));
1103                 console_unlock();
1104                 return 0;
1105         }
1106 
1107         fb_set_suspend(info, 1);
1108 
1109         pci_save_state(dev);
1110         pci_disable_device(dev);
1111         pci_set_power_state(dev, pci_choose_state(dev, state));
1112 
1113         mutex_unlock(&(par->open_lock));
1114         console_unlock();
1115 
1116         return 0;
1117 }
1118 
1119 
1120 /* PCI resume */
1121 
1122 static int ark_pci_resume (struct pci_dev* dev)
1123 {
1124         struct fb_info *info = pci_get_drvdata(dev);
1125         struct arkfb_info *par = info->par;
1126 
1127         dev_info(info->device, "resume\n");
1128 
1129         console_lock();
1130         mutex_lock(&(par->open_lock));
1131 
1132         if (par->ref_count == 0)
1133                 goto fail;
1134 
1135         pci_set_power_state(dev, PCI_D0);
1136         pci_restore_state(dev);
1137 
1138         if (pci_enable_device(dev))
1139                 goto fail;
1140 
1141         pci_set_master(dev);
1142 
1143         arkfb_set_par(info);
1144         fb_set_suspend(info, 0);
1145 
1146 fail:
1147         mutex_unlock(&(par->open_lock));
1148         console_unlock();
1149         return 0;
1150 }
1151 #else
1152 #define ark_pci_suspend NULL
1153 #define ark_pci_resume NULL
1154 #endif /* CONFIG_PM */
1155 
1156 /* List of boards that we are trying to support */
1157 
1158 static const struct pci_device_id ark_devices[] = {
1159         {PCI_DEVICE(0xEDD8, 0xA099)},
1160         {0, 0, 0, 0, 0, 0, 0}
1161 };
1162 
1163 
1164 MODULE_DEVICE_TABLE(pci, ark_devices);
1165 
1166 static struct pci_driver arkfb_pci_driver = {
1167         .name           = "arkfb",
1168         .id_table       = ark_devices,
1169         .probe          = ark_pci_probe,
1170         .remove         = ark_pci_remove,
1171         .suspend        = ark_pci_suspend,
1172         .resume         = ark_pci_resume,
1173 };
1174 
1175 /* Cleanup */
1176 
1177 static void __exit arkfb_cleanup(void)
1178 {
1179         pr_debug("arkfb: cleaning up\n");
1180         pci_unregister_driver(&arkfb_pci_driver);
1181 }
1182 
1183 /* Driver Initialisation */
1184 
1185 static int __init arkfb_init(void)
1186 {
1187 
1188 #ifndef MODULE
1189         char *option = NULL;
1190 
1191         if (fb_get_options("arkfb", &option))
1192                 return -ENODEV;
1193 
1194         if (option && *option)
1195                 mode_option = option;
1196 #endif
1197 
1198         pr_debug("arkfb: initializing\n");
1199         return pci_register_driver(&arkfb_pci_driver);
1200 }
1201 
1202 module_init(arkfb_init);
1203 module_exit(arkfb_cleanup);

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