This source file includes following definitions.
- flush_tlb_kernel_range
1
2 #ifndef _SPARC_TLBFLUSH_H
3 #define _SPARC_TLBFLUSH_H
4
5 #include <asm/cachetlb_32.h>
6
7 #define flush_tlb_all() \
8 sparc32_cachetlb_ops->tlb_all()
9 #define flush_tlb_mm(mm) \
10 sparc32_cachetlb_ops->tlb_mm(mm)
11 #define flush_tlb_range(vma, start, end) \
12 sparc32_cachetlb_ops->tlb_range(vma, start, end)
13 #define flush_tlb_page(vma, addr) \
14 sparc32_cachetlb_ops->tlb_page(vma, addr)
15
16
17
18
19 static inline void flush_tlb_kernel_range(unsigned long start,
20 unsigned long end)
21 {
22 flush_tlb_all();
23 }
24
25 #endif