drivers/video/fbdev/s3c-fb.c

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This source file includes following definitions.
s3c_fb_validate_win_bpp
s3c_fb_check_var
s3c_fb_calc_pixclk
s3c_fb_align_word
vidosd_set_size
vidosd_set_alpha
shadow_protect_win
s3c_fb_enable
s3c_fb_set_par
s3c_fb_update_palette
chan_to_field
s3c_fb_setcolreg
s3c_fb_blank
s3c_fb_pan_display
s3c_fb_enable_irq
s3c_fb_disable_irq
s3c_fb_irq
s3c_fb_wait_for_vsync
s3c_fb_ioctl
s3c_fb_missing_pixclock
s3c_fb_alloc_memory
s3c_fb_free_memory
s3c_fb_release_win
s3c_fb_probe_win
s3c_fb_set_rgb_timing
s3c_fb_clear_win
s3c_fb_probe
s3c_fb_remove
s3c_fb_suspend
s3c_fb_resume
s3c_fb_runtime_suspend
s3c_fb_runtime_resume
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* linux/drivers/video/s3c-fb.c
   3  *
   4  * Copyright 2008 Openmoko Inc.
   5  * Copyright 2008-2010 Simtec Electronics
   6  *      Ben Dooks <ben@simtec.co.uk>
   7  *      http://armlinux.simtec.co.uk/
   8  *
   9  * Samsung SoC Framebuffer driver
  10 */
  11 
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/slab.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/fb.h>
  20 #include <linux/io.h>
  21 #include <linux/uaccess.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/platform_data/video_s3c.h>
  25 
  26 #include <video/samsung_fimd.h>
  27 
  28 /* This driver will export a number of framebuffer interfaces depending
  29  * on the configuration passed in via the platform data. Each fb instance
  30  * maps to a hardware window. Currently there is no support for runtime
  31  * setting of the alpha-blending functions that each window has, so only
  32  * window 0 is actually useful.
  33  *
  34  * Window 0 is treated specially, it is used for the basis of the LCD
  35  * output timings and as the control for the output power-down state.
  36 */
  37 
  38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
  39  * has been replaced by using the platform device name to pick the correct
  40  * configuration data for the system.
  41 */
  42 
  43 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
  44 #undef writel
  45 #define writel(v, r) do { \
  46         pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
  47         __raw_writel(v, r); \
  48 } while (0)
  49 #endif /* FB_S3C_DEBUG_REGWRITE */
  50 
  51 /* irq_flags bits */
  52 #define S3C_FB_VSYNC_IRQ_EN     0
  53 
  54 #define VSYNC_TIMEOUT_MSEC 50
  55 
  56 struct s3c_fb;
  57 
  58 #define VALID_BPP(x) (1 << ((x) - 1))
  59 
  60 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
  61 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
  62 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
  63 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
  64 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
  65 
  66 /**
  67  * struct s3c_fb_variant - fb variant information
  68  * @is_2443: Set if S3C2443/S3C2416 style hardware.
  69  * @nr_windows: The number of windows.
  70  * @vidtcon: The base for the VIDTCONx registers
  71  * @wincon: The base for the WINxCON registers.
  72  * @winmap: The base for the WINxMAP registers.
  73  * @keycon: The abse for the WxKEYCON registers.
  74  * @buf_start: Offset of buffer start registers.
  75  * @buf_size: Offset of buffer size registers.
  76  * @buf_end: Offset of buffer end registers.
  77  * @osd: The base for the OSD registers.
  78  * @palette: Address of palette memory, or 0 if none.
  79  * @has_prtcon: Set if has PRTCON register.
  80  * @has_shadowcon: Set if has SHADOWCON register.
  81  * @has_blendcon: Set if has BLENDCON register.
  82  * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
  83  * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.
  84  */
  85 struct s3c_fb_variant {
  86         unsigned int    is_2443:1;
  87         unsigned short  nr_windows;
  88         unsigned int    vidtcon;
  89         unsigned short  wincon;
  90         unsigned short  winmap;
  91         unsigned short  keycon;
  92         unsigned short  buf_start;
  93         unsigned short  buf_end;
  94         unsigned short  buf_size;
  95         unsigned short  osd;
  96         unsigned short  osd_stride;
  97         unsigned short  palette[S3C_FB_MAX_WIN];
  98 
  99         unsigned int    has_prtcon:1;
 100         unsigned int    has_shadowcon:1;
 101         unsigned int    has_blendcon:1;
 102         unsigned int    has_clksel:1;
 103         unsigned int    has_fixvclk:1;
 104 };
 105 
 106 /**
 107  * struct s3c_fb_win_variant
 108  * @has_osd_c: Set if has OSD C register.
 109  * @has_osd_d: Set if has OSD D register.
 110  * @has_osd_alpha: Set if can change alpha transparency for a window.
 111  * @palette_sz: Size of palette in entries.
 112  * @palette_16bpp: Set if palette is 16bits wide.
 113  * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
 114  *                register is located at the given offset from OSD_BASE.
 115  * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
 116  *
 117  * valid_bpp bit x is set if (x+1)BPP is supported.
 118  */
 119 struct s3c_fb_win_variant {
 120         unsigned int    has_osd_c:1;
 121         unsigned int    has_osd_d:1;
 122         unsigned int    has_osd_alpha:1;
 123         unsigned int    palette_16bpp:1;
 124         unsigned short  osd_size_off;
 125         unsigned short  palette_sz;
 126         u32             valid_bpp;
 127 };
 128 
 129 /**
 130  * struct s3c_fb_driverdata - per-device type driver data for init time.
 131  * @variant: The variant information for this driver.
 132  * @win: The window information for each window.
 133  */
 134 struct s3c_fb_driverdata {
 135         struct s3c_fb_variant   variant;
 136         struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
 137 };
 138 
 139 /**
 140  * struct s3c_fb_palette - palette information
 141  * @r: Red bitfield.
 142  * @g: Green bitfield.
 143  * @b: Blue bitfield.
 144  * @a: Alpha bitfield.
 145  */
 146 struct s3c_fb_palette {
 147         struct fb_bitfield      r;
 148         struct fb_bitfield      g;
 149         struct fb_bitfield      b;
 150         struct fb_bitfield      a;
 151 };
 152 
 153 /**
 154  * struct s3c_fb_win - per window private data for each framebuffer.
 155  * @windata: The platform data supplied for the window configuration.
 156  * @parent: The hardware that this window is part of.
 157  * @fbinfo: Pointer pack to the framebuffer info for this window.
 158  * @varint: The variant information for this window.
 159  * @palette_buffer: Buffer/cache to hold palette entries.
 160  * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
 161  * @index: The window number of this window.
 162  * @palette: The bitfields for changing r/g/b into a hardware palette entry.
 163  */
 164 struct s3c_fb_win {
 165         struct s3c_fb_pd_win    *windata;
 166         struct s3c_fb           *parent;
 167         struct fb_info          *fbinfo;
 168         struct s3c_fb_palette    palette;
 169         struct s3c_fb_win_variant variant;
 170 
 171         u32                     *palette_buffer;
 172         u32                      pseudo_palette[16];
 173         unsigned int             index;
 174 };
 175 
 176 /**
 177  * struct s3c_fb_vsync - vsync information
 178  * @wait:       a queue for processes waiting for vsync
 179  * @count:      vsync interrupt count
 180  */
 181 struct s3c_fb_vsync {
 182         wait_queue_head_t       wait;
 183         unsigned int            count;
 184 };
 185 
 186 /**
 187  * struct s3c_fb - overall hardware state of the hardware
 188  * @slock: The spinlock protection for this data structure.
 189  * @dev: The device that we bound to, for printing, etc.
 190  * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
 191  * @lcd_clk: The clk (sclk) feeding pixclk.
 192  * @regs: The mapped hardware registers.
 193  * @variant: Variant information for this hardware.
 194  * @enabled: A bitmask of enabled hardware windows.
 195  * @output_on: Flag if the physical output is enabled.
 196  * @pdata: The platform configuration data passed with the device.
 197  * @windows: The hardware windows that have been claimed.
 198  * @irq_no: IRQ line number
 199  * @irq_flags: irq flags
 200  * @vsync_info: VSYNC-related information (count, queues...)
 201  */
 202 struct s3c_fb {
 203         spinlock_t              slock;
 204         struct device           *dev;
 205         struct clk              *bus_clk;
 206         struct clk              *lcd_clk;
 207         void __iomem            *regs;
 208         struct s3c_fb_variant    variant;
 209 
 210         unsigned char            enabled;
 211         bool                     output_on;
 212 
 213         struct s3c_fb_platdata  *pdata;
 214         struct s3c_fb_win       *windows[S3C_FB_MAX_WIN];
 215 
 216         int                      irq_no;
 217         unsigned long            irq_flags;
 218         struct s3c_fb_vsync      vsync_info;
 219 };
 220 
 221 /**
 222  * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
 223  * @win: The device window.
 224  * @bpp: The bit depth.
 225  */
 226 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
 227 {
 228         return win->variant.valid_bpp & VALID_BPP(bpp);
 229 }
 230 
 231 /**
 232  * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
 233  * @var: The screen information to verify.
 234  * @info: The framebuffer device.
 235  *
 236  * Framebuffer layer call to verify the given information and allow us to
 237  * update various information depending on the hardware capabilities.
 238  */
 239 static int s3c_fb_check_var(struct fb_var_screeninfo *var,
 240                             struct fb_info *info)
 241 {
 242         struct s3c_fb_win *win = info->par;
 243         struct s3c_fb *sfb = win->parent;
 244 
 245         dev_dbg(sfb->dev, "checking parameters\n");
 246 
 247         var->xres_virtual = max(var->xres_virtual, var->xres);
 248         var->yres_virtual = max(var->yres_virtual, var->yres);
 249 
 250         if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
 251                 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
 252                         win->index, var->bits_per_pixel);
 253                 return -EINVAL;
 254         }
 255 
 256         /* always ensure these are zero, for drop through cases below */
 257         var->transp.offset = 0;
 258         var->transp.length = 0;
 259 
 260         switch (var->bits_per_pixel) {
 261         case 1:
 262         case 2:
 263         case 4:
 264         case 8:
 265                 if (sfb->variant.palette[win->index] != 0) {
 266                         /* non palletised, A:1,R:2,G:3,B:2 mode */
 267                         var->red.offset         = 5;
 268                         var->green.offset       = 2;
 269                         var->blue.offset        = 0;
 270                         var->red.length         = 2;
 271                         var->green.length       = 3;
 272                         var->blue.length        = 2;
 273                         var->transp.offset      = 7;
 274                         var->transp.length      = 1;
 275                 } else {
 276                         var->red.offset = 0;
 277                         var->red.length = var->bits_per_pixel;
 278                         var->green      = var->red;
 279                         var->blue       = var->red;
 280                 }
 281                 break;
 282 
 283         case 19:
 284                 /* 666 with one bit alpha/transparency */
 285                 var->transp.offset      = 18;
 286                 var->transp.length      = 1;
 287                 /* fall through */
 288         case 18:
 289                 var->bits_per_pixel     = 32;
 290 
 291                 /* 666 format */
 292                 var->red.offset         = 12;
 293                 var->green.offset       = 6;
 294                 var->blue.offset        = 0;
 295                 var->red.length         = 6;
 296                 var->green.length       = 6;
 297                 var->blue.length        = 6;
 298                 break;
 299 
 300         case 16:
 301                 /* 16 bpp, 565 format */
 302                 var->red.offset         = 11;
 303                 var->green.offset       = 5;
 304                 var->blue.offset        = 0;
 305                 var->red.length         = 5;
 306                 var->green.length       = 6;
 307                 var->blue.length        = 5;
 308                 break;
 309 
 310         case 32:
 311         case 28:
 312         case 25:
 313                 var->transp.length      = var->bits_per_pixel - 24;
 314                 var->transp.offset      = 24;
 315                 /* fall through */
 316         case 24:
 317                 /* our 24bpp is unpacked, so 32bpp */
 318                 var->bits_per_pixel     = 32;
 319                 var->red.offset         = 16;
 320                 var->red.length         = 8;
 321                 var->green.offset       = 8;
 322                 var->green.length       = 8;
 323                 var->blue.offset        = 0;
 324                 var->blue.length        = 8;
 325                 break;
 326 
 327         default:
 328                 dev_err(sfb->dev, "invalid bpp\n");
 329                 return -EINVAL;
 330         }
 331 
 332         dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
 333         return 0;
 334 }
 335 
 336 /**
 337  * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
 338  * @sfb: The hardware state.
 339  * @pixclock: The pixel clock wanted, in picoseconds.
 340  *
 341  * Given the specified pixel clock, work out the necessary divider to get
 342  * close to the output frequency.
 343  */
 344 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
 345 {
 346         unsigned long clk;
 347         unsigned long long tmp;
 348         unsigned int result;
 349 
 350         if (sfb->variant.has_clksel)
 351                 clk = clk_get_rate(sfb->bus_clk);
 352         else
 353                 clk = clk_get_rate(sfb->lcd_clk);
 354 
 355         tmp = (unsigned long long)clk;
 356         tmp *= pixclk;
 357 
 358         do_div(tmp, 1000000000UL);
 359         result = (unsigned int)tmp / 1000;
 360 
 361         dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
 362                 pixclk, clk, result, result ? clk / result : clk);
 363 
 364         return result;
 365 }
 366 
 367 /**
 368  * s3c_fb_align_word() - align pixel count to word boundary
 369  * @bpp: The number of bits per pixel
 370  * @pix: The value to be aligned.
 371  *
 372  * Align the given pixel count so that it will start on an 32bit word
 373  * boundary.
 374  */
 375 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 376 {
 377         int pix_per_word;
 378 
 379         if (bpp > 16)
 380                 return pix;
 381 
 382         pix_per_word = (8 * 32) / bpp;
 383         return ALIGN(pix, pix_per_word);
 384 }
 385 
 386 /**
 387  * vidosd_set_size() - set OSD size for a window
 388  *
 389  * @win: the window to set OSD size for
 390  * @size: OSD size register value
 391  */
 392 static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
 393 {
 394         struct s3c_fb *sfb = win->parent;
 395 
 396         /* OSD can be set up if osd_size_off != 0 for this window */
 397         if (win->variant.osd_size_off)
 398                 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
 399                                 + win->variant.osd_size_off);
 400 }
 401 
 402 /**
 403  * vidosd_set_alpha() - set alpha transparency for a window
 404  *
 405  * @win: the window to set OSD size for
 406  * @alpha: alpha register value
 407  */
 408 static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
 409 {
 410         struct s3c_fb *sfb = win->parent;
 411 
 412         if (win->variant.has_osd_alpha)
 413                 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
 414 }
 415 
 416 /**
 417  * shadow_protect_win() - disable updating values from shadow registers at vsync
 418  *
 419  * @win: window to protect registers for
 420  * @protect: 1 to protect (disable updates)
 421  */
 422 static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
 423 {
 424         struct s3c_fb *sfb = win->parent;
 425         u32 reg;
 426 
 427         if (protect) {
 428                 if (sfb->variant.has_prtcon) {
 429                         writel(PRTCON_PROTECT, sfb->regs + PRTCON);
 430                 } else if (sfb->variant.has_shadowcon) {
 431                         reg = readl(sfb->regs + SHADOWCON);
 432                         writel(reg | SHADOWCON_WINx_PROTECT(win->index),
 433                                 sfb->regs + SHADOWCON);
 434                 }
 435         } else {
 436                 if (sfb->variant.has_prtcon) {
 437                         writel(0, sfb->regs + PRTCON);
 438                 } else if (sfb->variant.has_shadowcon) {
 439                         reg = readl(sfb->regs + SHADOWCON);
 440                         writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
 441                                 sfb->regs + SHADOWCON);
 442                 }
 443         }
 444 }
 445 
 446 /**
 447  * s3c_fb_enable() - Set the state of the main LCD output
 448  * @sfb: The main framebuffer state.
 449  * @enable: The state to set.
 450  */
 451 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
 452 {
 453         u32 vidcon0 = readl(sfb->regs + VIDCON0);
 454 
 455         if (enable && !sfb->output_on)
 456                 pm_runtime_get_sync(sfb->dev);
 457 
 458         if (enable) {
 459                 vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 460         } else {
 461                 /* see the note in the framebuffer datasheet about
 462                  * why you cannot take both of these bits down at the
 463                  * same time. */
 464 
 465                 if (vidcon0 & VIDCON0_ENVID) {
 466                         vidcon0 |= VIDCON0_ENVID;
 467                         vidcon0 &= ~VIDCON0_ENVID_F;
 468                 }
 469         }
 470 
 471         writel(vidcon0, sfb->regs + VIDCON0);
 472 
 473         if (!enable && sfb->output_on)
 474                 pm_runtime_put_sync(sfb->dev);
 475 
 476         sfb->output_on = enable;
 477 }
 478 
 479 /**
 480  * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
 481  * @info: The framebuffer to change.
 482  *
 483  * Framebuffer layer request to set a new mode for the specified framebuffer
 484  */
 485 static int s3c_fb_set_par(struct fb_info *info)
 486 {
 487         struct fb_var_screeninfo *var = &info->var;
 488         struct s3c_fb_win *win = info->par;
 489         struct s3c_fb *sfb = win->parent;
 490         void __iomem *regs = sfb->regs;
 491         void __iomem *buf = regs;
 492         int win_no = win->index;
 493         u32 alpha = 0;
 494         u32 data;
 495         u32 pagewidth;
 496 
 497         dev_dbg(sfb->dev, "setting framebuffer parameters\n");
 498 
 499         pm_runtime_get_sync(sfb->dev);
 500 
 501         shadow_protect_win(win, 1);
 502 
 503         switch (var->bits_per_pixel) {
 504         case 32:
 505         case 24:
 506         case 16:
 507         case 12:
 508                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 509                 break;
 510         case 8:
 511                 if (win->variant.palette_sz >= 256)
 512                         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 513                 else
 514                         info->fix.visual = FB_VISUAL_TRUECOLOR;
 515                 break;
 516         case 1:
 517                 info->fix.visual = FB_VISUAL_MONO01;
 518                 break;
 519         default:
 520                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 521                 break;
 522         }
 523 
 524         info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 525 
 526         info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
 527         info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
 528 
 529         /* disable the window whilst we update it */
 530         writel(0, regs + WINCON(win_no));
 531 
 532         if (!sfb->output_on)
 533                 s3c_fb_enable(sfb, 1);
 534 
 535         /* write the buffer address */
 536 
 537         /* start and end registers stride is 8 */
 538         buf = regs + win_no * 8;
 539 
 540         writel(info->fix.smem_start, buf + sfb->variant.buf_start);
 541 
 542         data = info->fix.smem_start + info->fix.line_length * var->yres;
 543         writel(data, buf + sfb->variant.buf_end);
 544 
 545         pagewidth = (var->xres * var->bits_per_pixel) >> 3;
 546         data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
 547                VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) |
 548                VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) |
 549                VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth);
 550         writel(data, regs + sfb->variant.buf_size + (win_no * 4));
 551 
 552         /* write 'OSD' registers to control position of framebuffer */
 553 
 554         data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |
 555                VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0);
 556         writel(data, regs + VIDOSD_A(win_no, sfb->variant));
 557 
 558         data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
 559                                                      var->xres - 1)) |
 560                VIDOSDxB_BOTRIGHT_Y(var->yres - 1) |
 561                VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel,
 562                                                      var->xres - 1)) |
 563                VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1);
 564 
 565         writel(data, regs + VIDOSD_B(win_no, sfb->variant));
 566 
 567         data = var->xres * var->yres;
 568 
 569         alpha = VIDISD14C_ALPHA1_R(0xf) |
 570                 VIDISD14C_ALPHA1_G(0xf) |
 571                 VIDISD14C_ALPHA1_B(0xf);
 572 
 573         vidosd_set_alpha(win, alpha);
 574         vidosd_set_size(win, data);
 575 
 576         /* Enable DMA channel for this window */
 577         if (sfb->variant.has_shadowcon) {
 578                 data = readl(sfb->regs + SHADOWCON);
 579                 data |= SHADOWCON_CHx_ENABLE(win_no);
 580                 writel(data, sfb->regs + SHADOWCON);
 581         }
 582 
 583         data = WINCONx_ENWIN;
 584         sfb->enabled |= (1 << win->index);
 585 
 586         /* note, since we have to round up the bits-per-pixel, we end up
 587          * relying on the bitfield information for r/g/b/a to work out
 588          * exactly which mode of operation is intended. */
 589 
 590         switch (var->bits_per_pixel) {
 591         case 1:
 592                 data |= WINCON0_BPPMODE_1BPP;
 593                 data |= WINCONx_BITSWP;
 594                 data |= WINCONx_BURSTLEN_4WORD;
 595                 break;
 596         case 2:
 597                 data |= WINCON0_BPPMODE_2BPP;
 598                 data |= WINCONx_BITSWP;
 599                 data |= WINCONx_BURSTLEN_8WORD;
 600                 break;
 601         case 4:
 602                 data |= WINCON0_BPPMODE_4BPP;
 603                 data |= WINCONx_BITSWP;
 604                 data |= WINCONx_BURSTLEN_8WORD;
 605                 break;
 606         case 8:
 607                 if (var->transp.length != 0)
 608                         data |= WINCON1_BPPMODE_8BPP_1232;
 609                 else
 610                         data |= WINCON0_BPPMODE_8BPP_PALETTE;
 611                 data |= WINCONx_BURSTLEN_8WORD;
 612                 data |= WINCONx_BYTSWP;
 613                 break;
 614         case 16:
 615                 if (var->transp.length != 0)
 616                         data |= WINCON1_BPPMODE_16BPP_A1555;
 617                 else
 618                         data |= WINCON0_BPPMODE_16BPP_565;
 619                 data |= WINCONx_HAWSWP;
 620                 data |= WINCONx_BURSTLEN_16WORD;
 621                 break;
 622         case 24:
 623         case 32:
 624                 if (var->red.length == 6) {
 625                         if (var->transp.length != 0)
 626                                 data |= WINCON1_BPPMODE_19BPP_A1666;
 627                         else
 628                                 data |= WINCON1_BPPMODE_18BPP_666;
 629                 } else if (var->transp.length == 1)
 630                         data |= WINCON1_BPPMODE_25BPP_A1888
 631                                 | WINCON1_BLD_PIX;
 632                 else if ((var->transp.length == 4) ||
 633                         (var->transp.length == 8))
 634                         data |= WINCON1_BPPMODE_28BPP_A4888
 635                                 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 636                 else
 637                         data |= WINCON0_BPPMODE_24BPP_888;
 638 
 639                 data |= WINCONx_WSWP;
 640                 data |= WINCONx_BURSTLEN_16WORD;
 641                 break;
 642         }
 643 
 644         /* Enable the colour keying for the window below this one */
 645         if (win_no > 0) {
 646                 u32 keycon0_data = 0, keycon1_data = 0;
 647                 void __iomem *keycon = regs + sfb->variant.keycon;
 648 
 649                 keycon0_data = ~(WxKEYCON0_KEYBL_EN |
 650                                 WxKEYCON0_KEYEN_F |
 651                                 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 652 
 653                 keycon1_data = WxKEYCON1_COLVAL(0xffffff);
 654 
 655                 keycon += (win_no - 1) * 8;
 656 
 657                 writel(keycon0_data, keycon + WKEYCON0);
 658                 writel(keycon1_data, keycon + WKEYCON1);
 659         }
 660 
 661         writel(data, regs + sfb->variant.wincon + (win_no * 4));
 662         writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
 663 
 664         /* Set alpha value width */
 665         if (sfb->variant.has_blendcon) {
 666                 data = readl(sfb->regs + BLENDCON);
 667                 data &= ~BLENDCON_NEW_MASK;
 668                 if (var->transp.length > 4)
 669                         data |= BLENDCON_NEW_8BIT_ALPHA_VALUE;
 670                 else
 671                         data |= BLENDCON_NEW_4BIT_ALPHA_VALUE;
 672                 writel(data, sfb->regs + BLENDCON);
 673         }
 674 
 675         shadow_protect_win(win, 0);
 676 
 677         pm_runtime_put_sync(sfb->dev);
 678 
 679         return 0;
 680 }
 681 
 682 /**
 683  * s3c_fb_update_palette() - set or schedule a palette update.
 684  * @sfb: The hardware information.
 685  * @win: The window being updated.
 686  * @reg: The palette index being changed.
 687  * @value: The computed palette value.
 688  *
 689  * Change the value of a palette register, either by directly writing to
 690  * the palette (this requires the palette RAM to be disconnected from the
 691  * hardware whilst this is in progress) or schedule the update for later.
 692  *
 693  * At the moment, since we have no VSYNC interrupt support, we simply set
 694  * the palette entry directly.
 695  */
 696 static void s3c_fb_update_palette(struct s3c_fb *sfb,
 697                                   struct s3c_fb_win *win,
 698                                   unsigned int reg,
 699                                   u32 value)
 700 {
 701         void __iomem *palreg;
 702         u32 palcon;
 703 
 704         palreg = sfb->regs + sfb->variant.palette[win->index];
 705 
 706         dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
 707                 __func__, win->index, reg, palreg, value);
 708 
 709         win->palette_buffer[reg] = value;
 710 
 711         palcon = readl(sfb->regs + WPALCON);
 712         writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
 713 
 714         if (win->variant.palette_16bpp)
 715                 writew(value, palreg + (reg * 2));
 716         else
 717                 writel(value, palreg + (reg * 4));
 718 
 719         writel(palcon, sfb->regs + WPALCON);
 720 }
 721 
 722 static inline unsigned int chan_to_field(unsigned int chan,
 723                                          struct fb_bitfield *bf)
 724 {
 725         chan &= 0xffff;
 726         chan >>= 16 - bf->length;
 727         return chan << bf->offset;
 728 }
 729 
 730 /**
 731  * s3c_fb_setcolreg() - framebuffer layer request to change palette.
 732  * @regno: The palette index to change.
 733  * @red: The red field for the palette data.
 734  * @green: The green field for the palette data.
 735  * @blue: The blue field for the palette data.
 736  * @trans: The transparency (alpha) field for the palette data.
 737  * @info: The framebuffer being changed.
 738  */
 739 static int s3c_fb_setcolreg(unsigned regno,
 740                             unsigned red, unsigned green, unsigned blue,
 741                             unsigned transp, struct fb_info *info)
 742 {
 743         struct s3c_fb_win *win = info->par;
 744         struct s3c_fb *sfb = win->parent;
 745         unsigned int val;
 746 
 747         dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
 748                 __func__, win->index, regno, red, green, blue);
 749 
 750         pm_runtime_get_sync(sfb->dev);
 751 
 752         switch (info->fix.visual) {
 753         case FB_VISUAL_TRUECOLOR:
 754                 /* true-colour, use pseudo-palette */
 755 
 756                 if (regno < 16) {
 757                         u32 *pal = info->pseudo_palette;
 758 
 759                         val  = chan_to_field(red,   &info->var.red);
 760                         val |= chan_to_field(green, &info->var.green);
 761                         val |= chan_to_field(blue,  &info->var.blue);
 762 
 763                         pal[regno] = val;
 764                 }
 765                 break;
 766 
 767         case FB_VISUAL_PSEUDOCOLOR:
 768                 if (regno < win->variant.palette_sz) {
 769                         val  = chan_to_field(red, &win->palette.r);
 770                         val |= chan_to_field(green, &win->palette.g);
 771                         val |= chan_to_field(blue, &win->palette.b);
 772 
 773                         s3c_fb_update_palette(sfb, win, regno, val);
 774                 }
 775 
 776                 break;
 777 
 778         default:
 779                 pm_runtime_put_sync(sfb->dev);
 780                 return 1;       /* unknown type */
 781         }
 782 
 783         pm_runtime_put_sync(sfb->dev);
 784         return 0;
 785 }
 786 
 787 /**
 788  * s3c_fb_blank() - blank or unblank the given window
 789  * @blank_mode: The blank state from FB_BLANK_*
 790  * @info: The framebuffer to blank.
 791  *
 792  * Framebuffer layer request to change the power state.
 793  */
 794 static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 795 {
 796         struct s3c_fb_win *win = info->par;
 797         struct s3c_fb *sfb = win->parent;
 798         unsigned int index = win->index;
 799         u32 wincon;
 800         u32 output_on = sfb->output_on;
 801 
 802         dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
 803 
 804         pm_runtime_get_sync(sfb->dev);
 805 
 806         wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
 807 
 808         switch (blank_mode) {
 809         case FB_BLANK_POWERDOWN:
 810                 wincon &= ~WINCONx_ENWIN;
 811                 sfb->enabled &= ~(1 << index);
 812                 /* fall through - to FB_BLANK_NORMAL */
 813 
 814         case FB_BLANK_NORMAL:
 815                 /* disable the DMA and display 0x0 (black) */
 816                 shadow_protect_win(win, 1);
 817                 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
 818                        sfb->regs + sfb->variant.winmap + (index * 4));
 819                 shadow_protect_win(win, 0);
 820                 break;
 821 
 822         case FB_BLANK_UNBLANK:
 823                 shadow_protect_win(win, 1);
 824                 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
 825                 shadow_protect_win(win, 0);
 826                 wincon |= WINCONx_ENWIN;
 827                 sfb->enabled |= (1 << index);
 828                 break;
 829 
 830         case FB_BLANK_VSYNC_SUSPEND:
 831         case FB_BLANK_HSYNC_SUSPEND:
 832         default:
 833                 pm_runtime_put_sync(sfb->dev);
 834                 return 1;
 835         }
 836 
 837         shadow_protect_win(win, 1);
 838         writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
 839 
 840         /* Check the enabled state to see if we need to be running the
 841          * main LCD interface, as if there are no active windows then
 842          * it is highly likely that we also do not need to output
 843          * anything.
 844          */
 845         s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
 846         shadow_protect_win(win, 0);
 847 
 848         pm_runtime_put_sync(sfb->dev);
 849 
 850         return output_on == sfb->output_on;
 851 }
 852 
 853 /**
 854  * s3c_fb_pan_display() - Pan the display.
 855  *
 856  * Note that the offsets can be written to the device at any time, as their
 857  * values are latched at each vsync automatically. This also means that only
 858  * the last call to this function will have any effect on next vsync, but
 859  * there is no need to sleep waiting for it to prevent tearing.
 860  *
 861  * @var: The screen information to verify.
 862  * @info: The framebuffer device.
 863  */
 864 static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 865                               struct fb_info *info)
 866 {
 867         struct s3c_fb_win *win  = info->par;
 868         struct s3c_fb *sfb      = win->parent;
 869         void __iomem *buf       = sfb->regs + win->index * 8;
 870         unsigned int start_boff, end_boff;
 871 
 872         pm_runtime_get_sync(sfb->dev);
 873 
 874         /* Offset in bytes to the start of the displayed area */
 875         start_boff = var->yoffset * info->fix.line_length;
 876         /* X offset depends on the current bpp */
 877         if (info->var.bits_per_pixel >= 8) {
 878                 start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
 879         } else {
 880                 switch (info->var.bits_per_pixel) {
 881                 case 4:
 882                         start_boff += var->xoffset >> 1;
 883                         break;
 884                 case 2:
 885                         start_boff += var->xoffset >> 2;
 886                         break;
 887                 case 1:
 888                         start_boff += var->xoffset >> 3;
 889                         break;
 890                 default:
 891                         dev_err(sfb->dev, "invalid bpp\n");
 892                         pm_runtime_put_sync(sfb->dev);
 893                         return -EINVAL;
 894                 }
 895         }
 896         /* Offset in bytes to the end of the displayed area */
 897         end_boff = start_boff + info->var.yres * info->fix.line_length;
 898 
 899         /* Temporarily turn off per-vsync update from shadow registers until
 900          * both start and end addresses are updated to prevent corruption */
 901         shadow_protect_win(win, 1);
 902 
 903         writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
 904         writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
 905 
 906         shadow_protect_win(win, 0);
 907 
 908         pm_runtime_put_sync(sfb->dev);
 909         return 0;
 910 }
 911 
 912 /**
 913  * s3c_fb_enable_irq() - enable framebuffer interrupts
 914  * @sfb: main hardware state
 915  */
 916 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
 917 {
 918         void __iomem *regs = sfb->regs;
 919         u32 irq_ctrl_reg;
 920 
 921         if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
 922                 /* IRQ disabled, enable it */
 923                 irq_ctrl_reg = readl(regs + VIDINTCON0);
 924 
 925                 irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
 926                 irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
 927 
 928                 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
 929                 irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
 930                 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
 931                 irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
 932 
 933                 writel(irq_ctrl_reg, regs + VIDINTCON0);
 934         }
 935 }
 936 
 937 /**
 938  * s3c_fb_disable_irq() - disable framebuffer interrupts
 939  * @sfb: main hardware state
 940  */
 941 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
 942 {
 943         void __iomem *regs = sfb->regs;
 944         u32 irq_ctrl_reg;
 945 
 946         if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
 947                 /* IRQ enabled, disable it */
 948                 irq_ctrl_reg = readl(regs + VIDINTCON0);
 949 
 950                 irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
 951                 irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
 952 
 953                 writel(irq_ctrl_reg, regs + VIDINTCON0);
 954         }
 955 }
 956 
 957 static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
 958 {
 959         struct s3c_fb *sfb = dev_id;
 960         void __iomem  *regs = sfb->regs;
 961         u32 irq_sts_reg;
 962 
 963         spin_lock(&sfb->slock);
 964 
 965         irq_sts_reg = readl(regs + VIDINTCON1);
 966 
 967         if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
 968 
 969                 /* VSYNC interrupt, accept it */
 970                 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
 971 
 972                 sfb->vsync_info.count++;
 973                 wake_up_interruptible(&sfb->vsync_info.wait);
 974         }
 975 
 976         /* We only support waiting for VSYNC for now, so it's safe
 977          * to always disable irqs here.
 978          */
 979         s3c_fb_disable_irq(sfb);
 980 
 981         spin_unlock(&sfb->slock);
 982         return IRQ_HANDLED;
 983 }
 984 
 985 /**
 986  * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
 987  * @sfb: main hardware state
 988  * @crtc: head index.
 989  */
 990 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
 991 {
 992         unsigned long count;
 993         int ret;
 994 
 995         if (crtc != 0)
 996                 return -ENODEV;
 997 
 998         pm_runtime_get_sync(sfb->dev);
 999 
1000         count = sfb->vsync_info.count;
1001         s3c_fb_enable_irq(sfb);
1002         ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
1003                                        count != sfb->vsync_info.count,
1004                                        msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
1005 
1006         pm_runtime_put_sync(sfb->dev);
1007 
1008         if (ret == 0)
1009                 return -ETIMEDOUT;
1010 
1011         return 0;
1012 }
1013 
1014 static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
1015                         unsigned long arg)
1016 {
1017         struct s3c_fb_win *win = info->par;
1018         struct s3c_fb *sfb = win->parent;
1019         int ret;
1020         u32 crtc;
1021 
1022         switch (cmd) {
1023         case FBIO_WAITFORVSYNC:
1024                 if (get_user(crtc, (u32 __user *)arg)) {
1025                         ret = -EFAULT;
1026                         break;
1027                 }
1028 
1029                 ret = s3c_fb_wait_for_vsync(sfb, crtc);
1030                 break;
1031         default:
1032                 ret = -ENOTTY;
1033         }
1034 
1035         return ret;
1036 }
1037 
1038 static struct fb_ops s3c_fb_ops = {
1039         .owner          = THIS_MODULE,
1040         .fb_check_var   = s3c_fb_check_var,
1041         .fb_set_par     = s3c_fb_set_par,
1042         .fb_blank       = s3c_fb_blank,
1043         .fb_setcolreg   = s3c_fb_setcolreg,
1044         .fb_fillrect    = cfb_fillrect,
1045         .fb_copyarea    = cfb_copyarea,
1046         .fb_imageblit   = cfb_imageblit,
1047         .fb_pan_display = s3c_fb_pan_display,
1048         .fb_ioctl       = s3c_fb_ioctl,
1049 };
1050 
1051 /**
1052  * s3c_fb_missing_pixclock() - calculates pixel clock
1053  * @mode: The video mode to change.
1054  *
1055  * Calculate the pixel clock when none has been given through platform data.
1056  */
1057 static void s3c_fb_missing_pixclock(struct fb_videomode *mode)
1058 {
1059         u64 pixclk = 1000000000000ULL;
1060         u32 div;
1061 
1062         div  = mode->left_margin + mode->hsync_len + mode->right_margin +
1063                mode->xres;
1064         div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1065                mode->yres;
1066         div *= mode->refresh ? : 60;
1067 
1068         do_div(pixclk, div);
1069 
1070         mode->pixclock = pixclk;
1071 }
1072 
1073 /**
1074  * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1075  * @sfb: The base resources for the hardware.
1076  * @win: The window to initialise memory for.
1077  *
1078  * Allocate memory for the given framebuffer.
1079  */
1080 static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1081 {
1082         struct s3c_fb_pd_win *windata = win->windata;
1083         unsigned int real_size, virt_size, size;
1084         struct fb_info *fbi = win->fbinfo;
1085         dma_addr_t map_dma;
1086 
1087         dev_dbg(sfb->dev, "allocating memory for display\n");
1088 
1089         real_size = windata->xres * windata->yres;
1090         virt_size = windata->virtual_x * windata->virtual_y;
1091 
1092         dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1093                 real_size, windata->xres, windata->yres,
1094                 virt_size, windata->virtual_x, windata->virtual_y);
1095 
1096         size = (real_size > virt_size) ? real_size : virt_size;
1097         size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1098         size /= 8;
1099 
1100         fbi->fix.smem_len = size;
1101         size = PAGE_ALIGN(size);
1102 
1103         dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1104 
1105         fbi->screen_buffer = dma_alloc_wc(sfb->dev, size, &map_dma, GFP_KERNEL);
1106         if (!fbi->screen_buffer)
1107                 return -ENOMEM;
1108 
1109         dev_dbg(sfb->dev, "mapped %x to %p\n",
1110                 (unsigned int)map_dma, fbi->screen_buffer);
1111 
1112         memset(fbi->screen_buffer, 0x0, size);
1113         fbi->fix.smem_start = map_dma;
1114 
1115         return 0;
1116 }
1117 
1118 /**
1119  * s3c_fb_free_memory() - free the display memory for the given window
1120  * @sfb: The base resources for the hardware.
1121  * @win: The window to free the display memory for.
1122  *
1123  * Free the display memory allocated by s3c_fb_alloc_memory().
1124  */
1125 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1126 {
1127         struct fb_info *fbi = win->fbinfo;
1128 
1129         if (fbi->screen_buffer)
1130                 dma_free_wc(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1131                             fbi->screen_buffer, fbi->fix.smem_start);
1132 }
1133 
1134 /**
1135  * s3c_fb_release_win() - release resources for a framebuffer window.
1136  * @win: The window to cleanup the resources for.
1137  *
1138  * Release the resources that where claimed for the hardware window,
1139  * such as the framebuffer instance and any memory claimed for it.
1140  */
1141 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1142 {
1143         u32 data;
1144 
1145         if (win->fbinfo) {
1146                 if (sfb->variant.has_shadowcon) {
1147                         data = readl(sfb->regs + SHADOWCON);
1148                         data &= ~SHADOWCON_CHx_ENABLE(win->index);
1149                         data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1150                         writel(data, sfb->regs + SHADOWCON);
1151                 }
1152                 unregister_framebuffer(win->fbinfo);
1153                 if (win->fbinfo->cmap.len)
1154                         fb_dealloc_cmap(&win->fbinfo->cmap);
1155                 s3c_fb_free_memory(sfb, win);
1156                 framebuffer_release(win->fbinfo);
1157         }
1158 }
1159 
1160 /**
1161  * s3c_fb_probe_win() - register an hardware window
1162  * @sfb: The base resources for the hardware
1163  * @variant: The variant information for this window.
1164  * @res: Pointer to where to place the resultant window.
1165  *
1166  * Allocate and do the basic initialisation for one of the hardware's graphics
1167  * windows.
1168  */
1169 static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1170                             struct s3c_fb_win_variant *variant,
1171                             struct s3c_fb_win **res)
1172 {
1173         struct fb_var_screeninfo *var;
1174         struct fb_videomode initmode;
1175         struct s3c_fb_pd_win *windata;
1176         struct s3c_fb_win *win;
1177         struct fb_info *fbinfo;
1178         int palette_size;
1179         int ret;
1180 
1181         dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1182 
1183         init_waitqueue_head(&sfb->vsync_info.wait);
1184 
1185         palette_size = variant->palette_sz * 4;
1186 
1187         fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1188                                    palette_size * sizeof(u32), sfb->dev);
1189         if (!fbinfo)
1190                 return -ENOMEM;
1191 
1192         windata = sfb->pdata->win[win_no];
1193         initmode = *sfb->pdata->vtiming;
1194 
1195         WARN_ON(windata->max_bpp == 0);
1196         WARN_ON(windata->xres == 0);
1197         WARN_ON(windata->yres == 0);
1198 
1199         win = fbinfo->par;
1200         *res = win;
1201         var = &fbinfo->var;
1202         win->variant = *variant;
1203         win->fbinfo = fbinfo;
1204         win->parent = sfb;
1205         win->windata = windata;
1206         win->index = win_no;
1207         win->palette_buffer = (u32 *)(win + 1);
1208 
1209         ret = s3c_fb_alloc_memory(sfb, win);
1210         if (ret) {
1211                 dev_err(sfb->dev, "failed to allocate display memory\n");
1212                 return ret;
1213         }
1214 
1215         /* setup the r/b/g positions for the window's palette */
1216         if (win->variant.palette_16bpp) {
1217                 /* Set RGB 5:6:5 as default */
1218                 win->palette.r.offset = 11;
1219                 win->palette.r.length = 5;
1220                 win->palette.g.offset = 5;
1221                 win->palette.g.length = 6;
1222                 win->palette.b.offset = 0;
1223                 win->palette.b.length = 5;
1224 
1225         } else {
1226                 /* Set 8bpp or 8bpp and 1bit alpha */
1227                 win->palette.r.offset = 16;
1228                 win->palette.r.length = 8;
1229                 win->palette.g.offset = 8;
1230                 win->palette.g.length = 8;
1231                 win->palette.b.offset = 0;
1232                 win->palette.b.length = 8;
1233         }
1234 
1235         /* setup the initial video mode from the window */
1236         initmode.xres = windata->xres;
1237         initmode.yres = windata->yres;
1238         fb_videomode_to_var(&fbinfo->var, &initmode);
1239 
1240         fbinfo->fix.type        = FB_TYPE_PACKED_PIXELS;
1241         fbinfo->fix.accel       = FB_ACCEL_NONE;
1242         fbinfo->var.activate    = FB_ACTIVATE_NOW;
1243         fbinfo->var.vmode       = FB_VMODE_NONINTERLACED;
1244         fbinfo->var.bits_per_pixel = windata->default_bpp;
1245         fbinfo->fbops           = &s3c_fb_ops;
1246         fbinfo->flags           = FBINFO_FLAG_DEFAULT;
1247         fbinfo->pseudo_palette  = &win->pseudo_palette;
1248 
1249         /* prepare to actually start the framebuffer */
1250 
1251         ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1252         if (ret < 0) {
1253                 dev_err(sfb->dev, "check_var failed on initial video params\n");
1254                 return ret;
1255         }
1256 
1257         /* create initial colour map */
1258 
1259         ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1260         if (ret == 0)
1261                 fb_set_cmap(&fbinfo->cmap, fbinfo);
1262         else
1263                 dev_err(sfb->dev, "failed to allocate fb cmap\n");
1264 
1265         s3c_fb_set_par(fbinfo);
1266 
1267         dev_dbg(sfb->dev, "about to register framebuffer\n");
1268 
1269         /* run the check_var and set_par on our configuration. */
1270 
1271         ret = register_framebuffer(fbinfo);
1272         if (ret < 0) {
1273                 dev_err(sfb->dev, "failed to register framebuffer\n");
1274                 return ret;
1275         }
1276 
1277         dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1278 
1279         return 0;
1280 }
1281 
1282 /**
1283  * s3c_fb_set_rgb_timing() - set video timing for rgb interface.
1284  * @sfb: The base resources for the hardware.
1285  *
1286  * Set horizontal and vertical lcd rgb interface timing.
1287  */
1288 static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
1289 {
1290         struct fb_videomode *vmode = sfb->pdata->vtiming;
1291         void __iomem *regs = sfb->regs;
1292         int clkdiv;
1293         u32 data;
1294 
1295         if (!vmode->pixclock)
1296                 s3c_fb_missing_pixclock(vmode);
1297 
1298         clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
1299 
1300         data = sfb->pdata->vidcon0;
1301         data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
1302 
1303         if (clkdiv > 1)
1304                 data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
1305         else
1306                 data &= ~VIDCON0_CLKDIR;        /* 1:1 clock */
1307 
1308         if (sfb->variant.is_2443)
1309                 data |= (1 << 5);
1310         writel(data, regs + VIDCON0);
1311 
1312         data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
1313                VIDTCON0_VFPD(vmode->lower_margin - 1) |
1314                VIDTCON0_VSPW(vmode->vsync_len - 1);
1315         writel(data, regs + sfb->variant.vidtcon);
1316 
1317         data = VIDTCON1_HBPD(vmode->left_margin - 1) |
1318                VIDTCON1_HFPD(vmode->right_margin - 1) |
1319                VIDTCON1_HSPW(vmode->hsync_len - 1);
1320         writel(data, regs + sfb->variant.vidtcon + 4);
1321 
1322         data = VIDTCON2_LINEVAL(vmode->yres - 1) |
1323                VIDTCON2_HOZVAL(vmode->xres - 1) |
1324                VIDTCON2_LINEVAL_E(vmode->yres - 1) |
1325                VIDTCON2_HOZVAL_E(vmode->xres - 1);
1326         writel(data, regs + sfb->variant.vidtcon + 8);
1327 }
1328 
1329 /**
1330  * s3c_fb_clear_win() - clear hardware window registers.
1331  * @sfb: The base resources for the hardware.
1332  * @win: The window to process.
1333  *
1334  * Reset the specific window registers to a known state.
1335  */
1336 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1337 {
1338         void __iomem *regs = sfb->regs;
1339         u32 reg;
1340 
1341         writel(0, regs + sfb->variant.wincon + (win * 4));
1342         writel(0, regs + VIDOSD_A(win, sfb->variant));
1343         writel(0, regs + VIDOSD_B(win, sfb->variant));
1344         writel(0, regs + VIDOSD_C(win, sfb->variant));
1345 
1346         if (sfb->variant.has_shadowcon) {
1347                 reg = readl(sfb->regs + SHADOWCON);
1348                 reg &= ~(SHADOWCON_WINx_PROTECT(win) |
1349                         SHADOWCON_CHx_ENABLE(win) |
1350                         SHADOWCON_CHx_LOCAL_ENABLE(win));
1351                 writel(reg, sfb->regs + SHADOWCON);
1352         }
1353 }
1354 
1355 static int s3c_fb_probe(struct platform_device *pdev)
1356 {
1357         const struct platform_device_id *platid;
1358         struct s3c_fb_driverdata *fbdrv;
1359         struct device *dev = &pdev->dev;
1360         struct s3c_fb_platdata *pd;
1361         struct s3c_fb *sfb;
1362         struct resource *res;
1363         int win;
1364         int ret = 0;
1365         u32 reg;
1366 
1367         platid = platform_get_device_id(pdev);
1368         fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
1369 
1370         if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1371                 dev_err(dev, "too many windows, cannot attach\n");
1372                 return -EINVAL;
1373         }
1374 
1375         pd = dev_get_platdata(&pdev->dev);
1376         if (!pd) {
1377                 dev_err(dev, "no platform data specified\n");
1378                 return -EINVAL;
1379         }
1380 
1381         sfb = devm_kzalloc(dev, sizeof(*sfb), GFP_KERNEL);
1382         if (!sfb)
1383                 return -ENOMEM;
1384 
1385         dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1386 
1387         sfb->dev = dev;
1388         sfb->pdata = pd;
1389         sfb->variant = fbdrv->variant;
1390 
1391         spin_lock_init(&sfb->slock);
1392 
1393         sfb->bus_clk = devm_clk_get(dev, "lcd");
1394         if (IS_ERR(sfb->bus_clk)) {
1395                 dev_err(dev, "failed to get bus clock\n");
1396                 return PTR_ERR(sfb->bus_clk);
1397         }
1398 
1399         clk_prepare_enable(sfb->bus_clk);
1400 
1401         if (!sfb->variant.has_clksel) {
1402                 sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1403                 if (IS_ERR(sfb->lcd_clk)) {
1404                         dev_err(dev, "failed to get lcd clock\n");
1405                         ret = PTR_ERR(sfb->lcd_clk);
1406                         goto err_bus_clk;
1407                 }
1408 
1409                 clk_prepare_enable(sfb->lcd_clk);
1410         }
1411 
1412         pm_runtime_enable(sfb->dev);
1413 
1414         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1415         sfb->regs = devm_ioremap_resource(dev, res);
1416         if (IS_ERR(sfb->regs)) {
1417                 ret = PTR_ERR(sfb->regs);
1418                 goto err_lcd_clk;
1419         }
1420 
1421         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1422         if (!res) {
1423                 dev_err(dev, "failed to acquire irq resource\n");
1424                 ret = -ENOENT;
1425                 goto err_lcd_clk;
1426         }
1427         sfb->irq_no = res->start;
1428         ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
1429                           0, "s3c_fb", sfb);
1430         if (ret) {
1431                 dev_err(dev, "irq request failed\n");
1432                 goto err_lcd_clk;
1433         }
1434 
1435         dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1436 
1437         platform_set_drvdata(pdev, sfb);
1438         pm_runtime_get_sync(sfb->dev);
1439 
1440         /* setup gpio and output polarity controls */
1441 
1442         pd->setup_gpio();
1443 
1444         writel(pd->vidcon1, sfb->regs + VIDCON1);
1445 
1446         /* set video clock running at under-run */
1447         if (sfb->variant.has_fixvclk) {
1448                 reg = readl(sfb->regs + VIDCON1);
1449                 reg &= ~VIDCON1_VCLK_MASK;
1450                 reg |= VIDCON1_VCLK_RUN;
1451                 writel(reg, sfb->regs + VIDCON1);
1452         }
1453 
1454         /* zero all windows before we do anything */
1455 
1456         for (win = 0; win < fbdrv->variant.nr_windows; win++)
1457                 s3c_fb_clear_win(sfb, win);
1458 
1459         /* initialise colour key controls */
1460         for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1461                 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1462 
1463                 regs += (win * 8);
1464                 writel(0xffffff, regs + WKEYCON0);
1465                 writel(0xffffff, regs + WKEYCON1);
1466         }
1467 
1468         s3c_fb_set_rgb_timing(sfb);
1469 
1470         /* we have the register setup, start allocating framebuffers */
1471 
1472         for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1473                 if (!pd->win[win])
1474                         continue;
1475 
1476                 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1477                                        &sfb->windows[win]);
1478                 if (ret < 0) {
1479                         dev_err(dev, "failed to create window %d\n", win);
1480                         for (; win >= 0; win--)
1481                                 s3c_fb_release_win(sfb, sfb->windows[win]);
1482                         goto err_pm_runtime;
1483                 }
1484         }
1485 
1486         platform_set_drvdata(pdev, sfb);
1487         pm_runtime_put_sync(sfb->dev);
1488 
1489         return 0;
1490 
1491 err_pm_runtime:
1492         pm_runtime_put_sync(sfb->dev);
1493 
1494 err_lcd_clk:
1495         pm_runtime_disable(sfb->dev);
1496 
1497         if (!sfb->variant.has_clksel)
1498                 clk_disable_unprepare(sfb->lcd_clk);
1499 
1500 err_bus_clk:
1501         clk_disable_unprepare(sfb->bus_clk);
1502 
1503         return ret;
1504 }
1505 
1506 /**
1507  * s3c_fb_remove() - Cleanup on module finalisation
1508  * @pdev: The platform device we are bound to.
1509  *
1510  * Shutdown and then release all the resources that the driver allocated
1511  * on initialisation.
1512  */
1513 static int s3c_fb_remove(struct platform_device *pdev)
1514 {
1515         struct s3c_fb *sfb = platform_get_drvdata(pdev);
1516         int win;
1517 
1518         pm_runtime_get_sync(sfb->dev);
1519 
1520         for (win = 0; win < S3C_FB_MAX_WIN; win++)
1521                 if (sfb->windows[win])
1522                         s3c_fb_release_win(sfb, sfb->windows[win]);
1523 
1524         if (!sfb->variant.has_clksel)
1525                 clk_disable_unprepare(sfb->lcd_clk);
1526 
1527         clk_disable_unprepare(sfb->bus_clk);
1528 
1529         pm_runtime_put_sync(sfb->dev);
1530         pm_runtime_disable(sfb->dev);
1531 
1532         return 0;
1533 }
1534 
1535 #ifdef CONFIG_PM_SLEEP
1536 static int s3c_fb_suspend(struct device *dev)
1537 {
1538         struct s3c_fb *sfb = dev_get_drvdata(dev);
1539         struct s3c_fb_win *win;
1540         int win_no;
1541 
1542         pm_runtime_get_sync(sfb->dev);
1543 
1544         for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1545                 win = sfb->windows[win_no];
1546                 if (!win)
1547                         continue;
1548 
1549                 /* use the blank function to push into power-down */
1550                 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1551         }
1552 
1553         if (!sfb->variant.has_clksel)
1554                 clk_disable_unprepare(sfb->lcd_clk);
1555 
1556         clk_disable_unprepare(sfb->bus_clk);
1557 
1558         pm_runtime_put_sync(sfb->dev);
1559 
1560         return 0;
1561 }
1562 
1563 static int s3c_fb_resume(struct device *dev)
1564 {
1565         struct s3c_fb *sfb = dev_get_drvdata(dev);
1566         struct s3c_fb_platdata *pd = sfb->pdata;
1567         struct s3c_fb_win *win;
1568         int win_no;
1569         u32 reg;
1570 
1571         pm_runtime_get_sync(sfb->dev);
1572 
1573         clk_prepare_enable(sfb->bus_clk);
1574 
1575         if (!sfb->variant.has_clksel)
1576                 clk_prepare_enable(sfb->lcd_clk);
1577 
1578         /* setup gpio and output polarity controls */
1579         pd->setup_gpio();
1580         writel(pd->vidcon1, sfb->regs + VIDCON1);
1581 
1582         /* set video clock running at under-run */
1583         if (sfb->variant.has_fixvclk) {
1584                 reg = readl(sfb->regs + VIDCON1);
1585                 reg &= ~VIDCON1_VCLK_MASK;
1586                 reg |= VIDCON1_VCLK_RUN;
1587                 writel(reg, sfb->regs + VIDCON1);
1588         }
1589 
1590         /* zero all windows before we do anything */
1591         for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1592                 s3c_fb_clear_win(sfb, win_no);
1593 
1594         for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1595                 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1596                 win = sfb->windows[win_no];
1597                 if (!win)
1598                         continue;
1599 
1600                 shadow_protect_win(win, 1);
1601                 regs += (win_no * 8);
1602                 writel(0xffffff, regs + WKEYCON0);
1603                 writel(0xffffff, regs + WKEYCON1);
1604                 shadow_protect_win(win, 0);
1605         }
1606 
1607         s3c_fb_set_rgb_timing(sfb);
1608 
1609         /* restore framebuffers */
1610         for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1611                 win = sfb->windows[win_no];
1612                 if (!win)
1613                         continue;
1614 
1615                 dev_dbg(dev, "resuming window %d\n", win_no);
1616                 s3c_fb_set_par(win->fbinfo);
1617         }
1618 
1619         pm_runtime_put_sync(sfb->dev);
1620 
1621         return 0;
1622 }
1623 #endif
1624 
1625 #ifdef CONFIG_PM
1626 static int s3c_fb_runtime_suspend(struct device *dev)
1627 {
1628         struct s3c_fb *sfb = dev_get_drvdata(dev);
1629 
1630         if (!sfb->variant.has_clksel)
1631                 clk_disable_unprepare(sfb->lcd_clk);
1632 
1633         clk_disable_unprepare(sfb->bus_clk);
1634 
1635         return 0;
1636 }
1637 
1638 static int s3c_fb_runtime_resume(struct device *dev)
1639 {
1640         struct s3c_fb *sfb = dev_get_drvdata(dev);
1641         struct s3c_fb_platdata *pd = sfb->pdata;
1642 
1643         clk_prepare_enable(sfb->bus_clk);
1644 
1645         if (!sfb->variant.has_clksel)
1646                 clk_prepare_enable(sfb->lcd_clk);
1647 
1648         /* setup gpio and output polarity controls */
1649         pd->setup_gpio();
1650         writel(pd->vidcon1, sfb->regs + VIDCON1);
1651 
1652         return 0;
1653 }
1654 #endif
1655 
1656 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1657 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1658 
1659 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1660         [0] = {
1661                 .has_osd_c      = 1,
1662                 .osd_size_off   = 0x8,
1663                 .palette_sz     = 256,
1664                 .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1665                                    VALID_BPP(18) | VALID_BPP(24)),
1666         },
1667         [1] = {
1668                 .has_osd_c      = 1,
1669                 .has_osd_d      = 1,
1670                 .osd_size_off   = 0xc,
1671                 .has_osd_alpha  = 1,
1672                 .palette_sz     = 256,
1673                 .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1674                                    VALID_BPP(18) | VALID_BPP(19) |
1675                                    VALID_BPP(24) | VALID_BPP(25) |
1676                                    VALID_BPP(28)),
1677         },
1678         [2] = {
1679                 .has_osd_c      = 1,
1680                 .has_osd_d      = 1,
1681                 .osd_size_off   = 0xc,
1682                 .has_osd_alpha  = 1,
1683                 .palette_sz     = 16,
1684                 .palette_16bpp  = 1,
1685                 .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1686                                    VALID_BPP(18) | VALID_BPP(19) |
1687                                    VALID_BPP(24) | VALID_BPP(25) |
1688                                    VALID_BPP(28)),
1689         },
1690         [3] = {
1691                 .has_osd_c      = 1,
1692                 .has_osd_alpha  = 1,
1693                 .palette_sz     = 16,
1694                 .palette_16bpp  = 1,
1695                 .valid_bpp      = (VALID_BPP124  | VALID_BPP(16) |
1696                                    VALID_BPP(18) | VALID_BPP(19) |
1697                                    VALID_BPP(24) | VALID_BPP(25) |
1698                                    VALID_BPP(28)),
1699         },
1700         [4] = {
1701                 .has_osd_c      = 1,
1702                 .has_osd_alpha  = 1,
1703                 .palette_sz     = 4,
1704                 .palette_16bpp  = 1,
1705                 .valid_bpp      = (VALID_BPP(1) | VALID_BPP(2) |
1706                                    VALID_BPP(16) | VALID_BPP(18) |
1707                                    VALID_BPP(19) | VALID_BPP(24) |
1708                                    VALID_BPP(25) | VALID_BPP(28)),
1709         },
1710 };
1711 
1712 static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1713         .variant = {
1714                 .nr_windows     = 5,
1715                 .vidtcon        = VIDTCON0,
1716                 .wincon         = WINCON(0),
1717                 .winmap         = WINxMAP(0),
1718                 .keycon         = WKEYCON,
1719                 .osd            = VIDOSD_BASE,
1720                 .osd_stride     = 16,
1721                 .buf_start      = VIDW_BUF_START(0),
1722                 .buf_size       = VIDW_BUF_SIZE(0),
1723                 .buf_end        = VIDW_BUF_END(0),
1724 
1725                 .palette = {
1726                         [0] = 0x400,
1727                         [1] = 0x800,
1728                         [2] = 0x300,
1729                         [3] = 0x320,
1730                         [4] = 0x340,
1731                 },
1732 
1733                 .has_prtcon     = 1,
1734                 .has_clksel     = 1,
1735         },
1736         .win[0] = &s3c_fb_data_64xx_wins[0],
1737         .win[1] = &s3c_fb_data_64xx_wins[1],
1738         .win[2] = &s3c_fb_data_64xx_wins[2],
1739         .win[3] = &s3c_fb_data_64xx_wins[3],
1740         .win[4] = &s3c_fb_data_64xx_wins[4],
1741 };
1742 
1743 /* S3C2443/S3C2416 style hardware */
1744 static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1745         .variant = {
1746                 .nr_windows     = 2,
1747                 .is_2443        = 1,
1748 
1749                 .vidtcon        = 0x08,
1750                 .wincon         = 0x14,
1751                 .winmap         = 0xd0,
1752                 .keycon         = 0xb0,
1753                 .osd            = 0x28,
1754                 .osd_stride     = 12,
1755                 .buf_start      = 0x64,
1756                 .buf_size       = 0x94,
1757                 .buf_end        = 0x7c,
1758 
1759                 .palette = {
1760                         [0] = 0x400,
1761                         [1] = 0x800,
1762                 },
1763                 .has_clksel     = 1,
1764         },
1765         .win[0] = &(struct s3c_fb_win_variant) {
1766                 .palette_sz     = 256,
1767                 .valid_bpp      = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1768         },
1769         .win[1] = &(struct s3c_fb_win_variant) {
1770                 .has_osd_c      = 1,
1771                 .has_osd_alpha  = 1,
1772                 .palette_sz     = 256,
1773                 .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1774                                    VALID_BPP(18) | VALID_BPP(19) |
1775                                    VALID_BPP(24) | VALID_BPP(25) |
1776                                    VALID_BPP(28)),
1777         },
1778 };
1779 
1780 static const struct platform_device_id s3c_fb_driver_ids[] = {
1781         {
1782                 .name           = "s3c-fb",
1783                 .driver_data    = (unsigned long)&s3c_fb_data_64xx,
1784         }, {
1785                 .name           = "s3c2443-fb",
1786                 .driver_data    = (unsigned long)&s3c_fb_data_s3c2443,
1787         },
1788         {},
1789 };
1790 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
1791 
1792 static const struct dev_pm_ops s3cfb_pm_ops = {
1793         SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
1794         SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
1795                            NULL)
1796 };
1797 
1798 static struct platform_driver s3c_fb_driver = {
1799         .probe          = s3c_fb_probe,
1800         .remove         = s3c_fb_remove,
1801         .id_table       = s3c_fb_driver_ids,
1802         .driver         = {
1803                 .name   = "s3c-fb",
1804                 .pm     = &s3cfb_pm_ops,
1805         },
1806 };
1807 
1808 module_platform_driver(s3c_fb_driver);
1809 
1810 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1811 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
1812 MODULE_LICENSE("GPL");
1813 MODULE_ALIAS("platform:s3c-fb");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/video/fbdev/s3c-fb.c

DEFINITIONS
