drivers/video/fbdev/tdfxfb.c

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This source file includes following definitions.
vga_inb
vga_outb
gra_outb
seq_outb
seq_inb
crt_outb
crt_inb
att_outb
vga_disable_video
vga_enable_video
vga_enable_palette
tdfx_inl
tdfx_outl
banshee_make_room
banshee_wait_idle
do_setpalentry
do_calc_pll
do_write_regs
do_lfb_size
tdfxfb_check_var
tdfxfb_set_par
tdfxfb_setcolreg
tdfxfb_blank
tdfxfb_pan_display
tdfxfb_fillrect
tdfxfb_copyarea
tdfxfb_imageblit
tdfxfb_cursor
tdfxfb_i2c_setscl
tdfxfb_i2c_setsda
tdfxfb_i2c_getscl
tdfxfb_i2c_getsda
tdfxfb_ddc_setscl
tdfxfb_ddc_setsda
tdfxfb_ddc_getscl
tdfxfb_ddc_getsda
tdfxfb_setup_ddc_bus
tdfxfb_setup_i2c_bus
tdfxfb_create_i2c_busses
tdfxfb_delete_i2c_busses
tdfxfb_probe_i2c_connector
tdfxfb_probe
tdfxfb_setup
tdfxfb_remove
tdfxfb_init
tdfxfb_exit
   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  * tdfxfb.c
   5  *
   6  * Author: Hannu Mallat <hmallat@cc.hut.fi>
   7  *
   8  * Copyright © 1999 Hannu Mallat
   9  * All rights reserved
  10  *
  11  * Created      : Thu Sep 23 18:17:43 1999, hmallat
  12  * Last modified: Tue Nov  2 21:19:47 1999, hmallat
  13  *
  14  * I2C part copied from the i2c-voodoo3.c driver by:
  15  * Frodo Looijaard <frodol@dds.nl>,
  16  * Philip Edelbrock <phil@netroedge.com>,
  17  * Ralph Metzler <rjkm@thp.uni-koeln.de>, and
  18  * Mark D. Studebaker <mdsxyz123@yahoo.com>
  19  *
  20  * Lots of the information here comes from the Daryll Strauss' Banshee
  21  * patches to the XF86 server, and the rest comes from the 3dfx
  22  * Banshee specification. I'm very much indebted to Daryll for his
  23  * work on the X server.
  24  *
  25  * Voodoo3 support was contributed Harold Oga. Lots of additions
  26  * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
  27  * Kesmarki. Thanks guys!
  28  *
  29  * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
  30  * behave very differently from the Voodoo3/4/5. For anyone wanting to
  31  * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
  32  * located at http://www.sourceforge.net/projects/sstfb).
  33  *
  34  * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
  35  * I do wish the next version is a bit more complete. Without the XF86
  36  * patches I couldn't have gotten even this far... for instance, the
  37  * extensions to the VGA register set go completely unmentioned in the
  38  * spec! Also, lots of references are made to the 'SST core', but no
  39  * spec is publicly available, AFAIK.
  40  *
  41  * The structure of this driver comes pretty much from the Permedia
  42  * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
  43  *
  44  * TODO:
  45  * - multihead support (basically need to support an array of fb_infos)
  46  * - support other architectures (PPC, Alpha); does the fact that the VGA
  47  *   core can be accessed only thru I/O (not memory mapped) complicate
  48  *   things?
  49  *
  50  * Version history:
  51  *
  52  * 0.1.4 (released 2002-05-28)  ported over to new fbdev api by James Simmons
  53  *
  54  * 0.1.3 (released 1999-11-02)  added Attila's panning support, code
  55  *                              reorg, hwcursor address page size alignment
  56  *                              (for mmapping both frame buffer and regs),
  57  *                              and my changes to get rid of hardcoded
  58  *                              VGA i/o register locations (uses PCI
  59  *                              configuration info now)
  60  * 0.1.2 (released 1999-10-19)  added Attila Kesmarki's bug fixes and
  61  *                              improvements
  62  * 0.1.1 (released 1999-10-07)  added Voodoo3 support by Harold Oga.
  63  * 0.1.0 (released 1999-10-06)  initial version
  64  *
  65  */
  66 
  67 #include <linux/module.h>
  68 #include <linux/kernel.h>
  69 #include <linux/errno.h>
  70 #include <linux/string.h>
  71 #include <linux/mm.h>
  72 #include <linux/slab.h>
  73 #include <linux/fb.h>
  74 #include <linux/init.h>
  75 #include <linux/pci.h>
  76 #include <asm/io.h>
  77 
  78 #include <video/tdfx.h>
  79 
  80 #define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b)
  81 
  82 #define BANSHEE_MAX_PIXCLOCK 270000
  83 #define VOODOO3_MAX_PIXCLOCK 300000
  84 #define VOODOO5_MAX_PIXCLOCK 350000
  85 
  86 static const struct fb_fix_screeninfo tdfx_fix = {
  87         .type =         FB_TYPE_PACKED_PIXELS,
  88         .visual =       FB_VISUAL_PSEUDOCOLOR,
  89         .ypanstep =     1,
  90         .ywrapstep =    1,
  91         .accel =        FB_ACCEL_3DFX_BANSHEE
  92 };
  93 
  94 static const struct fb_var_screeninfo tdfx_var = {
  95         /* "640x480, 8 bpp @ 60 Hz */
  96         .xres =         640,
  97         .yres =         480,
  98         .xres_virtual = 640,
  99         .yres_virtual = 1024,
 100         .bits_per_pixel = 8,
 101         .red =          {0, 8, 0},
 102         .blue =         {0, 8, 0},
 103         .green =        {0, 8, 0},
 104         .activate =     FB_ACTIVATE_NOW,
 105         .height =       -1,
 106         .width =        -1,
 107         .accel_flags =  FB_ACCELF_TEXT,
 108         .pixclock =     39722,
 109         .left_margin =  40,
 110         .right_margin = 24,
 111         .upper_margin = 32,
 112         .lower_margin = 11,
 113         .hsync_len =    96,
 114         .vsync_len =    2,
 115         .vmode =        FB_VMODE_NONINTERLACED
 116 };
 117 
 118 /*
 119  * PCI driver prototypes
 120  */
 121 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id);
 122 static void tdfxfb_remove(struct pci_dev *pdev);
 123 
 124 static const struct pci_device_id tdfxfb_id_table[] = {
 125         { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
 126           PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 127           0xff0000, 0 },
 128         { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
 129           PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 130           0xff0000, 0 },
 131         { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
 132           PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 133           0xff0000, 0 },
 134         { 0, }
 135 };
 136 
 137 static struct pci_driver tdfxfb_driver = {
 138         .name           = "tdfxfb",
 139         .id_table       = tdfxfb_id_table,
 140         .probe          = tdfxfb_probe,
 141         .remove         = tdfxfb_remove,
 142 };
 143 
 144 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
 145 
 146 /*
 147  * Driver data
 148  */
 149 static int nopan;
 150 static int nowrap = 1;      /* not implemented (yet) */
 151 static int hwcursor = 1;
 152 static char *mode_option;
 153 static bool nomtrr;
 154 
 155 /* -------------------------------------------------------------------------
 156  *                      Hardware-specific funcions
 157  * ------------------------------------------------------------------------- */
 158 
 159 static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
 160 {
 161         return inb(par->iobase + reg - 0x300);
 162 }
 163 
 164 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
 165 {
 166         outb(val, par->iobase + reg - 0x300);
 167 }
 168 
 169 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
 170 {
 171         vga_outb(par, GRA_I, idx);
 172         wmb();
 173         vga_outb(par, GRA_D, val);
 174         wmb();
 175 }
 176 
 177 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
 178 {
 179         vga_outb(par, SEQ_I, idx);
 180         wmb();
 181         vga_outb(par, SEQ_D, val);
 182         wmb();
 183 }
 184 
 185 static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
 186 {
 187         vga_outb(par, SEQ_I, idx);
 188         mb();
 189         return vga_inb(par, SEQ_D);
 190 }
 191 
 192 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
 193 {
 194         vga_outb(par, CRT_I, idx);
 195         wmb();
 196         vga_outb(par, CRT_D, val);
 197         wmb();
 198 }
 199 
 200 static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
 201 {
 202         vga_outb(par, CRT_I, idx);
 203         mb();
 204         return vga_inb(par, CRT_D);
 205 }
 206 
 207 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
 208 {
 209         unsigned char tmp;
 210 
 211         tmp = vga_inb(par, IS1_R);
 212         vga_outb(par, ATT_IW, idx);
 213         vga_outb(par, ATT_IW, val);
 214 }
 215 
 216 static inline void vga_disable_video(struct tdfx_par *par)
 217 {
 218         unsigned char s;
 219 
 220         s = seq_inb(par, 0x01) | 0x20;
 221         seq_outb(par, 0x00, 0x01);
 222         seq_outb(par, 0x01, s);
 223         seq_outb(par, 0x00, 0x03);
 224 }
 225 
 226 static inline void vga_enable_video(struct tdfx_par *par)
 227 {
 228         unsigned char s;
 229 
 230         s = seq_inb(par, 0x01) & 0xdf;
 231         seq_outb(par, 0x00, 0x01);
 232         seq_outb(par, 0x01, s);
 233         seq_outb(par, 0x00, 0x03);
 234 }
 235 
 236 static inline void vga_enable_palette(struct tdfx_par *par)
 237 {
 238         vga_inb(par, IS1_R);
 239         mb();
 240         vga_outb(par, ATT_IW, 0x20);
 241 }
 242 
 243 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
 244 {
 245         return readl(par->regbase_virt + reg);
 246 }
 247 
 248 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
 249 {
 250         writel(val, par->regbase_virt + reg);
 251 }
 252 
 253 static inline void banshee_make_room(struct tdfx_par *par, int size)
 254 {
 255         /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
 256          * won't quit if you ask for more. */
 257         while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
 258                 cpu_relax();
 259 }
 260 
 261 static int banshee_wait_idle(struct fb_info *info)
 262 {
 263         struct tdfx_par *par = info->par;
 264         int i = 0;
 265 
 266         banshee_make_room(par, 1);
 267         tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
 268 
 269         do {
 270                 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
 271                         i++;
 272         } while (i < 3);
 273 
 274         return 0;
 275 }
 276 
 277 /*
 278  * Set the color of a palette entry in 8bpp mode
 279  */
 280 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
 281 {
 282         banshee_make_room(par, 2);
 283         tdfx_outl(par, DACADDR, regno);
 284         /* read after write makes it working */
 285         tdfx_inl(par, DACADDR);
 286         tdfx_outl(par, DACDATA, c);
 287 }
 288 
 289 static u32 do_calc_pll(int freq, int *freq_out)
 290 {
 291         int m, n, k, best_m, best_n, best_k, best_error;
 292         int fref = 14318;
 293 
 294         best_error = freq;
 295         best_n = best_m = best_k = 0;
 296 
 297         for (k = 3; k >= 0; k--) {
 298                 for (m = 63; m >= 0; m--) {
 299                         /*
 300                          * Estimate value of n that produces target frequency
 301                          * with current m and k
 302                          */
 303                         int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
 304 
 305                         /* Search neighborhood of estimated n */
 306                         for (n = max(0, n_estimated);
 307                                 n <= min(255, n_estimated + 1);
 308                                 n++) {
 309                                 /*
 310                                  * Calculate PLL freqency with current m, k and
 311                                  * estimated n
 312                                  */
 313                                 int f = (fref * (n + 2) / (m + 2)) >> k;
 314                                 int error = abs(f - freq);
 315 
 316                                 /*
 317                                  * If this is the closest we've come to the
 318                                  * target frequency then remember n, m and k
 319                                  */
 320                                 if (error < best_error) {
 321                                         best_error = error;
 322                                         best_n = n;
 323                                         best_m = m;
 324                                         best_k = k;
 325                                 }
 326                         }
 327                 }
 328         }
 329 
 330         n = best_n;
 331         m = best_m;
 332         k = best_k;
 333         *freq_out = (fref * (n + 2) / (m + 2)) >> k;
 334 
 335         return (n << 8) | (m << 2) | k;
 336 }
 337 
 338 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
 339 {
 340         struct tdfx_par *par = info->par;
 341         int i;
 342 
 343         banshee_wait_idle(info);
 344 
 345         tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
 346 
 347         crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
 348 
 349         banshee_make_room(par, 3);
 350         tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
 351         tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
 352 #if 0
 353         tdfx_outl(par, PLLCTRL1, reg->mempll);
 354         tdfx_outl(par, PLLCTRL2, reg->gfxpll);
 355 #endif
 356         tdfx_outl(par, PLLCTRL0, reg->vidpll);
 357 
 358         vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
 359 
 360         for (i = 0; i < 5; i++)
 361                 seq_outb(par, i, reg->seq[i]);
 362 
 363         for (i = 0; i < 25; i++)
 364                 crt_outb(par, i, reg->crt[i]);
 365 
 366         for (i = 0; i < 9; i++)
 367                 gra_outb(par, i, reg->gra[i]);
 368 
 369         for (i = 0; i < 21; i++)
 370                 att_outb(par, i, reg->att[i]);
 371 
 372         crt_outb(par, 0x1a, reg->ext[0]);
 373         crt_outb(par, 0x1b, reg->ext[1]);
 374 
 375         vga_enable_palette(par);
 376         vga_enable_video(par);
 377 
 378         banshee_make_room(par, 9);
 379         tdfx_outl(par, VGAINIT0, reg->vgainit0);
 380         tdfx_outl(par, DACMODE, reg->dacmode);
 381         tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
 382         tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
 383 
 384         tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
 385         tdfx_outl(par, VIDDESKSTART, reg->startaddr);
 386         tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
 387         tdfx_outl(par, VGAINIT1, reg->vgainit1);
 388         tdfx_outl(par, MISCINIT0, reg->miscinit0);
 389 
 390         banshee_make_room(par, 8);
 391         tdfx_outl(par, SRCBASE, reg->startaddr);
 392         tdfx_outl(par, DSTBASE, reg->startaddr);
 393         tdfx_outl(par, COMMANDEXTRA_2D, 0);
 394         tdfx_outl(par, CLIP0MIN, 0);
 395         tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
 396         tdfx_outl(par, CLIP1MIN, 0);
 397         tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
 398         tdfx_outl(par, SRCXY, 0);
 399 
 400         banshee_wait_idle(info);
 401 }
 402 
 403 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
 404 {
 405         u32 draminit0 = tdfx_inl(par, DRAMINIT0);
 406         u32 draminit1 = tdfx_inl(par, DRAMINIT1);
 407         u32 miscinit1;
 408         int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
 409         int chip_size; /* in MB */
 410         int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
 411 
 412         if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
 413                 /* Banshee/Voodoo3 */
 414                 chip_size = 2;
 415                 if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE))
 416                         chip_size = 1;
 417         } else {
 418                 /* Voodoo4/5 */
 419                 has_sgram = 0;
 420                 chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
 421                 chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
 422         }
 423 
 424         /* disable block writes for SDRAM */
 425         miscinit1 = tdfx_inl(par, MISCINIT1);
 426         miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
 427         miscinit1 |= MISCINIT1_CLUT_INV;
 428 
 429         banshee_make_room(par, 1);
 430         tdfx_outl(par, MISCINIT1, miscinit1);
 431         return num_chips * chip_size * 1024l * 1024;
 432 }
 433 
 434 /* ------------------------------------------------------------------------- */
 435 
 436 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 437 {
 438         struct tdfx_par *par = info->par;
 439         u32 lpitch;
 440 
 441         if (var->bits_per_pixel != 8  && var->bits_per_pixel != 16 &&
 442             var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
 443                 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 444                 return -EINVAL;
 445         }
 446 
 447         if (var->xres != var->xres_virtual)
 448                 var->xres_virtual = var->xres;
 449 
 450         if (var->yres > var->yres_virtual)
 451                 var->yres_virtual = var->yres;
 452 
 453         if (var->xoffset) {
 454                 DPRINTK("xoffset not supported\n");
 455                 return -EINVAL;
 456         }
 457         var->yoffset = 0;
 458 
 459         /*
 460          * Banshee doesn't support interlace, but Voodoo4/5 and probably
 461          * Voodoo3 do.
 462          * no direct information about device id now?
 463          *  use max_pixclock for this...
 464          */
 465         if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
 466             (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
 467                 DPRINTK("interlace not supported\n");
 468                 return -EINVAL;
 469         }
 470 
 471         if (info->monspecs.hfmax && info->monspecs.vfmax &&
 472             info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) {
 473                 DPRINTK("mode outside monitor's specs\n");
 474                 return -EINVAL;
 475         }
 476 
 477         var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
 478         lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
 479 
 480         if (var->xres < 320 || var->xres > 2048) {
 481                 DPRINTK("width not supported: %u\n", var->xres);
 482                 return -EINVAL;
 483         }
 484 
 485         if (var->yres < 200 || var->yres > 2048) {
 486                 DPRINTK("height not supported: %u\n", var->yres);
 487                 return -EINVAL;
 488         }
 489 
 490         if (lpitch * var->yres_virtual > info->fix.smem_len) {
 491                 var->yres_virtual = info->fix.smem_len / lpitch;
 492                 if (var->yres_virtual < var->yres) {
 493                         DPRINTK("no memory for screen (%ux%ux%u)\n",
 494                                 var->xres, var->yres_virtual,
 495                                 var->bits_per_pixel);
 496                         return -EINVAL;
 497                 }
 498         }
 499 
 500         if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
 501                 DPRINTK("pixclock too high (%ldKHz)\n",
 502                         PICOS2KHZ(var->pixclock));
 503                 return -EINVAL;
 504         }
 505 
 506         var->transp.offset = 0;
 507         var->transp.length = 0;
 508         switch (var->bits_per_pixel) {
 509         case 8:
 510                 var->red.length = 8;
 511                 var->red.offset = 0;
 512                 var->green = var->red;
 513                 var->blue = var->red;
 514                 break;
 515         case 16:
 516                 var->red.offset   = 11;
 517                 var->red.length   = 5;
 518                 var->green.offset = 5;
 519                 var->green.length = 6;
 520                 var->blue.offset  = 0;
 521                 var->blue.length  = 5;
 522                 break;
 523         case 32:
 524                 var->transp.offset = 24;
 525                 var->transp.length = 8;
 526                 /* fall through */
 527         case 24:
 528                 var->red.offset = 16;
 529                 var->green.offset = 8;
 530                 var->blue.offset = 0;
 531                 var->red.length = var->green.length = var->blue.length = 8;
 532                 break;
 533         }
 534         var->width = -1;
 535         var->height = -1;
 536 
 537         var->accel_flags = FB_ACCELF_TEXT;
 538 
 539         DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 540                 var->xres, var->yres, var->bits_per_pixel);
 541         return 0;
 542 }
 543 
 544 static int tdfxfb_set_par(struct fb_info *info)
 545 {
 546         struct tdfx_par *par = info->par;
 547         u32 hdispend = info->var.xres;
 548         u32 hsyncsta = hdispend + info->var.right_margin;
 549         u32 hsyncend = hsyncsta + info->var.hsync_len;
 550         u32 htotal   = hsyncend + info->var.left_margin;
 551         u32 hd, hs, he, ht, hbs, hbe;
 552         u32 vd, vs, ve, vt, vbs, vbe;
 553         struct banshee_reg reg;
 554         int fout, freq;
 555         u32 wd;
 556         u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
 557 
 558         memset(&reg, 0, sizeof(reg));
 559 
 560         reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
 561                      VIDCFG_CURS_X11 |
 562                      ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) |
 563                      (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
 564 
 565         /* PLL settings */
 566         freq = PICOS2KHZ(info->var.pixclock);
 567 
 568         reg.vidcfg &= ~VIDCFG_2X;
 569 
 570         if (freq > par->max_pixclock / 2) {
 571                 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
 572                 reg.dacmode |= DACMODE_2X;
 573                 reg.vidcfg  |= VIDCFG_2X;
 574                 hdispend >>= 1;
 575                 hsyncsta >>= 1;
 576                 hsyncend >>= 1;
 577                 htotal   >>= 1;
 578         }
 579 
 580         wd = (hdispend >> 3) - 1;
 581         hd  = wd;
 582         hs  = (hsyncsta >> 3) - 1;
 583         he  = (hsyncend >> 3) - 1;
 584         ht  = (htotal >> 3) - 1;
 585         hbs = hd;
 586         hbe = ht;
 587 
 588         if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
 589                 vd = (info->var.yres << 1) - 1;
 590                 vs  = vd + (info->var.lower_margin << 1);
 591                 ve  = vs + (info->var.vsync_len << 1);
 592                 vt = ve + (info->var.upper_margin << 1) - 1;
 593                 reg.screensize = info->var.xres | (info->var.yres << 13);
 594                 reg.vidcfg |= VIDCFG_HALF_MODE;
 595                 reg.crt[0x09] = 0x80;
 596         } else {
 597                 vd = info->var.yres - 1;
 598                 vs  = vd + info->var.lower_margin;
 599                 ve  = vs + info->var.vsync_len;
 600                 vt = ve + info->var.upper_margin - 1;
 601                 reg.screensize = info->var.xres | (info->var.yres << 12);
 602                 reg.vidcfg &= ~VIDCFG_HALF_MODE;
 603         }
 604         vbs = vd;
 605         vbe = vt;
 606 
 607         /* this is all pretty standard VGA register stuffing */
 608         reg.misc[0x00] = 0x0f |
 609                         (info->var.xres < 400 ? 0xa0 :
 610                          info->var.xres < 480 ? 0x60 :
 611                          info->var.xres < 768 ? 0xe0 : 0x20);
 612 
 613         reg.gra[0x05] = 0x40;
 614         reg.gra[0x06] = 0x05;
 615         reg.gra[0x07] = 0x0f;
 616         reg.gra[0x08] = 0xff;
 617 
 618         reg.att[0x00] = 0x00;
 619         reg.att[0x01] = 0x01;
 620         reg.att[0x02] = 0x02;
 621         reg.att[0x03] = 0x03;
 622         reg.att[0x04] = 0x04;
 623         reg.att[0x05] = 0x05;
 624         reg.att[0x06] = 0x06;
 625         reg.att[0x07] = 0x07;
 626         reg.att[0x08] = 0x08;
 627         reg.att[0x09] = 0x09;
 628         reg.att[0x0a] = 0x0a;
 629         reg.att[0x0b] = 0x0b;
 630         reg.att[0x0c] = 0x0c;
 631         reg.att[0x0d] = 0x0d;
 632         reg.att[0x0e] = 0x0e;
 633         reg.att[0x0f] = 0x0f;
 634         reg.att[0x10] = 0x41;
 635         reg.att[0x12] = 0x0f;
 636 
 637         reg.seq[0x00] = 0x03;
 638         reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
 639         reg.seq[0x02] = 0x0f;
 640         reg.seq[0x03] = 0x00;
 641         reg.seq[0x04] = 0x0e;
 642 
 643         reg.crt[0x00] = ht - 4;
 644         reg.crt[0x01] = hd;
 645         reg.crt[0x02] = hbs;
 646         reg.crt[0x03] = 0x80 | (hbe & 0x1f);
 647         reg.crt[0x04] = hs;
 648         reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
 649         reg.crt[0x06] = vt;
 650         reg.crt[0x07] = ((vs & 0x200) >> 2) |
 651                         ((vd & 0x200) >> 3) |
 652                         ((vt & 0x200) >> 4) | 0x10 |
 653                         ((vbs & 0x100) >> 5) |
 654                         ((vs & 0x100) >> 6) |
 655                         ((vd & 0x100) >> 7) |
 656                         ((vt & 0x100) >> 8);
 657         reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
 658         reg.crt[0x10] = vs;
 659         reg.crt[0x11] = (ve & 0x0f) | 0x20;
 660         reg.crt[0x12] = vd;
 661         reg.crt[0x13] = wd;
 662         reg.crt[0x15] = vbs;
 663         reg.crt[0x16] = vbe + 1;
 664         reg.crt[0x17] = 0xc3;
 665         reg.crt[0x18] = 0xff;
 666 
 667         /* Banshee's nonvga stuff */
 668         reg.ext[0x00] = (((ht & 0x100) >> 8) |
 669                         ((hd & 0x100) >> 6) |
 670                         ((hbs & 0x100) >> 4) |
 671                         ((hbe & 0x40) >> 1) |
 672                         ((hs & 0x100) >> 2) |
 673                         ((he & 0x20) << 2));
 674         reg.ext[0x01] = (((vt & 0x400) >> 10) |
 675                         ((vd & 0x400) >> 8) |
 676                         ((vbs & 0x400) >> 6) |
 677                         ((vbe & 0x400) >> 4));
 678 
 679         reg.vgainit0 =  VGAINIT0_8BIT_DAC     |
 680                         VGAINIT0_EXT_ENABLE   |
 681                         VGAINIT0_WAKEUP_3C3   |
 682                         VGAINIT0_ALT_READBACK |
 683                         VGAINIT0_EXTSHIFTOUT;
 684         reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
 685 
 686         if (hwcursor)
 687                 reg.curspataddr = info->fix.smem_len;
 688 
 689         reg.cursloc   = 0;
 690 
 691         reg.cursc0    = 0;
 692         reg.cursc1    = 0xffffff;
 693 
 694         reg.stride    = info->var.xres * cpp;
 695         reg.startaddr = info->var.yoffset * reg.stride
 696                         + info->var.xoffset * cpp;
 697 
 698         reg.vidpll = do_calc_pll(freq, &fout);
 699 #if 0
 700         reg.mempll = do_calc_pll(..., &fout);
 701         reg.gfxpll = do_calc_pll(..., &fout);
 702 #endif
 703 
 704         if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
 705                 reg.vidcfg |= VIDCFG_INTERLACE;
 706         reg.miscinit0 = tdfx_inl(par, MISCINIT0);
 707 
 708 #if defined(__BIG_ENDIAN)
 709         switch (info->var.bits_per_pixel) {
 710         case 8:
 711         case 24:
 712                 reg.miscinit0 &= ~(1 << 30);
 713                 reg.miscinit0 &= ~(1 << 31);
 714                 break;
 715         case 16:
 716                 reg.miscinit0 |= (1 << 30);
 717                 reg.miscinit0 |= (1 << 31);
 718                 break;
 719         case 32:
 720                 reg.miscinit0 |= (1 << 30);
 721                 reg.miscinit0 &= ~(1 << 31);
 722                 break;
 723         }
 724 #endif
 725         do_write_regs(info, &reg);
 726 
 727         /* Now change fb_fix_screeninfo according to changes in par */
 728         info->fix.line_length = reg.stride;
 729         info->fix.visual = (info->var.bits_per_pixel == 8)
 730                                 ? FB_VISUAL_PSEUDOCOLOR
 731                                 : FB_VISUAL_TRUECOLOR;
 732         DPRINTK("Graphics mode is now set at %dx%d depth %d\n",
 733                 info->var.xres, info->var.yres, info->var.bits_per_pixel);
 734         return 0;
 735 }
 736 
 737 /* A handy macro shamelessly pinched from matroxfb */
 738 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
 739 
 740 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 741                             unsigned blue, unsigned transp,
 742                             struct fb_info *info)
 743 {
 744         struct tdfx_par *par = info->par;
 745         u32 rgbcol;
 746 
 747         if (regno >= info->cmap.len || regno > 255)
 748                 return 1;
 749 
 750         /* grayscale works only partially under directcolor */
 751         if (info->var.grayscale) {
 752                 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
 753                 blue = (red * 77 + green * 151 + blue * 28) >> 8;
 754                 green = blue;
 755                 red = blue;
 756         }
 757 
 758         switch (info->fix.visual) {
 759         case FB_VISUAL_PSEUDOCOLOR:
 760                 rgbcol = (((u32)red   & 0xff00) << 8) |
 761                          (((u32)green & 0xff00) << 0) |
 762                          (((u32)blue  & 0xff00) >> 8);
 763                 do_setpalentry(par, regno, rgbcol);
 764                 break;
 765         /* Truecolor has no hardware color palettes. */
 766         case FB_VISUAL_TRUECOLOR:
 767                 if (regno < 16) {
 768                         rgbcol = (CNVT_TOHW(red, info->var.red.length) <<
 769                                   info->var.red.offset) |
 770                                 (CNVT_TOHW(green, info->var.green.length) <<
 771                                  info->var.green.offset) |
 772                                 (CNVT_TOHW(blue, info->var.blue.length) <<
 773                                  info->var.blue.offset) |
 774                                 (CNVT_TOHW(transp, info->var.transp.length) <<
 775                                  info->var.transp.offset);
 776                         par->palette[regno] = rgbcol;
 777                 }
 778 
 779                 break;
 780         default:
 781                 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
 782                 break;
 783         }
 784 
 785         return 0;
 786 }
 787 
 788 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
 789 static int tdfxfb_blank(int blank, struct fb_info *info)
 790 {
 791         struct tdfx_par *par = info->par;
 792         int vgablank = 1;
 793         u32 dacmode = tdfx_inl(par, DACMODE);
 794 
 795         dacmode &= ~(BIT(1) | BIT(3));
 796 
 797         switch (blank) {
 798         case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
 799                 vgablank = 0;
 800                 break;
 801         case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
 802                 break;
 803         case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
 804                 dacmode |= BIT(3);
 805                 break;
 806         case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
 807                 dacmode |= BIT(1);
 808                 break;
 809         case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
 810                 dacmode |= BIT(1) | BIT(3);
 811                 break;
 812         }
 813 
 814         banshee_make_room(par, 1);
 815         tdfx_outl(par, DACMODE, dacmode);
 816         if (vgablank)
 817                 vga_disable_video(par);
 818         else
 819                 vga_enable_video(par);
 820         return 0;
 821 }
 822 
 823 /*
 824  * Set the starting position of the visible screen to var->yoffset
 825  */
 826 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
 827                               struct fb_info *info)
 828 {
 829         struct tdfx_par *par = info->par;
 830         u32 addr = var->yoffset * info->fix.line_length;
 831 
 832         if (nopan || var->xoffset)
 833                 return -EINVAL;
 834 
 835         banshee_make_room(par, 1);
 836         tdfx_outl(par, VIDDESKSTART, addr);
 837 
 838         return 0;
 839 }
 840 
 841 #ifdef CONFIG_FB_3DFX_ACCEL
 842 /*
 843  * FillRect 2D command (solidfill or invert (via ROP_XOR))
 844  */
 845 static void tdfxfb_fillrect(struct fb_info *info,
 846                             const struct fb_fillrect *rect)
 847 {
 848         struct tdfx_par *par = info->par;
 849         u32 bpp = info->var.bits_per_pixel;
 850         u32 stride = info->fix.line_length;
 851         u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 852         int tdfx_rop;
 853         u32 dx = rect->dx;
 854         u32 dy = rect->dy;
 855         u32 dstbase = 0;
 856 
 857         if (rect->rop == ROP_COPY)
 858                 tdfx_rop = TDFX_ROP_COPY;
 859         else
 860                 tdfx_rop = TDFX_ROP_XOR;
 861 
 862         /* assume always rect->height < 4096 */
 863         if (dy + rect->height > 4095) {
 864                 dstbase = stride * dy;
 865                 dy = 0;
 866         }
 867         /* assume always rect->width < 4096 */
 868         if (dx + rect->width > 4095) {
 869                 dstbase += dx * bpp >> 3;
 870                 dx = 0;
 871         }
 872         banshee_make_room(par, 6);
 873         tdfx_outl(par, DSTFORMAT, fmt);
 874         if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
 875                 tdfx_outl(par, COLORFORE, rect->color);
 876         } else { /* FB_VISUAL_TRUECOLOR */
 877                 tdfx_outl(par, COLORFORE, par->palette[rect->color]);
 878         }
 879         tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
 880         tdfx_outl(par, DSTBASE, dstbase);
 881         tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
 882         tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
 883 }
 884 
 885 /*
 886  * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
 887  */
 888 static void tdfxfb_copyarea(struct fb_info *info,
 889                             const struct fb_copyarea *area)
 890 {
 891         struct tdfx_par *par = info->par;
 892         u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
 893         u32 bpp = info->var.bits_per_pixel;
 894         u32 stride = info->fix.line_length;
 895         u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
 896         u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 897         u32 dstbase = 0;
 898         u32 srcbase = 0;
 899 
 900         /* assume always area->height < 4096 */
 901         if (sy + area->height > 4095) {
 902                 srcbase = stride * sy;
 903                 sy = 0;
 904         }
 905         /* assume always area->width < 4096 */
 906         if (sx + area->width > 4095) {
 907                 srcbase += sx * bpp >> 3;
 908                 sx = 0;
 909         }
 910         /* assume always area->height < 4096 */
 911         if (dy + area->height > 4095) {
 912                 dstbase = stride * dy;
 913                 dy = 0;
 914         }
 915         /* assume always area->width < 4096 */
 916         if (dx + area->width > 4095) {
 917                 dstbase += dx * bpp >> 3;
 918                 dx = 0;
 919         }
 920 
 921         if (area->sx <= area->dx) {
 922                 /* -X */
 923                 blitcmd |= BIT(14);
 924                 sx += area->width - 1;
 925                 dx += area->width - 1;
 926         }
 927         if (area->sy <= area->dy) {
 928                 /* -Y */
 929                 blitcmd |= BIT(15);
 930                 sy += area->height - 1;
 931                 dy += area->height - 1;
 932         }
 933 
 934         banshee_make_room(par, 8);
 935 
 936         tdfx_outl(par, SRCFORMAT, fmt);
 937         tdfx_outl(par, DSTFORMAT, fmt);
 938         tdfx_outl(par, COMMAND_2D, blitcmd);
 939         tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
 940         tdfx_outl(par, DSTXY, dx | (dy << 16));
 941         tdfx_outl(par, SRCBASE, srcbase);
 942         tdfx_outl(par, DSTBASE, dstbase);
 943         tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
 944 }
 945 
 946 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
 947 {
 948         struct tdfx_par *par = info->par;
 949         int size = image->height * ((image->width * image->depth + 7) >> 3);
 950         int fifo_free;
 951         int i, stride = info->fix.line_length;
 952         u32 bpp = info->var.bits_per_pixel;
 953         u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 954         u8 *chardata = (u8 *) image->data;
 955         u32 srcfmt;
 956         u32 dx = image->dx;
 957         u32 dy = image->dy;
 958         u32 dstbase = 0;
 959 
 960         if (image->depth != 1) {
 961 #ifdef BROKEN_CODE
 962                 banshee_make_room(par, 6 + ((size + 3) >> 2));
 963                 srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) |
 964                         0x400000;
 965 #else
 966                 cfb_imageblit(info, image);
 967 #endif
 968                 return;
 969         }
 970         banshee_make_room(par, 9);
 971         switch (info->fix.visual) {
 972         case FB_VISUAL_PSEUDOCOLOR:
 973                 tdfx_outl(par, COLORFORE, image->fg_color);
 974                 tdfx_outl(par, COLORBACK, image->bg_color);
 975                 break;
 976         case FB_VISUAL_TRUECOLOR:
 977         default:
 978                 tdfx_outl(par, COLORFORE,
 979                           par->palette[image->fg_color]);
 980                 tdfx_outl(par, COLORBACK,
 981                           par->palette[image->bg_color]);
 982         }
 983 #ifdef __BIG_ENDIAN
 984         srcfmt = 0x400000 | BIT(20);
 985 #else
 986         srcfmt = 0x400000;
 987 #endif
 988         /* assume always image->height < 4096 */
 989         if (dy + image->height > 4095) {
 990                 dstbase = stride * dy;
 991                 dy = 0;
 992         }
 993         /* assume always image->width < 4096 */
 994         if (dx + image->width > 4095) {
 995                 dstbase += dx * bpp >> 3;
 996                 dx = 0;
 997         }
 998 
 999         tdfx_outl(par, DSTBASE, dstbase);
1000         tdfx_outl(par, SRCXY, 0);
1001         tdfx_outl(par, DSTXY, dx | (dy << 16));
1002         tdfx_outl(par, COMMAND_2D,
1003                   COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
1004         tdfx_outl(par, SRCFORMAT, srcfmt);
1005         tdfx_outl(par, DSTFORMAT, dstfmt);
1006         tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1007 
1008         /* A count of how many free FIFO entries we've requested.
1009          * When this goes negative, we need to request more. */
1010         fifo_free = 0;
1011 
1012         /* Send four bytes at a time of data */
1013         for (i = (size >> 2); i > 0; i--) {
1014                 if (--fifo_free < 0) {
1015                         fifo_free = 31;
1016                         banshee_make_room(par, fifo_free);
1017                 }
1018                 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
1019                 chardata += 4;
1020         }
1021 
1022         /* Send the leftovers now */
1023         banshee_make_room(par, 3);
1024         switch (size % 4) {
1025         case 0:
1026                 break;
1027         case 1:
1028                 tdfx_outl(par, LAUNCH_2D, *chardata);
1029                 break;
1030         case 2:
1031                 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
1032                 break;
1033         case 3:
1034                 tdfx_outl(par, LAUNCH_2D,
1035                         *(u16 *)chardata | (chardata[3] << 24));
1036                 break;
1037         }
1038 }
1039 #endif /* CONFIG_FB_3DFX_ACCEL */
1040 
1041 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1042 {
1043         struct tdfx_par *par = info->par;
1044         u32 vidcfg;
1045 
1046         if (!hwcursor)
1047                 return -EINVAL; /* just to force soft_cursor() call */
1048 
1049         /* Too large of a cursor or wrong bpp :-( */
1050         if (cursor->image.width > 64 ||
1051             cursor->image.height > 64 ||
1052             cursor->image.depth > 1)
1053                 return -EINVAL;
1054 
1055         vidcfg = tdfx_inl(par, VIDPROCCFG);
1056         if (cursor->enable)
1057                 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
1058         else
1059                 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
1060 
1061         /*
1062          * If the cursor is not be changed this means either we want the
1063          * current cursor state (if enable is set) or we want to query what
1064          * we can do with the cursor (if enable is not set)
1065          */
1066         if (!cursor->set)
1067                 return 0;
1068 
1069         /* fix cursor color - XFree86 forgets to restore it properly */
1070         if (cursor->set & FB_CUR_SETCMAP) {
1071                 struct fb_cmap cmap = info->cmap;
1072                 u32 bg_idx = cursor->image.bg_color;
1073                 u32 fg_idx = cursor->image.fg_color;
1074                 unsigned long bg_color, fg_color;
1075 
1076                 fg_color = (((u32)cmap.red[fg_idx]   & 0xff00) << 8) |
1077                            (((u32)cmap.green[fg_idx] & 0xff00) << 0) |
1078                            (((u32)cmap.blue[fg_idx]  & 0xff00) >> 8);
1079                 bg_color = (((u32)cmap.red[bg_idx]   & 0xff00) << 8) |
1080                            (((u32)cmap.green[bg_idx] & 0xff00) << 0) |
1081                            (((u32)cmap.blue[bg_idx]  & 0xff00) >> 8);
1082                 banshee_make_room(par, 2);
1083                 tdfx_outl(par, HWCURC0, bg_color);
1084                 tdfx_outl(par, HWCURC1, fg_color);
1085         }
1086 
1087         if (cursor->set & FB_CUR_SETPOS) {
1088                 int x = cursor->image.dx;
1089                 int y = cursor->image.dy - info->var.yoffset;
1090 
1091                 x += 63;
1092                 y += 63;
1093                 banshee_make_room(par, 1);
1094                 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1095         }
1096         if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
1097                 /*
1098                  * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1099                  *    The reason is so the card can fetch 8 words at a time
1100                  * and are stored on chip for use for the next 8 scanlines.
1101                  * This reduces the number of times for access to draw the
1102                  * cursor for each screen refresh.
1103                  *    Each pattern is a bitmap of 64 bit wide and 64 bit high
1104                  * (total of 8192 bits or 1024 bytes). The two patterns are
1105                  * stored in such a way that pattern 0 always resides in the
1106                  * lower half (least significant 64 bits) of a 128 bit word
1107                  * and pattern 1 the upper half. If you examine the data of
1108                  * the cursor image the graphics card uses then from the
1109                  * beginning you see line one of pattern 0, line one of
1110                  * pattern 1, line two of pattern 0, line two of pattern 1,
1111                  * etc etc. The linear stride for the cursor is always 16 bytes
1112                  * (128 bits) which is the maximum cursor width times two for
1113                  * the two monochrome patterns.
1114                  */
1115                 u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len;
1116                 u8 *bitmap = (u8 *)cursor->image.data;
1117                 u8 *mask = (u8 *)cursor->mask;
1118                 int i;
1119 
1120                 fb_memset(cursorbase, 0, 1024);
1121 
1122                 for (i = 0; i < cursor->image.height; i++) {
1123                         int h = 0;
1124                         int j = (cursor->image.width + 7) >> 3;
1125 
1126                         for (; j > 0; j--) {
1127                                 u8 data = *mask ^ *bitmap;
1128                                 if (cursor->rop == ROP_COPY)
1129                                         data = *mask & *bitmap;
1130                                 /* Pattern 0. Copy the cursor mask to it */
1131                                 fb_writeb(*mask, cursorbase + h);
1132                                 mask++;
1133                                 /* Pattern 1. Copy the cursor bitmap to it */
1134                                 fb_writeb(data, cursorbase + h + 8);
1135                                 bitmap++;
1136                                 h++;
1137                         }
1138                         cursorbase += 16;
1139                 }
1140         }
1141         return 0;
1142 }
1143 
1144 static struct fb_ops tdfxfb_ops = {
1145         .owner          = THIS_MODULE,
1146         .fb_check_var   = tdfxfb_check_var,
1147         .fb_set_par     = tdfxfb_set_par,
1148         .fb_setcolreg   = tdfxfb_setcolreg,
1149         .fb_blank       = tdfxfb_blank,
1150         .fb_pan_display = tdfxfb_pan_display,
1151         .fb_sync        = banshee_wait_idle,
1152         .fb_cursor      = tdfxfb_cursor,
1153 #ifdef CONFIG_FB_3DFX_ACCEL
1154         .fb_fillrect    = tdfxfb_fillrect,
1155         .fb_copyarea    = tdfxfb_copyarea,
1156         .fb_imageblit   = tdfxfb_imageblit,
1157 #else
1158         .fb_fillrect    = cfb_fillrect,
1159         .fb_copyarea    = cfb_copyarea,
1160         .fb_imageblit   = cfb_imageblit,
1161 #endif
1162 };
1163 
1164 #ifdef CONFIG_FB_3DFX_I2C
1165 /* The voo GPIO registers don't have individual masks for each bit
1166    so we always have to read before writing. */
1167 
1168 static void tdfxfb_i2c_setscl(void *data, int val)
1169 {
1170         struct tdfxfb_i2c_chan  *chan = data;
1171         struct tdfx_par         *par = chan->par;
1172         unsigned int r;
1173 
1174         r = tdfx_inl(par, VIDSERPARPORT);
1175         if (val)
1176                 r |= I2C_SCL_OUT;
1177         else
1178                 r &= ~I2C_SCL_OUT;
1179         tdfx_outl(par, VIDSERPARPORT, r);
1180         tdfx_inl(par, VIDSERPARPORT);   /* flush posted write */
1181 }
1182 
1183 static void tdfxfb_i2c_setsda(void *data, int val)
1184 {
1185         struct tdfxfb_i2c_chan  *chan = data;
1186         struct tdfx_par         *par = chan->par;
1187         unsigned int r;
1188 
1189         r = tdfx_inl(par, VIDSERPARPORT);
1190         if (val)
1191                 r |= I2C_SDA_OUT;
1192         else
1193                 r &= ~I2C_SDA_OUT;
1194         tdfx_outl(par, VIDSERPARPORT, r);
1195         tdfx_inl(par, VIDSERPARPORT);   /* flush posted write */
1196 }
1197 
1198 /* The GPIO pins are open drain, so the pins always remain outputs.
1199    We rely on the i2c-algo-bit routines to set the pins high before
1200    reading the input from other chips. */
1201 
1202 static int tdfxfb_i2c_getscl(void *data)
1203 {
1204         struct tdfxfb_i2c_chan  *chan = data;
1205         struct tdfx_par         *par = chan->par;
1206 
1207         return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
1208 }
1209 
1210 static int tdfxfb_i2c_getsda(void *data)
1211 {
1212         struct tdfxfb_i2c_chan  *chan = data;
1213         struct tdfx_par         *par = chan->par;
1214 
1215         return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
1216 }
1217 
1218 static void tdfxfb_ddc_setscl(void *data, int val)
1219 {
1220         struct tdfxfb_i2c_chan  *chan = data;
1221         struct tdfx_par         *par = chan->par;
1222         unsigned int r;
1223 
1224         r = tdfx_inl(par, VIDSERPARPORT);
1225         if (val)
1226                 r |= DDC_SCL_OUT;
1227         else
1228                 r &= ~DDC_SCL_OUT;
1229         tdfx_outl(par, VIDSERPARPORT, r);
1230         tdfx_inl(par, VIDSERPARPORT);   /* flush posted write */
1231 }
1232 
1233 static void tdfxfb_ddc_setsda(void *data, int val)
1234 {
1235         struct tdfxfb_i2c_chan  *chan = data;
1236         struct tdfx_par         *par = chan->par;
1237         unsigned int r;
1238 
1239         r = tdfx_inl(par, VIDSERPARPORT);
1240         if (val)
1241                 r |= DDC_SDA_OUT;
1242         else
1243                 r &= ~DDC_SDA_OUT;
1244         tdfx_outl(par, VIDSERPARPORT, r);
1245         tdfx_inl(par, VIDSERPARPORT);   /* flush posted write */
1246 }
1247 
1248 static int tdfxfb_ddc_getscl(void *data)
1249 {
1250         struct tdfxfb_i2c_chan  *chan = data;
1251         struct tdfx_par         *par = chan->par;
1252 
1253         return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
1254 }
1255 
1256 static int tdfxfb_ddc_getsda(void *data)
1257 {
1258         struct tdfxfb_i2c_chan  *chan = data;
1259         struct tdfx_par         *par = chan->par;
1260 
1261         return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
1262 }
1263 
1264 static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name,
1265                                 struct device *dev)
1266 {
1267         int rc;
1268 
1269         strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1270         chan->adapter.owner             = THIS_MODULE;
1271         chan->adapter.class             = I2C_CLASS_DDC;
1272         chan->adapter.algo_data         = &chan->algo;
1273         chan->adapter.dev.parent        = dev;
1274         chan->algo.setsda               = tdfxfb_ddc_setsda;
1275         chan->algo.setscl               = tdfxfb_ddc_setscl;
1276         chan->algo.getsda               = tdfxfb_ddc_getsda;
1277         chan->algo.getscl               = tdfxfb_ddc_getscl;
1278         chan->algo.udelay               = 10;
1279         chan->algo.timeout              = msecs_to_jiffies(500);
1280         chan->algo.data                 = chan;
1281 
1282         i2c_set_adapdata(&chan->adapter, chan);
1283 
1284         rc = i2c_bit_add_bus(&chan->adapter);
1285         if (rc == 0)
1286                 DPRINTK("I2C bus %s registered.\n", name);
1287         else
1288                 chan->par = NULL;
1289 
1290         return rc;
1291 }
1292 
1293 static int tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, const char *name,
1294                                 struct device *dev)
1295 {
1296         int rc;
1297 
1298         strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1299         chan->adapter.owner             = THIS_MODULE;
1300         chan->adapter.algo_data         = &chan->algo;
1301         chan->adapter.dev.parent        = dev;
1302         chan->algo.setsda               = tdfxfb_i2c_setsda;
1303         chan->algo.setscl               = tdfxfb_i2c_setscl;
1304         chan->algo.getsda               = tdfxfb_i2c_getsda;
1305         chan->algo.getscl               = tdfxfb_i2c_getscl;
1306         chan->algo.udelay               = 10;
1307         chan->algo.timeout              = msecs_to_jiffies(500);
1308         chan->algo.data                 = chan;
1309 
1310         i2c_set_adapdata(&chan->adapter, chan);
1311 
1312         rc = i2c_bit_add_bus(&chan->adapter);
1313         if (rc == 0)
1314                 DPRINTK("I2C bus %s registered.\n", name);
1315         else
1316                 chan->par = NULL;
1317 
1318         return rc;
1319 }
1320 
1321 static void tdfxfb_create_i2c_busses(struct fb_info *info)
1322 {
1323         struct tdfx_par *par = info->par;
1324 
1325         tdfx_outl(par, VIDINFORMAT, 0x8160);
1326         tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
1327 
1328         par->chan[0].par = par;
1329         par->chan[1].par = par;
1330 
1331         tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->dev);
1332         tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->dev);
1333 }
1334 
1335 static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
1336 {
1337         if (par->chan[0].par)
1338                 i2c_del_adapter(&par->chan[0].adapter);
1339         par->chan[0].par = NULL;
1340 
1341         if (par->chan[1].par)
1342                 i2c_del_adapter(&par->chan[1].adapter);
1343         par->chan[1].par = NULL;
1344 }
1345 
1346 static int tdfxfb_probe_i2c_connector(struct tdfx_par *par,
1347                                       struct fb_monspecs *specs)
1348 {
1349         u8 *edid = NULL;
1350 
1351         DPRINTK("Probe DDC Bus\n");
1352         if (par->chan[0].par)
1353                 edid = fb_ddc_read(&par->chan[0].adapter);
1354 
1355         if (edid) {
1356                 fb_edid_to_monspecs(edid, specs);
1357                 kfree(edid);
1358                 return 0;
1359         }
1360         return 1;
1361 }
1362 #endif /* CONFIG_FB_3DFX_I2C */
1363 
1364 /**
1365  *      tdfxfb_probe - Device Initializiation
1366  *
1367  *      @pdev:  PCI Device to initialize
1368  *      @id:    PCI Device ID
1369  *
1370  *      Initializes and allocates resources for PCI device @pdev.
1371  *
1372  */
1373 static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1374 {
1375         struct tdfx_par *default_par;
1376         struct fb_info *info;
1377         int err, lpitch;
1378         struct fb_monspecs *specs;
1379         bool found;
1380 
1381         err = pci_enable_device(pdev);
1382         if (err) {
1383                 printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err);
1384                 return err;
1385         }
1386 
1387         info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
1388 
1389         if (!info)
1390                 return -ENOMEM;
1391 
1392         default_par = info->par;
1393         info->fix = tdfx_fix;
1394 
1395         /* Configure the default fb_fix_screeninfo first */
1396         switch (pdev->device) {
1397         case PCI_DEVICE_ID_3DFX_BANSHEE:
1398                 strcpy(info->fix.id, "3Dfx Banshee");
1399                 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1400                 break;
1401         case PCI_DEVICE_ID_3DFX_VOODOO3:
1402                 strcpy(info->fix.id, "3Dfx Voodoo3");
1403                 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1404                 break;
1405         case PCI_DEVICE_ID_3DFX_VOODOO5:
1406                 strcpy(info->fix.id, "3Dfx Voodoo5");
1407                 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1408                 break;
1409         }
1410 
1411         info->fix.mmio_start = pci_resource_start(pdev, 0);
1412         info->fix.mmio_len = pci_resource_len(pdev, 0);
1413         if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len,
1414                                 "tdfx regbase")) {
1415                 printk(KERN_ERR "tdfxfb: Can't reserve regbase\n");
1416                 goto out_err;
1417         }
1418 
1419         default_par->regbase_virt =
1420                 ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
1421         if (!default_par->regbase_virt) {
1422                 printk(KERN_ERR "fb: Can't remap %s register area.\n",
1423                                 info->fix.id);
1424                 goto out_err_regbase;
1425         }
1426 
1427         info->fix.smem_start = pci_resource_start(pdev, 1);
1428         info->fix.smem_len = do_lfb_size(default_par, pdev->device);
1429         if (!info->fix.smem_len) {
1430                 printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id);
1431                 goto out_err_regbase;
1432         }
1433 
1434         if (!request_mem_region(info->fix.smem_start,
1435                                 pci_resource_len(pdev, 1), "tdfx smem")) {
1436                 printk(KERN_ERR "tdfxfb: Can't reserve smem\n");
1437                 goto out_err_regbase;
1438         }
1439 
1440         info->screen_base = ioremap_wc(info->fix.smem_start,
1441                                        info->fix.smem_len);
1442         if (!info->screen_base) {
1443                 printk(KERN_ERR "fb: Can't remap %s framebuffer.\n",
1444                                 info->fix.id);
1445                 goto out_err_screenbase;
1446         }
1447 
1448         default_par->iobase = pci_resource_start(pdev, 2);
1449 
1450         if (!request_region(pci_resource_start(pdev, 2),
1451                             pci_resource_len(pdev, 2), "tdfx iobase")) {
1452                 printk(KERN_ERR "tdfxfb: Can't reserve iobase\n");
1453                 goto out_err_screenbase;
1454         }
1455 
1456         printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id,
1457                         info->fix.smem_len >> 10);
1458 
1459         if (!nomtrr)
1460                 default_par->wc_cookie= arch_phys_wc_add(info->fix.smem_start,
1461                                                          info->fix.smem_len);
1462 
1463         info->fix.ypanstep      = nopan ? 0 : 1;
1464         info->fix.ywrapstep     = nowrap ? 0 : 1;
1465 
1466         info->fbops             = &tdfxfb_ops;
1467         info->pseudo_palette    = default_par->palette;
1468         info->flags             = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1469 #ifdef CONFIG_FB_3DFX_ACCEL
1470         info->flags             |= FBINFO_HWACCEL_FILLRECT |
1471                                    FBINFO_HWACCEL_COPYAREA |
1472                                    FBINFO_HWACCEL_IMAGEBLIT |
1473                                    FBINFO_READS_FAST;
1474 #endif
1475         /* reserve 8192 bits for cursor */
1476         /* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */
1477         if (hwcursor)
1478                 info->fix.smem_len = (info->fix.smem_len - 1024) &
1479                                         (PAGE_MASK << 1);
1480         specs = &info->monspecs;
1481         found = false;
1482         info->var.bits_per_pixel = 8;
1483 #ifdef CONFIG_FB_3DFX_I2C
1484         tdfxfb_create_i2c_busses(info);
1485         err = tdfxfb_probe_i2c_connector(default_par, specs);
1486 
1487         if (!err) {
1488                 if (specs->modedb == NULL)
1489                         DPRINTK("Unable to get Mode Database\n");
1490                 else {
1491                         const struct fb_videomode *m;
1492 
1493                         fb_videomode_to_modelist(specs->modedb,
1494                                                  specs->modedb_len,
1495                                                  &info->modelist);
1496                         m = fb_find_best_display(specs, &info->modelist);
1497                         if (m) {
1498                                 fb_videomode_to_var(&info->var, m);
1499                                 /* fill all other info->var's fields */
1500                                 if (tdfxfb_check_var(&info->var, info) < 0)
1501                                         info->var = tdfx_var;
1502                                 else
1503                                         found = true;
1504                         }
1505                 }
1506         }
1507 #endif
1508         if (!mode_option && !found)
1509                 mode_option = "640x480@60";
1510 
1511         if (mode_option) {
1512                 err = fb_find_mode(&info->var, info, mode_option,
1513                                    specs->modedb, specs->modedb_len,
1514                                    NULL, info->var.bits_per_pixel);
1515                 if (!err || err == 4)
1516                         info->var = tdfx_var;
1517         }
1518 
1519         if (found) {
1520                 fb_destroy_modedb(specs->modedb);
1521                 specs->modedb = NULL;
1522         }
1523 
1524         /* maximize virtual vertical length */
1525         lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1526         info->var.yres_virtual = info->fix.smem_len / lpitch;
1527         if (info->var.yres_virtual < info->var.yres)
1528                 goto out_err_iobase;
1529 
1530         if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1531                 printk(KERN_ERR "tdfxfb: Can't allocate color map\n");
1532                 goto out_err_iobase;
1533         }
1534 
1535         if (register_framebuffer(info) < 0) {
1536                 printk(KERN_ERR "tdfxfb: can't register framebuffer\n");
1537                 fb_dealloc_cmap(&info->cmap);
1538                 goto out_err_iobase;
1539         }
1540         /*
1541          * Our driver data
1542          */
1543         pci_set_drvdata(pdev, info);
1544         return 0;
1545 
1546 out_err_iobase:
1547 #ifdef CONFIG_FB_3DFX_I2C
1548         tdfxfb_delete_i2c_busses(default_par);
1549 #endif
1550         arch_phys_wc_del(default_par->wc_cookie);
1551         release_region(pci_resource_start(pdev, 2),
1552                        pci_resource_len(pdev, 2));
1553 out_err_screenbase:
1554         if (info->screen_base)
1555                 iounmap(info->screen_base);
1556         release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1));
1557 out_err_regbase:
1558         /*
1559          * Cleanup after anything that was remapped/allocated.
1560          */
1561         if (default_par->regbase_virt)
1562                 iounmap(default_par->regbase_virt);
1563         release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1564 out_err:
1565         framebuffer_release(info);
1566         return -ENXIO;
1567 }
1568 
1569 #ifndef MODULE
1570 static void __init tdfxfb_setup(char *options)
1571 {
1572         char *this_opt;
1573 
1574         if (!options || !*options)
1575                 return;
1576 
1577         while ((this_opt = strsep(&options, ",")) != NULL) {
1578                 if (!*this_opt)
1579                         continue;
1580                 if (!strcmp(this_opt, "nopan")) {
1581                         nopan = 1;
1582                 } else if (!strcmp(this_opt, "nowrap")) {
1583                         nowrap = 1;
1584                 } else if (!strncmp(this_opt, "hwcursor=", 9)) {
1585                         hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1586                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1587                         nomtrr = 1;
1588                 } else {
1589                         mode_option = this_opt;
1590                 }
1591         }
1592 }
1593 #endif
1594 
1595 /**
1596  *      tdfxfb_remove - Device removal
1597  *
1598  *      @pdev:  PCI Device to cleanup
1599  *
1600  *      Releases all resources allocated during the course of the driver's
1601  *      lifetime for the PCI device @pdev.
1602  *
1603  */
1604 static void tdfxfb_remove(struct pci_dev *pdev)
1605 {
1606         struct fb_info *info = pci_get_drvdata(pdev);
1607         struct tdfx_par *par = info->par;
1608 
1609         unregister_framebuffer(info);
1610 #ifdef CONFIG_FB_3DFX_I2C
1611         tdfxfb_delete_i2c_busses(par);
1612 #endif
1613         arch_phys_wc_del(par->wc_cookie);
1614         iounmap(par->regbase_virt);
1615         iounmap(info->screen_base);
1616 
1617         /* Clean up after reserved regions */
1618         release_region(pci_resource_start(pdev, 2),
1619                        pci_resource_len(pdev, 2));
1620         release_mem_region(pci_resource_start(pdev, 1),
1621                            pci_resource_len(pdev, 1));
1622         release_mem_region(pci_resource_start(pdev, 0),
1623                            pci_resource_len(pdev, 0));
1624         fb_dealloc_cmap(&info->cmap);
1625         framebuffer_release(info);
1626 }
1627 
1628 static int __init tdfxfb_init(void)
1629 {
1630 #ifndef MODULE
1631         char *option = NULL;
1632 
1633         if (fb_get_options("tdfxfb", &option))
1634                 return -ENODEV;
1635 
1636         tdfxfb_setup(option);
1637 #endif
1638         return pci_register_driver(&tdfxfb_driver);
1639 }
1640 
1641 static void __exit tdfxfb_exit(void)
1642 {
1643         pci_unregister_driver(&tdfxfb_driver);
1644 }
1645 
1646 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1647 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1648 MODULE_LICENSE("GPL");
1649 
1650 module_param(hwcursor, int, 0644);
1651 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1652                         "(1=enable, 0=disable, default=1)");
1653 module_param(mode_option, charp, 0);
1654 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1655 module_param(nomtrr, bool, 0);
1656 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)");
1657 
1658 module_init(tdfxfb_init);
1659 module_exit(tdfxfb_exit);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/video/fbdev/tdfxfb.c

DEFINITIONS
