drivers/video/fbdev/pxa168fb.h

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   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __PXA168FB_H__
   3 #define __PXA168FB_H__
   4 
   5 /* ------------< LCD register >------------ */
   6 /* Video Frame 0&1 start address registers */
   7 #define LCD_SPU_DMA_START_ADDR_Y0               0x00C0
   8 #define LCD_SPU_DMA_START_ADDR_U0               0x00C4
   9 #define LCD_SPU_DMA_START_ADDR_V0               0x00C8
  10 #define LCD_CFG_DMA_START_ADDR_0                0x00CC /* Cmd address */
  11 #define LCD_SPU_DMA_START_ADDR_Y1               0x00D0
  12 #define LCD_SPU_DMA_START_ADDR_U1               0x00D4
  13 #define LCD_SPU_DMA_START_ADDR_V1               0x00D8
  14 #define LCD_CFG_DMA_START_ADDR_1                0x00DC /* Cmd address */
  15 
  16 /* YC & UV Pitch */
  17 #define LCD_SPU_DMA_PITCH_YC                    0x00E0
  18 #define     SPU_DMA_PITCH_C(c)                  ((c) << 16)
  19 #define     SPU_DMA_PITCH_Y(y)                  (y)
  20 #define LCD_SPU_DMA_PITCH_UV                    0x00E4
  21 #define     SPU_DMA_PITCH_V(v)                  ((v) << 16)
  22 #define     SPU_DMA_PITCH_U(u)                  (u)
  23 
  24 /* Video Starting Point on Screen Register */
  25 #define LCD_SPUT_DMA_OVSA_HPXL_VLN              0x00E8
  26 #define     CFG_DMA_OVSA_VLN(y)                 ((y) << 16) /* 0~0xfff */
  27 #define     CFG_DMA_OVSA_HPXL(x)                (x)     /* 0~0xfff */
  28 
  29 /* Video Size Register */
  30 #define LCD_SPU_DMA_HPXL_VLN                    0x00EC
  31 #define     CFG_DMA_VLN(y)                      ((y) << 16)
  32 #define     CFG_DMA_HPXL(x)                     (x)
  33 
  34 /* Video Size After zooming Register */
  35 #define LCD_SPU_DZM_HPXL_VLN                    0x00F0
  36 #define     CFG_DZM_VLN(y)                      ((y) << 16)
  37 #define     CFG_DZM_HPXL(x)                     (x)
  38 
  39 /* Graphic Frame 0&1 Starting Address Register */
  40 #define LCD_CFG_GRA_START_ADDR0                 0x00F4
  41 #define LCD_CFG_GRA_START_ADDR1                 0x00F8
  42 
  43 /* Graphic Frame Pitch */
  44 #define LCD_CFG_GRA_PITCH                       0x00FC
  45 
  46 /* Graphic Starting Point on Screen Register */
  47 #define LCD_SPU_GRA_OVSA_HPXL_VLN               0x0100
  48 #define     CFG_GRA_OVSA_VLN(y)                 ((y) << 16)
  49 #define     CFG_GRA_OVSA_HPXL(x)                (x)
  50 
  51 /* Graphic Size Register */
  52 #define LCD_SPU_GRA_HPXL_VLN                    0x0104
  53 #define     CFG_GRA_VLN(y)                      ((y) << 16)
  54 #define     CFG_GRA_HPXL(x)                     (x)
  55 
  56 /* Graphic Size after Zooming Register */
  57 #define LCD_SPU_GZM_HPXL_VLN                    0x0108
  58 #define     CFG_GZM_VLN(y)                      ((y) << 16)
  59 #define     CFG_GZM_HPXL(x)                     (x)
  60 
  61 /* HW Cursor Starting Point on Screen Register */
  62 #define LCD_SPU_HWC_OVSA_HPXL_VLN               0x010C
  63 #define     CFG_HWC_OVSA_VLN(y)                 ((y) << 16)
  64 #define     CFG_HWC_OVSA_HPXL(x)                (x)
  65 
  66 /* HW Cursor Size */
  67 #define LCD_SPU_HWC_HPXL_VLN                    0x0110
  68 #define     CFG_HWC_VLN(y)                      ((y) << 16)
  69 #define     CFG_HWC_HPXL(x)                     (x)
  70 
  71 /* Total Screen Size Register */
  72 #define LCD_SPUT_V_H_TOTAL                      0x0114
  73 #define     CFG_V_TOTAL(y)                      ((y) << 16)
  74 #define     CFG_H_TOTAL(x)                      (x)
  75 
  76 /* Total Screen Active Size Register */
  77 #define LCD_SPU_V_H_ACTIVE                      0x0118
  78 #define     CFG_V_ACTIVE(y)                     ((y) << 16)
  79 #define     CFG_H_ACTIVE(x)                     (x)
  80 
  81 /* Screen H&V Porch Register */
  82 #define LCD_SPU_H_PORCH                         0x011C
  83 #define     CFG_H_BACK_PORCH(b)                 ((b) << 16)
  84 #define     CFG_H_FRONT_PORCH(f)                (f)
  85 #define LCD_SPU_V_PORCH                         0x0120
  86 #define     CFG_V_BACK_PORCH(b)                 ((b) << 16)
  87 #define     CFG_V_FRONT_PORCH(f)                (f)
  88 
  89 /* Screen Blank Color Register */
  90 #define LCD_SPU_BLANKCOLOR                      0x0124
  91 #define     CFG_BLANKCOLOR_MASK                 0x00FFFFFF
  92 #define     CFG_BLANKCOLOR_R_MASK               0x000000FF
  93 #define     CFG_BLANKCOLOR_G_MASK               0x0000FF00
  94 #define     CFG_BLANKCOLOR_B_MASK               0x00FF0000
  95 
  96 /* HW Cursor Color 1&2 Register */
  97 #define LCD_SPU_ALPHA_COLOR1                    0x0128
  98 #define     CFG_HWC_COLOR1                      0x00FFFFFF
  99 #define     CFG_HWC_COLOR1_R(red)               ((red) << 16)
 100 #define     CFG_HWC_COLOR1_G(green)             ((green) << 8)
 101 #define     CFG_HWC_COLOR1_B(blue)              (blue)
 102 #define     CFG_HWC_COLOR1_R_MASK               0x000000FF
 103 #define     CFG_HWC_COLOR1_G_MASK               0x0000FF00
 104 #define     CFG_HWC_COLOR1_B_MASK               0x00FF0000
 105 #define LCD_SPU_ALPHA_COLOR2                    0x012C
 106 #define     CFG_HWC_COLOR2                      0x00FFFFFF
 107 #define     CFG_HWC_COLOR2_R_MASK               0x000000FF
 108 #define     CFG_HWC_COLOR2_G_MASK               0x0000FF00
 109 #define     CFG_HWC_COLOR2_B_MASK               0x00FF0000
 110 
 111 /* Video YUV Color Key Control */
 112 #define LCD_SPU_COLORKEY_Y                      0x0130
 113 #define     CFG_CKEY_Y2(y2)                     ((y2) << 24)
 114 #define     CFG_CKEY_Y2_MASK                    0xFF000000
 115 #define     CFG_CKEY_Y1(y1)                     ((y1) << 16)
 116 #define     CFG_CKEY_Y1_MASK                    0x00FF0000
 117 #define     CFG_CKEY_Y(y)                       ((y) << 8)
 118 #define     CFG_CKEY_Y_MASK                     0x0000FF00
 119 #define     CFG_ALPHA_Y(y)                      (y)
 120 #define     CFG_ALPHA_Y_MASK                    0x000000FF
 121 #define LCD_SPU_COLORKEY_U                      0x0134
 122 #define     CFG_CKEY_U2(u2)                     ((u2) << 24)
 123 #define     CFG_CKEY_U2_MASK                    0xFF000000
 124 #define     CFG_CKEY_U1(u1)                     ((u1) << 16)
 125 #define     CFG_CKEY_U1_MASK                    0x00FF0000
 126 #define     CFG_CKEY_U(u)                       ((u) << 8)
 127 #define     CFG_CKEY_U_MASK                     0x0000FF00
 128 #define     CFG_ALPHA_U(u)                      (u)
 129 #define     CFG_ALPHA_U_MASK                    0x000000FF
 130 #define LCD_SPU_COLORKEY_V                      0x0138
 131 #define     CFG_CKEY_V2(v2)                     ((v2) << 24)
 132 #define     CFG_CKEY_V2_MASK                    0xFF000000
 133 #define     CFG_CKEY_V1(v1)                     ((v1) << 16)
 134 #define     CFG_CKEY_V1_MASK                    0x00FF0000
 135 #define     CFG_CKEY_V(v)                       ((v) << 8)
 136 #define     CFG_CKEY_V_MASK                     0x0000FF00
 137 #define     CFG_ALPHA_V(v)                      (v)
 138 #define     CFG_ALPHA_V_MASK                    0x000000FF
 139 
 140 /* SPI Read Data Register */
 141 #define LCD_SPU_SPI_RXDATA                      0x0140
 142 
 143 /* Smart Panel Read Data Register */
 144 #define LCD_SPU_ISA_RSDATA                      0x0144
 145 #define     ISA_RXDATA_16BIT_1_DATA_MASK        0x000000FF
 146 #define     ISA_RXDATA_16BIT_2_DATA_MASK        0x0000FF00
 147 #define     ISA_RXDATA_16BIT_3_DATA_MASK        0x00FF0000
 148 #define     ISA_RXDATA_16BIT_4_DATA_MASK        0xFF000000
 149 #define     ISA_RXDATA_32BIT_1_DATA_MASK        0x00FFFFFF
 150 
 151 /* HWC SRAM Read Data Register */
 152 #define LCD_SPU_HWC_RDDAT                       0x0158
 153 
 154 /* Gamma Table SRAM Read Data Register */
 155 #define LCD_SPU_GAMMA_RDDAT                     0x015c
 156 #define     CFG_GAMMA_RDDAT_MASK                0x000000FF
 157 
 158 /* Palette Table SRAM Read Data Register */
 159 #define LCD_SPU_PALETTE_RDDAT                   0x0160
 160 #define     CFG_PALETTE_RDDAT_MASK              0x00FFFFFF
 161 
 162 /* I/O Pads Input Read Only Register */
 163 #define LCD_SPU_IOPAD_IN                        0x0178
 164 #define     CFG_IOPAD_IN_MASK                   0x0FFFFFFF
 165 
 166 /* Reserved Read Only Registers */
 167 #define LCD_CFG_RDREG5F                         0x017C
 168 #define     IRE_FRAME_CNT_MASK                  0x000000C0
 169 #define     IPE_FRAME_CNT_MASK                  0x00000030
 170 #define     GRA_FRAME_CNT_MASK                  0x0000000C  /* Graphic */
 171 #define     DMA_FRAME_CNT_MASK                  0x00000003  /* Video */
 172 
 173 /* SPI Control Register. */
 174 #define LCD_SPU_SPI_CTRL                        0x0180
 175 #define     CFG_SCLKCNT(div)                    ((div) << 24)  /* 0xFF~0x2 */
 176 #define     CFG_SCLKCNT_MASK                    0xFF000000
 177 #define     CFG_RXBITS(rx)                      ((rx) << 16)   /* 0x1F~0x1 */
 178 #define     CFG_RXBITS_MASK                     0x00FF0000
 179 #define     CFG_TXBITS(tx)                      ((tx) << 8)    /* 0x1F~0x1 */
 180 #define     CFG_TXBITS_MASK                     0x0000FF00
 181 #define     CFG_CLKINV(clk)                     ((clk) << 7)
 182 #define     CFG_CLKINV_MASK                     0x00000080
 183 #define     CFG_KEEPXFER(transfer)              ((transfer) << 6)
 184 #define     CFG_KEEPXFER_MASK                   0x00000040
 185 #define     CFG_RXBITSTO0(rx)                   ((rx) << 5)
 186 #define     CFG_RXBITSTO0_MASK                  0x00000020
 187 #define     CFG_TXBITSTO0(tx)                   ((tx) << 4)
 188 #define     CFG_TXBITSTO0_MASK                  0x00000010
 189 #define     CFG_SPI_ENA(spi)                    ((spi) << 3)
 190 #define     CFG_SPI_ENA_MASK                    0x00000008
 191 #define     CFG_SPI_SEL(spi)                    ((spi) << 2)
 192 #define     CFG_SPI_SEL_MASK                    0x00000004
 193 #define     CFG_SPI_3W4WB(wire)                 ((wire) << 1)
 194 #define     CFG_SPI_3W4WB_MASK                  0x00000002
 195 #define     CFG_SPI_START(start)                (start)
 196 #define     CFG_SPI_START_MASK                  0x00000001
 197 
 198 /* SPI Tx Data Register */
 199 #define LCD_SPU_SPI_TXDATA                      0x0184
 200 
 201 /*
 202    1. Smart Pannel 8-bit Bus Control Register.
 203    2. AHB Slave Path Data Port Register
 204 */
 205 #define LCD_SPU_SMPN_CTRL                       0x0188
 206 
 207 /* DMA Control 0 Register */
 208 #define LCD_SPU_DMA_CTRL0                       0x0190
 209 #define     CFG_NOBLENDING(nb)                  ((nb) << 31)
 210 #define     CFG_NOBLENDING_MASK                 0x80000000
 211 #define     CFG_GAMMA_ENA(gn)                   ((gn) << 30)
 212 #define     CFG_GAMMA_ENA_MASK                  0x40000000
 213 #define     CFG_CBSH_ENA(cn)                    ((cn) << 29)
 214 #define     CFG_CBSH_ENA_MASK                   0x20000000
 215 #define     CFG_PALETTE_ENA(pn)                 ((pn) << 28)
 216 #define     CFG_PALETTE_ENA_MASK                0x10000000
 217 #define     CFG_ARBFAST_ENA(an)                 ((an) << 27)
 218 #define     CFG_ARBFAST_ENA_MASK                0x08000000
 219 #define     CFG_HWC_1BITMOD(mode)               ((mode) << 26)
 220 #define     CFG_HWC_1BITMOD_MASK                0x04000000
 221 #define     CFG_HWC_1BITENA(mn)                 ((mn) << 25)
 222 #define     CFG_HWC_1BITENA_MASK                0x02000000
 223 #define     CFG_HWC_ENA(cn)                     ((cn) << 24)
 224 #define     CFG_HWC_ENA_MASK                    0x01000000
 225 #define     CFG_DMAFORMAT(dmaformat)            ((dmaformat) << 20)
 226 #define     CFG_DMAFORMAT_MASK                  0x00F00000
 227 #define     CFG_GRAFORMAT(graformat)            ((graformat) << 16)
 228 #define     CFG_GRAFORMAT_MASK                  0x000F0000
 229 /* for graphic part */
 230 #define     CFG_GRA_FTOGGLE(toggle)             ((toggle) << 15)
 231 #define     CFG_GRA_FTOGGLE_MASK                0x00008000
 232 #define     CFG_GRA_HSMOOTH(smooth)             ((smooth) << 14)
 233 #define     CFG_GRA_HSMOOTH_MASK                0x00004000
 234 #define     CFG_GRA_TSTMODE(test)               ((test) << 13)
 235 #define     CFG_GRA_TSTMODE_MASK                0x00002000
 236 #define     CFG_GRA_SWAPRB(swap)                ((swap) << 12)
 237 #define     CFG_GRA_SWAPRB_MASK                 0x00001000
 238 #define     CFG_GRA_SWAPUV(swap)                ((swap) << 11)
 239 #define     CFG_GRA_SWAPUV_MASK                 0x00000800
 240 #define     CFG_GRA_SWAPYU(swap)                ((swap) << 10)
 241 #define     CFG_GRA_SWAPYU_MASK                 0x00000400
 242 #define     CFG_YUV2RGB_GRA(cvrt)               ((cvrt) << 9)
 243 #define     CFG_YUV2RGB_GRA_MASK                0x00000200
 244 #define     CFG_GRA_ENA(gra)                    ((gra) << 8)
 245 #define     CFG_GRA_ENA_MASK                    0x00000100
 246 /* for video part */
 247 #define     CFG_DMA_FTOGGLE(toggle)             ((toggle) << 7)
 248 #define     CFG_DMA_FTOGGLE_MASK                0x00000080
 249 #define     CFG_DMA_HSMOOTH(smooth)             ((smooth) << 6)
 250 #define     CFG_DMA_HSMOOTH_MASK                0x00000040
 251 #define     CFG_DMA_TSTMODE(test)               ((test) << 5)
 252 #define     CFG_DMA_TSTMODE_MASK                0x00000020
 253 #define     CFG_DMA_SWAPRB(swap)                ((swap) << 4)
 254 #define     CFG_DMA_SWAPRB_MASK                 0x00000010
 255 #define     CFG_DMA_SWAPUV(swap)                ((swap) << 3)
 256 #define     CFG_DMA_SWAPUV_MASK                 0x00000008
 257 #define     CFG_DMA_SWAPYU(swap)                ((swap) << 2)
 258 #define     CFG_DMA_SWAPYU_MASK                 0x00000004
 259 #define     CFG_DMA_SWAP_MASK                   0x0000001C
 260 #define     CFG_YUV2RGB_DMA(cvrt)               ((cvrt) << 1)
 261 #define     CFG_YUV2RGB_DMA_MASK                0x00000002
 262 #define     CFG_DMA_ENA(video)                  (video)
 263 #define     CFG_DMA_ENA_MASK                    0x00000001
 264 
 265 /* DMA Control 1 Register */
 266 #define LCD_SPU_DMA_CTRL1                       0x0194
 267 #define     CFG_FRAME_TRIG(trig)                ((trig) << 31)
 268 #define     CFG_FRAME_TRIG_MASK                 0x80000000
 269 #define     CFG_VSYNC_TRIG(trig)                ((trig) << 28)
 270 #define     CFG_VSYNC_TRIG_MASK                 0x70000000
 271 #define     CFG_VSYNC_INV(inv)                  ((inv) << 27)
 272 #define     CFG_VSYNC_INV_MASK                  0x08000000
 273 #define     CFG_COLOR_KEY_MODE(cmode)           ((cmode) << 24)
 274 #define     CFG_COLOR_KEY_MASK                  0x07000000
 275 #define     CFG_CARRY(carry)                    ((carry) << 23)
 276 #define     CFG_CARRY_MASK                      0x00800000
 277 #define     CFG_LNBUF_ENA(lnbuf)                ((lnbuf) << 22)
 278 #define     CFG_LNBUF_ENA_MASK                  0x00400000
 279 #define     CFG_GATED_ENA(gated)                ((gated) << 21)
 280 #define     CFG_GATED_ENA_MASK                  0x00200000
 281 #define     CFG_PWRDN_ENA(power)                ((power) << 20)
 282 #define     CFG_PWRDN_ENA_MASK                  0x00100000
 283 #define     CFG_DSCALE(dscale)                  ((dscale) << 18)
 284 #define     CFG_DSCALE_MASK                     0x000C0000
 285 #define     CFG_ALPHA_MODE(amode)               ((amode) << 16)
 286 #define     CFG_ALPHA_MODE_MASK                 0x00030000
 287 #define     CFG_ALPHA(alpha)                    ((alpha) << 8)
 288 #define     CFG_ALPHA_MASK                      0x0000FF00
 289 #define     CFG_PXLCMD(pxlcmd)                  (pxlcmd)
 290 #define     CFG_PXLCMD_MASK                     0x000000FF
 291 
 292 /* SRAM Control Register */
 293 #define LCD_SPU_SRAM_CTRL                       0x0198
 294 #define     CFG_SRAM_INIT_WR_RD(mode)           ((mode) << 14)
 295 #define     CFG_SRAM_INIT_WR_RD_MASK            0x0000C000
 296 #define     CFG_SRAM_ADDR_LCDID(id)             ((id) << 8)
 297 #define     CFG_SRAM_ADDR_LCDID_MASK            0x00000F00
 298 #define     CFG_SRAM_ADDR(addr)                 (addr)
 299 #define     CFG_SRAM_ADDR_MASK                  0x000000FF
 300 
 301 /* SRAM Write Data Register */
 302 #define LCD_SPU_SRAM_WRDAT                      0x019C
 303 
 304 /* SRAM RTC/WTC Control Register */
 305 #define LCD_SPU_SRAM_PARA0                      0x01A0
 306 
 307 /* SRAM Power Down Control Register */
 308 #define LCD_SPU_SRAM_PARA1                      0x01A4
 309 #define     CFG_CSB_256x32(hwc)                 ((hwc) << 15)   /* HWC */
 310 #define     CFG_CSB_256x32_MASK                 0x00008000
 311 #define     CFG_CSB_256x24(palette)             ((palette) << 14)       /* Palette */
 312 #define     CFG_CSB_256x24_MASK                 0x00004000
 313 #define     CFG_CSB_256x8(gamma)                ((gamma) << 13) /* Gamma */
 314 #define     CFG_CSB_256x8_MASK                  0x00002000
 315 #define     CFG_PDWN256x32(pdwn)                ((pdwn) << 7)   /* HWC */
 316 #define     CFG_PDWN256x32_MASK                 0x00000080
 317 #define     CFG_PDWN256x24(pdwn)                ((pdwn) << 6)   /* Palette */
 318 #define     CFG_PDWN256x24_MASK                 0x00000040
 319 #define     CFG_PDWN256x8(pdwn)                 ((pdwn) << 5)   /* Gamma */
 320 #define     CFG_PDWN256x8_MASK                  0x00000020
 321 #define     CFG_PDWN32x32(pdwn)                 ((pdwn) << 3)
 322 #define     CFG_PDWN32x32_MASK                  0x00000008
 323 #define     CFG_PDWN16x66(pdwn)                 ((pdwn) << 2)
 324 #define     CFG_PDWN16x66_MASK                  0x00000004
 325 #define     CFG_PDWN32x66(pdwn)                 ((pdwn) << 1)
 326 #define     CFG_PDWN32x66_MASK                  0x00000002
 327 #define     CFG_PDWN64x66(pdwn)                 (pdwn)
 328 #define     CFG_PDWN64x66_MASK                  0x00000001
 329 
 330 /* Smart or Dumb Panel Clock Divider */
 331 #define LCD_CFG_SCLK_DIV                        0x01A8
 332 #define     SCLK_SOURCE_SELECT(src)             ((src) << 31)
 333 #define     SCLK_SOURCE_SELECT_MASK             0x80000000
 334 #define     CLK_FRACDIV(frac)                   ((frac) << 16)
 335 #define     CLK_FRACDIV_MASK                    0x0FFF0000
 336 #define     CLK_INT_DIV(div)                    (div)
 337 #define     CLK_INT_DIV_MASK                    0x0000FFFF
 338 
 339 /* Video Contrast Register */
 340 #define LCD_SPU_CONTRAST                        0x01AC
 341 #define     CFG_BRIGHTNESS(bright)              ((bright) << 16)
 342 #define     CFG_BRIGHTNESS_MASK                 0xFFFF0000
 343 #define     CFG_CONTRAST(contrast)              (contrast)
 344 #define     CFG_CONTRAST_MASK                   0x0000FFFF
 345 
 346 /* Video Saturation Register */
 347 #define LCD_SPU_SATURATION                      0x01B0
 348 #define     CFG_C_MULTS(mult)                   ((mult) << 16)
 349 #define     CFG_C_MULTS_MASK                    0xFFFF0000
 350 #define     CFG_SATURATION(sat)                 (sat)
 351 #define     CFG_SATURATION_MASK                 0x0000FFFF
 352 
 353 /* Video Hue Adjust Register */
 354 #define LCD_SPU_CBSH_HUE                        0x01B4
 355 #define     CFG_SIN0(sin0)                      ((sin0) << 16)
 356 #define     CFG_SIN0_MASK                       0xFFFF0000
 357 #define     CFG_COS0(con0)                      (con0)
 358 #define     CFG_COS0_MASK                       0x0000FFFF
 359 
 360 /* Dump LCD Panel Control Register */
 361 #define LCD_SPU_DUMB_CTRL                       0x01B8
 362 #define     CFG_DUMBMODE(mode)                  ((mode) << 28)
 363 #define     CFG_DUMBMODE_MASK                   0xF0000000
 364 #define     CFG_LCDGPIO_O(data)                 ((data) << 20)
 365 #define     CFG_LCDGPIO_O_MASK                  0x0FF00000
 366 #define     CFG_LCDGPIO_ENA(gpio)               ((gpio) << 12)
 367 #define     CFG_LCDGPIO_ENA_MASK                0x000FF000
 368 #define     CFG_BIAS_OUT(bias)                  ((bias) << 8)
 369 #define     CFG_BIAS_OUT_MASK                   0x00000100
 370 #define     CFG_REVERSE_RGB(rRGB)               ((rRGB) << 7)
 371 #define     CFG_REVERSE_RGB_MASK                0x00000080
 372 #define     CFG_INV_COMPBLANK(blank)            ((blank) << 6)
 373 #define     CFG_INV_COMPBLANK_MASK              0x00000040
 374 #define     CFG_INV_COMPSYNC(sync)              ((sync) << 5)
 375 #define     CFG_INV_COMPSYNC_MASK               0x00000020
 376 #define     CFG_INV_HENA(hena)                  ((hena) << 4)
 377 #define     CFG_INV_HENA_MASK                   0x00000010
 378 #define     CFG_INV_VSYNC(vsync)                ((vsync) << 3)
 379 #define     CFG_INV_VSYNC_MASK                  0x00000008
 380 #define     CFG_INV_HSYNC(hsync)                ((hsync) << 2)
 381 #define     CFG_INV_HSYNC_MASK                  0x00000004
 382 #define     CFG_INV_PCLK(pclk)                  ((pclk) << 1)
 383 #define     CFG_INV_PCLK_MASK                   0x00000002
 384 #define     CFG_DUMB_ENA(dumb)                  (dumb)
 385 #define     CFG_DUMB_ENA_MASK                   0x00000001
 386 
 387 /* LCD I/O Pads Control Register */
 388 #define SPU_IOPAD_CONTROL                       0x01BC
 389 #define     CFG_GRA_VM_ENA(vm)                  ((vm) << 15)        /* gfx */
 390 #define     CFG_GRA_VM_ENA_MASK                 0x00008000
 391 #define     CFG_DMA_VM_ENA(vm)                  ((vm) << 13)    /* video */
 392 #define     CFG_DMA_VM_ENA_MASK                 0x00002000
 393 #define     CFG_CMD_VM_ENA(vm)                  ((vm) << 13)
 394 #define     CFG_CMD_VM_ENA_MASK                 0x00000800
 395 #define     CFG_CSC(csc)                        ((csc) << 8)    /* csc */
 396 #define     CFG_CSC_MASK                        0x00000300
 397 #define     CFG_AXICTRL(axi)                    ((axi) << 4)
 398 #define     CFG_AXICTRL_MASK                    0x000000F0
 399 #define     CFG_IOPADMODE(iopad)                (iopad)
 400 #define     CFG_IOPADMODE_MASK                  0x0000000F
 401 
 402 /* LCD Interrupt Control Register */
 403 #define SPU_IRQ_ENA                             0x01C0
 404 #define     DMA_FRAME_IRQ0_ENA(irq)             ((irq) << 31)
 405 #define     DMA_FRAME_IRQ0_ENA_MASK             0x80000000
 406 #define     DMA_FRAME_IRQ1_ENA(irq)             ((irq) << 30)
 407 #define     DMA_FRAME_IRQ1_ENA_MASK             0x40000000
 408 #define     DMA_FF_UNDERFLOW_ENA(ff)            ((ff) << 29)
 409 #define     DMA_FF_UNDERFLOW_ENA_MASK           0x20000000
 410 #define     GRA_FRAME_IRQ0_ENA(irq)             ((irq) << 27)
 411 #define     GRA_FRAME_IRQ0_ENA_MASK             0x08000000
 412 #define     GRA_FRAME_IRQ1_ENA(irq)             ((irq) << 26)
 413 #define     GRA_FRAME_IRQ1_ENA_MASK             0x04000000
 414 #define     GRA_FF_UNDERFLOW_ENA(ff)            ((ff) << 25)
 415 #define     GRA_FF_UNDERFLOW_ENA_MASK           0x02000000
 416 #define     VSYNC_IRQ_ENA(vsync_irq)            ((vsync_irq) << 23)
 417 #define     VSYNC_IRQ_ENA_MASK                  0x00800000
 418 #define     DUMB_FRAMEDONE_ENA(fdone)           ((fdone) << 22)
 419 #define     DUMB_FRAMEDONE_ENA_MASK             0x00400000
 420 #define     TWC_FRAMEDONE_ENA(fdone)            ((fdone) << 21)
 421 #define     TWC_FRAMEDONE_ENA_MASK              0x00200000
 422 #define     HWC_FRAMEDONE_ENA(fdone)            ((fdone) << 20)
 423 #define     HWC_FRAMEDONE_ENA_MASK              0x00100000
 424 #define     SLV_IRQ_ENA(irq)                    ((irq) << 19)
 425 #define     SLV_IRQ_ENA_MASK                    0x00080000
 426 #define     SPI_IRQ_ENA(irq)                    ((irq) << 18)
 427 #define     SPI_IRQ_ENA_MASK                    0x00040000
 428 #define     PWRDN_IRQ_ENA(irq)                  ((irq) << 17)
 429 #define     PWRDN_IRQ_ENA_MASK                  0x00020000
 430 #define     ERR_IRQ_ENA(irq)                    ((irq) << 16)
 431 #define     ERR_IRQ_ENA_MASK                    0x00010000
 432 #define     CLEAN_SPU_IRQ_ISR(irq)              (irq)
 433 #define     CLEAN_SPU_IRQ_ISR_MASK              0x0000FFFF
 434 
 435 /* LCD Interrupt Status Register */
 436 #define SPU_IRQ_ISR                             0x01C4
 437 #define     DMA_FRAME_IRQ0(irq)                 ((irq) << 31)
 438 #define     DMA_FRAME_IRQ0_MASK                 0x80000000
 439 #define     DMA_FRAME_IRQ1(irq)                 ((irq) << 30)
 440 #define     DMA_FRAME_IRQ1_MASK                 0x40000000
 441 #define     DMA_FF_UNDERFLOW(ff)                ((ff) << 29)
 442 #define     DMA_FF_UNDERFLOW_MASK               0x20000000
 443 #define     GRA_FRAME_IRQ0(irq)                 ((irq) << 27)
 444 #define     GRA_FRAME_IRQ0_MASK                 0x08000000
 445 #define     GRA_FRAME_IRQ1(irq)                 ((irq) << 26)
 446 #define     GRA_FRAME_IRQ1_MASK                 0x04000000
 447 #define     GRA_FF_UNDERFLOW(ff)                ((ff) << 25)
 448 #define     GRA_FF_UNDERFLOW_MASK               0x02000000
 449 #define     VSYNC_IRQ(vsync_irq)                ((vsync_irq) << 23)
 450 #define     VSYNC_IRQ_MASK                      0x00800000
 451 #define     DUMB_FRAMEDONE(fdone)               ((fdone) << 22)
 452 #define     DUMB_FRAMEDONE_MASK                 0x00400000
 453 #define     TWC_FRAMEDONE(fdone)                ((fdone) << 21)
 454 #define     TWC_FRAMEDONE_MASK                  0x00200000
 455 #define     HWC_FRAMEDONE(fdone)                ((fdone) << 20)
 456 #define     HWC_FRAMEDONE_MASK                  0x00100000
 457 #define     SLV_IRQ(irq)                        ((irq) << 19)
 458 #define     SLV_IRQ_MASK                        0x00080000
 459 #define     SPI_IRQ(irq)                        ((irq) << 18)
 460 #define     SPI_IRQ_MASK                        0x00040000
 461 #define     PWRDN_IRQ(irq)                      ((irq) << 17)
 462 #define     PWRDN_IRQ_MASK                      0x00020000
 463 #define     ERR_IRQ(irq)                        ((irq) << 16)
 464 #define     ERR_IRQ_MASK                        0x00010000
 465 /* read-only */
 466 #define     DMA_FRAME_IRQ0_LEVEL_MASK           0x00008000
 467 #define     DMA_FRAME_IRQ1_LEVEL_MASK           0x00004000
 468 #define     DMA_FRAME_CNT_ISR_MASK              0x00003000
 469 #define     GRA_FRAME_IRQ0_LEVEL_MASK           0x00000800
 470 #define     GRA_FRAME_IRQ1_LEVEL_MASK           0x00000400
 471 #define     GRA_FRAME_CNT_ISR_MASK              0x00000300
 472 #define     VSYNC_IRQ_LEVEL_MASK                0x00000080
 473 #define     DUMB_FRAMEDONE_LEVEL_MASK           0x00000040
 474 #define     TWC_FRAMEDONE_LEVEL_MASK            0x00000020
 475 #define     HWC_FRAMEDONE_LEVEL_MASK            0x00000010
 476 #define     SLV_FF_EMPTY_MASK                   0x00000008
 477 #define     DMA_FF_ALLEMPTY_MASK                0x00000004
 478 #define     GRA_FF_ALLEMPTY_MASK                0x00000002
 479 #define     PWRDN_IRQ_LEVEL_MASK                0x00000001
 480 
 481 
 482 /*
 483  * defined Video Memory Color format for DMA control 0 register
 484  * DMA0 bit[23:20]
 485  */
 486 #define VMODE_RGB565            0x0
 487 #define VMODE_RGB1555           0x1
 488 #define VMODE_RGB888PACKED      0x2
 489 #define VMODE_RGB888UNPACKED    0x3
 490 #define VMODE_RGBA888           0x4
 491 #define VMODE_YUV422PACKED      0x5
 492 #define VMODE_YUV422PLANAR      0x6
 493 #define VMODE_YUV420PLANAR      0x7
 494 #define VMODE_SMPNCMD           0x8
 495 #define VMODE_PALETTE4BIT       0x9
 496 #define VMODE_PALETTE8BIT       0xa
 497 #define VMODE_RESERVED          0xb
 498 
 499 /*
 500  * defined Graphic Memory Color format for DMA control 0 register
 501  * DMA0 bit[19:16]
 502  */
 503 #define GMODE_RGB565            0x0
 504 #define GMODE_RGB1555           0x1
 505 #define GMODE_RGB888PACKED      0x2
 506 #define GMODE_RGB888UNPACKED    0x3
 507 #define GMODE_RGBA888           0x4
 508 #define GMODE_YUV422PACKED      0x5
 509 #define GMODE_YUV422PLANAR      0x6
 510 #define GMODE_YUV420PLANAR      0x7
 511 #define GMODE_SMPNCMD           0x8
 512 #define GMODE_PALETTE4BIT       0x9
 513 #define GMODE_PALETTE8BIT       0xa
 514 #define GMODE_RESERVED          0xb
 515 
 516 /*
 517  * define for DMA control 1 register
 518  */
 519 #define DMA1_FRAME_TRIG         31 /* bit location */
 520 #define DMA1_VSYNC_MODE         28
 521 #define DMA1_VSYNC_INV          27
 522 #define DMA1_CKEY               24
 523 #define DMA1_CARRY              23
 524 #define DMA1_LNBUF_ENA          22
 525 #define DMA1_GATED_ENA          21
 526 #define DMA1_PWRDN_ENA          20
 527 #define DMA1_DSCALE             18
 528 #define DMA1_ALPHA_MODE         16
 529 #define DMA1_ALPHA              08
 530 #define DMA1_PXLCMD             00
 531 
 532 /*
 533  * defined for Configure Dumb Mode
 534  * DUMB LCD Panel bit[31:28]
 535  */
 536 #define DUMB16_RGB565_0         0x0
 537 #define DUMB16_RGB565_1         0x1
 538 #define DUMB18_RGB666_0         0x2
 539 #define DUMB18_RGB666_1         0x3
 540 #define DUMB12_RGB444_0         0x4
 541 #define DUMB12_RGB444_1         0x5
 542 #define DUMB24_RGB888_0         0x6
 543 #define DUMB_BLANK              0x7
 544 
 545 /*
 546  * defined for Configure I/O Pin Allocation Mode
 547  * LCD LCD I/O Pads control register bit[3:0]
 548  */
 549 #define IOPAD_DUMB24            0x0
 550 #define IOPAD_DUMB18SPI         0x1
 551 #define IOPAD_DUMB18GPIO        0x2
 552 #define IOPAD_DUMB16SPI         0x3
 553 #define IOPAD_DUMB16GPIO        0x4
 554 #define IOPAD_DUMB12            0x5
 555 #define IOPAD_SMART18SPI        0x6
 556 #define IOPAD_SMART16SPI        0x7
 557 #define IOPAD_SMART8BOTH        0x8
 558 
 559 #endif /* __PXA168FB_H__ */
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root/drivers/video/fbdev/pxa168fb.h

INCLUDED FROM
