This source file includes following definitions.
- h_total
- v_total
- hsp
- vsp
- d_pitch
- chan_to_field
- mb862xxfb_setcolreg
- mb862xxfb_check_var
- mb862xxfb_set_par
- mb862xxfb_pan
- mb862xxfb_blank
- mb862xxfb_ioctl
- mb862xxfb_init_fbinfo
- mb862xxfb_show_dispregs
- mb862xx_intr
- mb862xx_gdc_init
- of_platform_mb862xx_probe
- of_platform_mb862xx_remove
- coralp_init
- init_dram_ctrl
- carmine_init
- mb862xx_pci_gdc_init
- mb862xx_pci_probe
- mb862xx_pci_remove
- mb862xxfb_init
- mb862xxfb_exit
1
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3
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5
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7
8
9
10
11 #undef DEBUG
12
13 #include <linux/fb.h>
14 #include <linux/delay.h>
15 #include <linux/uaccess.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #if defined(CONFIG_OF)
21 #include <linux/of_platform.h>
22 #endif
23 #include "mb862xxfb.h"
24 #include "mb862xx_reg.h"
25
26 #define NR_PALETTE 256
27 #define MB862XX_MEM_SIZE 0x1000000
28 #define CORALP_MEM_SIZE 0x2000000
29 #define CARMINE_MEM_SIZE 0x8000000
30 #define DRV_NAME "mb862xxfb"
31
32 #if defined(CONFIG_SOCRATES)
33 static struct mb862xx_gc_mode socrates_gc_mode = {
34
35 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
36
37 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
38 };
39 #endif
40
41
42 static inline int h_total(struct fb_var_screeninfo *var)
43 {
44 return var->xres + var->left_margin +
45 var->right_margin + var->hsync_len;
46 }
47
48 static inline int v_total(struct fb_var_screeninfo *var)
49 {
50 return var->yres + var->upper_margin +
51 var->lower_margin + var->vsync_len;
52 }
53
54 static inline int hsp(struct fb_var_screeninfo *var)
55 {
56 return var->xres + var->right_margin - 1;
57 }
58
59 static inline int vsp(struct fb_var_screeninfo *var)
60 {
61 return var->yres + var->lower_margin - 1;
62 }
63
64 static inline int d_pitch(struct fb_var_screeninfo *var)
65 {
66 return var->xres * var->bits_per_pixel / 8;
67 }
68
69 static inline unsigned int chan_to_field(unsigned int chan,
70 struct fb_bitfield *bf)
71 {
72 chan &= 0xffff;
73 chan >>= 16 - bf->length;
74 return chan << bf->offset;
75 }
76
77 static int mb862xxfb_setcolreg(unsigned regno,
78 unsigned red, unsigned green, unsigned blue,
79 unsigned transp, struct fb_info *info)
80 {
81 struct mb862xxfb_par *par = info->par;
82 unsigned int val;
83
84 switch (info->fix.visual) {
85 case FB_VISUAL_TRUECOLOR:
86 if (regno < 16) {
87 val = chan_to_field(red, &info->var.red);
88 val |= chan_to_field(green, &info->var.green);
89 val |= chan_to_field(blue, &info->var.blue);
90 par->pseudo_palette[regno] = val;
91 }
92 break;
93 case FB_VISUAL_PSEUDOCOLOR:
94 if (regno < 256) {
95 val = (red >> 8) << 16;
96 val |= (green >> 8) << 8;
97 val |= blue >> 8;
98 outreg(disp, GC_L0PAL0 + (regno * 4), val);
99 }
100 break;
101 default:
102 return 1;
103 }
104 return 0;
105 }
106
107 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
108 struct fb_info *fbi)
109 {
110 unsigned long tmp;
111
112 if (fbi->dev)
113 dev_dbg(fbi->dev, "%s\n", __func__);
114
115
116 if (var->hsync_len > 255 || var->vsync_len > 255)
117 return -EINVAL;
118
119 if ((var->xres + var->right_margin) >= 4096)
120 return -EINVAL;
121
122 if ((var->yres + var->lower_margin) > 4096)
123 return -EINVAL;
124
125 if (h_total(var) > 4096 || v_total(var) > 4096)
126 return -EINVAL;
127
128 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
129 return -EINVAL;
130
131 if (var->bits_per_pixel <= 8)
132 var->bits_per_pixel = 8;
133 else if (var->bits_per_pixel <= 16)
134 var->bits_per_pixel = 16;
135 else if (var->bits_per_pixel <= 32)
136 var->bits_per_pixel = 32;
137
138
139
140
141
142 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
143 int r;
144
145 var->bits_per_pixel = 0;
146 do {
147 var->bits_per_pixel += 8;
148 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
149 } while (r && var->bits_per_pixel <= 32);
150
151 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
152 return -EINVAL;
153 }
154
155
156 tmp = (var->xres * var->bits_per_pixel) / 8;
157 if ((tmp & 15) != 0)
158 return -EINVAL;
159
160
161 switch (var->bits_per_pixel) {
162 case 8:
163 var->red.length = var->bits_per_pixel;
164 var->green.length = var->bits_per_pixel;
165 var->blue.length = var->bits_per_pixel;
166 var->red.offset = 0;
167 var->green.offset = 0;
168 var->blue.offset = 0;
169 var->transp.length = 0;
170 break;
171 case 16:
172 var->red.length = 5;
173 var->green.length = 5;
174 var->blue.length = 5;
175 var->red.offset = 10;
176 var->green.offset = 5;
177 var->blue.offset = 0;
178 var->transp.length = 0;
179 break;
180 case 24:
181 case 32:
182 var->transp.length = 8;
183 var->red.length = 8;
184 var->green.length = 8;
185 var->blue.length = 8;
186 var->transp.offset = 24;
187 var->red.offset = 16;
188 var->green.offset = 8;
189 var->blue.offset = 0;
190 break;
191 default:
192 return -EINVAL;
193 }
194 return 0;
195 }
196
197
198
199
200 static int mb862xxfb_set_par(struct fb_info *fbi)
201 {
202 struct mb862xxfb_par *par = fbi->par;
203 unsigned long reg, sc;
204
205 dev_dbg(par->dev, "%s\n", __func__);
206 if (par->type == BT_CORALP)
207 mb862xxfb_init_accel(fbi, fbi->var.xres);
208
209 if (par->pre_init)
210 return 0;
211
212
213 reg = inreg(disp, GC_DCM1);
214 reg &= ~GC_DCM01_DEN;
215 outreg(disp, GC_DCM1, reg);
216
217
218 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
219 reg = inreg(disp, GC_DCM1);
220 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
221 reg |= sc << 8;
222 outreg(disp, GC_DCM1, reg);
223 dev_dbg(par->dev, "SC 0x%lx\n", sc);
224
225
226 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
227 (fbi->var.yres - 1));
228 if (fbi->var.bits_per_pixel == 16)
229 reg |= GC_L0M_L0C_16;
230 outreg(disp, GC_L0M, reg);
231
232 if (fbi->var.bits_per_pixel == 32) {
233 reg = inreg(disp, GC_L0EM);
234 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
235 }
236 outreg(disp, GC_WY_WX, 0);
237 reg = pack(fbi->var.yres - 1, fbi->var.xres);
238 outreg(disp, GC_WH_WW, reg);
239 outreg(disp, GC_L0OA0, 0);
240 outreg(disp, GC_L0DA0, 0);
241 outreg(disp, GC_L0DY_L0DX, 0);
242 outreg(disp, GC_L0WY_L0WX, 0);
243 outreg(disp, GC_L0WH_L0WW, reg);
244
245
246 reg = inreg(disp, GC_CPM_CUTC);
247 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
248 outreg(disp, GC_CPM_CUTC, reg);
249
250
251 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
252 outreg(disp, GC_HDB_HDP, reg);
253 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
254 outreg(disp, GC_VDP_VSP, reg);
255 reg = ((fbi->var.vsync_len - 1) << 24) |
256 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
257 outreg(disp, GC_VSW_HSW_HSP, reg);
258 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
259 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
260
261
262 reg = inreg(disp, GC_DCM1);
263 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
264 reg &= ~GC_DCM01_ESY;
265 outreg(disp, GC_DCM1, reg);
266 return 0;
267 }
268
269 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
270 struct fb_info *info)
271 {
272 struct mb862xxfb_par *par = info->par;
273 unsigned long reg;
274
275 reg = pack(var->yoffset, var->xoffset);
276 outreg(disp, GC_L0WY_L0WX, reg);
277
278 reg = pack(info->var.yres_virtual, info->var.xres_virtual);
279 outreg(disp, GC_L0WH_L0WW, reg);
280 return 0;
281 }
282
283 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
284 {
285 struct mb862xxfb_par *par = fbi->par;
286 unsigned long reg;
287
288 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
289
290 switch (mode) {
291 case FB_BLANK_POWERDOWN:
292 reg = inreg(disp, GC_DCM1);
293 reg &= ~GC_DCM01_DEN;
294 outreg(disp, GC_DCM1, reg);
295 break;
296 case FB_BLANK_UNBLANK:
297 reg = inreg(disp, GC_DCM1);
298 reg |= GC_DCM01_DEN;
299 outreg(disp, GC_DCM1, reg);
300 break;
301 case FB_BLANK_NORMAL:
302 case FB_BLANK_VSYNC_SUSPEND:
303 case FB_BLANK_HSYNC_SUSPEND:
304 default:
305 return 1;
306 }
307 return 0;
308 }
309
310 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
311 unsigned long arg)
312 {
313 struct mb862xxfb_par *par = fbi->par;
314 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
315 void __user *argp = (void __user *)arg;
316 int *enable;
317 u32 l1em = 0;
318
319 switch (cmd) {
320 case MB862XX_L1_GET_CFG:
321 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
322 return -EFAULT;
323 break;
324 case MB862XX_L1_SET_CFG:
325 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
326 return -EFAULT;
327 if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
328 return -EINVAL;
329 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
330
331 outreg(cap, GC_CAP_CSC,
332 pack((l1_cfg->sh << 11) / l1_cfg->dh,
333 (l1_cfg->sw << 11) / l1_cfg->dw));
334 l1em = inreg(disp, GC_L1EM);
335 l1em &= ~GC_L1EM_DM;
336 } else if ((l1_cfg->sw <= l1_cfg->dw) &&
337 (l1_cfg->sh <= l1_cfg->dh)) {
338
339 outreg(cap, GC_CAP_CSC,
340 pack((l1_cfg->sh << 11) / l1_cfg->dh,
341 (l1_cfg->sw << 11) / l1_cfg->dw));
342 outreg(cap, GC_CAP_CMSS,
343 pack(l1_cfg->sw >> 1, l1_cfg->sh));
344 outreg(cap, GC_CAP_CMDS,
345 pack(l1_cfg->dw >> 1, l1_cfg->dh));
346 l1em = inreg(disp, GC_L1EM);
347 l1em |= GC_L1EM_DM;
348 }
349
350 if (l1_cfg->mirror) {
351 outreg(cap, GC_CAP_CBM,
352 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
353 l1em |= l1_cfg->dw * 2 - 8;
354 } else {
355 outreg(cap, GC_CAP_CBM,
356 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
357 l1em &= 0xffff0000;
358 }
359 outreg(disp, GC_L1EM, l1em);
360 break;
361 case MB862XX_L1_ENABLE:
362 enable = (int *)arg;
363 if (*enable) {
364 outreg(disp, GC_L1DA, par->cap_buf);
365 outreg(cap, GC_CAP_IMG_START,
366 pack(l1_cfg->sy >> 1, l1_cfg->sx));
367 outreg(cap, GC_CAP_IMG_END,
368 pack(l1_cfg->sh, l1_cfg->sw));
369 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
370 (par->l1_stride << 16));
371 outreg(disp, GC_L1WY_L1WX,
372 pack(l1_cfg->dy, l1_cfg->dx));
373 outreg(disp, GC_L1WH_L1WW,
374 pack(l1_cfg->dh - 1, l1_cfg->dw));
375 outreg(disp, GC_DLS, 1);
376 outreg(cap, GC_CAP_VCM,
377 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
378 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
379 GC_DCM1_DEN | GC_DCM1_L1E);
380 } else {
381 outreg(cap, GC_CAP_VCM,
382 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
383 outreg(disp, GC_DCM1,
384 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
385 }
386 break;
387 case MB862XX_L1_CAP_CTL:
388 enable = (int *)arg;
389 if (*enable) {
390 outreg(cap, GC_CAP_VCM,
391 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
392 } else {
393 outreg(cap, GC_CAP_VCM,
394 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
395 }
396 break;
397 default:
398 return -EINVAL;
399 }
400 return 0;
401 }
402
403
404 static struct fb_ops mb862xxfb_ops = {
405 .owner = THIS_MODULE,
406 .fb_check_var = mb862xxfb_check_var,
407 .fb_set_par = mb862xxfb_set_par,
408 .fb_setcolreg = mb862xxfb_setcolreg,
409 .fb_blank = mb862xxfb_blank,
410 .fb_pan_display = mb862xxfb_pan,
411 .fb_fillrect = cfb_fillrect,
412 .fb_copyarea = cfb_copyarea,
413 .fb_imageblit = cfb_imageblit,
414 .fb_ioctl = mb862xxfb_ioctl,
415 };
416
417
418 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
419 {
420 struct mb862xxfb_par *par = fbi->par;
421 struct mb862xx_gc_mode *mode = par->gc_mode;
422 unsigned long reg;
423 int stride;
424
425 fbi->fbops = &mb862xxfb_ops;
426 fbi->pseudo_palette = par->pseudo_palette;
427 fbi->screen_base = par->fb_base;
428 fbi->screen_size = par->mapped_vram;
429
430 strcpy(fbi->fix.id, DRV_NAME);
431 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
432 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
433 fbi->fix.mmio_len = par->mmio_len;
434 fbi->fix.accel = FB_ACCEL_NONE;
435 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
436 fbi->fix.type_aux = 0;
437 fbi->fix.xpanstep = 1;
438 fbi->fix.ypanstep = 1;
439 fbi->fix.ywrapstep = 0;
440
441 reg = inreg(disp, GC_DCM1);
442 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
443
444 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
445 unsigned long hsp, vsp, ht, vt;
446
447 dev_dbg(par->dev, "using bootloader's disp. mode\n");
448 fbi->var.pixclock = (sc * 1000000) / par->refclk;
449 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
450 reg = inreg(disp, GC_VDP_VSP);
451 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
452 vsp = (reg & 0x0fff) + 1;
453 fbi->var.xres_virtual = fbi->var.xres;
454 fbi->var.yres_virtual = fbi->var.yres;
455 reg = inreg(disp, GC_L0EM);
456 if (reg & GC_L0EM_L0EC_24) {
457 fbi->var.bits_per_pixel = 32;
458 } else {
459 reg = inreg(disp, GC_L0M);
460 if (reg & GC_L0M_L0C_16)
461 fbi->var.bits_per_pixel = 16;
462 else
463 fbi->var.bits_per_pixel = 8;
464 }
465 reg = inreg(disp, GC_VSW_HSW_HSP);
466 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
467 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
468 hsp = (reg & 0xffff) + 1;
469 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
470 fbi->var.right_margin = hsp - fbi->var.xres;
471 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
472 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
473 fbi->var.lower_margin = vsp - fbi->var.yres;
474 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
475 } else if (mode) {
476 dev_dbg(par->dev, "using supplied mode\n");
477 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
478 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
479 } else {
480 int ret;
481
482 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
483 NULL, 0, NULL, 16);
484 if (ret == 0 || ret == 4) {
485 dev_err(par->dev,
486 "failed to get initial mode\n");
487 return -EINVAL;
488 }
489 }
490
491 fbi->var.xoffset = 0;
492 fbi->var.yoffset = 0;
493 fbi->var.grayscale = 0;
494 fbi->var.nonstd = 0;
495 fbi->var.height = -1;
496 fbi->var.width = -1;
497 fbi->var.accel_flags = 0;
498 fbi->var.vmode = FB_VMODE_NONINTERLACED;
499 fbi->var.activate = FB_ACTIVATE_NOW;
500 fbi->flags = FBINFO_DEFAULT |
501 #ifdef __BIG_ENDIAN
502 FBINFO_FOREIGN_ENDIAN |
503 #endif
504 FBINFO_HWACCEL_XPAN |
505 FBINFO_HWACCEL_YPAN;
506
507
508 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
509 dev_err(par->dev, "check_var() failed on initial setup?\n");
510
511 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
512 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
513 fbi->fix.line_length = (fbi->var.xres_virtual *
514 fbi->var.bits_per_pixel) / 8;
515 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
516
517
518
519
520
521 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
522 par->cap_len = 0x1bd800;
523 par->l1_cfg.sx = 0;
524 par->l1_cfg.sy = 0;
525 par->l1_cfg.sw = 720;
526 par->l1_cfg.sh = 576;
527 par->l1_cfg.dx = 0;
528 par->l1_cfg.dy = 0;
529 par->l1_cfg.dw = 720;
530 par->l1_cfg.dh = 576;
531 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
532 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
533 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
534 (par->l1_stride << 16));
535 outreg(cap, GC_CAP_CBOA, par->cap_buf);
536 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
537 return 0;
538 }
539
540
541
542
543 static ssize_t mb862xxfb_show_dispregs(struct device *dev,
544 struct device_attribute *attr, char *buf)
545 {
546 struct fb_info *fbi = dev_get_drvdata(dev);
547 struct mb862xxfb_par *par = fbi->par;
548 char *ptr = buf;
549 unsigned int reg;
550
551 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
552 ptr += sprintf(ptr, "%08x = %08x\n",
553 reg, inreg(disp, reg));
554
555 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
556 ptr += sprintf(ptr, "%08x = %08x\n",
557 reg, inreg(disp, reg));
558
559 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
560 ptr += sprintf(ptr, "%08x = %08x\n",
561 reg, inreg(disp, reg));
562
563 for (reg = 0x400; reg <= 0x410; reg += 4)
564 ptr += sprintf(ptr, "geo %08x = %08x\n",
565 reg, inreg(geo, reg));
566
567 for (reg = 0x400; reg <= 0x410; reg += 4)
568 ptr += sprintf(ptr, "draw %08x = %08x\n",
569 reg, inreg(draw, reg));
570
571 for (reg = 0x440; reg <= 0x450; reg += 4)
572 ptr += sprintf(ptr, "draw %08x = %08x\n",
573 reg, inreg(draw, reg));
574
575 return ptr - buf;
576 }
577
578 static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
579
580 static irqreturn_t mb862xx_intr(int irq, void *dev_id)
581 {
582 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
583 unsigned long reg_ist, mask;
584
585 if (!par)
586 return IRQ_NONE;
587
588 if (par->type == BT_CARMINE) {
589
590 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
591 mask = inreg(ctrl, GC_CTRL_INT_MASK);
592 if (reg_ist == 0)
593 return IRQ_HANDLED;
594
595 reg_ist &= mask;
596 if (reg_ist == 0)
597 return IRQ_HANDLED;
598
599
600 outreg(ctrl, 0x0, reg_ist);
601 } else {
602
603 reg_ist = inreg(host, GC_IST);
604 mask = inreg(host, GC_IMASK);
605
606 reg_ist &= mask;
607 if (reg_ist == 0)
608 return IRQ_HANDLED;
609
610
611 outreg(host, GC_IST, ~reg_ist);
612 }
613 return IRQ_HANDLED;
614 }
615
616 #if defined(CONFIG_FB_MB862XX_LIME)
617
618
619
620 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
621 {
622 unsigned long ccf, mmr;
623 unsigned long ver, rev;
624
625 if (!par)
626 return -ENODEV;
627
628 #if defined(CONFIG_FB_PRE_INIT_FB)
629 par->pre_init = 1;
630 #endif
631 par->host = par->mmio_base;
632 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
633 par->disp = par->mmio_base + MB862XX_DISP_BASE;
634 par->cap = par->mmio_base + MB862XX_CAP_BASE;
635 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
636 par->geo = par->mmio_base + MB862XX_GEO_BASE;
637 par->pio = par->mmio_base + MB862XX_PIO_BASE;
638
639 par->refclk = GC_DISP_REFCLK_400;
640
641 ver = inreg(host, GC_CID);
642 rev = inreg(pio, GC_REVISION);
643 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
644 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
645 (int)rev & 0xff);
646 par->type = BT_LIME;
647 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
648 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
649 } else {
650 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
651 return -ENODEV;
652 }
653
654 if (!par->pre_init) {
655 outreg(host, GC_CCF, ccf);
656 udelay(200);
657 outreg(host, GC_MMR, mmr);
658 udelay(10);
659 }
660
661
662 outreg(host, GC_IST, 0);
663 outreg(host, GC_IMASK, GC_INT_EN);
664 return 0;
665 }
666
667 static int of_platform_mb862xx_probe(struct platform_device *ofdev)
668 {
669 struct device_node *np = ofdev->dev.of_node;
670 struct device *dev = &ofdev->dev;
671 struct mb862xxfb_par *par;
672 struct fb_info *info;
673 struct resource res;
674 resource_size_t res_size;
675 unsigned long ret = -ENODEV;
676
677 if (of_address_to_resource(np, 0, &res)) {
678 dev_err(dev, "Invalid address\n");
679 return -ENXIO;
680 }
681
682 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
683 if (!info)
684 return -ENOMEM;
685
686 par = info->par;
687 par->info = info;
688 par->dev = dev;
689
690 par->irq = irq_of_parse_and_map(np, 0);
691 if (par->irq == NO_IRQ) {
692 dev_err(dev, "failed to map irq\n");
693 ret = -ENODEV;
694 goto fbrel;
695 }
696
697 res_size = resource_size(&res);
698 par->res = request_mem_region(res.start, res_size, DRV_NAME);
699 if (par->res == NULL) {
700 dev_err(dev, "Cannot claim framebuffer/mmio\n");
701 ret = -ENXIO;
702 goto irqdisp;
703 }
704
705 #if defined(CONFIG_SOCRATES)
706 par->gc_mode = &socrates_gc_mode;
707 #endif
708
709 par->fb_base_phys = res.start;
710 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
711 par->mmio_len = MB862XX_MMIO_SIZE;
712 if (par->gc_mode)
713 par->mapped_vram = par->gc_mode->max_vram;
714 else
715 par->mapped_vram = MB862XX_MEM_SIZE;
716
717 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
718 if (par->fb_base == NULL) {
719 dev_err(dev, "Cannot map framebuffer\n");
720 goto rel_reg;
721 }
722
723 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
724 if (par->mmio_base == NULL) {
725 dev_err(dev, "Cannot map registers\n");
726 goto fb_unmap;
727 }
728
729 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
730 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
731 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
732 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
733
734 if (mb862xx_gdc_init(par))
735 goto io_unmap;
736
737 if (request_irq(par->irq, mb862xx_intr, 0,
738 DRV_NAME, (void *)par)) {
739 dev_err(dev, "Cannot request irq\n");
740 goto io_unmap;
741 }
742
743 mb862xxfb_init_fbinfo(info);
744
745 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
746 dev_err(dev, "Could not allocate cmap for fb_info.\n");
747 goto free_irq;
748 }
749
750 if ((info->fbops->fb_set_par)(info))
751 dev_err(dev, "set_var() failed on initial setup?\n");
752
753 if (register_framebuffer(info)) {
754 dev_err(dev, "failed to register framebuffer\n");
755 goto rel_cmap;
756 }
757
758 dev_set_drvdata(dev, info);
759
760 if (device_create_file(dev, &dev_attr_dispregs))
761 dev_err(dev, "Can't create sysfs regdump file\n");
762 return 0;
763
764 rel_cmap:
765 fb_dealloc_cmap(&info->cmap);
766 free_irq:
767 outreg(host, GC_IMASK, 0);
768 free_irq(par->irq, (void *)par);
769 io_unmap:
770 iounmap(par->mmio_base);
771 fb_unmap:
772 iounmap(par->fb_base);
773 rel_reg:
774 release_mem_region(res.start, res_size);
775 irqdisp:
776 irq_dispose_mapping(par->irq);
777 fbrel:
778 framebuffer_release(info);
779 return ret;
780 }
781
782 static int of_platform_mb862xx_remove(struct platform_device *ofdev)
783 {
784 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
785 struct mb862xxfb_par *par = fbi->par;
786 resource_size_t res_size = resource_size(par->res);
787 unsigned long reg;
788
789 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
790
791
792 reg = inreg(disp, GC_DCM1);
793 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
794 outreg(disp, GC_DCM1, reg);
795
796
797 outreg(host, GC_IMASK, 0);
798
799 free_irq(par->irq, (void *)par);
800 irq_dispose_mapping(par->irq);
801
802 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
803
804 unregister_framebuffer(fbi);
805 fb_dealloc_cmap(&fbi->cmap);
806
807 iounmap(par->mmio_base);
808 iounmap(par->fb_base);
809
810 release_mem_region(par->res->start, res_size);
811 framebuffer_release(fbi);
812 return 0;
813 }
814
815
816
817
818 static struct of_device_id of_platform_mb862xx_tbl[] = {
819 { .compatible = "fujitsu,MB86276", },
820 { .compatible = "fujitsu,lime", },
821 { .compatible = "fujitsu,MB86277", },
822 { .compatible = "fujitsu,mint", },
823 { .compatible = "fujitsu,MB86293", },
824 { .compatible = "fujitsu,MB86294", },
825 { .compatible = "fujitsu,coral", },
826 { }
827 };
828 MODULE_DEVICE_TABLE(of, of_platform_mb862xx_tbl);
829
830 static struct platform_driver of_platform_mb862xxfb_driver = {
831 .driver = {
832 .name = DRV_NAME,
833 .of_match_table = of_platform_mb862xx_tbl,
834 },
835 .probe = of_platform_mb862xx_probe,
836 .remove = of_platform_mb862xx_remove,
837 };
838 #endif
839
840 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
841 static int coralp_init(struct mb862xxfb_par *par)
842 {
843 int cn, ver;
844
845 par->host = par->mmio_base;
846 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
847 par->disp = par->mmio_base + MB862XX_DISP_BASE;
848 par->cap = par->mmio_base + MB862XX_CAP_BASE;
849 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
850 par->geo = par->mmio_base + MB862XX_GEO_BASE;
851 par->pio = par->mmio_base + MB862XX_PIO_BASE;
852
853 par->refclk = GC_DISP_REFCLK_400;
854
855 if (par->mapped_vram >= 0x2000000) {
856
857 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
858 udelay(1);
859 }
860
861 ver = inreg(host, GC_CID);
862 cn = (ver & GC_CID_CNAME_MSK) >> 8;
863 ver = ver & GC_CID_VERSION_MSK;
864 if (cn == 3) {
865 unsigned long reg;
866
867 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
868 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
869 par->pdev->revision);
870 reg = inreg(disp, GC_DCM1);
871 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
872 par->pre_init = 1;
873
874 if (!par->pre_init) {
875 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
876 udelay(200);
877 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
878 udelay(10);
879 }
880
881 outreg(host, GC_IST, 0);
882 } else {
883 return -ENODEV;
884 }
885
886 mb862xx_i2c_init(par);
887 return 0;
888 }
889
890 static int init_dram_ctrl(struct mb862xxfb_par *par)
891 {
892 unsigned long i = 0;
893
894
895
896
897
898 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
899
900
901 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
902 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
903 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
904 GC_EVB_DCTL_REFRESH_SETTIME2);
905 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
906 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
907 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
908
909
910 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
911 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
912 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
913 dev_err(par->dev, "VRAM init failed.\n");
914 return -EINVAL;
915 }
916 }
917 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
918 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
919 return 0;
920 }
921
922 static int carmine_init(struct mb862xxfb_par *par)
923 {
924 unsigned long reg;
925
926 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
927 par->i2c = par->mmio_base + MB86297_I2C_BASE;
928 par->disp = par->mmio_base + MB86297_DISP0_BASE;
929 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
930 par->cap = par->mmio_base + MB86297_CAP0_BASE;
931 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
932 par->draw = par->mmio_base + MB86297_DRAW_BASE;
933 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
934 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
935
936 par->refclk = GC_DISP_REFCLK_533;
937
938
939 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
940 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
941
942
943 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
944 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
945 par->pdev->revision);
946 else
947 goto err_init;
948
949 reg &= ~GC_CTRL_CLK_EN_2D3D;
950 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
951
952
953 if (init_dram_ctrl(par) < 0)
954 goto err_init;
955
956 outreg(ctrl, GC_CTRL_INT_MASK, 0);
957 return 0;
958
959 err_init:
960 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
961 return -EINVAL;
962 }
963
964 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
965 {
966 switch (par->type) {
967 case BT_CORALP:
968 return coralp_init(par);
969 case BT_CARMINE:
970 return carmine_init(par);
971 default:
972 return -ENODEV;
973 }
974 }
975
976 #define CHIP_ID(id) \
977 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
978
979 static const struct pci_device_id mb862xx_pci_tbl[] = {
980
981 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
982 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
983
984 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
985 { 0, }
986 };
987
988 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
989
990 static int mb862xx_pci_probe(struct pci_dev *pdev,
991 const struct pci_device_id *ent)
992 {
993 struct mb862xxfb_par *par;
994 struct fb_info *info;
995 struct device *dev = &pdev->dev;
996 int ret;
997
998 ret = pci_enable_device(pdev);
999 if (ret < 0) {
1000 dev_err(dev, "Cannot enable PCI device\n");
1001 goto out;
1002 }
1003
1004 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1005 if (!info) {
1006 ret = -ENOMEM;
1007 goto dis_dev;
1008 }
1009
1010 par = info->par;
1011 par->info = info;
1012 par->dev = dev;
1013 par->pdev = pdev;
1014 par->irq = pdev->irq;
1015
1016 ret = pci_request_regions(pdev, DRV_NAME);
1017 if (ret < 0) {
1018 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1019 goto rel_fb;
1020 }
1021
1022 switch (pdev->device) {
1023 case PCI_DEVICE_ID_FUJITSU_CORALP:
1024 case PCI_DEVICE_ID_FUJITSU_CORALPA:
1025 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1026 par->mapped_vram = CORALP_MEM_SIZE;
1027 if (par->mapped_vram >= 0x2000000) {
1028 par->mmio_base_phys = par->fb_base_phys +
1029 MB862XX_MMIO_HIGH_BASE;
1030 } else {
1031 par->mmio_base_phys = par->fb_base_phys +
1032 MB862XX_MMIO_BASE;
1033 }
1034 par->mmio_len = MB862XX_MMIO_SIZE;
1035 par->type = BT_CORALP;
1036 break;
1037 case PCI_DEVICE_ID_FUJITSU_CARMINE:
1038 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1039 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1040 par->mmio_len = pci_resource_len(par->pdev, 3);
1041 par->mapped_vram = CARMINE_MEM_SIZE;
1042 par->type = BT_CARMINE;
1043 break;
1044 default:
1045
1046 ret = -EIO;
1047 goto rel_reg;
1048 }
1049
1050 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1051 if (par->fb_base == NULL) {
1052 dev_err(dev, "Cannot map framebuffer\n");
1053 ret = -EIO;
1054 goto rel_reg;
1055 }
1056
1057 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1058 if (par->mmio_base == NULL) {
1059 dev_err(dev, "Cannot map registers\n");
1060 ret = -EIO;
1061 goto fb_unmap;
1062 }
1063
1064 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
1065 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1066 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
1067 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1068
1069 ret = mb862xx_pci_gdc_init(par);
1070 if (ret)
1071 goto io_unmap;
1072
1073 ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1074 DRV_NAME, (void *)par);
1075 if (ret) {
1076 dev_err(dev, "Cannot request irq\n");
1077 goto io_unmap;
1078 }
1079
1080 mb862xxfb_init_fbinfo(info);
1081
1082 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1083 dev_err(dev, "Could not allocate cmap for fb_info.\n");
1084 ret = -ENOMEM;
1085 goto free_irq;
1086 }
1087
1088 if ((info->fbops->fb_set_par)(info))
1089 dev_err(dev, "set_var() failed on initial setup?\n");
1090
1091 ret = register_framebuffer(info);
1092 if (ret < 0) {
1093 dev_err(dev, "failed to register framebuffer\n");
1094 goto rel_cmap;
1095 }
1096
1097 pci_set_drvdata(pdev, info);
1098
1099 if (device_create_file(dev, &dev_attr_dispregs))
1100 dev_err(dev, "Can't create sysfs regdump file\n");
1101
1102 if (par->type == BT_CARMINE)
1103 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1104 else
1105 outreg(host, GC_IMASK, GC_INT_EN);
1106
1107 return 0;
1108
1109 rel_cmap:
1110 fb_dealloc_cmap(&info->cmap);
1111 free_irq:
1112 free_irq(par->irq, (void *)par);
1113 io_unmap:
1114 iounmap(par->mmio_base);
1115 fb_unmap:
1116 iounmap(par->fb_base);
1117 rel_reg:
1118 pci_release_regions(pdev);
1119 rel_fb:
1120 framebuffer_release(info);
1121 dis_dev:
1122 pci_disable_device(pdev);
1123 out:
1124 return ret;
1125 }
1126
1127 static void mb862xx_pci_remove(struct pci_dev *pdev)
1128 {
1129 struct fb_info *fbi = pci_get_drvdata(pdev);
1130 struct mb862xxfb_par *par = fbi->par;
1131 unsigned long reg;
1132
1133 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1134
1135
1136 reg = inreg(disp, GC_DCM1);
1137 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1138 outreg(disp, GC_DCM1, reg);
1139
1140 if (par->type == BT_CARMINE) {
1141 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1142 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1143 } else {
1144 outreg(host, GC_IMASK, 0);
1145 }
1146
1147 mb862xx_i2c_exit(par);
1148
1149 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1150
1151 unregister_framebuffer(fbi);
1152 fb_dealloc_cmap(&fbi->cmap);
1153
1154 free_irq(par->irq, (void *)par);
1155 iounmap(par->mmio_base);
1156 iounmap(par->fb_base);
1157
1158 pci_release_regions(pdev);
1159 framebuffer_release(fbi);
1160 pci_disable_device(pdev);
1161 }
1162
1163 static struct pci_driver mb862xxfb_pci_driver = {
1164 .name = DRV_NAME,
1165 .id_table = mb862xx_pci_tbl,
1166 .probe = mb862xx_pci_probe,
1167 .remove = mb862xx_pci_remove,
1168 };
1169 #endif
1170
1171 static int mb862xxfb_init(void)
1172 {
1173 int ret = -ENODEV;
1174
1175 #if defined(CONFIG_FB_MB862XX_LIME)
1176 ret = platform_driver_register(&of_platform_mb862xxfb_driver);
1177 #endif
1178 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1179 ret = pci_register_driver(&mb862xxfb_pci_driver);
1180 #endif
1181 return ret;
1182 }
1183
1184 static void __exit mb862xxfb_exit(void)
1185 {
1186 #if defined(CONFIG_FB_MB862XX_LIME)
1187 platform_driver_unregister(&of_platform_mb862xxfb_driver);
1188 #endif
1189 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1190 pci_unregister_driver(&mb862xxfb_pci_driver);
1191 #endif
1192 }
1193
1194 module_init(mb862xxfb_init);
1195 module_exit(mb862xxfb_exit);
1196
1197 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1198 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1199 MODULE_LICENSE("GPL v2");