drivers/pci/pci.h

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
pci_create_firmware_label_files
pci_remove_firmware_label_files
pci_wakeup_event
pci_has_subordinate
pci_power_manageable
pcie_downstream_port
pci_proc_attach_device
pci_proc_detach_device
pci_proc_detach_bus
pci_create_legacy_files
pci_remove_legacy_files
pci_no_msi
pci_msi_set_enable
pci_msix_clear_and_set_ctrl
pci_no_d1d2
pci_match_one_device
pci_dev_set_io_state
pci_dev_set_disconnected
pci_dev_is_disconnected
pci_dev_assign_added
pci_dev_is_added
pci_save_dpc_state
pci_restore_dpc_state
pci_ats_init
pci_restore_ats_state
pci_iov_init
pci_iov_release
pci_iov_remove
pci_restore_iov_state
pci_iov_bus_range
pci_resource_alignment
pci_dev_specific_acs_enabled
pci_dev_specific_enable_acs
pci_dev_specific_disable_acs_redir
pcie_aspm_init_link_state
pcie_aspm_exit_link_state
pcie_aspm_pm_state_change
pcie_aspm_powersave_config_link
pcie_aspm_create_sysfs_dev_files
pcie_aspm_remove_sysfs_dev_files
pcie_set_ecrc_checking
pcie_ecrc_get_policy
pci_ptm_init
pci_enable_ptm
pci_dev_specific_reset
pci_rebar_size_to_bytes
of_pci_parse_bus_range
of_get_pci_domain_nr
of_pci_get_max_link_speed
pci_set_of_node
pci_release_of_node
pci_set_bus_of_node
pci_release_bus_of_node
devm_of_pci_get_host_bridge_resources
pci_no_aer
pci_aer_init
pci_aer_exit
pci_aer_clear_fatal_status
pci_aer_clear_device_status
pci_acpi_program_hp_params
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DRIVERS_PCI_H
   3 #define DRIVERS_PCI_H
   4 
   5 #include <linux/pci.h>
   6 
   7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
   8 #define MAX_NR_DEVFNS 256
   9 
  10 #define PCI_FIND_CAP_TTL        48
  11 
  12 #define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
  13 
  14 extern const unsigned char pcie_link_speed[];
  15 extern bool pci_early_dump;
  16 
  17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  18 
  19 /* Functions internal to the PCI core code */
  20 
  21 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  22 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  23 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  24 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  25 { return; }
  26 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  27 { return; }
  28 #else
  29 void pci_create_firmware_label_files(struct pci_dev *pdev);
  30 void pci_remove_firmware_label_files(struct pci_dev *pdev);
  31 #endif
  32 void pci_cleanup_rom(struct pci_dev *dev);
  33 
  34 enum pci_mmap_api {
  35         PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  36         PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  37 };
  38 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  39                   enum pci_mmap_api mmap_api);
  40 
  41 int pci_probe_reset_function(struct pci_dev *dev);
  42 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  43 int pci_bus_error_reset(struct pci_dev *dev);
  44 
  45 #define PCI_PM_D2_DELAY         200
  46 #define PCI_PM_D3_WAIT          10
  47 #define PCI_PM_D3COLD_WAIT      100
  48 #define PCI_PM_BUS_WAIT         50
  49 
  50 /**
  51  * struct pci_platform_pm_ops - Firmware PM callbacks
  52  *
  53  * @bridge_d3: Does the bridge allow entering into D3
  54  *
  55  * @is_manageable: returns 'true' if given device is power manageable by the
  56  *                 platform firmware
  57  *
  58  * @set_state: invokes the platform firmware to set the device's power state
  59  *
  60  * @get_state: queries the platform firmware for a device's current power state
  61  *
  62  * @refresh_state: asks the platform to refresh the device's power state data
  63  *
  64  * @choose_state: returns PCI power state of given device preferred by the
  65  *                platform; to be used during system-wide transitions from a
  66  *                sleeping state to the working state and vice versa
  67  *
  68  * @set_wakeup: enables/disables wakeup capability for the device
  69  *
  70  * @need_resume: returns 'true' if the given device (which is currently
  71  *               suspended) needs to be resumed to be configured for system
  72  *               wakeup.
  73  *
  74  * If given platform is generally capable of power managing PCI devices, all of
  75  * these callbacks are mandatory.
  76  */
  77 struct pci_platform_pm_ops {
  78         bool (*bridge_d3)(struct pci_dev *dev);
  79         bool (*is_manageable)(struct pci_dev *dev);
  80         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  81         pci_power_t (*get_state)(struct pci_dev *dev);
  82         void (*refresh_state)(struct pci_dev *dev);
  83         pci_power_t (*choose_state)(struct pci_dev *dev);
  84         int (*set_wakeup)(struct pci_dev *dev, bool enable);
  85         bool (*need_resume)(struct pci_dev *dev);
  86 };
  87 
  88 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
  89 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  90 void pci_refresh_power_state(struct pci_dev *dev);
  91 void pci_power_up(struct pci_dev *dev);
  92 void pci_disable_enabled_device(struct pci_dev *dev);
  93 int pci_finish_runtime_suspend(struct pci_dev *dev);
  94 void pcie_clear_root_pme_status(struct pci_dev *dev);
  95 bool pci_check_pme_status(struct pci_dev *dev);
  96 void pci_pme_wakeup_bus(struct pci_bus *bus);
  97 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  98 void pci_pme_restore(struct pci_dev *dev);
  99 bool pci_dev_need_resume(struct pci_dev *dev);
 100 void pci_dev_adjust_pme(struct pci_dev *dev);
 101 void pci_dev_complete_resume(struct pci_dev *pci_dev);
 102 void pci_config_pm_runtime_get(struct pci_dev *dev);
 103 void pci_config_pm_runtime_put(struct pci_dev *dev);
 104 void pci_pm_init(struct pci_dev *dev);
 105 void pci_ea_init(struct pci_dev *dev);
 106 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
 107 void pci_free_cap_save_buffers(struct pci_dev *dev);
 108 bool pci_bridge_d3_possible(struct pci_dev *dev);
 109 void pci_bridge_d3_update(struct pci_dev *dev);
 110 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
 111 
 112 static inline void pci_wakeup_event(struct pci_dev *dev)
 113 {
 114         /* Wait 100 ms before the system can be put into a sleep state. */
 115         pm_wakeup_event(&dev->dev, 100);
 116 }
 117 
 118 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
 119 {
 120         return !!(pci_dev->subordinate);
 121 }
 122 
 123 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
 124 {
 125         /*
 126          * Currently we allow normal PCI devices and PCI bridges transition
 127          * into D3 if their bridge_d3 is set.
 128          */
 129         return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
 130 }
 131 
 132 static inline bool pcie_downstream_port(const struct pci_dev *dev)
 133 {
 134         int type = pci_pcie_type(dev);
 135 
 136         return type == PCI_EXP_TYPE_ROOT_PORT ||
 137                type == PCI_EXP_TYPE_DOWNSTREAM ||
 138                type == PCI_EXP_TYPE_PCIE_BRIDGE;
 139 }
 140 
 141 int pci_vpd_init(struct pci_dev *dev);
 142 void pci_vpd_release(struct pci_dev *dev);
 143 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
 144 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
 145 
 146 /* PCI Virtual Channel */
 147 int pci_save_vc_state(struct pci_dev *dev);
 148 void pci_restore_vc_state(struct pci_dev *dev);
 149 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
 150 
 151 /* PCI /proc functions */
 152 #ifdef CONFIG_PROC_FS
 153 int pci_proc_attach_device(struct pci_dev *dev);
 154 int pci_proc_detach_device(struct pci_dev *dev);
 155 int pci_proc_detach_bus(struct pci_bus *bus);
 156 #else
 157 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 158 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 159 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 160 #endif
 161 
 162 /* Functions for PCI Hotplug drivers to use */
 163 int pci_hp_add_bridge(struct pci_dev *dev);
 164 
 165 #ifdef HAVE_PCI_LEGACY
 166 void pci_create_legacy_files(struct pci_bus *bus);
 167 void pci_remove_legacy_files(struct pci_bus *bus);
 168 #else
 169 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 170 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 171 #endif
 172 
 173 /* Lock for read/write access to pci device and bus lists */
 174 extern struct rw_semaphore pci_bus_sem;
 175 extern struct mutex pci_slot_mutex;
 176 
 177 extern raw_spinlock_t pci_lock;
 178 
 179 extern unsigned int pci_pm_d3_delay;
 180 
 181 #ifdef CONFIG_PCI_MSI
 182 void pci_no_msi(void);
 183 #else
 184 static inline void pci_no_msi(void) { }
 185 #endif
 186 
 187 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
 188 {
 189         u16 control;
 190 
 191         pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 192         control &= ~PCI_MSI_FLAGS_ENABLE;
 193         if (enable)
 194                 control |= PCI_MSI_FLAGS_ENABLE;
 195         pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 196 }
 197 
 198 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
 199 {
 200         u16 ctrl;
 201 
 202         pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
 203         ctrl &= ~clear;
 204         ctrl |= set;
 205         pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
 206 }
 207 
 208 void pci_realloc_get_opt(char *);
 209 
 210 static inline int pci_no_d1d2(struct pci_dev *dev)
 211 {
 212         unsigned int parent_dstates = 0;
 213 
 214         if (dev->bus->self)
 215                 parent_dstates = dev->bus->self->no_d1d2;
 216         return (dev->no_d1d2 || parent_dstates);
 217 
 218 }
 219 extern const struct attribute_group *pci_dev_groups[];
 220 extern const struct attribute_group *pcibus_groups[];
 221 extern const struct device_type pci_dev_type;
 222 extern const struct attribute_group *pci_bus_groups[];
 223 
 224 extern unsigned long pci_hotplug_io_size;
 225 extern unsigned long pci_hotplug_mem_size;
 226 extern unsigned long pci_hotplug_bus_size;
 227 
 228 /**
 229  * pci_match_one_device - Tell if a PCI device structure has a matching
 230  *                        PCI device id structure
 231  * @id: single PCI device id structure to match
 232  * @dev: the PCI device structure to match against
 233  *
 234  * Returns the matching pci_device_id structure or %NULL if there is no match.
 235  */
 236 static inline const struct pci_device_id *
 237 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 238 {
 239         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 240             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 241             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 242             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 243             !((id->class ^ dev->class) & id->class_mask))
 244                 return id;
 245         return NULL;
 246 }
 247 
 248 /* PCI slot sysfs helper code */
 249 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 250 
 251 extern struct kset *pci_slots_kset;
 252 
 253 struct pci_slot_attribute {
 254         struct attribute attr;
 255         ssize_t (*show)(struct pci_slot *, char *);
 256         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 257 };
 258 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 259 
 260 enum pci_bar_type {
 261         pci_bar_unknown,        /* Standard PCI BAR probe */
 262         pci_bar_io,             /* An I/O port BAR */
 263         pci_bar_mem32,          /* A 32-bit memory BAR */
 264         pci_bar_mem64,          /* A 64-bit memory BAR */
 265 };
 266 
 267 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
 268 void pci_put_host_bridge_device(struct device *dev);
 269 
 270 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
 271 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 272                                 int crs_timeout);
 273 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 274                                         int crs_timeout);
 275 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
 276 
 277 int pci_setup_device(struct pci_dev *dev);
 278 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 279                     struct resource *res, unsigned int reg);
 280 void pci_configure_ari(struct pci_dev *dev);
 281 void __pci_bus_size_bridges(struct pci_bus *bus,
 282                         struct list_head *realloc_head);
 283 void __pci_bus_assign_resources(const struct pci_bus *bus,
 284                                 struct list_head *realloc_head,
 285                                 struct list_head *fail_head);
 286 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 287 
 288 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 289 void pci_disable_bridge_window(struct pci_dev *dev);
 290 struct pci_bus *pci_bus_get(struct pci_bus *bus);
 291 void pci_bus_put(struct pci_bus *bus);
 292 
 293 /* PCIe link information */
 294 #define PCIE_SPEED2STR(speed) \
 295         ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
 296          (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
 297          (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
 298          (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
 299          "Unknown speed")
 300 
 301 /* PCIe speed to Mb/s reduced by encoding overhead */
 302 #define PCIE_SPEED2MBS_ENC(speed) \
 303         ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 304          (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
 305          (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
 306          (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 307          0)
 308 
 309 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 310 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 311 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
 312                            enum pcie_link_width *width);
 313 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
 314 void pcie_report_downtraining(struct pci_dev *dev);
 315 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
 316 
 317 /* Single Root I/O Virtualization */
 318 struct pci_sriov {
 319         int             pos;            /* Capability position */
 320         int             nres;           /* Number of resources */
 321         u32             cap;            /* SR-IOV Capabilities */
 322         u16             ctrl;           /* SR-IOV Control */
 323         u16             total_VFs;      /* Total VFs associated with the PF */
 324         u16             initial_VFs;    /* Initial VFs associated with the PF */
 325         u16             num_VFs;        /* Number of VFs available */
 326         u16             offset;         /* First VF Routing ID offset */
 327         u16             stride;         /* Following VF stride */
 328         u16             vf_device;      /* VF device ID */
 329         u32             pgsz;           /* Page size for BAR alignment */
 330         u8              link;           /* Function Dependency Link */
 331         u8              max_VF_buses;   /* Max buses consumed by VFs */
 332         u16             driver_max_VFs; /* Max num VFs driver supports */
 333         struct pci_dev  *dev;           /* Lowest numbered PF */
 334         struct pci_dev  *self;          /* This PF */
 335         u32             class;          /* VF device */
 336         u8              hdr_type;       /* VF header type */
 337         u16             subsystem_vendor; /* VF subsystem vendor */
 338         u16             subsystem_device; /* VF subsystem device */
 339         resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
 340         bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 341 };
 342 
 343 /**
 344  * pci_dev_set_io_state - Set the new error state if possible.
 345  *
 346  * @dev - pci device to set new error_state
 347  * @new - the state we want dev to be in
 348  *
 349  * Must be called with device_lock held.
 350  *
 351  * Returns true if state has been changed to the requested state.
 352  */
 353 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
 354                                         pci_channel_state_t new)
 355 {
 356         bool changed = false;
 357 
 358         device_lock_assert(&dev->dev);
 359         switch (new) {
 360         case pci_channel_io_perm_failure:
 361                 switch (dev->error_state) {
 362                 case pci_channel_io_frozen:
 363                 case pci_channel_io_normal:
 364                 case pci_channel_io_perm_failure:
 365                         changed = true;
 366                         break;
 367                 }
 368                 break;
 369         case pci_channel_io_frozen:
 370                 switch (dev->error_state) {
 371                 case pci_channel_io_frozen:
 372                 case pci_channel_io_normal:
 373                         changed = true;
 374                         break;
 375                 }
 376                 break;
 377         case pci_channel_io_normal:
 378                 switch (dev->error_state) {
 379                 case pci_channel_io_frozen:
 380                 case pci_channel_io_normal:
 381                         changed = true;
 382                         break;
 383                 }
 384                 break;
 385         }
 386         if (changed)
 387                 dev->error_state = new;
 388         return changed;
 389 }
 390 
 391 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
 392 {
 393         device_lock(&dev->dev);
 394         pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
 395         device_unlock(&dev->dev);
 396 
 397         return 0;
 398 }
 399 
 400 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
 401 {
 402         return dev->error_state == pci_channel_io_perm_failure;
 403 }
 404 
 405 /* pci_dev priv_flags */
 406 #define PCI_DEV_ADDED 0
 407 
 408 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
 409 {
 410         assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
 411 }
 412 
 413 static inline bool pci_dev_is_added(const struct pci_dev *dev)
 414 {
 415         return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
 416 }
 417 
 418 #ifdef CONFIG_PCIEAER
 419 #include <linux/aer.h>
 420 
 421 #define AER_MAX_MULTI_ERR_DEVICES       5       /* Not likely to have more */
 422 
 423 struct aer_err_info {
 424         struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
 425         int error_dev_num;
 426 
 427         unsigned int id:16;
 428 
 429         unsigned int severity:2;        /* 0:NONFATAL | 1:FATAL | 2:COR */
 430         unsigned int __pad1:5;
 431         unsigned int multi_error_valid:1;
 432 
 433         unsigned int first_error:5;
 434         unsigned int __pad2:2;
 435         unsigned int tlp_header_valid:1;
 436 
 437         unsigned int status;            /* COR/UNCOR Error Status */
 438         unsigned int mask;              /* COR/UNCOR Error Mask */
 439         struct aer_header_log_regs tlp; /* TLP Header */
 440 };
 441 
 442 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
 443 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 444 #endif  /* CONFIG_PCIEAER */
 445 
 446 #ifdef CONFIG_PCIE_DPC
 447 void pci_save_dpc_state(struct pci_dev *dev);
 448 void pci_restore_dpc_state(struct pci_dev *dev);
 449 #else
 450 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
 451 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
 452 #endif
 453 
 454 #ifdef CONFIG_PCI_ATS
 455 /* Address Translation Service */
 456 void pci_ats_init(struct pci_dev *dev);
 457 void pci_restore_ats_state(struct pci_dev *dev);
 458 #else
 459 static inline void pci_ats_init(struct pci_dev *d) { }
 460 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
 461 #endif /* CONFIG_PCI_ATS */
 462 
 463 #ifdef CONFIG_PCI_IOV
 464 int pci_iov_init(struct pci_dev *dev);
 465 void pci_iov_release(struct pci_dev *dev);
 466 void pci_iov_remove(struct pci_dev *dev);
 467 void pci_iov_update_resource(struct pci_dev *dev, int resno);
 468 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 469 void pci_restore_iov_state(struct pci_dev *dev);
 470 int pci_iov_bus_range(struct pci_bus *bus);
 471 extern const struct attribute_group sriov_dev_attr_group;
 472 #else
 473 static inline int pci_iov_init(struct pci_dev *dev)
 474 {
 475         return -ENODEV;
 476 }
 477 static inline void pci_iov_release(struct pci_dev *dev)
 478 
 479 {
 480 }
 481 static inline void pci_iov_remove(struct pci_dev *dev)
 482 {
 483 }
 484 static inline void pci_restore_iov_state(struct pci_dev *dev)
 485 {
 486 }
 487 static inline int pci_iov_bus_range(struct pci_bus *bus)
 488 {
 489         return 0;
 490 }
 491 
 492 #endif /* CONFIG_PCI_IOV */
 493 
 494 unsigned long pci_cardbus_resource_alignment(struct resource *);
 495 
 496 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 497                                                      struct resource *res)
 498 {
 499 #ifdef CONFIG_PCI_IOV
 500         int resno = res - dev->resource;
 501 
 502         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 503                 return pci_sriov_resource_alignment(dev, resno);
 504 #endif
 505         if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
 506                 return pci_cardbus_resource_alignment(res);
 507         return resource_alignment(res);
 508 }
 509 
 510 void pci_enable_acs(struct pci_dev *dev);
 511 #ifdef CONFIG_PCI_QUIRKS
 512 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
 513 int pci_dev_specific_enable_acs(struct pci_dev *dev);
 514 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
 515 #else
 516 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
 517                                                u16 acs_flags)
 518 {
 519         return -ENOTTY;
 520 }
 521 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
 522 {
 523         return -ENOTTY;
 524 }
 525 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
 526 {
 527         return -ENOTTY;
 528 }
 529 #endif
 530 
 531 /* PCI error reporting and recovery */
 532 void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
 533                       u32 service);
 534 
 535 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
 536 #ifdef CONFIG_PCIEASPM
 537 void pcie_aspm_init_link_state(struct pci_dev *pdev);
 538 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 539 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 540 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 541 #else
 542 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
 543 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
 544 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
 545 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 546 #endif
 547 
 548 #ifdef CONFIG_PCIEASPM_DEBUG
 549 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
 550 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
 551 #else
 552 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
 553 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
 554 #endif
 555 
 556 #ifdef CONFIG_PCIE_ECRC
 557 void pcie_set_ecrc_checking(struct pci_dev *dev);
 558 void pcie_ecrc_get_policy(char *str);
 559 #else
 560 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
 561 static inline void pcie_ecrc_get_policy(char *str) { }
 562 #endif
 563 
 564 #ifdef CONFIG_PCIE_PTM
 565 void pci_ptm_init(struct pci_dev *dev);
 566 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
 567 #else
 568 static inline void pci_ptm_init(struct pci_dev *dev) { }
 569 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
 570 { return -EINVAL; }
 571 #endif
 572 
 573 struct pci_dev_reset_methods {
 574         u16 vendor;
 575         u16 device;
 576         int (*reset)(struct pci_dev *dev, int probe);
 577 };
 578 
 579 #ifdef CONFIG_PCI_QUIRKS
 580 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 581 #else
 582 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 583 {
 584         return -ENOTTY;
 585 }
 586 #endif
 587 
 588 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
 589 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 590                           struct resource *res);
 591 #endif
 592 
 593 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
 594 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
 595 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
 596 static inline u64 pci_rebar_size_to_bytes(int size)
 597 {
 598         return 1ULL << (size + 20);
 599 }
 600 
 601 struct device_node;
 602 
 603 #ifdef CONFIG_OF
 604 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 605 int of_get_pci_domain_nr(struct device_node *node);
 606 int of_pci_get_max_link_speed(struct device_node *node);
 607 void pci_set_of_node(struct pci_dev *dev);
 608 void pci_release_of_node(struct pci_dev *dev);
 609 void pci_set_bus_of_node(struct pci_bus *bus);
 610 void pci_release_bus_of_node(struct pci_bus *bus);
 611 
 612 #else
 613 static inline int
 614 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
 615 {
 616         return -EINVAL;
 617 }
 618 
 619 static inline int
 620 of_get_pci_domain_nr(struct device_node *node)
 621 {
 622         return -1;
 623 }
 624 
 625 static inline int
 626 of_pci_get_max_link_speed(struct device_node *node)
 627 {
 628         return -EINVAL;
 629 }
 630 
 631 static inline void pci_set_of_node(struct pci_dev *dev) { }
 632 static inline void pci_release_of_node(struct pci_dev *dev) { }
 633 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
 634 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
 635 #endif /* CONFIG_OF */
 636 
 637 #if defined(CONFIG_OF_ADDRESS)
 638 int devm_of_pci_get_host_bridge_resources(struct device *dev,
 639                         unsigned char busno, unsigned char bus_max,
 640                         struct list_head *resources, resource_size_t *io_base);
 641 #else
 642 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
 643                         unsigned char busno, unsigned char bus_max,
 644                         struct list_head *resources, resource_size_t *io_base)
 645 {
 646         return -EINVAL;
 647 }
 648 #endif
 649 
 650 #ifdef CONFIG_PCIEAER
 651 void pci_no_aer(void);
 652 void pci_aer_init(struct pci_dev *dev);
 653 void pci_aer_exit(struct pci_dev *dev);
 654 extern const struct attribute_group aer_stats_attr_group;
 655 void pci_aer_clear_fatal_status(struct pci_dev *dev);
 656 void pci_aer_clear_device_status(struct pci_dev *dev);
 657 #else
 658 static inline void pci_no_aer(void) { }
 659 static inline void pci_aer_init(struct pci_dev *d) { }
 660 static inline void pci_aer_exit(struct pci_dev *d) { }
 661 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
 662 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
 663 #endif
 664 
 665 #ifdef CONFIG_ACPI
 666 int pci_acpi_program_hp_params(struct pci_dev *dev);
 667 #else
 668 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
 669 {
 670         return -ENODEV;
 671 }
 672 #endif
 673 
 674 #endif /* DRIVERS_PCI_H */
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pci/pci.h

INCLUDED FROM

DEFINITIONS
