This source file includes following definitions.
- spear13xx_pcie_establish_link
- spear13xx_pcie_irq_handler
- spear13xx_pcie_enable_interrupts
- spear13xx_pcie_link_up
- spear13xx_pcie_host_init
- spear13xx_add_pcie_port
- spear13xx_pcie_probe
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12 #include <linux/clk.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/of.h>
17 #include <linux/pci.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/resource.h>
21
22 #include "pcie-designware.h"
23
24 struct spear13xx_pcie {
25 struct dw_pcie *pci;
26 void __iomem *app_base;
27 struct phy *phy;
28 struct clk *clk;
29 bool is_gen1;
30 };
31
32 struct pcie_app_reg {
33 u32 app_ctrl_0;
34 u32 app_ctrl_1;
35 u32 app_status_0;
36 u32 app_status_1;
37 u32 msg_status;
38 u32 msg_payload;
39 u32 int_sts;
40 u32 int_clr;
41 u32 int_mask;
42 u32 mst_bmisc;
43 u32 phy_ctrl;
44 u32 phy_status;
45 u32 cxpl_debug_info_0;
46 u32 cxpl_debug_info_1;
47 u32 ven_msg_ctrl_0;
48 u32 ven_msg_ctrl_1;
49 u32 ven_msg_data_0;
50 u32 ven_msg_data_1;
51 u32 ven_msi_0;
52 u32 ven_msi_1;
53 u32 mst_rmisc;
54 };
55
56
57 #define APP_LTSSM_ENABLE_ID 3
58 #define DEVICE_TYPE_RC (4 << 25)
59 #define MISCTRL_EN_ID 30
60 #define REG_TRANSLATION_ENABLE 31
61
62
63 #define XMLH_LINK_UP (1 << 6)
64
65
66 #define MSI_CTRL_INT (1 << 26)
67
68 #define EXP_CAP_ID_OFFSET 0x70
69
70 #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
71
72 static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
73 {
74 struct dw_pcie *pci = spear13xx_pcie->pci;
75 struct pcie_port *pp = &pci->pp;
76 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
77 u32 val;
78 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
79
80 if (dw_pcie_link_up(pci)) {
81 dev_err(pci->dev, "link already up\n");
82 return 0;
83 }
84
85 dw_pcie_setup_rc(pp);
86
87
88
89
90
91
92 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
93 val &= ~PCI_EXP_DEVCTL_READRQ;
94 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
95
96 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
97 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
98
99
100
101
102
103 if (spear13xx_pcie->is_gen1) {
104 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
105 4, &val);
106 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
107 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
108 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
109 dw_pcie_write(pci->dbi_base + exp_cap_off +
110 PCI_EXP_LNKCAP, 4, val);
111 }
112
113 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
114 2, &val);
115 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
116 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
117 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
118 dw_pcie_write(pci->dbi_base + exp_cap_off +
119 PCI_EXP_LNKCTL2, 2, val);
120 }
121 }
122
123
124 writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
125 | (1 << APP_LTSSM_ENABLE_ID)
126 | ((u32)1 << REG_TRANSLATION_ENABLE),
127 &app_reg->app_ctrl_0);
128
129 return dw_pcie_wait_for_link(pci);
130 }
131
132 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
133 {
134 struct spear13xx_pcie *spear13xx_pcie = arg;
135 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
136 struct dw_pcie *pci = spear13xx_pcie->pci;
137 struct pcie_port *pp = &pci->pp;
138 unsigned int status;
139
140 status = readl(&app_reg->int_sts);
141
142 if (status & MSI_CTRL_INT) {
143 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
144 dw_handle_msi_irq(pp);
145 }
146
147 writel(status, &app_reg->int_clr);
148
149 return IRQ_HANDLED;
150 }
151
152 static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
153 {
154 struct dw_pcie *pci = spear13xx_pcie->pci;
155 struct pcie_port *pp = &pci->pp;
156 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
157
158
159 if (IS_ENABLED(CONFIG_PCI_MSI)) {
160 dw_pcie_msi_init(pp);
161 writel(readl(&app_reg->int_mask) |
162 MSI_CTRL_INT, &app_reg->int_mask);
163 }
164 }
165
166 static int spear13xx_pcie_link_up(struct dw_pcie *pci)
167 {
168 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
169 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
170
171 if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
172 return 1;
173
174 return 0;
175 }
176
177 static int spear13xx_pcie_host_init(struct pcie_port *pp)
178 {
179 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
180 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
181
182 spear13xx_pcie_establish_link(spear13xx_pcie);
183 spear13xx_pcie_enable_interrupts(spear13xx_pcie);
184
185 return 0;
186 }
187
188 static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
189 .host_init = spear13xx_pcie_host_init,
190 };
191
192 static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
193 struct platform_device *pdev)
194 {
195 struct dw_pcie *pci = spear13xx_pcie->pci;
196 struct pcie_port *pp = &pci->pp;
197 struct device *dev = &pdev->dev;
198 int ret;
199
200 pp->irq = platform_get_irq(pdev, 0);
201 if (pp->irq < 0) {
202 dev_err(dev, "failed to get irq\n");
203 return pp->irq;
204 }
205 ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
206 IRQF_SHARED | IRQF_NO_THREAD,
207 "spear1340-pcie", spear13xx_pcie);
208 if (ret) {
209 dev_err(dev, "failed to request irq %d\n", pp->irq);
210 return ret;
211 }
212
213 pp->ops = &spear13xx_pcie_host_ops;
214
215 ret = dw_pcie_host_init(pp);
216 if (ret) {
217 dev_err(dev, "failed to initialize host\n");
218 return ret;
219 }
220
221 return 0;
222 }
223
224 static const struct dw_pcie_ops dw_pcie_ops = {
225 .link_up = spear13xx_pcie_link_up,
226 };
227
228 static int spear13xx_pcie_probe(struct platform_device *pdev)
229 {
230 struct device *dev = &pdev->dev;
231 struct dw_pcie *pci;
232 struct spear13xx_pcie *spear13xx_pcie;
233 struct device_node *np = dev->of_node;
234 struct resource *dbi_base;
235 int ret;
236
237 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
238 if (!spear13xx_pcie)
239 return -ENOMEM;
240
241 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
242 if (!pci)
243 return -ENOMEM;
244
245 pci->dev = dev;
246 pci->ops = &dw_pcie_ops;
247
248 spear13xx_pcie->pci = pci;
249
250 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
251 if (IS_ERR(spear13xx_pcie->phy)) {
252 ret = PTR_ERR(spear13xx_pcie->phy);
253 if (ret == -EPROBE_DEFER)
254 dev_info(dev, "probe deferred\n");
255 else
256 dev_err(dev, "couldn't get pcie-phy\n");
257 return ret;
258 }
259
260 phy_init(spear13xx_pcie->phy);
261
262 spear13xx_pcie->clk = devm_clk_get(dev, NULL);
263 if (IS_ERR(spear13xx_pcie->clk)) {
264 dev_err(dev, "couldn't get clk for pcie\n");
265 return PTR_ERR(spear13xx_pcie->clk);
266 }
267 ret = clk_prepare_enable(spear13xx_pcie->clk);
268 if (ret) {
269 dev_err(dev, "couldn't enable clk for pcie\n");
270 return ret;
271 }
272
273 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
274 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
275 if (IS_ERR(pci->dbi_base)) {
276 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
277 ret = PTR_ERR(pci->dbi_base);
278 goto fail_clk;
279 }
280 spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
281
282 if (of_property_read_bool(np, "st,pcie-is-gen1"))
283 spear13xx_pcie->is_gen1 = true;
284
285 platform_set_drvdata(pdev, spear13xx_pcie);
286
287 ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
288 if (ret < 0)
289 goto fail_clk;
290
291 return 0;
292
293 fail_clk:
294 clk_disable_unprepare(spear13xx_pcie->clk);
295
296 return ret;
297 }
298
299 static const struct of_device_id spear13xx_pcie_of_match[] = {
300 { .compatible = "st,spear1340-pcie", },
301 {},
302 };
303
304 static struct platform_driver spear13xx_pcie_driver = {
305 .probe = spear13xx_pcie_probe,
306 .driver = {
307 .name = "spear-pcie",
308 .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
309 .suppress_bind_attrs = true,
310 },
311 };
312
313 builtin_platform_driver(spear13xx_pcie_driver);