This source file includes following definitions.
- dw_pcie_rd_own_conf
- dw_pcie_wr_own_conf
- dw_msi_ack_irq
- dw_msi_mask_irq
- dw_msi_unmask_irq
- dw_handle_msi_irq
- dw_chained_msi_isr
- dw_pci_setup_msi_msg
- dw_pci_msi_set_affinity
- dw_pci_bottom_mask
- dw_pci_bottom_unmask
- dw_pci_bottom_ack
- dw_pcie_irq_domain_alloc
- dw_pcie_irq_domain_free
- dw_pcie_allocate_domains
- dw_pcie_free_msi
- dw_pcie_msi_init
- dw_pcie_host_init
- dw_pcie_host_deinit
- dw_pcie_access_other_conf
- dw_pcie_rd_other_conf
- dw_pcie_wr_other_conf
- dw_pcie_valid_device
- dw_pcie_rd_conf
- dw_pcie_wr_conf
- dw_pcie_setup_rc
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11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/of_address.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci_regs.h>
16 #include <linux/platform_device.h>
17
18 #include "../../pci.h"
19 #include "pcie-designware.h"
20
21 static struct pci_ops dw_pcie_ops;
22
23 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
24 u32 *val)
25 {
26 struct dw_pcie *pci;
27
28 if (pp->ops->rd_own_conf)
29 return pp->ops->rd_own_conf(pp, where, size, val);
30
31 pci = to_dw_pcie_from_pp(pp);
32 return dw_pcie_read(pci->dbi_base + where, size, val);
33 }
34
35 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
36 u32 val)
37 {
38 struct dw_pcie *pci;
39
40 if (pp->ops->wr_own_conf)
41 return pp->ops->wr_own_conf(pp, where, size, val);
42
43 pci = to_dw_pcie_from_pp(pp);
44 return dw_pcie_write(pci->dbi_base + where, size, val);
45 }
46
47 static void dw_msi_ack_irq(struct irq_data *d)
48 {
49 irq_chip_ack_parent(d);
50 }
51
52 static void dw_msi_mask_irq(struct irq_data *d)
53 {
54 pci_msi_mask_irq(d);
55 irq_chip_mask_parent(d);
56 }
57
58 static void dw_msi_unmask_irq(struct irq_data *d)
59 {
60 pci_msi_unmask_irq(d);
61 irq_chip_unmask_parent(d);
62 }
63
64 static struct irq_chip dw_pcie_msi_irq_chip = {
65 .name = "PCI-MSI",
66 .irq_ack = dw_msi_ack_irq,
67 .irq_mask = dw_msi_mask_irq,
68 .irq_unmask = dw_msi_unmask_irq,
69 };
70
71 static struct msi_domain_info dw_pcie_msi_domain_info = {
72 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
73 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
74 .chip = &dw_pcie_msi_irq_chip,
75 };
76
77
78 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
79 {
80 int i, pos, irq;
81 unsigned long val;
82 u32 status, num_ctrls;
83 irqreturn_t ret = IRQ_NONE;
84
85 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
86
87 for (i = 0; i < num_ctrls; i++) {
88 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
89 (i * MSI_REG_CTRL_BLOCK_SIZE),
90 4, &status);
91 if (!status)
92 continue;
93
94 ret = IRQ_HANDLED;
95 val = status;
96 pos = 0;
97 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
98 pos)) != MAX_MSI_IRQS_PER_CTRL) {
99 irq = irq_find_mapping(pp->irq_domain,
100 (i * MAX_MSI_IRQS_PER_CTRL) +
101 pos);
102 generic_handle_irq(irq);
103 pos++;
104 }
105 }
106
107 return ret;
108 }
109
110
111 static void dw_chained_msi_isr(struct irq_desc *desc)
112 {
113 struct irq_chip *chip = irq_desc_get_chip(desc);
114 struct pcie_port *pp;
115
116 chained_irq_enter(chip, desc);
117
118 pp = irq_desc_get_handler_data(desc);
119 dw_handle_msi_irq(pp);
120
121 chained_irq_exit(chip, desc);
122 }
123
124 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
125 {
126 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
128 u64 msi_target;
129
130 msi_target = (u64)pp->msi_data;
131
132 msg->address_lo = lower_32_bits(msi_target);
133 msg->address_hi = upper_32_bits(msi_target);
134
135 msg->data = d->hwirq;
136
137 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
138 (int)d->hwirq, msg->address_hi, msg->address_lo);
139 }
140
141 static int dw_pci_msi_set_affinity(struct irq_data *d,
142 const struct cpumask *mask, bool force)
143 {
144 return -EINVAL;
145 }
146
147 static void dw_pci_bottom_mask(struct irq_data *d)
148 {
149 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
150 unsigned int res, bit, ctrl;
151 unsigned long flags;
152
153 raw_spin_lock_irqsave(&pp->lock, flags);
154
155 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
156 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
157 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
158
159 pp->irq_mask[ctrl] |= BIT(bit);
160 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
161 pp->irq_mask[ctrl]);
162
163 raw_spin_unlock_irqrestore(&pp->lock, flags);
164 }
165
166 static void dw_pci_bottom_unmask(struct irq_data *d)
167 {
168 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
169 unsigned int res, bit, ctrl;
170 unsigned long flags;
171
172 raw_spin_lock_irqsave(&pp->lock, flags);
173
174 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
175 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
176 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
177
178 pp->irq_mask[ctrl] &= ~BIT(bit);
179 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4,
180 pp->irq_mask[ctrl]);
181
182 raw_spin_unlock_irqrestore(&pp->lock, flags);
183 }
184
185 static void dw_pci_bottom_ack(struct irq_data *d)
186 {
187 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
188 unsigned int res, bit, ctrl;
189
190 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
191 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
192 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
193
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit));
195 }
196
197 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
198 .name = "DWPCI-MSI",
199 .irq_ack = dw_pci_bottom_ack,
200 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
201 .irq_set_affinity = dw_pci_msi_set_affinity,
202 .irq_mask = dw_pci_bottom_mask,
203 .irq_unmask = dw_pci_bottom_unmask,
204 };
205
206 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
207 unsigned int virq, unsigned int nr_irqs,
208 void *args)
209 {
210 struct pcie_port *pp = domain->host_data;
211 unsigned long flags;
212 u32 i;
213 int bit;
214
215 raw_spin_lock_irqsave(&pp->lock, flags);
216
217 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
218 order_base_2(nr_irqs));
219
220 raw_spin_unlock_irqrestore(&pp->lock, flags);
221
222 if (bit < 0)
223 return -ENOSPC;
224
225 for (i = 0; i < nr_irqs; i++)
226 irq_domain_set_info(domain, virq + i, bit + i,
227 pp->msi_irq_chip,
228 pp, handle_edge_irq,
229 NULL, NULL);
230
231 return 0;
232 }
233
234 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
235 unsigned int virq, unsigned int nr_irqs)
236 {
237 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
238 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
239 unsigned long flags;
240
241 raw_spin_lock_irqsave(&pp->lock, flags);
242
243 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
244 order_base_2(nr_irqs));
245
246 raw_spin_unlock_irqrestore(&pp->lock, flags);
247 }
248
249 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
250 .alloc = dw_pcie_irq_domain_alloc,
251 .free = dw_pcie_irq_domain_free,
252 };
253
254 int dw_pcie_allocate_domains(struct pcie_port *pp)
255 {
256 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
257 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
258
259 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
260 &dw_pcie_msi_domain_ops, pp);
261 if (!pp->irq_domain) {
262 dev_err(pci->dev, "Failed to create IRQ domain\n");
263 return -ENOMEM;
264 }
265
266 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
267 &dw_pcie_msi_domain_info,
268 pp->irq_domain);
269 if (!pp->msi_domain) {
270 dev_err(pci->dev, "Failed to create MSI domain\n");
271 irq_domain_remove(pp->irq_domain);
272 return -ENOMEM;
273 }
274
275 return 0;
276 }
277
278 void dw_pcie_free_msi(struct pcie_port *pp)
279 {
280 if (pp->msi_irq) {
281 irq_set_chained_handler(pp->msi_irq, NULL);
282 irq_set_handler_data(pp->msi_irq, NULL);
283 }
284
285 irq_domain_remove(pp->msi_domain);
286 irq_domain_remove(pp->irq_domain);
287
288 if (pp->msi_page)
289 __free_page(pp->msi_page);
290 }
291
292 void dw_pcie_msi_init(struct pcie_port *pp)
293 {
294 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
295 struct device *dev = pci->dev;
296 u64 msi_target;
297
298 pp->msi_page = alloc_page(GFP_KERNEL);
299 pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE,
300 DMA_FROM_DEVICE);
301 if (dma_mapping_error(dev, pp->msi_data)) {
302 dev_err(dev, "Failed to map MSI data\n");
303 __free_page(pp->msi_page);
304 pp->msi_page = NULL;
305 return;
306 }
307 msi_target = (u64)pp->msi_data;
308
309
310 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
311 lower_32_bits(msi_target));
312 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
313 upper_32_bits(msi_target));
314 }
315 EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
316
317 int dw_pcie_host_init(struct pcie_port *pp)
318 {
319 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
320 struct device *dev = pci->dev;
321 struct device_node *np = dev->of_node;
322 struct platform_device *pdev = to_platform_device(dev);
323 struct resource_entry *win, *tmp;
324 struct pci_bus *child;
325 struct pci_host_bridge *bridge;
326 struct resource *cfg_res;
327 u32 hdr_type;
328 int ret;
329
330 raw_spin_lock_init(&pci->pp.lock);
331
332 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
333 if (cfg_res) {
334 pp->cfg0_size = resource_size(cfg_res) >> 1;
335 pp->cfg1_size = resource_size(cfg_res) >> 1;
336 pp->cfg0_base = cfg_res->start;
337 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
338 } else if (!pp->va_cfg0_base) {
339 dev_err(dev, "Missing *config* reg space\n");
340 }
341
342 bridge = devm_pci_alloc_host_bridge(dev, 0);
343 if (!bridge)
344 return -ENOMEM;
345
346 ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
347 &bridge->windows, &pp->io_base);
348 if (ret)
349 return ret;
350
351 ret = devm_request_pci_bus_resources(dev, &bridge->windows);
352 if (ret)
353 return ret;
354
355
356 resource_list_for_each_entry_safe(win, tmp, &bridge->windows) {
357 switch (resource_type(win->res)) {
358 case IORESOURCE_IO:
359 ret = devm_pci_remap_iospace(dev, win->res,
360 pp->io_base);
361 if (ret) {
362 dev_warn(dev, "Error %d: failed to map resource %pR\n",
363 ret, win->res);
364 resource_list_destroy_entry(win);
365 } else {
366 pp->io = win->res;
367 pp->io->name = "I/O";
368 pp->io_size = resource_size(pp->io);
369 pp->io_bus_addr = pp->io->start - win->offset;
370 }
371 break;
372 case IORESOURCE_MEM:
373 pp->mem = win->res;
374 pp->mem->name = "MEM";
375 pp->mem_size = resource_size(pp->mem);
376 pp->mem_bus_addr = pp->mem->start - win->offset;
377 break;
378 case 0:
379 pp->cfg = win->res;
380 pp->cfg0_size = resource_size(pp->cfg) >> 1;
381 pp->cfg1_size = resource_size(pp->cfg) >> 1;
382 pp->cfg0_base = pp->cfg->start;
383 pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
384 break;
385 case IORESOURCE_BUS:
386 pp->busn = win->res;
387 break;
388 }
389 }
390
391 if (!pci->dbi_base) {
392 pci->dbi_base = devm_pci_remap_cfgspace(dev,
393 pp->cfg->start,
394 resource_size(pp->cfg));
395 if (!pci->dbi_base) {
396 dev_err(dev, "Error with ioremap\n");
397 return -ENOMEM;
398 }
399 }
400
401 pp->mem_base = pp->mem->start;
402
403 if (!pp->va_cfg0_base) {
404 pp->va_cfg0_base = devm_pci_remap_cfgspace(dev,
405 pp->cfg0_base, pp->cfg0_size);
406 if (!pp->va_cfg0_base) {
407 dev_err(dev, "Error with ioremap in function\n");
408 return -ENOMEM;
409 }
410 }
411
412 if (!pp->va_cfg1_base) {
413 pp->va_cfg1_base = devm_pci_remap_cfgspace(dev,
414 pp->cfg1_base,
415 pp->cfg1_size);
416 if (!pp->va_cfg1_base) {
417 dev_err(dev, "Error with ioremap\n");
418 return -ENOMEM;
419 }
420 }
421
422 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
423 if (ret)
424 pci->num_viewport = 2;
425
426 if (pci_msi_enabled()) {
427
428
429
430
431
432 if (!pp->ops->set_num_vectors) {
433 pp->num_vectors = MSI_DEF_NUM_VECTORS;
434 } else {
435 pp->ops->set_num_vectors(pp);
436
437 if (pp->num_vectors > MAX_MSI_IRQS ||
438 pp->num_vectors == 0) {
439 dev_err(dev,
440 "Invalid number of vectors\n");
441 return -EINVAL;
442 }
443 }
444
445 if (!pp->ops->msi_host_init) {
446 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
447
448 ret = dw_pcie_allocate_domains(pp);
449 if (ret)
450 return ret;
451
452 if (pp->msi_irq)
453 irq_set_chained_handler_and_data(pp->msi_irq,
454 dw_chained_msi_isr,
455 pp);
456 } else {
457 ret = pp->ops->msi_host_init(pp);
458 if (ret < 0)
459 return ret;
460 }
461 }
462
463 if (pp->ops->host_init) {
464 ret = pp->ops->host_init(pp);
465 if (ret)
466 goto err_free_msi;
467 }
468
469 ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type);
470 if (ret != PCIBIOS_SUCCESSFUL) {
471 dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n",
472 ret);
473 ret = pcibios_err_to_errno(ret);
474 goto err_free_msi;
475 }
476 if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
477 dev_err(pci->dev,
478 "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
479 hdr_type);
480 ret = -EIO;
481 goto err_free_msi;
482 }
483
484 pp->root_bus_nr = pp->busn->start;
485
486 bridge->dev.parent = dev;
487 bridge->sysdata = pp;
488 bridge->busnr = pp->root_bus_nr;
489 bridge->ops = &dw_pcie_ops;
490 bridge->map_irq = of_irq_parse_and_map_pci;
491 bridge->swizzle_irq = pci_common_swizzle;
492
493 ret = pci_scan_root_bus_bridge(bridge);
494 if (ret)
495 goto err_free_msi;
496
497 pp->root_bus = bridge->bus;
498
499 if (pp->ops->scan_bus)
500 pp->ops->scan_bus(pp);
501
502 pci_bus_size_bridges(pp->root_bus);
503 pci_bus_assign_resources(pp->root_bus);
504
505 list_for_each_entry(child, &pp->root_bus->children, node)
506 pcie_bus_configure_settings(child);
507
508 pci_bus_add_devices(pp->root_bus);
509 return 0;
510
511 err_free_msi:
512 if (pci_msi_enabled() && !pp->ops->msi_host_init)
513 dw_pcie_free_msi(pp);
514 return ret;
515 }
516 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
517
518 void dw_pcie_host_deinit(struct pcie_port *pp)
519 {
520 pci_stop_root_bus(pp->root_bus);
521 pci_remove_root_bus(pp->root_bus);
522 if (pci_msi_enabled() && !pp->ops->msi_host_init)
523 dw_pcie_free_msi(pp);
524 }
525 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
526
527 static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
528 u32 devfn, int where, int size, u32 *val,
529 bool write)
530 {
531 int ret, type;
532 u32 busdev, cfg_size;
533 u64 cpu_addr;
534 void __iomem *va_cfg_base;
535 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
536
537 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
538 PCIE_ATU_FUNC(PCI_FUNC(devfn));
539
540 if (bus->parent->number == pp->root_bus_nr) {
541 type = PCIE_ATU_TYPE_CFG0;
542 cpu_addr = pp->cfg0_base;
543 cfg_size = pp->cfg0_size;
544 va_cfg_base = pp->va_cfg0_base;
545 } else {
546 type = PCIE_ATU_TYPE_CFG1;
547 cpu_addr = pp->cfg1_base;
548 cfg_size = pp->cfg1_size;
549 va_cfg_base = pp->va_cfg1_base;
550 }
551
552 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
553 type, cpu_addr,
554 busdev, cfg_size);
555 if (write)
556 ret = dw_pcie_write(va_cfg_base + where, size, *val);
557 else
558 ret = dw_pcie_read(va_cfg_base + where, size, val);
559
560 if (pci->num_viewport <= 2)
561 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
562 PCIE_ATU_TYPE_IO, pp->io_base,
563 pp->io_bus_addr, pp->io_size);
564
565 return ret;
566 }
567
568 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
569 u32 devfn, int where, int size, u32 *val)
570 {
571 if (pp->ops->rd_other_conf)
572 return pp->ops->rd_other_conf(pp, bus, devfn, where,
573 size, val);
574
575 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val,
576 false);
577 }
578
579 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
580 u32 devfn, int where, int size, u32 val)
581 {
582 if (pp->ops->wr_other_conf)
583 return pp->ops->wr_other_conf(pp, bus, devfn, where,
584 size, val);
585
586 return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val,
587 true);
588 }
589
590 static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
591 int dev)
592 {
593 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
594
595
596 if (bus->number != pp->root_bus_nr) {
597 if (!dw_pcie_link_up(pci))
598 return 0;
599 }
600
601
602 if (bus->number == pp->root_bus_nr && dev > 0)
603 return 0;
604
605 return 1;
606 }
607
608 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
609 int size, u32 *val)
610 {
611 struct pcie_port *pp = bus->sysdata;
612
613 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
614 *val = 0xffffffff;
615 return PCIBIOS_DEVICE_NOT_FOUND;
616 }
617
618 if (bus->number == pp->root_bus_nr)
619 return dw_pcie_rd_own_conf(pp, where, size, val);
620
621 return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
622 }
623
624 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
625 int where, int size, u32 val)
626 {
627 struct pcie_port *pp = bus->sysdata;
628
629 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
630 return PCIBIOS_DEVICE_NOT_FOUND;
631
632 if (bus->number == pp->root_bus_nr)
633 return dw_pcie_wr_own_conf(pp, where, size, val);
634
635 return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
636 }
637
638 static struct pci_ops dw_pcie_ops = {
639 .read = dw_pcie_rd_conf,
640 .write = dw_pcie_wr_conf,
641 };
642
643 void dw_pcie_setup_rc(struct pcie_port *pp)
644 {
645 u32 val, ctrl, num_ctrls;
646 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
647
648
649
650
651
652 dw_pcie_dbi_ro_wr_en(pci);
653
654 dw_pcie_setup(pci);
655
656 if (!pp->ops->msi_host_init) {
657 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
658
659
660 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
661 pp->irq_mask[ctrl] = ~0;
662 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK +
663 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
664 4, pp->irq_mask[ctrl]);
665 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
666 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
667 4, ~0);
668 }
669 }
670
671
672 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
673 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
674
675
676 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
677 val &= 0xffff00ff;
678 val |= 0x00000100;
679 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
680
681
682 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
683 val &= 0xff000000;
684 val |= 0x00ff0100;
685 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
686
687
688 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
689 val &= 0xffff0000;
690 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
691 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
692 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
693
694
695
696
697
698
699 if (!pp->ops->rd_other_conf) {
700 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
701 PCIE_ATU_TYPE_MEM, pp->mem_base,
702 pp->mem_bus_addr, pp->mem_size);
703 if (pci->num_viewport > 2)
704 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
705 PCIE_ATU_TYPE_IO, pp->io_base,
706 pp->io_bus_addr, pp->io_size);
707 }
708
709 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
710
711
712 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
713
714 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
715 val |= PORT_LOGIC_SPEED_CHANGE;
716 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
717
718 dw_pcie_dbi_ro_wr_dis(pci);
719 }
720 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);