root/drivers/pci/controller/dwc/pci-imx6.c

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DEFINITIONS

This source file includes following definitions.
  1. pcie_phy_poll_ack
  2. pcie_phy_wait_ack
  3. pcie_phy_read
  4. pcie_phy_write
  5. imx6_pcie_reset_phy
  6. imx6q_pcie_abort_handler
  7. imx6_pcie_attach_pd
  8. imx6_pcie_assert_core_reset
  9. imx6_pcie_grp_offset
  10. imx6_pcie_enable_ref_clk
  11. imx7d_pcie_wait_for_phy_pll_lock
  12. imx6_pcie_deassert_core_reset
  13. imx6_pcie_configure_type
  14. imx6_pcie_init_phy
  15. imx6_setup_phy_mpll
  16. imx6_pcie_wait_for_speed_change
  17. imx6_pcie_ltssm_enable
  18. imx6_pcie_establish_link
  19. imx6_pcie_host_init
  20. imx6_add_pcie_port
  21. imx6_pcie_ltssm_disable
  22. imx6_pcie_pm_turnoff
  23. imx6_pcie_clk_disable
  24. imx6_pcie_suspend_noirq
  25. imx6_pcie_resume_noirq
  26. imx6_pcie_probe
  27. imx6_pcie_shutdown
  28. imx6_pcie_quirk
  29. imx6_pcie_init

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCIe host controller driver for Freescale i.MX6 SoCs
   4  *
   5  * Copyright (C) 2013 Kosagi
   6  *              http://www.kosagi.com
   7  *
   8  * Author: Sean Cross <xobs@kosagi.com>
   9  */
  10 
  11 #include <linux/bitfield.h>
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/gpio.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
  19 #include <linux/module.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_address.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/resource.h>
  28 #include <linux/signal.h>
  29 #include <linux/types.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/reset.h>
  32 #include <linux/pm_domain.h>
  33 #include <linux/pm_runtime.h>
  34 
  35 #include "pcie-designware.h"
  36 
  37 #define IMX8MQ_GPR_PCIE_REF_USE_PAD             BIT(9)
  38 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN     BIT(10)
  39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE        BIT(11)
  40 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE     GENMASK(11, 8)
  41 #define IMX8MQ_PCIE2_BASE_ADDR                  0x33c00000
  42 
  43 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
  44 
  45 enum imx6_pcie_variants {
  46         IMX6Q,
  47         IMX6SX,
  48         IMX6QP,
  49         IMX7D,
  50         IMX8MQ,
  51 };
  52 
  53 #define IMX6_PCIE_FLAG_IMX6_PHY                 BIT(0)
  54 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE        BIT(1)
  55 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND         BIT(2)
  56 
  57 struct imx6_pcie_drvdata {
  58         enum imx6_pcie_variants variant;
  59         u32 flags;
  60         int dbi_length;
  61 };
  62 
  63 struct imx6_pcie {
  64         struct dw_pcie          *pci;
  65         int                     reset_gpio;
  66         bool                    gpio_active_high;
  67         struct clk              *pcie_bus;
  68         struct clk              *pcie_phy;
  69         struct clk              *pcie_inbound_axi;
  70         struct clk              *pcie;
  71         struct clk              *pcie_aux;
  72         struct regmap           *iomuxc_gpr;
  73         u32                     controller_id;
  74         struct reset_control    *pciephy_reset;
  75         struct reset_control    *apps_reset;
  76         struct reset_control    *turnoff_reset;
  77         u32                     tx_deemph_gen1;
  78         u32                     tx_deemph_gen2_3p5db;
  79         u32                     tx_deemph_gen2_6db;
  80         u32                     tx_swing_full;
  81         u32                     tx_swing_low;
  82         int                     link_gen;
  83         struct regulator        *vpcie;
  84         void __iomem            *phy_base;
  85 
  86         /* power domain for pcie */
  87         struct device           *pd_pcie;
  88         /* power domain for pcie phy */
  89         struct device           *pd_pcie_phy;
  90         const struct imx6_pcie_drvdata *drvdata;
  91 };
  92 
  93 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
  94 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX    200
  95 #define PHY_PLL_LOCK_WAIT_TIMEOUT       (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
  96 
  97 /* PCIe Root Complex registers (memory-mapped) */
  98 #define PCIE_RC_IMX6_MSI_CAP                    0x50
  99 #define PCIE_RC_LCR                             0x7c
 100 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1        0x1
 101 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2        0x2
 102 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK        0xf
 103 
 104 #define PCIE_RC_LCSR                            0x80
 105 
 106 /* PCIe Port Logic registers (memory-mapped) */
 107 #define PL_OFFSET 0x700
 108 
 109 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
 110 #define PCIE_PHY_CTRL_DATA(x)           FIELD_PREP(GENMASK(15, 0), (x))
 111 #define PCIE_PHY_CTRL_CAP_ADR           BIT(16)
 112 #define PCIE_PHY_CTRL_CAP_DAT           BIT(17)
 113 #define PCIE_PHY_CTRL_WR                BIT(18)
 114 #define PCIE_PHY_CTRL_RD                BIT(19)
 115 
 116 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
 117 #define PCIE_PHY_STAT_ACK               BIT(16)
 118 
 119 #define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
 120 
 121 /* PHY registers (not memory-mapped) */
 122 #define PCIE_PHY_ATEOVRD                        0x10
 123 #define  PCIE_PHY_ATEOVRD_EN                    BIT(2)
 124 #define  PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT      0
 125 #define  PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK       0x1
 126 
 127 #define PCIE_PHY_MPLL_OVRD_IN_LO                0x11
 128 #define  PCIE_PHY_MPLL_MULTIPLIER_SHIFT         2
 129 #define  PCIE_PHY_MPLL_MULTIPLIER_MASK          0x7f
 130 #define  PCIE_PHY_MPLL_MULTIPLIER_OVRD          BIT(9)
 131 
 132 #define PCIE_PHY_RX_ASIC_OUT 0x100D
 133 #define PCIE_PHY_RX_ASIC_OUT_VALID      (1 << 0)
 134 
 135 /* iMX7 PCIe PHY registers */
 136 #define PCIE_PHY_CMN_REG4               0x14
 137 /* These are probably the bits that *aren't* DCC_FB_EN */
 138 #define PCIE_PHY_CMN_REG4_DCC_FB_EN     0x29
 139 
 140 #define PCIE_PHY_CMN_REG15              0x54
 141 #define PCIE_PHY_CMN_REG15_DLY_4        BIT(2)
 142 #define PCIE_PHY_CMN_REG15_PLL_PD       BIT(5)
 143 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD  BIT(7)
 144 
 145 #define PCIE_PHY_CMN_REG24              0x90
 146 #define PCIE_PHY_CMN_REG24_RX_EQ        BIT(6)
 147 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL    BIT(3)
 148 
 149 #define PCIE_PHY_CMN_REG26              0x98
 150 #define PCIE_PHY_CMN_REG26_ATT_MODE     0xBC
 151 
 152 #define PHY_RX_OVRD_IN_LO 0x1005
 153 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN            BIT(5)
 154 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN             BIT(3)
 155 
 156 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
 157 {
 158         struct dw_pcie *pci = imx6_pcie->pci;
 159         bool val;
 160         u32 max_iterations = 10;
 161         u32 wait_counter = 0;
 162 
 163         do {
 164                 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
 165                         PCIE_PHY_STAT_ACK;
 166                 wait_counter++;
 167 
 168                 if (val == exp_val)
 169                         return 0;
 170 
 171                 udelay(1);
 172         } while (wait_counter < max_iterations);
 173 
 174         return -ETIMEDOUT;
 175 }
 176 
 177 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
 178 {
 179         struct dw_pcie *pci = imx6_pcie->pci;
 180         u32 val;
 181         int ret;
 182 
 183         val = PCIE_PHY_CTRL_DATA(addr);
 184         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 185 
 186         val |= PCIE_PHY_CTRL_CAP_ADR;
 187         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 188 
 189         ret = pcie_phy_poll_ack(imx6_pcie, true);
 190         if (ret)
 191                 return ret;
 192 
 193         val = PCIE_PHY_CTRL_DATA(addr);
 194         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 195 
 196         return pcie_phy_poll_ack(imx6_pcie, false);
 197 }
 198 
 199 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
 200 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
 201 {
 202         struct dw_pcie *pci = imx6_pcie->pci;
 203         u32 phy_ctl;
 204         int ret;
 205 
 206         ret = pcie_phy_wait_ack(imx6_pcie, addr);
 207         if (ret)
 208                 return ret;
 209 
 210         /* assert Read signal */
 211         phy_ctl = PCIE_PHY_CTRL_RD;
 212         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
 213 
 214         ret = pcie_phy_poll_ack(imx6_pcie, true);
 215         if (ret)
 216                 return ret;
 217 
 218         *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
 219 
 220         /* deassert Read signal */
 221         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
 222 
 223         return pcie_phy_poll_ack(imx6_pcie, false);
 224 }
 225 
 226 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
 227 {
 228         struct dw_pcie *pci = imx6_pcie->pci;
 229         u32 var;
 230         int ret;
 231 
 232         /* write addr */
 233         /* cap addr */
 234         ret = pcie_phy_wait_ack(imx6_pcie, addr);
 235         if (ret)
 236                 return ret;
 237 
 238         var = PCIE_PHY_CTRL_DATA(data);
 239         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 240 
 241         /* capture data */
 242         var |= PCIE_PHY_CTRL_CAP_DAT;
 243         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 244 
 245         ret = pcie_phy_poll_ack(imx6_pcie, true);
 246         if (ret)
 247                 return ret;
 248 
 249         /* deassert cap data */
 250         var = PCIE_PHY_CTRL_DATA(data);
 251         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 252 
 253         /* wait for ack de-assertion */
 254         ret = pcie_phy_poll_ack(imx6_pcie, false);
 255         if (ret)
 256                 return ret;
 257 
 258         /* assert wr signal */
 259         var = PCIE_PHY_CTRL_WR;
 260         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 261 
 262         /* wait for ack */
 263         ret = pcie_phy_poll_ack(imx6_pcie, true);
 264         if (ret)
 265                 return ret;
 266 
 267         /* deassert wr signal */
 268         var = PCIE_PHY_CTRL_DATA(data);
 269         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 270 
 271         /* wait for ack de-assertion */
 272         ret = pcie_phy_poll_ack(imx6_pcie, false);
 273         if (ret)
 274                 return ret;
 275 
 276         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
 277 
 278         return 0;
 279 }
 280 
 281 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
 282 {
 283         u16 tmp;
 284 
 285         if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
 286                 return;
 287 
 288         pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 289         tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 290                 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 291         pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
 292 
 293         usleep_range(2000, 3000);
 294 
 295         pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 296         tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 297                   PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 298         pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
 299 }
 300 
 301 #ifdef CONFIG_ARM
 302 /*  Added for PCI abort handling */
 303 static int imx6q_pcie_abort_handler(unsigned long addr,
 304                 unsigned int fsr, struct pt_regs *regs)
 305 {
 306         unsigned long pc = instruction_pointer(regs);
 307         unsigned long instr = *(unsigned long *)pc;
 308         int reg = (instr >> 12) & 15;
 309 
 310         /*
 311          * If the instruction being executed was a read,
 312          * make it look like it read all-ones.
 313          */
 314         if ((instr & 0x0c100000) == 0x04100000) {
 315                 unsigned long val;
 316 
 317                 if (instr & 0x00400000)
 318                         val = 255;
 319                 else
 320                         val = -1;
 321 
 322                 regs->uregs[reg] = val;
 323                 regs->ARM_pc += 4;
 324                 return 0;
 325         }
 326 
 327         if ((instr & 0x0e100090) == 0x00100090) {
 328                 regs->uregs[reg] = -1;
 329                 regs->ARM_pc += 4;
 330                 return 0;
 331         }
 332 
 333         return 1;
 334 }
 335 #endif
 336 
 337 static int imx6_pcie_attach_pd(struct device *dev)
 338 {
 339         struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 340         struct device_link *link;
 341 
 342         /* Do nothing when in a single power domain */
 343         if (dev->pm_domain)
 344                 return 0;
 345 
 346         imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
 347         if (IS_ERR(imx6_pcie->pd_pcie))
 348                 return PTR_ERR(imx6_pcie->pd_pcie);
 349         /* Do nothing when power domain missing */
 350         if (!imx6_pcie->pd_pcie)
 351                 return 0;
 352         link = device_link_add(dev, imx6_pcie->pd_pcie,
 353                         DL_FLAG_STATELESS |
 354                         DL_FLAG_PM_RUNTIME |
 355                         DL_FLAG_RPM_ACTIVE);
 356         if (!link) {
 357                 dev_err(dev, "Failed to add device_link to pcie pd.\n");
 358                 return -EINVAL;
 359         }
 360 
 361         imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
 362         if (IS_ERR(imx6_pcie->pd_pcie_phy))
 363                 return PTR_ERR(imx6_pcie->pd_pcie_phy);
 364 
 365         link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
 366                         DL_FLAG_STATELESS |
 367                         DL_FLAG_PM_RUNTIME |
 368                         DL_FLAG_RPM_ACTIVE);
 369         if (!link) {
 370                 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
 371                 return -EINVAL;
 372         }
 373 
 374         return 0;
 375 }
 376 
 377 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 378 {
 379         struct device *dev = imx6_pcie->pci->dev;
 380 
 381         switch (imx6_pcie->drvdata->variant) {
 382         case IMX7D:
 383         case IMX8MQ:
 384                 reset_control_assert(imx6_pcie->pciephy_reset);
 385                 reset_control_assert(imx6_pcie->apps_reset);
 386                 break;
 387         case IMX6SX:
 388                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 389                                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
 390                                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
 391                 /* Force PCIe PHY reset */
 392                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
 393                                    IMX6SX_GPR5_PCIE_BTNRST_RESET,
 394                                    IMX6SX_GPR5_PCIE_BTNRST_RESET);
 395                 break;
 396         case IMX6QP:
 397                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 398                                    IMX6Q_GPR1_PCIE_SW_RST,
 399                                    IMX6Q_GPR1_PCIE_SW_RST);
 400                 break;
 401         case IMX6Q:
 402                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 403                                    IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 404                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 405                                    IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
 406                 break;
 407         }
 408 
 409         if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
 410                 int ret = regulator_disable(imx6_pcie->vpcie);
 411 
 412                 if (ret)
 413                         dev_err(dev, "failed to disable vpcie regulator: %d\n",
 414                                 ret);
 415         }
 416 }
 417 
 418 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 419 {
 420         WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
 421         return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 422 }
 423 
 424 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 425 {
 426         struct dw_pcie *pci = imx6_pcie->pci;
 427         struct device *dev = pci->dev;
 428         unsigned int offset;
 429         int ret = 0;
 430 
 431         switch (imx6_pcie->drvdata->variant) {
 432         case IMX6SX:
 433                 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
 434                 if (ret) {
 435                         dev_err(dev, "unable to enable pcie_axi clock\n");
 436                         break;
 437                 }
 438 
 439                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 440                                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
 441                 break;
 442         case IMX6QP:            /* FALLTHROUGH */
 443         case IMX6Q:
 444                 /* power up core phy and enable ref clock */
 445                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 446                                    IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
 447                 /*
 448                  * the async reset input need ref clock to sync internally,
 449                  * when the ref clock comes after reset, internal synced
 450                  * reset time is too short, cannot meet the requirement.
 451                  * add one ~10us delay here.
 452                  */
 453                 usleep_range(10, 100);
 454                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 455                                    IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 456                 break;
 457         case IMX7D:
 458                 break;
 459         case IMX8MQ:
 460                 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
 461                 if (ret) {
 462                         dev_err(dev, "unable to enable pcie_aux clock\n");
 463                         break;
 464                 }
 465 
 466                 offset = imx6_pcie_grp_offset(imx6_pcie);
 467                 /*
 468                  * Set the over ride low and enabled
 469                  * make sure that REF_CLK is turned on.
 470                  */
 471                 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
 472                                    IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
 473                                    0);
 474                 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
 475                                    IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
 476                                    IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
 477                 break;
 478         }
 479 
 480         return ret;
 481 }
 482 
 483 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
 484 {
 485         u32 val;
 486         struct device *dev = imx6_pcie->pci->dev;
 487 
 488         if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
 489                                      IOMUXC_GPR22, val,
 490                                      val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
 491                                      PHY_PLL_LOCK_WAIT_USLEEP_MAX,
 492                                      PHY_PLL_LOCK_WAIT_TIMEOUT))
 493                 dev_err(dev, "PCIe PLL lock timeout\n");
 494 }
 495 
 496 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 497 {
 498         struct dw_pcie *pci = imx6_pcie->pci;
 499         struct device *dev = pci->dev;
 500         int ret;
 501 
 502         if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
 503                 ret = regulator_enable(imx6_pcie->vpcie);
 504                 if (ret) {
 505                         dev_err(dev, "failed to enable vpcie regulator: %d\n",
 506                                 ret);
 507                         return;
 508                 }
 509         }
 510 
 511         ret = clk_prepare_enable(imx6_pcie->pcie_phy);
 512         if (ret) {
 513                 dev_err(dev, "unable to enable pcie_phy clock\n");
 514                 goto err_pcie_phy;
 515         }
 516 
 517         ret = clk_prepare_enable(imx6_pcie->pcie_bus);
 518         if (ret) {
 519                 dev_err(dev, "unable to enable pcie_bus clock\n");
 520                 goto err_pcie_bus;
 521         }
 522 
 523         ret = clk_prepare_enable(imx6_pcie->pcie);
 524         if (ret) {
 525                 dev_err(dev, "unable to enable pcie clock\n");
 526                 goto err_pcie;
 527         }
 528 
 529         ret = imx6_pcie_enable_ref_clk(imx6_pcie);
 530         if (ret) {
 531                 dev_err(dev, "unable to enable pcie ref clock\n");
 532                 goto err_ref_clk;
 533         }
 534 
 535         /* allow the clocks to stabilize */
 536         usleep_range(200, 500);
 537 
 538         /* Some boards don't have PCIe reset GPIO. */
 539         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 540                 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
 541                                         imx6_pcie->gpio_active_high);
 542                 msleep(100);
 543                 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
 544                                         !imx6_pcie->gpio_active_high);
 545         }
 546 
 547         switch (imx6_pcie->drvdata->variant) {
 548         case IMX8MQ:
 549                 reset_control_deassert(imx6_pcie->pciephy_reset);
 550                 break;
 551         case IMX7D:
 552                 reset_control_deassert(imx6_pcie->pciephy_reset);
 553 
 554                 /* Workaround for ERR010728, failure of PCI-e PLL VCO to
 555                  * oscillate, especially when cold.  This turns off "Duty-cycle
 556                  * Corrector" and other mysterious undocumented things.
 557                  */
 558                 if (likely(imx6_pcie->phy_base)) {
 559                         /* De-assert DCC_FB_EN */
 560                         writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
 561                                imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
 562                         /* Assert RX_EQS and RX_EQS_SEL */
 563                         writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
 564                                 | PCIE_PHY_CMN_REG24_RX_EQ,
 565                                imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
 566                         /* Assert ATT_MODE */
 567                         writel(PCIE_PHY_CMN_REG26_ATT_MODE,
 568                                imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
 569                 } else {
 570                         dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
 571                 }
 572 
 573                 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
 574                 break;
 575         case IMX6SX:
 576                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
 577                                    IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
 578                 break;
 579         case IMX6QP:
 580                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 581                                    IMX6Q_GPR1_PCIE_SW_RST, 0);
 582 
 583                 usleep_range(200, 500);
 584                 break;
 585         case IMX6Q:             /* Nothing to do */
 586                 break;
 587         }
 588 
 589         return;
 590 
 591 err_ref_clk:
 592         clk_disable_unprepare(imx6_pcie->pcie);
 593 err_pcie:
 594         clk_disable_unprepare(imx6_pcie->pcie_bus);
 595 err_pcie_bus:
 596         clk_disable_unprepare(imx6_pcie->pcie_phy);
 597 err_pcie_phy:
 598         if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
 599                 ret = regulator_disable(imx6_pcie->vpcie);
 600                 if (ret)
 601                         dev_err(dev, "failed to disable vpcie regulator: %d\n",
 602                                 ret);
 603         }
 604 }
 605 
 606 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 607 {
 608         unsigned int mask, val;
 609 
 610         if (imx6_pcie->drvdata->variant == IMX8MQ &&
 611             imx6_pcie->controller_id == 1) {
 612                 mask   = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
 613                 val    = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
 614                                     PCI_EXP_TYPE_ROOT_PORT);
 615         } else {
 616                 mask = IMX6Q_GPR12_DEVICE_TYPE;
 617                 val  = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
 618                                   PCI_EXP_TYPE_ROOT_PORT);
 619         }
 620 
 621         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
 622 }
 623 
 624 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 625 {
 626         switch (imx6_pcie->drvdata->variant) {
 627         case IMX8MQ:
 628                 /*
 629                  * TODO: Currently this code assumes external
 630                  * oscillator is being used
 631                  */
 632                 regmap_update_bits(imx6_pcie->iomuxc_gpr,
 633                                    imx6_pcie_grp_offset(imx6_pcie),
 634                                    IMX8MQ_GPR_PCIE_REF_USE_PAD,
 635                                    IMX8MQ_GPR_PCIE_REF_USE_PAD);
 636                 break;
 637         case IMX7D:
 638                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 639                                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
 640                 break;
 641         case IMX6SX:
 642                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 643                                    IMX6SX_GPR12_PCIE_RX_EQ_MASK,
 644                                    IMX6SX_GPR12_PCIE_RX_EQ_2);
 645                 /* FALLTHROUGH */
 646         default:
 647                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 648                                    IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 649 
 650                 /* configure constant input signal to the pcie ctrl and phy */
 651                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 652                                    IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
 653 
 654                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 655                                    IMX6Q_GPR8_TX_DEEMPH_GEN1,
 656                                    imx6_pcie->tx_deemph_gen1 << 0);
 657                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 658                                    IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
 659                                    imx6_pcie->tx_deemph_gen2_3p5db << 6);
 660                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 661                                    IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
 662                                    imx6_pcie->tx_deemph_gen2_6db << 12);
 663                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 664                                    IMX6Q_GPR8_TX_SWING_FULL,
 665                                    imx6_pcie->tx_swing_full << 18);
 666                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 667                                    IMX6Q_GPR8_TX_SWING_LOW,
 668                                    imx6_pcie->tx_swing_low << 25);
 669                 break;
 670         }
 671 
 672         imx6_pcie_configure_type(imx6_pcie);
 673 }
 674 
 675 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
 676 {
 677         unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
 678         int mult, div;
 679         u16 val;
 680 
 681         if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
 682                 return 0;
 683 
 684         switch (phy_rate) {
 685         case 125000000:
 686                 /*
 687                  * The default settings of the MPLL are for a 125MHz input
 688                  * clock, so no need to reconfigure anything in that case.
 689                  */
 690                 return 0;
 691         case 100000000:
 692                 mult = 25;
 693                 div = 0;
 694                 break;
 695         case 200000000:
 696                 mult = 25;
 697                 div = 1;
 698                 break;
 699         default:
 700                 dev_err(imx6_pcie->pci->dev,
 701                         "Unsupported PHY reference clock rate %lu\n", phy_rate);
 702                 return -EINVAL;
 703         }
 704 
 705         pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
 706         val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
 707                  PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
 708         val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
 709         val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
 710         pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
 711 
 712         pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
 713         val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
 714                  PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
 715         val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
 716         val |= PCIE_PHY_ATEOVRD_EN;
 717         pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
 718 
 719         return 0;
 720 }
 721 
 722 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
 723 {
 724         struct dw_pcie *pci = imx6_pcie->pci;
 725         struct device *dev = pci->dev;
 726         u32 tmp;
 727         unsigned int retries;
 728 
 729         for (retries = 0; retries < 200; retries++) {
 730                 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 731                 /* Test if the speed change finished. */
 732                 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
 733                         return 0;
 734                 usleep_range(100, 1000);
 735         }
 736 
 737         dev_err(dev, "Speed change timeout\n");
 738         return -ETIMEDOUT;
 739 }
 740 
 741 static void imx6_pcie_ltssm_enable(struct device *dev)
 742 {
 743         struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 744 
 745         switch (imx6_pcie->drvdata->variant) {
 746         case IMX6Q:
 747         case IMX6SX:
 748         case IMX6QP:
 749                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 750                                    IMX6Q_GPR12_PCIE_CTL_2,
 751                                    IMX6Q_GPR12_PCIE_CTL_2);
 752                 break;
 753         case IMX7D:
 754         case IMX8MQ:
 755                 reset_control_deassert(imx6_pcie->apps_reset);
 756                 break;
 757         }
 758 }
 759 
 760 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
 761 {
 762         struct dw_pcie *pci = imx6_pcie->pci;
 763         struct device *dev = pci->dev;
 764         u32 tmp;
 765         int ret;
 766 
 767         /*
 768          * Force Gen1 operation when starting the link.  In case the link is
 769          * started in Gen2 mode, there is a possibility the devices on the
 770          * bus will not be detected at all.  This happens with PCIe switches.
 771          */
 772         tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
 773         tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 774         tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
 775         dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
 776 
 777         /* Start LTSSM. */
 778         imx6_pcie_ltssm_enable(dev);
 779 
 780         ret = dw_pcie_wait_for_link(pci);
 781         if (ret)
 782                 goto err_reset_phy;
 783 
 784         if (imx6_pcie->link_gen == 2) {
 785                 /* Allow Gen2 mode after the link is up. */
 786                 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
 787                 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 788                 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
 789                 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
 790 
 791                 /*
 792                  * Start Directed Speed Change so the best possible
 793                  * speed both link partners support can be negotiated.
 794                  */
 795                 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 796                 tmp |= PORT_LOGIC_SPEED_CHANGE;
 797                 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
 798 
 799                 if (imx6_pcie->drvdata->flags &
 800                     IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
 801                         /*
 802                          * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
 803                          * from i.MX6 family when no link speed transition
 804                          * occurs and we go Gen1 -> yep, Gen1. The difference
 805                          * is that, in such case, it will not be cleared by HW
 806                          * which will cause the following code to report false
 807                          * failure.
 808                          */
 809 
 810                         ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
 811                         if (ret) {
 812                                 dev_err(dev, "Failed to bring link up!\n");
 813                                 goto err_reset_phy;
 814                         }
 815                 }
 816 
 817                 /* Make sure link training is finished as well! */
 818                 ret = dw_pcie_wait_for_link(pci);
 819                 if (ret) {
 820                         dev_err(dev, "Failed to bring link up!\n");
 821                         goto err_reset_phy;
 822                 }
 823         } else {
 824                 dev_info(dev, "Link: Gen2 disabled\n");
 825         }
 826 
 827         tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
 828         dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
 829         return 0;
 830 
 831 err_reset_phy:
 832         dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
 833                 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
 834                 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
 835         imx6_pcie_reset_phy(imx6_pcie);
 836         return ret;
 837 }
 838 
 839 static int imx6_pcie_host_init(struct pcie_port *pp)
 840 {
 841         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 842         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
 843 
 844         imx6_pcie_assert_core_reset(imx6_pcie);
 845         imx6_pcie_init_phy(imx6_pcie);
 846         imx6_pcie_deassert_core_reset(imx6_pcie);
 847         imx6_setup_phy_mpll(imx6_pcie);
 848         dw_pcie_setup_rc(pp);
 849         imx6_pcie_establish_link(imx6_pcie);
 850 
 851         if (IS_ENABLED(CONFIG_PCI_MSI))
 852                 dw_pcie_msi_init(pp);
 853 
 854         return 0;
 855 }
 856 
 857 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
 858         .host_init = imx6_pcie_host_init,
 859 };
 860 
 861 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
 862                               struct platform_device *pdev)
 863 {
 864         struct dw_pcie *pci = imx6_pcie->pci;
 865         struct pcie_port *pp = &pci->pp;
 866         struct device *dev = &pdev->dev;
 867         int ret;
 868 
 869         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 870                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 871                 if (pp->msi_irq <= 0) {
 872                         dev_err(dev, "failed to get MSI irq\n");
 873                         return -ENODEV;
 874                 }
 875         }
 876 
 877         pp->ops = &imx6_pcie_host_ops;
 878 
 879         ret = dw_pcie_host_init(pp);
 880         if (ret) {
 881                 dev_err(dev, "failed to initialize host\n");
 882                 return ret;
 883         }
 884 
 885         return 0;
 886 }
 887 
 888 static const struct dw_pcie_ops dw_pcie_ops = {
 889         /* No special ops needed, but pcie-designware still expects this struct */
 890 };
 891 
 892 #ifdef CONFIG_PM_SLEEP
 893 static void imx6_pcie_ltssm_disable(struct device *dev)
 894 {
 895         struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 896 
 897         switch (imx6_pcie->drvdata->variant) {
 898         case IMX6SX:
 899         case IMX6QP:
 900                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 901                                    IMX6Q_GPR12_PCIE_CTL_2, 0);
 902                 break;
 903         case IMX7D:
 904                 reset_control_assert(imx6_pcie->apps_reset);
 905                 break;
 906         default:
 907                 dev_err(dev, "ltssm_disable not supported\n");
 908         }
 909 }
 910 
 911 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
 912 {
 913         struct device *dev = imx6_pcie->pci->dev;
 914 
 915         /* Some variants have a turnoff reset in DT */
 916         if (imx6_pcie->turnoff_reset) {
 917                 reset_control_assert(imx6_pcie->turnoff_reset);
 918                 reset_control_deassert(imx6_pcie->turnoff_reset);
 919                 goto pm_turnoff_sleep;
 920         }
 921 
 922         /* Others poke directly at IOMUXC registers */
 923         switch (imx6_pcie->drvdata->variant) {
 924         case IMX6SX:
 925                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 926                                 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
 927                                 IMX6SX_GPR12_PCIE_PM_TURN_OFF);
 928                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 929                                 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
 930                 break;
 931         default:
 932                 dev_err(dev, "PME_Turn_Off not implemented\n");
 933                 return;
 934         }
 935 
 936         /*
 937          * Components with an upstream port must respond to
 938          * PME_Turn_Off with PME_TO_Ack but we can't check.
 939          *
 940          * The standard recommends a 1-10ms timeout after which to
 941          * proceed anyway as if acks were received.
 942          */
 943 pm_turnoff_sleep:
 944         usleep_range(1000, 10000);
 945 }
 946 
 947 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
 948 {
 949         clk_disable_unprepare(imx6_pcie->pcie);
 950         clk_disable_unprepare(imx6_pcie->pcie_phy);
 951         clk_disable_unprepare(imx6_pcie->pcie_bus);
 952 
 953         switch (imx6_pcie->drvdata->variant) {
 954         case IMX6SX:
 955                 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
 956                 break;
 957         case IMX7D:
 958                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 959                                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
 960                                    IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
 961                 break;
 962         case IMX8MQ:
 963                 clk_disable_unprepare(imx6_pcie->pcie_aux);
 964                 break;
 965         default:
 966                 break;
 967         }
 968 }
 969 
 970 static int imx6_pcie_suspend_noirq(struct device *dev)
 971 {
 972         struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 973 
 974         if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
 975                 return 0;
 976 
 977         imx6_pcie_pm_turnoff(imx6_pcie);
 978         imx6_pcie_clk_disable(imx6_pcie);
 979         imx6_pcie_ltssm_disable(dev);
 980 
 981         return 0;
 982 }
 983 
 984 static int imx6_pcie_resume_noirq(struct device *dev)
 985 {
 986         int ret;
 987         struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 988         struct pcie_port *pp = &imx6_pcie->pci->pp;
 989 
 990         if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
 991                 return 0;
 992 
 993         imx6_pcie_assert_core_reset(imx6_pcie);
 994         imx6_pcie_init_phy(imx6_pcie);
 995         imx6_pcie_deassert_core_reset(imx6_pcie);
 996         dw_pcie_setup_rc(pp);
 997 
 998         ret = imx6_pcie_establish_link(imx6_pcie);
 999         if (ret < 0)
1000                 dev_info(dev, "pcie link is down after resume.\n");
1001 
1002         return 0;
1003 }
1004 #endif
1005 
1006 static const struct dev_pm_ops imx6_pcie_pm_ops = {
1007         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
1008                                       imx6_pcie_resume_noirq)
1009 };
1010 
1011 static int imx6_pcie_probe(struct platform_device *pdev)
1012 {
1013         struct device *dev = &pdev->dev;
1014         struct dw_pcie *pci;
1015         struct imx6_pcie *imx6_pcie;
1016         struct device_node *np;
1017         struct resource *dbi_base;
1018         struct device_node *node = dev->of_node;
1019         int ret;
1020         u16 val;
1021 
1022         imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
1023         if (!imx6_pcie)
1024                 return -ENOMEM;
1025 
1026         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1027         if (!pci)
1028                 return -ENOMEM;
1029 
1030         pci->dev = dev;
1031         pci->ops = &dw_pcie_ops;
1032 
1033         imx6_pcie->pci = pci;
1034         imx6_pcie->drvdata = of_device_get_match_data(dev);
1035 
1036         /* Find the PHY if one is defined, only imx7d uses it */
1037         np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1038         if (np) {
1039                 struct resource res;
1040 
1041                 ret = of_address_to_resource(np, 0, &res);
1042                 if (ret) {
1043                         dev_err(dev, "Unable to map PCIe PHY\n");
1044                         return ret;
1045                 }
1046                 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1047                 if (IS_ERR(imx6_pcie->phy_base)) {
1048                         dev_err(dev, "Unable to map PCIe PHY\n");
1049                         return PTR_ERR(imx6_pcie->phy_base);
1050                 }
1051         }
1052 
1053         dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1054         pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
1055         if (IS_ERR(pci->dbi_base))
1056                 return PTR_ERR(pci->dbi_base);
1057 
1058         /* Fetch GPIOs */
1059         imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1060         imx6_pcie->gpio_active_high = of_property_read_bool(node,
1061                                                 "reset-gpio-active-high");
1062         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1063                 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1064                                 imx6_pcie->gpio_active_high ?
1065                                         GPIOF_OUT_INIT_HIGH :
1066                                         GPIOF_OUT_INIT_LOW,
1067                                 "PCIe reset");
1068                 if (ret) {
1069                         dev_err(dev, "unable to get reset gpio\n");
1070                         return ret;
1071                 }
1072         } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1073                 return imx6_pcie->reset_gpio;
1074         }
1075 
1076         /* Fetch clocks */
1077         imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1078         if (IS_ERR(imx6_pcie->pcie_phy)) {
1079                 dev_err(dev, "pcie_phy clock source missing or invalid\n");
1080                 return PTR_ERR(imx6_pcie->pcie_phy);
1081         }
1082 
1083         imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1084         if (IS_ERR(imx6_pcie->pcie_bus)) {
1085                 dev_err(dev, "pcie_bus clock source missing or invalid\n");
1086                 return PTR_ERR(imx6_pcie->pcie_bus);
1087         }
1088 
1089         imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1090         if (IS_ERR(imx6_pcie->pcie)) {
1091                 dev_err(dev, "pcie clock source missing or invalid\n");
1092                 return PTR_ERR(imx6_pcie->pcie);
1093         }
1094 
1095         switch (imx6_pcie->drvdata->variant) {
1096         case IMX6SX:
1097                 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1098                                                            "pcie_inbound_axi");
1099                 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
1100                         dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
1101                         return PTR_ERR(imx6_pcie->pcie_inbound_axi);
1102                 }
1103                 break;
1104         case IMX8MQ:
1105                 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1106                 if (IS_ERR(imx6_pcie->pcie_aux)) {
1107                         dev_err(dev, "pcie_aux clock source missing or invalid\n");
1108                         return PTR_ERR(imx6_pcie->pcie_aux);
1109                 }
1110                 /* fall through */
1111         case IMX7D:
1112                 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1113                         imx6_pcie->controller_id = 1;
1114 
1115                 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1116                                                                             "pciephy");
1117                 if (IS_ERR(imx6_pcie->pciephy_reset)) {
1118                         dev_err(dev, "Failed to get PCIEPHY reset control\n");
1119                         return PTR_ERR(imx6_pcie->pciephy_reset);
1120                 }
1121 
1122                 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1123                                                                          "apps");
1124                 if (IS_ERR(imx6_pcie->apps_reset)) {
1125                         dev_err(dev, "Failed to get PCIE APPS reset control\n");
1126                         return PTR_ERR(imx6_pcie->apps_reset);
1127                 }
1128                 break;
1129         default:
1130                 break;
1131         }
1132 
1133         /* Grab turnoff reset */
1134         imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1135         if (IS_ERR(imx6_pcie->turnoff_reset)) {
1136                 dev_err(dev, "Failed to get TURNOFF reset control\n");
1137                 return PTR_ERR(imx6_pcie->turnoff_reset);
1138         }
1139 
1140         /* Grab GPR config register range */
1141         imx6_pcie->iomuxc_gpr =
1142                  syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1143         if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1144                 dev_err(dev, "unable to find iomuxc registers\n");
1145                 return PTR_ERR(imx6_pcie->iomuxc_gpr);
1146         }
1147 
1148         /* Grab PCIe PHY Tx Settings */
1149         if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1150                                  &imx6_pcie->tx_deemph_gen1))
1151                 imx6_pcie->tx_deemph_gen1 = 0;
1152 
1153         if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1154                                  &imx6_pcie->tx_deemph_gen2_3p5db))
1155                 imx6_pcie->tx_deemph_gen2_3p5db = 0;
1156 
1157         if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1158                                  &imx6_pcie->tx_deemph_gen2_6db))
1159                 imx6_pcie->tx_deemph_gen2_6db = 20;
1160 
1161         if (of_property_read_u32(node, "fsl,tx-swing-full",
1162                                  &imx6_pcie->tx_swing_full))
1163                 imx6_pcie->tx_swing_full = 127;
1164 
1165         if (of_property_read_u32(node, "fsl,tx-swing-low",
1166                                  &imx6_pcie->tx_swing_low))
1167                 imx6_pcie->tx_swing_low = 127;
1168 
1169         /* Limit link speed */
1170         ret = of_property_read_u32(node, "fsl,max-link-speed",
1171                                    &imx6_pcie->link_gen);
1172         if (ret)
1173                 imx6_pcie->link_gen = 1;
1174 
1175         imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1176         if (IS_ERR(imx6_pcie->vpcie)) {
1177                 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
1178                         return PTR_ERR(imx6_pcie->vpcie);
1179                 imx6_pcie->vpcie = NULL;
1180         }
1181 
1182         platform_set_drvdata(pdev, imx6_pcie);
1183 
1184         ret = imx6_pcie_attach_pd(dev);
1185         if (ret)
1186                 return ret;
1187 
1188         ret = imx6_add_pcie_port(imx6_pcie, pdev);
1189         if (ret < 0)
1190                 return ret;
1191 
1192         if (pci_msi_enabled()) {
1193                 val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP +
1194                                         PCI_MSI_FLAGS);
1195                 val |= PCI_MSI_FLAGS_ENABLE;
1196                 dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP + PCI_MSI_FLAGS,
1197                                    val);
1198         }
1199 
1200         return 0;
1201 }
1202 
1203 static void imx6_pcie_shutdown(struct platform_device *pdev)
1204 {
1205         struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1206 
1207         /* bring down link, so bootloader gets clean state in case of reboot */
1208         imx6_pcie_assert_core_reset(imx6_pcie);
1209 }
1210 
1211 static const struct imx6_pcie_drvdata drvdata[] = {
1212         [IMX6Q] = {
1213                 .variant = IMX6Q,
1214                 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1215                          IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1216                 .dbi_length = 0x200,
1217         },
1218         [IMX6SX] = {
1219                 .variant = IMX6SX,
1220                 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1221                          IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1222                          IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1223         },
1224         [IMX6QP] = {
1225                 .variant = IMX6QP,
1226                 .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1227                          IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1228         },
1229         [IMX7D] = {
1230                 .variant = IMX7D,
1231                 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1232         },
1233         [IMX8MQ] = {
1234                 .variant = IMX8MQ,
1235         },
1236 };
1237 
1238 static const struct of_device_id imx6_pcie_of_match[] = {
1239         { .compatible = "fsl,imx6q-pcie",  .data = &drvdata[IMX6Q],  },
1240         { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1241         { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1242         { .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },
1243         { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1244         {},
1245 };
1246 
1247 static struct platform_driver imx6_pcie_driver = {
1248         .driver = {
1249                 .name   = "imx6q-pcie",
1250                 .of_match_table = imx6_pcie_of_match,
1251                 .suppress_bind_attrs = true,
1252                 .pm = &imx6_pcie_pm_ops,
1253                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1254         },
1255         .probe    = imx6_pcie_probe,
1256         .shutdown = imx6_pcie_shutdown,
1257 };
1258 
1259 static void imx6_pcie_quirk(struct pci_dev *dev)
1260 {
1261         struct pci_bus *bus = dev->bus;
1262         struct pcie_port *pp = bus->sysdata;
1263 
1264         /* Bus parent is the PCI bridge, its parent is this platform driver */
1265         if (!bus->dev.parent || !bus->dev.parent->parent)
1266                 return;
1267 
1268         /* Make sure we only quirk devices associated with this driver */
1269         if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
1270                 return;
1271 
1272         if (bus->number == pp->root_bus_nr) {
1273                 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1274                 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1275 
1276                 /*
1277                  * Limit config length to avoid the kernel reading beyond
1278                  * the register set and causing an abort on i.MX 6Quad
1279                  */
1280                 if (imx6_pcie->drvdata->dbi_length) {
1281                         dev->cfg_size = imx6_pcie->drvdata->dbi_length;
1282                         dev_info(&dev->dev, "Limiting cfg_size to %d\n",
1283                                         dev->cfg_size);
1284                 }
1285         }
1286 }
1287 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
1288                         PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
1289 
1290 static int __init imx6_pcie_init(void)
1291 {
1292 #ifdef CONFIG_ARM
1293         /*
1294          * Since probe() can be deferred we need to make sure that
1295          * hook_fault_code is not called after __init memory is freed
1296          * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1297          * we can install the handler here without risking it
1298          * accessing some uninitialized driver state.
1299          */
1300         hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1301                         "external abort on non-linefetch");
1302 #endif
1303 
1304         return platform_driver_register(&imx6_pcie_driver);
1305 }
1306 device_initcall(imx6_pcie_init);

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