This source file includes following definitions.
- advk_writel
- advk_readl
- advk_pcie_link_up
- advk_pcie_wait_for_link
- advk_pcie_wait_for_retrain
- advk_pcie_setup_hw
- advk_pcie_check_pio_status
- advk_pcie_wait_pio
- advk_pci_bridge_emul_pcie_conf_read
- advk_pci_bridge_emul_pcie_conf_write
- advk_sw_pci_bridge_init
- advk_pcie_valid_device
- advk_pcie_rd_conf
- advk_pcie_wr_conf
- advk_msi_irq_compose_msi_msg
- advk_msi_set_affinity
- advk_msi_irq_domain_alloc
- advk_msi_irq_domain_free
- advk_pcie_irq_mask
- advk_pcie_irq_unmask
- advk_pcie_irq_map
- advk_pcie_init_msi_irq_domain
- advk_pcie_remove_msi_irq_domain
- advk_pcie_init_irq_domain
- advk_pcie_remove_irq_domain
- advk_pcie_handle_msi
- advk_pcie_handle_int
- advk_pcie_irq_handler
- advk_pcie_parse_request_of_pci_ranges
- advk_pcie_probe
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11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21
22 #include "../pci.h"
23 #include "../pci-bridge-emul.h"
24
25
26 #define PCIE_CORE_DEV_ID_REG 0x0
27 #define PCIE_CORE_CMD_STATUS_REG 0x4
28 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
29 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
30 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
31 #define PCIE_CORE_DEV_REV_REG 0x8
32 #define PCIE_CORE_PCIEXP_CAP 0xc0
33 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
34 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
35 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
36 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
37 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
38 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
39 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
40 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
41 #define PCIE_CORE_LINK_TRAINING BIT(5)
42 #define PCIE_CORE_LINK_WIDTH_SHIFT 20
43 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
44 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
45 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
46 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
47 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
48 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1
49 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2
50 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3
51 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4
52
53 #define PIO_BASE_ADDR 0x4000
54 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
55 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
56 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
57 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
58 #define PIO_COMPLETION_STATUS_SHIFT 7
59 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
60 #define PIO_COMPLETION_STATUS_OK 0
61 #define PIO_COMPLETION_STATUS_UR 1
62 #define PIO_COMPLETION_STATUS_CRS 2
63 #define PIO_COMPLETION_STATUS_CA 4
64 #define PIO_NON_POSTED_REQ BIT(0)
65 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
66 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
67 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
68 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
69 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
70 #define PIO_START (PIO_BASE_ADDR + 0x1c)
71 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
72 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
73
74
75 #define CONTROL_BASE_ADDR 0x4800
76 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
77 #define PCIE_GEN_SEL_MSK 0x3
78 #define PCIE_GEN_SEL_SHIFT 0x0
79 #define SPEED_GEN_1 0
80 #define SPEED_GEN_2 1
81 #define SPEED_GEN_3 2
82 #define IS_RC_MSK 1
83 #define IS_RC_SHIFT 2
84 #define LANE_CNT_MSK 0x18
85 #define LANE_CNT_SHIFT 0x3
86 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
87 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
88 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
89 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
90 #define LINK_TRAINING_EN BIT(6)
91 #define LEGACY_INTA BIT(28)
92 #define LEGACY_INTB BIT(29)
93 #define LEGACY_INTC BIT(30)
94 #define LEGACY_INTD BIT(31)
95 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
96 #define HOT_RESET_GEN BIT(0)
97 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
98 #define PCIE_CORE_CTRL2_RESERVED 0x7
99 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
100 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
101 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
102 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
103 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
104 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
105 #define PCIE_MSG_PM_PME_MASK BIT(7)
106 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
107 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
108 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
109 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
110 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
111 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
112 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
113 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
114 #define PCIE_ISR1_FLUSH BIT(5)
115 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
116 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
117 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
118 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
119 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
120 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
121 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
122
123
124 #define LMI_BASE_ADDR 0x6000
125 #define CFG_REG (LMI_BASE_ADDR + 0x0)
126 #define LTSSM_SHIFT 24
127 #define LTSSM_MASK 0x3f
128 #define LTSSM_L0 0x10
129 #define RC_BAR_CONFIG 0x300
130
131
132 #define CTRL_CORE_BASE_ADDR 0x18000
133 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
134 #define CTRL_MODE_SHIFT 0x0
135 #define CTRL_MODE_MASK 0x1
136 #define PCIE_CORE_MODE_DIRECT 0x0
137 #define PCIE_CORE_MODE_COMMAND 0x1
138
139
140 #define CENTRAL_INT_BASE_ADDR 0x1b000
141 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
142 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
143 #define PCIE_IRQ_CMDQ_INT BIT(0)
144 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
145 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
146 #define PCIE_IRQ_DMA_INT BIT(4)
147 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
148 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
149 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
150 #define PCIE_IRQ_COMPQ_INT BIT(12)
151 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
152 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
153 #define PCIE_IRQ_CORE_INT BIT(16)
154 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
155 #define PCIE_IRQ_DPMU_INT BIT(18)
156 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
157 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
158 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
159 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
160 #define PCIE_IRQ_EP_STATUS BIT(23)
161 #define PCIE_IRQ_ALL_MASK 0xfff0fb
162 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
163
164
165 #define PCIE_CONFIG_RD_TYPE0 0x8
166 #define PCIE_CONFIG_RD_TYPE1 0x9
167 #define PCIE_CONFIG_WR_TYPE0 0xa
168 #define PCIE_CONFIG_WR_TYPE1 0xb
169
170 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
171 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
172 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
173 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
174 #define PCIE_CONF_ADDR(bus, devfn, where) \
175 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
176 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
177
178 #define PIO_TIMEOUT_MS 1
179
180 #define LINK_WAIT_MAX_RETRIES 10
181 #define LINK_WAIT_USLEEP_MIN 90000
182 #define LINK_WAIT_USLEEP_MAX 100000
183 #define RETRAIN_WAIT_MAX_RETRIES 10
184 #define RETRAIN_WAIT_USLEEP_US 2000
185
186 #define MSI_IRQ_NUM 32
187
188 struct advk_pcie {
189 struct platform_device *pdev;
190 void __iomem *base;
191 struct list_head resources;
192 struct irq_domain *irq_domain;
193 struct irq_chip irq_chip;
194 struct irq_domain *msi_domain;
195 struct irq_domain *msi_inner_domain;
196 struct irq_chip msi_bottom_irq_chip;
197 struct irq_chip msi_irq_chip;
198 struct msi_domain_info msi_domain_info;
199 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
200 struct mutex msi_used_lock;
201 u16 msi_msg;
202 int root_bus_nr;
203 struct pci_bridge_emul bridge;
204 };
205
206 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
207 {
208 writel(val, pcie->base + reg);
209 }
210
211 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
212 {
213 return readl(pcie->base + reg);
214 }
215
216 static int advk_pcie_link_up(struct advk_pcie *pcie)
217 {
218 u32 val, ltssm_state;
219
220 val = advk_readl(pcie, CFG_REG);
221 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
222 return ltssm_state >= LTSSM_L0;
223 }
224
225 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
226 {
227 struct device *dev = &pcie->pdev->dev;
228 int retries;
229
230
231 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
232 if (advk_pcie_link_up(pcie)) {
233 dev_info(dev, "link up\n");
234 return 0;
235 }
236
237 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
238 }
239
240 dev_err(dev, "link never came up\n");
241 return -ETIMEDOUT;
242 }
243
244 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
245 {
246 size_t retries;
247
248 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
249 if (!advk_pcie_link_up(pcie))
250 break;
251 udelay(RETRAIN_WAIT_USLEEP_US);
252 }
253 }
254
255 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
256 {
257 u32 reg;
258
259
260 reg = advk_readl(pcie, CTRL_CONFIG_REG);
261 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
262 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
263 advk_writel(pcie, reg, CTRL_CONFIG_REG);
264
265
266 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
267 reg |= (IS_RC_MSK << IS_RC_SHIFT);
268 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
269
270
271 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
272 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
273 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
274 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
275 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
276
277
278 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
279 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
280 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
281 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
282 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
283 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
284
285
286 reg = PCIE_CORE_CTRL2_RESERVED |
287 PCIE_CORE_CTRL2_TD_ENABLE;
288 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
289
290
291 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
292 reg &= ~PCIE_GEN_SEL_MSK;
293 reg |= SPEED_GEN_2;
294 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
295
296
297 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
298 reg &= ~LANE_CNT_MSK;
299 reg |= LANE_COUNT_1;
300 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
301
302
303 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
304 reg |= LINK_TRAINING_EN;
305 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
306
307
308 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
309 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
310 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
311
312
313 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
314 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
315 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
316
317
318 reg = PCIE_ISR0_ALL_MASK;
319 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
320 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
321
322 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
323
324
325 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
326
327
328 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
329 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
330
331 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
332 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
333 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
334
335
336 reg = advk_readl(pcie, PIO_CTRL);
337 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
338 advk_writel(pcie, reg, PIO_CTRL);
339
340
341 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
342 reg |= PCIE_CORE_LINK_TRAINING;
343 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
344
345 advk_pcie_wait_for_link(pcie);
346
347 reg = PCIE_CORE_LINK_L0S_ENTRY |
348 (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
349 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
350
351 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
352 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
353 PCIE_CORE_CMD_IO_ACCESS_EN |
354 PCIE_CORE_CMD_MEM_IO_REQ_EN;
355 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
356 }
357
358 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
359 {
360 struct device *dev = &pcie->pdev->dev;
361 u32 reg;
362 unsigned int status;
363 char *strcomp_status, *str_posted;
364
365 reg = advk_readl(pcie, PIO_STAT);
366 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
367 PIO_COMPLETION_STATUS_SHIFT;
368
369 if (!status)
370 return;
371
372 switch (status) {
373 case PIO_COMPLETION_STATUS_UR:
374 strcomp_status = "UR";
375 break;
376 case PIO_COMPLETION_STATUS_CRS:
377 strcomp_status = "CRS";
378 break;
379 case PIO_COMPLETION_STATUS_CA:
380 strcomp_status = "CA";
381 break;
382 default:
383 strcomp_status = "Unknown";
384 break;
385 }
386
387 if (reg & PIO_NON_POSTED_REQ)
388 str_posted = "Non-posted";
389 else
390 str_posted = "Posted";
391
392 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
393 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
394 }
395
396 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
397 {
398 struct device *dev = &pcie->pdev->dev;
399 unsigned long timeout;
400
401 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
402
403 while (time_before(jiffies, timeout)) {
404 u32 start, isr;
405
406 start = advk_readl(pcie, PIO_START);
407 isr = advk_readl(pcie, PIO_ISR);
408 if (!start && isr)
409 return 0;
410 }
411
412 dev_err(dev, "config read/write timed out\n");
413 return -ETIMEDOUT;
414 }
415
416
417 static pci_bridge_emul_read_status_t
418 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
419 int reg, u32 *value)
420 {
421 struct advk_pcie *pcie = bridge->data;
422
423
424 switch (reg) {
425 case PCI_EXP_SLTCTL:
426 *value = PCI_EXP_SLTSTA_PDS << 16;
427 return PCI_BRIDGE_EMUL_HANDLED;
428
429 case PCI_EXP_RTCTL: {
430 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
431 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
432 return PCI_BRIDGE_EMUL_HANDLED;
433 }
434
435 case PCI_EXP_RTSTA: {
436 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
437 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
438 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16);
439 return PCI_BRIDGE_EMUL_HANDLED;
440 }
441
442 case PCI_EXP_LNKCTL: {
443
444 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
445 ~(PCI_EXP_LNKSTA_LT << 16);
446 if (!advk_pcie_link_up(pcie))
447 val |= (PCI_EXP_LNKSTA_LT << 16);
448 *value = val;
449 return PCI_BRIDGE_EMUL_HANDLED;
450 }
451
452 case PCI_CAP_LIST_ID:
453 case PCI_EXP_DEVCAP:
454 case PCI_EXP_DEVCTL:
455 case PCI_EXP_LNKCAP:
456 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
457 return PCI_BRIDGE_EMUL_HANDLED;
458 default:
459 return PCI_BRIDGE_EMUL_NOT_HANDLED;
460 }
461
462 }
463
464 static void
465 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
466 int reg, u32 old, u32 new, u32 mask)
467 {
468 struct advk_pcie *pcie = bridge->data;
469
470 switch (reg) {
471 case PCI_EXP_DEVCTL:
472 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
473 break;
474
475 case PCI_EXP_LNKCTL:
476 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
477 if (new & PCI_EXP_LNKCTL_RL)
478 advk_pcie_wait_for_retrain(pcie);
479 break;
480
481 case PCI_EXP_RTCTL: {
482
483 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
484 ~PCIE_MSG_PM_PME_MASK;
485 if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
486 val |= PCIE_MSG_PM_PME_MASK;
487 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
488 break;
489 }
490
491 case PCI_EXP_RTSTA:
492 new = (new & PCI_EXP_RTSTA_PME) >> 9;
493 advk_writel(pcie, new, PCIE_ISR0_REG);
494 break;
495
496 default:
497 break;
498 }
499 }
500
501 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
502 .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
503 .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
504 };
505
506
507
508
509
510 static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
511 {
512 struct pci_bridge_emul *bridge = &pcie->bridge;
513
514 bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
515 bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
516 bridge->conf.class_revision =
517 advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
518
519
520 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
521 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
522
523
524 bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
525 bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
526
527
528 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
529
530 bridge->has_pcie = true;
531 bridge->data = pcie;
532 bridge->ops = &advk_pci_bridge_emul_ops;
533
534 pci_bridge_emul_init(bridge, 0);
535
536 }
537
538 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
539 int devfn)
540 {
541 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
542 return false;
543
544 return true;
545 }
546
547 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
548 int where, int size, u32 *val)
549 {
550 struct advk_pcie *pcie = bus->sysdata;
551 u32 reg;
552 int ret;
553
554 if (!advk_pcie_valid_device(pcie, bus, devfn)) {
555 *val = 0xffffffff;
556 return PCIBIOS_DEVICE_NOT_FOUND;
557 }
558
559 if (bus->number == pcie->root_bus_nr)
560 return pci_bridge_emul_conf_read(&pcie->bridge, where,
561 size, val);
562
563
564 advk_writel(pcie, 0, PIO_START);
565 advk_writel(pcie, 1, PIO_ISR);
566
567
568 reg = advk_readl(pcie, PIO_CTRL);
569 reg &= ~PIO_CTRL_TYPE_MASK;
570 if (bus->primary == pcie->root_bus_nr)
571 reg |= PCIE_CONFIG_RD_TYPE0;
572 else
573 reg |= PCIE_CONFIG_RD_TYPE1;
574 advk_writel(pcie, reg, PIO_CTRL);
575
576
577 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
578 advk_writel(pcie, reg, PIO_ADDR_LS);
579 advk_writel(pcie, 0, PIO_ADDR_MS);
580
581
582 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
583
584
585 advk_writel(pcie, 1, PIO_START);
586
587 ret = advk_pcie_wait_pio(pcie);
588 if (ret < 0)
589 return PCIBIOS_SET_FAILED;
590
591 advk_pcie_check_pio_status(pcie);
592
593
594 *val = advk_readl(pcie, PIO_RD_DATA);
595 if (size == 1)
596 *val = (*val >> (8 * (where & 3))) & 0xff;
597 else if (size == 2)
598 *val = (*val >> (8 * (where & 3))) & 0xffff;
599
600 return PCIBIOS_SUCCESSFUL;
601 }
602
603 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
604 int where, int size, u32 val)
605 {
606 struct advk_pcie *pcie = bus->sysdata;
607 u32 reg;
608 u32 data_strobe = 0x0;
609 int offset;
610 int ret;
611
612 if (!advk_pcie_valid_device(pcie, bus, devfn))
613 return PCIBIOS_DEVICE_NOT_FOUND;
614
615 if (bus->number == pcie->root_bus_nr)
616 return pci_bridge_emul_conf_write(&pcie->bridge, where,
617 size, val);
618
619 if (where % size)
620 return PCIBIOS_SET_FAILED;
621
622
623 advk_writel(pcie, 0, PIO_START);
624 advk_writel(pcie, 1, PIO_ISR);
625
626
627 reg = advk_readl(pcie, PIO_CTRL);
628 reg &= ~PIO_CTRL_TYPE_MASK;
629 if (bus->primary == pcie->root_bus_nr)
630 reg |= PCIE_CONFIG_WR_TYPE0;
631 else
632 reg |= PCIE_CONFIG_WR_TYPE1;
633 advk_writel(pcie, reg, PIO_CTRL);
634
635
636 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
637 advk_writel(pcie, reg, PIO_ADDR_LS);
638 advk_writel(pcie, 0, PIO_ADDR_MS);
639
640
641 offset = where & 0x3;
642 reg = val << (8 * offset);
643 data_strobe = GENMASK(size - 1, 0) << offset;
644
645
646 advk_writel(pcie, reg, PIO_WR_DATA);
647
648
649 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
650
651
652 advk_writel(pcie, 1, PIO_START);
653
654 ret = advk_pcie_wait_pio(pcie);
655 if (ret < 0)
656 return PCIBIOS_SET_FAILED;
657
658 advk_pcie_check_pio_status(pcie);
659
660 return PCIBIOS_SUCCESSFUL;
661 }
662
663 static struct pci_ops advk_pcie_ops = {
664 .read = advk_pcie_rd_conf,
665 .write = advk_pcie_wr_conf,
666 };
667
668 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
669 struct msi_msg *msg)
670 {
671 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
672 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
673
674 msg->address_lo = lower_32_bits(msi_msg);
675 msg->address_hi = upper_32_bits(msi_msg);
676 msg->data = data->irq;
677 }
678
679 static int advk_msi_set_affinity(struct irq_data *irq_data,
680 const struct cpumask *mask, bool force)
681 {
682 return -EINVAL;
683 }
684
685 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
686 unsigned int virq,
687 unsigned int nr_irqs, void *args)
688 {
689 struct advk_pcie *pcie = domain->host_data;
690 int hwirq, i;
691
692 mutex_lock(&pcie->msi_used_lock);
693 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
694 0, nr_irqs, 0);
695 if (hwirq >= MSI_IRQ_NUM) {
696 mutex_unlock(&pcie->msi_used_lock);
697 return -ENOSPC;
698 }
699
700 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
701 mutex_unlock(&pcie->msi_used_lock);
702
703 for (i = 0; i < nr_irqs; i++)
704 irq_domain_set_info(domain, virq + i, hwirq + i,
705 &pcie->msi_bottom_irq_chip,
706 domain->host_data, handle_simple_irq,
707 NULL, NULL);
708
709 return hwirq;
710 }
711
712 static void advk_msi_irq_domain_free(struct irq_domain *domain,
713 unsigned int virq, unsigned int nr_irqs)
714 {
715 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
716 struct advk_pcie *pcie = domain->host_data;
717
718 mutex_lock(&pcie->msi_used_lock);
719 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
720 mutex_unlock(&pcie->msi_used_lock);
721 }
722
723 static const struct irq_domain_ops advk_msi_domain_ops = {
724 .alloc = advk_msi_irq_domain_alloc,
725 .free = advk_msi_irq_domain_free,
726 };
727
728 static void advk_pcie_irq_mask(struct irq_data *d)
729 {
730 struct advk_pcie *pcie = d->domain->host_data;
731 irq_hw_number_t hwirq = irqd_to_hwirq(d);
732 u32 mask;
733
734 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
735 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
736 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
737 }
738
739 static void advk_pcie_irq_unmask(struct irq_data *d)
740 {
741 struct advk_pcie *pcie = d->domain->host_data;
742 irq_hw_number_t hwirq = irqd_to_hwirq(d);
743 u32 mask;
744
745 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
746 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
747 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
748 }
749
750 static int advk_pcie_irq_map(struct irq_domain *h,
751 unsigned int virq, irq_hw_number_t hwirq)
752 {
753 struct advk_pcie *pcie = h->host_data;
754
755 advk_pcie_irq_mask(irq_get_irq_data(virq));
756 irq_set_status_flags(virq, IRQ_LEVEL);
757 irq_set_chip_and_handler(virq, &pcie->irq_chip,
758 handle_level_irq);
759 irq_set_chip_data(virq, pcie);
760
761 return 0;
762 }
763
764 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
765 .map = advk_pcie_irq_map,
766 .xlate = irq_domain_xlate_onecell,
767 };
768
769 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
770 {
771 struct device *dev = &pcie->pdev->dev;
772 struct device_node *node = dev->of_node;
773 struct irq_chip *bottom_ic, *msi_ic;
774 struct msi_domain_info *msi_di;
775 phys_addr_t msi_msg_phys;
776
777 mutex_init(&pcie->msi_used_lock);
778
779 bottom_ic = &pcie->msi_bottom_irq_chip;
780
781 bottom_ic->name = "MSI";
782 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
783 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
784
785 msi_ic = &pcie->msi_irq_chip;
786 msi_ic->name = "advk-MSI";
787
788 msi_di = &pcie->msi_domain_info;
789 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
790 MSI_FLAG_MULTI_PCI_MSI;
791 msi_di->chip = msi_ic;
792
793 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
794
795 advk_writel(pcie, lower_32_bits(msi_msg_phys),
796 PCIE_MSI_ADDR_LOW_REG);
797 advk_writel(pcie, upper_32_bits(msi_msg_phys),
798 PCIE_MSI_ADDR_HIGH_REG);
799
800 pcie->msi_inner_domain =
801 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
802 &advk_msi_domain_ops, pcie);
803 if (!pcie->msi_inner_domain)
804 return -ENOMEM;
805
806 pcie->msi_domain =
807 pci_msi_create_irq_domain(of_node_to_fwnode(node),
808 msi_di, pcie->msi_inner_domain);
809 if (!pcie->msi_domain) {
810 irq_domain_remove(pcie->msi_inner_domain);
811 return -ENOMEM;
812 }
813
814 return 0;
815 }
816
817 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
818 {
819 irq_domain_remove(pcie->msi_domain);
820 irq_domain_remove(pcie->msi_inner_domain);
821 }
822
823 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
824 {
825 struct device *dev = &pcie->pdev->dev;
826 struct device_node *node = dev->of_node;
827 struct device_node *pcie_intc_node;
828 struct irq_chip *irq_chip;
829 int ret = 0;
830
831 pcie_intc_node = of_get_next_child(node, NULL);
832 if (!pcie_intc_node) {
833 dev_err(dev, "No PCIe Intc node found\n");
834 return -ENODEV;
835 }
836
837 irq_chip = &pcie->irq_chip;
838
839 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
840 dev_name(dev));
841 if (!irq_chip->name) {
842 ret = -ENOMEM;
843 goto out_put_node;
844 }
845
846 irq_chip->irq_mask = advk_pcie_irq_mask;
847 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
848 irq_chip->irq_unmask = advk_pcie_irq_unmask;
849
850 pcie->irq_domain =
851 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
852 &advk_pcie_irq_domain_ops, pcie);
853 if (!pcie->irq_domain) {
854 dev_err(dev, "Failed to get a INTx IRQ domain\n");
855 ret = -ENOMEM;
856 goto out_put_node;
857 }
858
859 out_put_node:
860 of_node_put(pcie_intc_node);
861 return ret;
862 }
863
864 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
865 {
866 irq_domain_remove(pcie->irq_domain);
867 }
868
869 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
870 {
871 u32 msi_val, msi_mask, msi_status, msi_idx;
872 u16 msi_data;
873
874 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
875 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
876 msi_status = msi_val & ~msi_mask;
877
878 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
879 if (!(BIT(msi_idx) & msi_status))
880 continue;
881
882 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
883 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
884 generic_handle_irq(msi_data);
885 }
886
887 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
888 PCIE_ISR0_REG);
889 }
890
891 static void advk_pcie_handle_int(struct advk_pcie *pcie)
892 {
893 u32 isr0_val, isr0_mask, isr0_status;
894 u32 isr1_val, isr1_mask, isr1_status;
895 int i, virq;
896
897 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
898 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
899 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
900
901 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
902 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
903 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
904
905 if (!isr0_status && !isr1_status) {
906 advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
907 advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
908 return;
909 }
910
911
912 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
913 advk_pcie_handle_msi(pcie);
914
915
916 for (i = 0; i < PCI_NUM_INTX; i++) {
917 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
918 continue;
919
920 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
921 PCIE_ISR1_REG);
922
923 virq = irq_find_mapping(pcie->irq_domain, i);
924 generic_handle_irq(virq);
925 }
926 }
927
928 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
929 {
930 struct advk_pcie *pcie = arg;
931 u32 status;
932
933 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
934 if (!(status & PCIE_IRQ_CORE_INT))
935 return IRQ_NONE;
936
937 advk_pcie_handle_int(pcie);
938
939
940 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
941
942 return IRQ_HANDLED;
943 }
944
945 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
946 {
947 int err, res_valid = 0;
948 struct device *dev = &pcie->pdev->dev;
949 struct resource_entry *win, *tmp;
950 resource_size_t iobase;
951
952 INIT_LIST_HEAD(&pcie->resources);
953
954 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
955 &pcie->resources, &iobase);
956 if (err)
957 return err;
958
959 err = devm_request_pci_bus_resources(dev, &pcie->resources);
960 if (err)
961 goto out_release_res;
962
963 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
964 struct resource *res = win->res;
965
966 switch (resource_type(res)) {
967 case IORESOURCE_IO:
968 err = devm_pci_remap_iospace(dev, res, iobase);
969 if (err) {
970 dev_warn(dev, "error %d: failed to map resource %pR\n",
971 err, res);
972 resource_list_destroy_entry(win);
973 }
974 break;
975 case IORESOURCE_MEM:
976 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
977 break;
978 case IORESOURCE_BUS:
979 pcie->root_bus_nr = res->start;
980 break;
981 }
982 }
983
984 if (!res_valid) {
985 dev_err(dev, "non-prefetchable memory resource required\n");
986 err = -EINVAL;
987 goto out_release_res;
988 }
989
990 return 0;
991
992 out_release_res:
993 pci_free_resource_list(&pcie->resources);
994 return err;
995 }
996
997 static int advk_pcie_probe(struct platform_device *pdev)
998 {
999 struct device *dev = &pdev->dev;
1000 struct advk_pcie *pcie;
1001 struct resource *res;
1002 struct pci_host_bridge *bridge;
1003 int ret, irq;
1004
1005 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
1006 if (!bridge)
1007 return -ENOMEM;
1008
1009 pcie = pci_host_bridge_priv(bridge);
1010 pcie->pdev = pdev;
1011
1012 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1013 pcie->base = devm_ioremap_resource(dev, res);
1014 if (IS_ERR(pcie->base))
1015 return PTR_ERR(pcie->base);
1016
1017 irq = platform_get_irq(pdev, 0);
1018 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
1019 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
1020 pcie);
1021 if (ret) {
1022 dev_err(dev, "Failed to register interrupt\n");
1023 return ret;
1024 }
1025
1026 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
1027 if (ret) {
1028 dev_err(dev, "Failed to parse resources\n");
1029 return ret;
1030 }
1031
1032 advk_pcie_setup_hw(pcie);
1033
1034 advk_sw_pci_bridge_init(pcie);
1035
1036 ret = advk_pcie_init_irq_domain(pcie);
1037 if (ret) {
1038 dev_err(dev, "Failed to initialize irq\n");
1039 return ret;
1040 }
1041
1042 ret = advk_pcie_init_msi_irq_domain(pcie);
1043 if (ret) {
1044 dev_err(dev, "Failed to initialize irq\n");
1045 advk_pcie_remove_irq_domain(pcie);
1046 return ret;
1047 }
1048
1049 list_splice_init(&pcie->resources, &bridge->windows);
1050 bridge->dev.parent = dev;
1051 bridge->sysdata = pcie;
1052 bridge->busnr = 0;
1053 bridge->ops = &advk_pcie_ops;
1054 bridge->map_irq = of_irq_parse_and_map_pci;
1055 bridge->swizzle_irq = pci_common_swizzle;
1056
1057 ret = pci_host_probe(bridge);
1058 if (ret < 0) {
1059 advk_pcie_remove_msi_irq_domain(pcie);
1060 advk_pcie_remove_irq_domain(pcie);
1061 return ret;
1062 }
1063
1064 return 0;
1065 }
1066
1067 static const struct of_device_id advk_pcie_of_match_table[] = {
1068 { .compatible = "marvell,armada-3700-pcie", },
1069 {},
1070 };
1071
1072 static struct platform_driver advk_pcie_driver = {
1073 .driver = {
1074 .name = "advk-pcie",
1075 .of_match_table = advk_pcie_of_match_table,
1076
1077 .suppress_bind_attrs = true,
1078 },
1079 .probe = advk_pcie_probe,
1080 };
1081 builtin_platform_driver(advk_pcie_driver);