This source file includes following definitions.
- nwl_bridge_readl
- nwl_bridge_writel
- nwl_pcie_link_up
- nwl_phy_link_up
- nwl_wait_for_link
- nwl_pcie_valid_device
- nwl_pcie_map_bus
- nwl_pcie_misc_handler
- nwl_pcie_leg_handler
- nwl_pcie_handle_msi_irq
- nwl_pcie_msi_handler_high
- nwl_pcie_msi_handler_low
- nwl_mask_leg_irq
- nwl_unmask_leg_irq
- nwl_legacy_map
- nwl_compose_msi_msg
- nwl_msi_set_affinity
- nwl_irq_domain_alloc
- nwl_irq_domain_free
- nwl_pcie_init_msi_irq_domain
- nwl_pcie_init_irq_domain
- nwl_pcie_enable_msi
- nwl_pcie_bridge_init
- nwl_pcie_parse_dt
- nwl_pcie_probe
1
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3
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5
6
7
8
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/msi.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_irq.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqchip/chained_irq.h>
23
24 #include "../pci.h"
25
26
27 #define BRCFG_PCIE_RX0 0x00000000
28 #define BRCFG_INTERRUPT 0x00000010
29 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
30
31
32 #define E_BREG_CAPABILITIES 0x00000200
33 #define E_BREG_CONTROL 0x00000208
34 #define E_BREG_BASE_LO 0x00000210
35 #define E_BREG_BASE_HI 0x00000214
36 #define E_ECAM_CAPABILITIES 0x00000220
37 #define E_ECAM_CONTROL 0x00000228
38 #define E_ECAM_BASE_LO 0x00000230
39 #define E_ECAM_BASE_HI 0x00000234
40
41
42 #define I_MSII_CAPABILITIES 0x00000300
43 #define I_MSII_CONTROL 0x00000308
44 #define I_MSII_BASE_LO 0x00000310
45 #define I_MSII_BASE_HI 0x00000314
46
47 #define I_ISUB_CONTROL 0x000003E8
48 #define SET_ISUB_CONTROL BIT(0)
49
50 #define MSGF_MISC_STATUS 0x00000400
51 #define MSGF_MISC_MASK 0x00000404
52 #define MSGF_LEG_STATUS 0x00000420
53 #define MSGF_LEG_MASK 0x00000424
54 #define MSGF_MSI_STATUS_LO 0x00000440
55 #define MSGF_MSI_STATUS_HI 0x00000444
56 #define MSGF_MSI_MASK_LO 0x00000448
57 #define MSGF_MSI_MASK_HI 0x0000044C
58
59
60 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
61 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
62 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
63 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
64 CFG_ENABLE_INT_MSG_FWD | \
65 CFG_ENABLE_ERR_MSG_FWD)
66
67
68 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
69 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
70 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
71 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
72 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
73 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
74 #define MSGF_MISC_SR_FATAL_AER BIT(16)
75 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
76 #define MSGF_MISC_SR_CORR_AER BIT(18)
77 #define MSGF_MISC_SR_UR_DETECT BIT(20)
78 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
79 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
80 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
81 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
82 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
83
84 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
85 MSGF_MISC_SR_RXMSG_OVER | \
86 MSGF_MISC_SR_SLAVE_ERR | \
87 MSGF_MISC_SR_MASTER_ERR | \
88 MSGF_MISC_SR_I_ADDR_ERR | \
89 MSGF_MISC_SR_E_ADDR_ERR | \
90 MSGF_MISC_SR_FATAL_AER | \
91 MSGF_MISC_SR_NON_FATAL_AER | \
92 MSGF_MISC_SR_CORR_AER | \
93 MSGF_MISC_SR_UR_DETECT | \
94 MSGF_MISC_SR_NON_FATAL_DEV | \
95 MSGF_MISC_SR_FATAL_DEV | \
96 MSGF_MISC_SR_LINK_DOWN | \
97 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
98 MSGF_MSIC_SR_LINK_BWIDTH)
99
100
101 #define MSGF_LEG_SR_INTA BIT(0)
102 #define MSGF_LEG_SR_INTB BIT(1)
103 #define MSGF_LEG_SR_INTC BIT(2)
104 #define MSGF_LEG_SR_INTD BIT(3)
105 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
106 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
107
108
109 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
110 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
111
112 #define MSII_PRESENT BIT(0)
113 #define MSII_ENABLE BIT(0)
114 #define MSII_STATUS_ENABLE BIT(15)
115
116
117 #define BRCFG_INTERRUPT_MASK BIT(0)
118 #define BREG_PRESENT BIT(0)
119 #define BREG_ENABLE BIT(0)
120 #define BREG_ENABLE_FORCE BIT(1)
121
122
123 #define E_ECAM_PRESENT BIT(0)
124 #define E_ECAM_CR_ENABLE BIT(0)
125 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
126 #define E_ECAM_SIZE_SHIFT 16
127 #define ECAM_BUS_LOC_SHIFT 20
128 #define ECAM_DEV_LOC_SHIFT 12
129 #define NWL_ECAM_VALUE_DEFAULT 12
130
131 #define CFG_DMA_REG_BAR GENMASK(2, 0)
132
133 #define INT_PCI_MSI_NR (2 * 32)
134
135
136 #define PS_LINKUP_OFFSET 0x00000238
137 #define PCIE_PHY_LINKUP_BIT BIT(0)
138 #define PHY_RDY_LINKUP_BIT BIT(1)
139
140
141 #define LINK_WAIT_MAX_RETRIES 10
142 #define LINK_WAIT_USLEEP_MIN 90000
143 #define LINK_WAIT_USLEEP_MAX 100000
144
145 struct nwl_msi {
146 struct irq_domain *msi_domain;
147 unsigned long *bitmap;
148 struct irq_domain *dev_domain;
149 struct mutex lock;
150 int irq_msi0;
151 int irq_msi1;
152 };
153
154 struct nwl_pcie {
155 struct device *dev;
156 void __iomem *breg_base;
157 void __iomem *pcireg_base;
158 void __iomem *ecam_base;
159 phys_addr_t phys_breg_base;
160 phys_addr_t phys_pcie_reg_base;
161 phys_addr_t phys_ecam_base;
162 u32 breg_size;
163 u32 pcie_reg_size;
164 u32 ecam_size;
165 int irq_intx;
166 int irq_misc;
167 u32 ecam_value;
168 u8 last_busno;
169 u8 root_busno;
170 struct nwl_msi msi;
171 struct irq_domain *legacy_irq_domain;
172 raw_spinlock_t leg_mask_lock;
173 };
174
175 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
176 {
177 return readl(pcie->breg_base + off);
178 }
179
180 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
181 {
182 writel(val, pcie->breg_base + off);
183 }
184
185 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
186 {
187 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
188 return true;
189 return false;
190 }
191
192 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
193 {
194 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
195 return true;
196 return false;
197 }
198
199 static int nwl_wait_for_link(struct nwl_pcie *pcie)
200 {
201 struct device *dev = pcie->dev;
202 int retries;
203
204
205 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
206 if (nwl_phy_link_up(pcie))
207 return 0;
208 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
209 }
210
211 dev_err(dev, "PHY link never came up\n");
212 return -ETIMEDOUT;
213 }
214
215 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
216 {
217 struct nwl_pcie *pcie = bus->sysdata;
218
219
220 if (bus->number != pcie->root_busno) {
221 if (!nwl_pcie_link_up(pcie))
222 return false;
223 }
224
225
226 if (bus->number == pcie->root_busno && devfn > 0)
227 return false;
228
229 return true;
230 }
231
232
233
234
235
236
237
238
239
240
241
242 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
243 int where)
244 {
245 struct nwl_pcie *pcie = bus->sysdata;
246 int relbus;
247
248 if (!nwl_pcie_valid_device(bus, devfn))
249 return NULL;
250
251 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
252 (devfn << ECAM_DEV_LOC_SHIFT);
253
254 return pcie->ecam_base + relbus + where;
255 }
256
257
258 static struct pci_ops nwl_pcie_ops = {
259 .map_bus = nwl_pcie_map_bus,
260 .read = pci_generic_config_read,
261 .write = pci_generic_config_write,
262 };
263
264 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
265 {
266 struct nwl_pcie *pcie = data;
267 struct device *dev = pcie->dev;
268 u32 misc_stat;
269
270
271 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
272 MSGF_MISC_SR_MASKALL;
273 if (!misc_stat)
274 return IRQ_NONE;
275
276 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
277 dev_err(dev, "Received Message FIFO Overflow\n");
278
279 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
280 dev_err(dev, "Slave error\n");
281
282 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
283 dev_err(dev, "Master error\n");
284
285 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
286 dev_err(dev, "In Misc Ingress address translation error\n");
287
288 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
289 dev_err(dev, "In Misc Egress address translation error\n");
290
291 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
292 dev_err(dev, "Fatal Error in AER Capability\n");
293
294 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
295 dev_err(dev, "Non-Fatal Error in AER Capability\n");
296
297 if (misc_stat & MSGF_MISC_SR_CORR_AER)
298 dev_err(dev, "Correctable Error in AER Capability\n");
299
300 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
301 dev_err(dev, "Unsupported request Detected\n");
302
303 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
304 dev_err(dev, "Non-Fatal Error Detected\n");
305
306 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
307 dev_err(dev, "Fatal Error Detected\n");
308
309 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
310 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
311
312 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
313 dev_info(dev, "Link Bandwidth Management Status bit set\n");
314
315
316 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
317
318 return IRQ_HANDLED;
319 }
320
321 static void nwl_pcie_leg_handler(struct irq_desc *desc)
322 {
323 struct irq_chip *chip = irq_desc_get_chip(desc);
324 struct nwl_pcie *pcie;
325 unsigned long status;
326 u32 bit;
327 u32 virq;
328
329 chained_irq_enter(chip, desc);
330 pcie = irq_desc_get_handler_data(desc);
331
332 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
333 MSGF_LEG_SR_MASKALL) != 0) {
334 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
335 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
336 if (virq)
337 generic_handle_irq(virq);
338 }
339 }
340
341 chained_irq_exit(chip, desc);
342 }
343
344 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
345 {
346 struct nwl_msi *msi;
347 unsigned long status;
348 u32 bit;
349 u32 virq;
350
351 msi = &pcie->msi;
352
353 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
354 for_each_set_bit(bit, &status, 32) {
355 nwl_bridge_writel(pcie, 1 << bit, status_reg);
356 virq = irq_find_mapping(msi->dev_domain, bit);
357 if (virq)
358 generic_handle_irq(virq);
359 }
360 }
361 }
362
363 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
364 {
365 struct irq_chip *chip = irq_desc_get_chip(desc);
366 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
367
368 chained_irq_enter(chip, desc);
369 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
370 chained_irq_exit(chip, desc);
371 }
372
373 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
374 {
375 struct irq_chip *chip = irq_desc_get_chip(desc);
376 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
377
378 chained_irq_enter(chip, desc);
379 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
380 chained_irq_exit(chip, desc);
381 }
382
383 static void nwl_mask_leg_irq(struct irq_data *data)
384 {
385 struct irq_desc *desc = irq_to_desc(data->irq);
386 struct nwl_pcie *pcie;
387 unsigned long flags;
388 u32 mask;
389 u32 val;
390
391 pcie = irq_desc_get_chip_data(desc);
392 mask = 1 << (data->hwirq - 1);
393 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
394 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
395 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
396 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
397 }
398
399 static void nwl_unmask_leg_irq(struct irq_data *data)
400 {
401 struct irq_desc *desc = irq_to_desc(data->irq);
402 struct nwl_pcie *pcie;
403 unsigned long flags;
404 u32 mask;
405 u32 val;
406
407 pcie = irq_desc_get_chip_data(desc);
408 mask = 1 << (data->hwirq - 1);
409 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
410 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
411 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
412 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
413 }
414
415 static struct irq_chip nwl_leg_irq_chip = {
416 .name = "nwl_pcie:legacy",
417 .irq_enable = nwl_unmask_leg_irq,
418 .irq_disable = nwl_mask_leg_irq,
419 .irq_mask = nwl_mask_leg_irq,
420 .irq_unmask = nwl_unmask_leg_irq,
421 };
422
423 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
424 irq_hw_number_t hwirq)
425 {
426 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
427 irq_set_chip_data(irq, domain->host_data);
428 irq_set_status_flags(irq, IRQ_LEVEL);
429
430 return 0;
431 }
432
433 static const struct irq_domain_ops legacy_domain_ops = {
434 .map = nwl_legacy_map,
435 .xlate = pci_irqd_intx_xlate,
436 };
437
438 #ifdef CONFIG_PCI_MSI
439 static struct irq_chip nwl_msi_irq_chip = {
440 .name = "nwl_pcie:msi",
441 .irq_enable = pci_msi_unmask_irq,
442 .irq_disable = pci_msi_mask_irq,
443 .irq_mask = pci_msi_mask_irq,
444 .irq_unmask = pci_msi_unmask_irq,
445 };
446
447 static struct msi_domain_info nwl_msi_domain_info = {
448 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
449 MSI_FLAG_MULTI_PCI_MSI),
450 .chip = &nwl_msi_irq_chip,
451 };
452 #endif
453
454 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
455 {
456 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
457 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
458
459 msg->address_lo = lower_32_bits(msi_addr);
460 msg->address_hi = upper_32_bits(msi_addr);
461 msg->data = data->hwirq;
462 }
463
464 static int nwl_msi_set_affinity(struct irq_data *irq_data,
465 const struct cpumask *mask, bool force)
466 {
467 return -EINVAL;
468 }
469
470 static struct irq_chip nwl_irq_chip = {
471 .name = "Xilinx MSI",
472 .irq_compose_msi_msg = nwl_compose_msi_msg,
473 .irq_set_affinity = nwl_msi_set_affinity,
474 };
475
476 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
477 unsigned int nr_irqs, void *args)
478 {
479 struct nwl_pcie *pcie = domain->host_data;
480 struct nwl_msi *msi = &pcie->msi;
481 int bit;
482 int i;
483
484 mutex_lock(&msi->lock);
485 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
486 get_count_order(nr_irqs));
487 if (bit < 0) {
488 mutex_unlock(&msi->lock);
489 return -ENOSPC;
490 }
491
492 for (i = 0; i < nr_irqs; i++) {
493 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
494 domain->host_data, handle_simple_irq,
495 NULL, NULL);
496 }
497 mutex_unlock(&msi->lock);
498 return 0;
499 }
500
501 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
502 unsigned int nr_irqs)
503 {
504 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
505 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
506 struct nwl_msi *msi = &pcie->msi;
507
508 mutex_lock(&msi->lock);
509 bitmap_release_region(msi->bitmap, data->hwirq,
510 get_count_order(nr_irqs));
511 mutex_unlock(&msi->lock);
512 }
513
514 static const struct irq_domain_ops dev_msi_domain_ops = {
515 .alloc = nwl_irq_domain_alloc,
516 .free = nwl_irq_domain_free,
517 };
518
519 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
520 {
521 #ifdef CONFIG_PCI_MSI
522 struct device *dev = pcie->dev;
523 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
524 struct nwl_msi *msi = &pcie->msi;
525
526 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
527 &dev_msi_domain_ops, pcie);
528 if (!msi->dev_domain) {
529 dev_err(dev, "failed to create dev IRQ domain\n");
530 return -ENOMEM;
531 }
532 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
533 &nwl_msi_domain_info,
534 msi->dev_domain);
535 if (!msi->msi_domain) {
536 dev_err(dev, "failed to create msi IRQ domain\n");
537 irq_domain_remove(msi->dev_domain);
538 return -ENOMEM;
539 }
540 #endif
541 return 0;
542 }
543
544 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
545 {
546 struct device *dev = pcie->dev;
547 struct device_node *node = dev->of_node;
548 struct device_node *legacy_intc_node;
549
550 legacy_intc_node = of_get_next_child(node, NULL);
551 if (!legacy_intc_node) {
552 dev_err(dev, "No legacy intc node found\n");
553 return -EINVAL;
554 }
555
556 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
557 PCI_NUM_INTX,
558 &legacy_domain_ops,
559 pcie);
560 of_node_put(legacy_intc_node);
561 if (!pcie->legacy_irq_domain) {
562 dev_err(dev, "failed to create IRQ domain\n");
563 return -ENOMEM;
564 }
565
566 raw_spin_lock_init(&pcie->leg_mask_lock);
567 nwl_pcie_init_msi_irq_domain(pcie);
568 return 0;
569 }
570
571 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
572 {
573 struct device *dev = pcie->dev;
574 struct platform_device *pdev = to_platform_device(dev);
575 struct nwl_msi *msi = &pcie->msi;
576 unsigned long base;
577 int ret;
578 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
579
580 mutex_init(&msi->lock);
581
582 msi->bitmap = kzalloc(size, GFP_KERNEL);
583 if (!msi->bitmap)
584 return -ENOMEM;
585
586
587 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
588 if (msi->irq_msi1 < 0) {
589 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1);
590 ret = -EINVAL;
591 goto err;
592 }
593
594 irq_set_chained_handler_and_data(msi->irq_msi1,
595 nwl_pcie_msi_handler_high, pcie);
596
597
598 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
599 if (msi->irq_msi0 < 0) {
600 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0);
601 ret = -EINVAL;
602 goto err;
603 }
604
605 irq_set_chained_handler_and_data(msi->irq_msi0,
606 nwl_pcie_msi_handler_low, pcie);
607
608
609 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
610 if (!ret) {
611 dev_err(dev, "MSI not present\n");
612 ret = -EIO;
613 goto err;
614 }
615
616
617 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
618 MSII_ENABLE, I_MSII_CONTROL);
619
620
621 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
622 MSII_STATUS_ENABLE, I_MSII_CONTROL);
623
624
625 base = pcie->phys_pcie_reg_base;
626 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
627 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
628
629
630
631
632
633 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
634
635 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
636 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
637
638 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
639
640
641
642
643
644 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
645
646 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
647 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
648
649 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
650
651 return 0;
652 err:
653 kfree(msi->bitmap);
654 msi->bitmap = NULL;
655 return ret;
656 }
657
658 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
659 {
660 struct device *dev = pcie->dev;
661 struct platform_device *pdev = to_platform_device(dev);
662 u32 breg_val, ecam_val, first_busno = 0;
663 int err;
664
665 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
666 if (!breg_val) {
667 dev_err(dev, "BREG is not present\n");
668 return breg_val;
669 }
670
671
672 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
673 E_BREG_BASE_LO);
674 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
675 E_BREG_BASE_HI);
676
677
678 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
679 E_BREG_CONTROL);
680
681
682 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
683 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
684
685
686 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
687
688
689 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
690 BRCFG_PCIE_RX_MSG_FILTER);
691
692 err = nwl_wait_for_link(pcie);
693 if (err)
694 return err;
695
696 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
697 if (!ecam_val) {
698 dev_err(dev, "ECAM is not present\n");
699 return ecam_val;
700 }
701
702
703 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
704 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
705
706 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
707 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
708 E_ECAM_CONTROL);
709
710 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
711 E_ECAM_BASE_LO);
712 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
713 E_ECAM_BASE_HI);
714
715
716 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
717 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
718
719 ecam_val = first_busno;
720 ecam_val |= (first_busno + 1) << 8;
721 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
722 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
723
724 if (nwl_pcie_link_up(pcie))
725 dev_info(dev, "Link is UP\n");
726 else
727 dev_info(dev, "Link is DOWN\n");
728
729
730 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
731 if (pcie->irq_misc < 0) {
732 dev_err(dev, "failed to get misc IRQ %d\n",
733 pcie->irq_misc);
734 return -EINVAL;
735 }
736
737 err = devm_request_irq(dev, pcie->irq_misc,
738 nwl_pcie_misc_handler, IRQF_SHARED,
739 "nwl_pcie:misc", pcie);
740 if (err) {
741 dev_err(dev, "fail to register misc IRQ#%d\n",
742 pcie->irq_misc);
743 return err;
744 }
745
746
747 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
748
749
750 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
751 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
752
753
754 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
755
756
757
758 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
759
760
761 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
762 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
763
764
765 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
766
767
768 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
769 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
770
771 return 0;
772 }
773
774 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
775 struct platform_device *pdev)
776 {
777 struct device *dev = pcie->dev;
778 struct resource *res;
779
780 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
781 pcie->breg_base = devm_ioremap_resource(dev, res);
782 if (IS_ERR(pcie->breg_base))
783 return PTR_ERR(pcie->breg_base);
784 pcie->phys_breg_base = res->start;
785
786 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
787 pcie->pcireg_base = devm_ioremap_resource(dev, res);
788 if (IS_ERR(pcie->pcireg_base))
789 return PTR_ERR(pcie->pcireg_base);
790 pcie->phys_pcie_reg_base = res->start;
791
792 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
793 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
794 if (IS_ERR(pcie->ecam_base))
795 return PTR_ERR(pcie->ecam_base);
796 pcie->phys_ecam_base = res->start;
797
798
799 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
800 if (pcie->irq_intx < 0) {
801 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
802 return pcie->irq_intx;
803 }
804
805 irq_set_chained_handler_and_data(pcie->irq_intx,
806 nwl_pcie_leg_handler, pcie);
807
808 return 0;
809 }
810
811 static const struct of_device_id nwl_pcie_of_match[] = {
812 { .compatible = "xlnx,nwl-pcie-2.11", },
813 {}
814 };
815
816 static int nwl_pcie_probe(struct platform_device *pdev)
817 {
818 struct device *dev = &pdev->dev;
819 struct nwl_pcie *pcie;
820 struct pci_bus *bus;
821 struct pci_bus *child;
822 struct pci_host_bridge *bridge;
823 int err;
824 resource_size_t iobase = 0;
825 LIST_HEAD(res);
826
827 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
828 if (!bridge)
829 return -ENODEV;
830
831 pcie = pci_host_bridge_priv(bridge);
832
833 pcie->dev = dev;
834 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
835
836 err = nwl_pcie_parse_dt(pcie, pdev);
837 if (err) {
838 dev_err(dev, "Parsing DT failed\n");
839 return err;
840 }
841
842 err = nwl_pcie_bridge_init(pcie);
843 if (err) {
844 dev_err(dev, "HW Initialization failed\n");
845 return err;
846 }
847
848 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
849 &iobase);
850 if (err) {
851 dev_err(dev, "Getting bridge resources failed\n");
852 return err;
853 }
854
855 err = devm_request_pci_bus_resources(dev, &res);
856 if (err)
857 goto error;
858
859 err = nwl_pcie_init_irq_domain(pcie);
860 if (err) {
861 dev_err(dev, "Failed creating IRQ Domain\n");
862 goto error;
863 }
864
865 list_splice_init(&res, &bridge->windows);
866 bridge->dev.parent = dev;
867 bridge->sysdata = pcie;
868 bridge->busnr = pcie->root_busno;
869 bridge->ops = &nwl_pcie_ops;
870 bridge->map_irq = of_irq_parse_and_map_pci;
871 bridge->swizzle_irq = pci_common_swizzle;
872
873 if (IS_ENABLED(CONFIG_PCI_MSI)) {
874 err = nwl_pcie_enable_msi(pcie);
875 if (err < 0) {
876 dev_err(dev, "failed to enable MSI support: %d\n", err);
877 goto error;
878 }
879 }
880
881 err = pci_scan_root_bus_bridge(bridge);
882 if (err)
883 goto error;
884
885 bus = bridge->bus;
886
887 pci_assign_unassigned_bus_resources(bus);
888 list_for_each_entry(child, &bus->children, node)
889 pcie_bus_configure_settings(child);
890 pci_bus_add_devices(bus);
891 return 0;
892
893 error:
894 pci_free_resource_list(&res);
895 return err;
896 }
897
898 static struct platform_driver nwl_pcie_driver = {
899 .driver = {
900 .name = "nwl-pcie",
901 .suppress_bind_attrs = true,
902 .of_match_table = nwl_pcie_of_match,
903 },
904 .probe = nwl_pcie_probe,
905 };
906 builtin_platform_driver(nwl_pcie_driver);