drivers/pci/controller/pcie-mobiveil.c

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This source file includes following definitions.
mobiveil_pcie_sel_page
mobiveil_pcie_comp_addr
mobiveil_pcie_read
mobiveil_pcie_write
mobiveil_csr_read
mobiveil_csr_write
mobiveil_csr_readl
mobiveil_csr_writel
mobiveil_pcie_link_up
mobiveil_pcie_valid_device
mobiveil_pcie_map_bus
mobiveil_pcie_isr
mobiveil_pcie_parse_dt
program_ib_windows
program_ob_windows
mobiveil_bringup_link
mobiveil_pcie_enable_msi
mobiveil_host_init
mobiveil_mask_intx_irq
mobiveil_unmask_intx_irq
mobiveil_pcie_intx_map
mobiveil_compose_msi_msg
mobiveil_msi_set_affinity
mobiveil_irq_msi_domain_alloc
mobiveil_irq_msi_domain_free
mobiveil_allocate_msi_domains
mobiveil_pcie_init_irq_domain
mobiveil_pcie_probe
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PCIe host controller driver for Mobiveil PCIe Host controller
   4  *
   5  * Copyright (c) 2018 Mobiveil Inc.
   6  * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
   7  */
   8 
   9 #include <linux/delay.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/irqchip/chained_irq.h>
  14 #include <linux/irqdomain.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/msi.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_pci.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/slab.h>
  25 
  26 #include "../pci.h"
  27 
  28 /* register offsets and bit positions */
  29 
  30 /*
  31  * translation tables are grouped into windows, each window registers are
  32  * grouped into blocks of 4 or 16 registers each
  33  */
  34 #define PAB_REG_BLOCK_SIZE              16
  35 #define PAB_EXT_REG_BLOCK_SIZE          4
  36 
  37 #define PAB_REG_ADDR(offset, win)       \
  38         (offset + (win * PAB_REG_BLOCK_SIZE))
  39 #define PAB_EXT_REG_ADDR(offset, win)   \
  40         (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
  41 
  42 #define LTSSM_STATUS                    0x0404
  43 #define  LTSSM_STATUS_L0_MASK           0x3f
  44 #define  LTSSM_STATUS_L0                0x2d
  45 
  46 #define PAB_CTRL                        0x0808
  47 #define  AMBA_PIO_ENABLE_SHIFT          0
  48 #define  PEX_PIO_ENABLE_SHIFT           1
  49 #define  PAGE_SEL_SHIFT                 13
  50 #define  PAGE_SEL_MASK                  0x3f
  51 #define  PAGE_LO_MASK                   0x3ff
  52 #define  PAGE_SEL_OFFSET_SHIFT          10
  53 
  54 #define PAB_AXI_PIO_CTRL                0x0840
  55 #define  APIO_EN_MASK                   0xf
  56 
  57 #define PAB_PEX_PIO_CTRL                0x08c0
  58 #define  PIO_ENABLE_SHIFT               0
  59 
  60 #define PAB_INTP_AMBA_MISC_ENB          0x0b0c
  61 #define PAB_INTP_AMBA_MISC_STAT         0x0b1c
  62 #define  PAB_INTP_INTX_MASK             0x01e0
  63 #define  PAB_INTP_MSI_MASK              0x8
  64 
  65 #define PAB_AXI_AMAP_CTRL(win)          PAB_REG_ADDR(0x0ba0, win)
  66 #define  WIN_ENABLE_SHIFT               0
  67 #define  WIN_TYPE_SHIFT                 1
  68 #define  WIN_TYPE_MASK                  0x3
  69 #define  WIN_SIZE_MASK                  0xfffffc00
  70 
  71 #define PAB_EXT_AXI_AMAP_SIZE(win)      PAB_EXT_REG_ADDR(0xbaf0, win)
  72 
  73 #define PAB_EXT_AXI_AMAP_AXI_WIN(win)   PAB_EXT_REG_ADDR(0x80a0, win)
  74 #define PAB_AXI_AMAP_AXI_WIN(win)       PAB_REG_ADDR(0x0ba4, win)
  75 #define  AXI_WINDOW_ALIGN_MASK          3
  76 
  77 #define PAB_AXI_AMAP_PEX_WIN_L(win)     PAB_REG_ADDR(0x0ba8, win)
  78 #define  PAB_BUS_SHIFT                  24
  79 #define  PAB_DEVICE_SHIFT               19
  80 #define  PAB_FUNCTION_SHIFT             16
  81 
  82 #define PAB_AXI_AMAP_PEX_WIN_H(win)     PAB_REG_ADDR(0x0bac, win)
  83 #define PAB_INTP_AXI_PIO_CLASS          0x474
  84 
  85 #define PAB_PEX_AMAP_CTRL(win)          PAB_REG_ADDR(0x4ba0, win)
  86 #define  AMAP_CTRL_EN_SHIFT             0
  87 #define  AMAP_CTRL_TYPE_SHIFT           1
  88 #define  AMAP_CTRL_TYPE_MASK            3
  89 
  90 #define PAB_EXT_PEX_AMAP_SIZEN(win)     PAB_EXT_REG_ADDR(0xbef0, win)
  91 #define PAB_EXT_PEX_AMAP_AXI_WIN(win)   PAB_EXT_REG_ADDR(0xb4a0, win)
  92 #define PAB_PEX_AMAP_AXI_WIN(win)       PAB_REG_ADDR(0x4ba4, win)
  93 #define PAB_PEX_AMAP_PEX_WIN_L(win)     PAB_REG_ADDR(0x4ba8, win)
  94 #define PAB_PEX_AMAP_PEX_WIN_H(win)     PAB_REG_ADDR(0x4bac, win)
  95 
  96 /* starting offset of INTX bits in status register */
  97 #define PAB_INTX_START                  5
  98 
  99 /* supported number of MSI interrupts */
 100 #define PCI_NUM_MSI                     16
 101 
 102 /* MSI registers */
 103 #define MSI_BASE_LO_OFFSET              0x04
 104 #define MSI_BASE_HI_OFFSET              0x08
 105 #define MSI_SIZE_OFFSET                 0x0c
 106 #define MSI_ENABLE_OFFSET               0x14
 107 #define MSI_STATUS_OFFSET               0x18
 108 #define MSI_DATA_OFFSET                 0x20
 109 #define MSI_ADDR_L_OFFSET               0x24
 110 #define MSI_ADDR_H_OFFSET               0x28
 111 
 112 /* outbound and inbound window definitions */
 113 #define WIN_NUM_0                       0
 114 #define WIN_NUM_1                       1
 115 #define CFG_WINDOW_TYPE                 0
 116 #define IO_WINDOW_TYPE                  1
 117 #define MEM_WINDOW_TYPE                 2
 118 #define IB_WIN_SIZE                     ((u64)256 * 1024 * 1024 * 1024)
 119 #define MAX_PIO_WINDOWS                 8
 120 
 121 /* Parameters for the waiting for link up routine */
 122 #define LINK_WAIT_MAX_RETRIES           10
 123 #define LINK_WAIT_MIN                   90000
 124 #define LINK_WAIT_MAX                   100000
 125 
 126 #define PAGED_ADDR_BNDRY                0xc00
 127 #define OFFSET_TO_PAGE_ADDR(off)        \
 128         ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
 129 #define OFFSET_TO_PAGE_IDX(off)         \
 130         ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
 131 
 132 struct mobiveil_msi {                   /* MSI information */
 133         struct mutex lock;              /* protect bitmap variable */
 134         struct irq_domain *msi_domain;
 135         struct irq_domain *dev_domain;
 136         phys_addr_t msi_pages_phys;
 137         int num_of_vectors;
 138         DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
 139 };
 140 
 141 struct mobiveil_pcie {
 142         struct platform_device *pdev;
 143         struct list_head resources;
 144         void __iomem *config_axi_slave_base;    /* endpoint config base */
 145         void __iomem *csr_axi_slave_base;       /* root port config base */
 146         void __iomem *apb_csr_base;     /* MSI register base */
 147         phys_addr_t pcie_reg_base;      /* Physical PCIe Controller Base */
 148         struct irq_domain *intx_domain;
 149         raw_spinlock_t intx_mask_lock;
 150         int irq;
 151         int apio_wins;
 152         int ppio_wins;
 153         int ob_wins_configured;         /* configured outbound windows */
 154         int ib_wins_configured;         /* configured inbound windows */
 155         struct resource *ob_io_res;
 156         char root_bus_nr;
 157         struct mobiveil_msi msi;
 158 };
 159 
 160 /*
 161  * mobiveil_pcie_sel_page - routine to access paged register
 162  *
 163  * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
 164  * for this scheme to work extracted higher 6 bits of the offset will be
 165  * written to pg_sel field of PAB_CTRL register and rest of the lower 10
 166  * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
 167  */
 168 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
 169 {
 170         u32 val;
 171 
 172         val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
 173         val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
 174         val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
 175 
 176         writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
 177 }
 178 
 179 static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
 180 {
 181         if (off < PAGED_ADDR_BNDRY) {
 182                 /* For directly accessed registers, clear the pg_sel field */
 183                 mobiveil_pcie_sel_page(pcie, 0);
 184                 return pcie->csr_axi_slave_base + off;
 185         }
 186 
 187         mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
 188         return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
 189 }
 190 
 191 static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
 192 {
 193         if ((uintptr_t)addr & (size - 1)) {
 194                 *val = 0;
 195                 return PCIBIOS_BAD_REGISTER_NUMBER;
 196         }
 197 
 198         switch (size) {
 199         case 4:
 200                 *val = readl(addr);
 201                 break;
 202         case 2:
 203                 *val = readw(addr);
 204                 break;
 205         case 1:
 206                 *val = readb(addr);
 207                 break;
 208         default:
 209                 *val = 0;
 210                 return PCIBIOS_BAD_REGISTER_NUMBER;
 211         }
 212 
 213         return PCIBIOS_SUCCESSFUL;
 214 }
 215 
 216 static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
 217 {
 218         if ((uintptr_t)addr & (size - 1))
 219                 return PCIBIOS_BAD_REGISTER_NUMBER;
 220 
 221         switch (size) {
 222         case 4:
 223                 writel(val, addr);
 224                 break;
 225         case 2:
 226                 writew(val, addr);
 227                 break;
 228         case 1:
 229                 writeb(val, addr);
 230                 break;
 231         default:
 232                 return PCIBIOS_BAD_REGISTER_NUMBER;
 233         }
 234 
 235         return PCIBIOS_SUCCESSFUL;
 236 }
 237 
 238 static u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
 239 {
 240         void *addr;
 241         u32 val;
 242         int ret;
 243 
 244         addr = mobiveil_pcie_comp_addr(pcie, off);
 245 
 246         ret = mobiveil_pcie_read(addr, size, &val);
 247         if (ret)
 248                 dev_err(&pcie->pdev->dev, "read CSR address failed\n");
 249 
 250         return val;
 251 }
 252 
 253 static void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
 254                                size_t size)
 255 {
 256         void *addr;
 257         int ret;
 258 
 259         addr = mobiveil_pcie_comp_addr(pcie, off);
 260 
 261         ret = mobiveil_pcie_write(addr, size, val);
 262         if (ret)
 263                 dev_err(&pcie->pdev->dev, "write CSR address failed\n");
 264 }
 265 
 266 static u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
 267 {
 268         return mobiveil_csr_read(pcie, off, 0x4);
 269 }
 270 
 271 static void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
 272 {
 273         mobiveil_csr_write(pcie, val, off, 0x4);
 274 }
 275 
 276 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
 277 {
 278         return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
 279                 LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
 280 }
 281 
 282 static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 283 {
 284         struct mobiveil_pcie *pcie = bus->sysdata;
 285 
 286         /* Only one device down on each root port */
 287         if ((bus->number == pcie->root_bus_nr) && (devfn > 0))
 288                 return false;
 289 
 290         /*
 291          * Do not read more than one device on the bus directly
 292          * attached to RC
 293          */
 294         if ((bus->primary == pcie->root_bus_nr) && (PCI_SLOT(devfn) > 0))
 295                 return false;
 296 
 297         return true;
 298 }
 299 
 300 /*
 301  * mobiveil_pcie_map_bus - routine to get the configuration base of either
 302  * root port or endpoint
 303  */
 304 static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
 305                                            unsigned int devfn, int where)
 306 {
 307         struct mobiveil_pcie *pcie = bus->sysdata;
 308         u32 value;
 309 
 310         if (!mobiveil_pcie_valid_device(bus, devfn))
 311                 return NULL;
 312 
 313         /* RC config access */
 314         if (bus->number == pcie->root_bus_nr)
 315                 return pcie->csr_axi_slave_base + where;
 316 
 317         /*
 318          * EP config access (in Config/APIO space)
 319          * Program PEX Address base (31..16 bits) with appropriate value
 320          * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
 321          * Relies on pci_lock serialization
 322          */
 323         value = bus->number << PAB_BUS_SHIFT |
 324                 PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
 325                 PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
 326 
 327         mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
 328 
 329         return pcie->config_axi_slave_base + where;
 330 }
 331 
 332 static struct pci_ops mobiveil_pcie_ops = {
 333         .map_bus = mobiveil_pcie_map_bus,
 334         .read = pci_generic_config_read,
 335         .write = pci_generic_config_write,
 336 };
 337 
 338 static void mobiveil_pcie_isr(struct irq_desc *desc)
 339 {
 340         struct irq_chip *chip = irq_desc_get_chip(desc);
 341         struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
 342         struct device *dev = &pcie->pdev->dev;
 343         struct mobiveil_msi *msi = &pcie->msi;
 344         u32 msi_data, msi_addr_lo, msi_addr_hi;
 345         u32 intr_status, msi_status;
 346         unsigned long shifted_status;
 347         u32 bit, virq, val, mask;
 348 
 349         /*
 350          * The core provides a single interrupt for both INTx/MSI messages.
 351          * So we'll read both INTx and MSI status
 352          */
 353 
 354         chained_irq_enter(chip, desc);
 355 
 356         /* read INTx status */
 357         val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
 358         mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
 359         intr_status = val & mask;
 360 
 361         /* Handle INTx */
 362         if (intr_status & PAB_INTP_INTX_MASK) {
 363                 shifted_status = mobiveil_csr_readl(pcie,
 364                                                     PAB_INTP_AMBA_MISC_STAT);
 365                 shifted_status &= PAB_INTP_INTX_MASK;
 366                 shifted_status >>= PAB_INTX_START;
 367                 do {
 368                         for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
 369                                 virq = irq_find_mapping(pcie->intx_domain,
 370                                                         bit + 1);
 371                                 if (virq)
 372                                         generic_handle_irq(virq);
 373                                 else
 374                                         dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
 375                                                             bit);
 376 
 377                                 /* clear interrupt handled */
 378                                 mobiveil_csr_writel(pcie,
 379                                                     1 << (PAB_INTX_START + bit),
 380                                                     PAB_INTP_AMBA_MISC_STAT);
 381                         }
 382 
 383                         shifted_status = mobiveil_csr_readl(pcie,
 384                                                             PAB_INTP_AMBA_MISC_STAT);
 385                         shifted_status &= PAB_INTP_INTX_MASK;
 386                         shifted_status >>= PAB_INTX_START;
 387                 } while (shifted_status != 0);
 388         }
 389 
 390         /* read extra MSI status register */
 391         msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
 392 
 393         /* handle MSI interrupts */
 394         while (msi_status & 1) {
 395                 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
 396 
 397                 /*
 398                  * MSI_STATUS_OFFSET register gets updated to zero
 399                  * once we pop not only the MSI data but also address
 400                  * from MSI hardware FIFO. So keeping these following
 401                  * two dummy reads.
 402                  */
 403                 msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
 404                                             MSI_ADDR_L_OFFSET);
 405                 msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
 406                                             MSI_ADDR_H_OFFSET);
 407                 dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
 408                         msi_data, msi_addr_hi, msi_addr_lo);
 409 
 410                 virq = irq_find_mapping(msi->dev_domain, msi_data);
 411                 if (virq)
 412                         generic_handle_irq(virq);
 413 
 414                 msi_status = readl_relaxed(pcie->apb_csr_base +
 415                                            MSI_STATUS_OFFSET);
 416         }
 417 
 418         /* Clear the interrupt status */
 419         mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
 420         chained_irq_exit(chip, desc);
 421 }
 422 
 423 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
 424 {
 425         struct device *dev = &pcie->pdev->dev;
 426         struct platform_device *pdev = pcie->pdev;
 427         struct device_node *node = dev->of_node;
 428         struct resource *res;
 429 
 430         /* map config resource */
 431         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 432                                            "config_axi_slave");
 433         pcie->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
 434         if (IS_ERR(pcie->config_axi_slave_base))
 435                 return PTR_ERR(pcie->config_axi_slave_base);
 436         pcie->ob_io_res = res;
 437 
 438         /* map csr resource */
 439         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 440                                            "csr_axi_slave");
 441         pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
 442         if (IS_ERR(pcie->csr_axi_slave_base))
 443                 return PTR_ERR(pcie->csr_axi_slave_base);
 444         pcie->pcie_reg_base = res->start;
 445 
 446         /* map MSI config resource */
 447         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb_csr");
 448         pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
 449         if (IS_ERR(pcie->apb_csr_base))
 450                 return PTR_ERR(pcie->apb_csr_base);
 451 
 452         /* read the number of windows requested */
 453         if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
 454                 pcie->apio_wins = MAX_PIO_WINDOWS;
 455 
 456         if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
 457                 pcie->ppio_wins = MAX_PIO_WINDOWS;
 458 
 459         pcie->irq = platform_get_irq(pdev, 0);
 460         if (pcie->irq <= 0) {
 461                 dev_err(dev, "failed to map IRQ: %d\n", pcie->irq);
 462                 return -ENODEV;
 463         }
 464 
 465         return 0;
 466 }
 467 
 468 static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
 469                                u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
 470 {
 471         u32 value;
 472         u64 size64 = ~(size - 1);
 473 
 474         if (win_num >= pcie->ppio_wins) {
 475                 dev_err(&pcie->pdev->dev,
 476                         "ERROR: max inbound windows reached !\n");
 477                 return;
 478         }
 479 
 480         value = mobiveil_csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
 481         value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
 482         value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
 483                  (lower_32_bits(size64) & WIN_SIZE_MASK);
 484         mobiveil_csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
 485 
 486         mobiveil_csr_writel(pcie, upper_32_bits(size64),
 487                             PAB_EXT_PEX_AMAP_SIZEN(win_num));
 488 
 489         mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr),
 490                             PAB_PEX_AMAP_AXI_WIN(win_num));
 491         mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
 492                             PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
 493 
 494         mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
 495                             PAB_PEX_AMAP_PEX_WIN_L(win_num));
 496         mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
 497                             PAB_PEX_AMAP_PEX_WIN_H(win_num));
 498 
 499         pcie->ib_wins_configured++;
 500 }
 501 
 502 /*
 503  * routine to program the outbound windows
 504  */
 505 static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
 506                                u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
 507 {
 508         u32 value;
 509         u64 size64 = ~(size - 1);
 510 
 511         if (win_num >= pcie->apio_wins) {
 512                 dev_err(&pcie->pdev->dev,
 513                         "ERROR: max outbound windows reached !\n");
 514                 return;
 515         }
 516 
 517         /*
 518          * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
 519          * to 4 KB in PAB_AXI_AMAP_CTRL register
 520          */
 521         value = mobiveil_csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
 522         value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
 523         value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
 524                  (lower_32_bits(size64) & WIN_SIZE_MASK);
 525         mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
 526 
 527         mobiveil_csr_writel(pcie, upper_32_bits(size64),
 528                             PAB_EXT_AXI_AMAP_SIZE(win_num));
 529 
 530         /*
 531          * program AXI window base with appropriate value in
 532          * PAB_AXI_AMAP_AXI_WIN0 register
 533          */
 534         mobiveil_csr_writel(pcie,
 535                             lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
 536                             PAB_AXI_AMAP_AXI_WIN(win_num));
 537         mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
 538                             PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
 539 
 540         mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
 541                             PAB_AXI_AMAP_PEX_WIN_L(win_num));
 542         mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
 543                             PAB_AXI_AMAP_PEX_WIN_H(win_num));
 544 
 545         pcie->ob_wins_configured++;
 546 }
 547 
 548 static int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
 549 {
 550         int retries;
 551 
 552         /* check if the link is up or not */
 553         for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
 554                 if (mobiveil_pcie_link_up(pcie))
 555                         return 0;
 556 
 557                 usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
 558         }
 559 
 560         dev_err(&pcie->pdev->dev, "link never came up\n");
 561 
 562         return -ETIMEDOUT;
 563 }
 564 
 565 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
 566 {
 567         phys_addr_t msg_addr = pcie->pcie_reg_base;
 568         struct mobiveil_msi *msi = &pcie->msi;
 569 
 570         pcie->msi.num_of_vectors = PCI_NUM_MSI;
 571         msi->msi_pages_phys = (phys_addr_t)msg_addr;
 572 
 573         writel_relaxed(lower_32_bits(msg_addr),
 574                        pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
 575         writel_relaxed(upper_32_bits(msg_addr),
 576                        pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
 577         writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
 578         writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
 579 }
 580 
 581 static int mobiveil_host_init(struct mobiveil_pcie *pcie)
 582 {
 583         u32 value, pab_ctrl, type;
 584         struct resource_entry *win;
 585 
 586         /* setup bus numbers */
 587         value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
 588         value &= 0xff000000;
 589         value |= 0x00ff0100;
 590         mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
 591 
 592         /*
 593          * program Bus Master Enable Bit in Command Register in PAB Config
 594          * Space
 595          */
 596         value = mobiveil_csr_readl(pcie, PCI_COMMAND);
 597         value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 598         mobiveil_csr_writel(pcie, value, PCI_COMMAND);
 599 
 600         /*
 601          * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
 602          * register
 603          */
 604         pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
 605         pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
 606         mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
 607 
 608         mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
 609                             PAB_INTP_AMBA_MISC_ENB);
 610 
 611         /*
 612          * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
 613          * PAB_AXI_PIO_CTRL Register
 614          */
 615         value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
 616         value |= APIO_EN_MASK;
 617         mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
 618 
 619         /* Enable PCIe PIO master */
 620         value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
 621         value |= 1 << PIO_ENABLE_SHIFT;
 622         mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
 623 
 624         /*
 625          * we'll program one outbound window for config reads and
 626          * another default inbound window for all the upstream traffic
 627          * rest of the outbound windows will be configured according to
 628          * the "ranges" field defined in device tree
 629          */
 630 
 631         /* config outbound translation window */
 632         program_ob_windows(pcie, WIN_NUM_0, pcie->ob_io_res->start, 0,
 633                            CFG_WINDOW_TYPE, resource_size(pcie->ob_io_res));
 634 
 635         /* memory inbound translation window */
 636         program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
 637 
 638         /* Get the I/O and memory ranges from DT */
 639         resource_list_for_each_entry(win, &pcie->resources) {
 640                 if (resource_type(win->res) == IORESOURCE_MEM)
 641                         type = MEM_WINDOW_TYPE;
 642                 else if (resource_type(win->res) == IORESOURCE_IO)
 643                         type = IO_WINDOW_TYPE;
 644                 else
 645                         continue;
 646 
 647                 /* configure outbound translation window */
 648                 program_ob_windows(pcie, pcie->ob_wins_configured,
 649                                    win->res->start,
 650                                    win->res->start - win->offset,
 651                                    type, resource_size(win->res));
 652         }
 653 
 654         /* fixup for PCIe class register */
 655         value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
 656         value &= 0xff;
 657         value |= (PCI_CLASS_BRIDGE_PCI << 16);
 658         mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
 659 
 660         /* setup MSI hardware registers */
 661         mobiveil_pcie_enable_msi(pcie);
 662 
 663         return 0;
 664 }
 665 
 666 static void mobiveil_mask_intx_irq(struct irq_data *data)
 667 {
 668         struct irq_desc *desc = irq_to_desc(data->irq);
 669         struct mobiveil_pcie *pcie;
 670         unsigned long flags;
 671         u32 mask, shifted_val;
 672 
 673         pcie = irq_desc_get_chip_data(desc);
 674         mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
 675         raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
 676         shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
 677         shifted_val &= ~mask;
 678         mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
 679         raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
 680 }
 681 
 682 static void mobiveil_unmask_intx_irq(struct irq_data *data)
 683 {
 684         struct irq_desc *desc = irq_to_desc(data->irq);
 685         struct mobiveil_pcie *pcie;
 686         unsigned long flags;
 687         u32 shifted_val, mask;
 688 
 689         pcie = irq_desc_get_chip_data(desc);
 690         mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
 691         raw_spin_lock_irqsave(&pcie->intx_mask_lock, flags);
 692         shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
 693         shifted_val |= mask;
 694         mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
 695         raw_spin_unlock_irqrestore(&pcie->intx_mask_lock, flags);
 696 }
 697 
 698 static struct irq_chip intx_irq_chip = {
 699         .name = "mobiveil_pcie:intx",
 700         .irq_enable = mobiveil_unmask_intx_irq,
 701         .irq_disable = mobiveil_mask_intx_irq,
 702         .irq_mask = mobiveil_mask_intx_irq,
 703         .irq_unmask = mobiveil_unmask_intx_irq,
 704 };
 705 
 706 /* routine to setup the INTx related data */
 707 static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 708                                   irq_hw_number_t hwirq)
 709 {
 710         irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
 711         irq_set_chip_data(irq, domain->host_data);
 712 
 713         return 0;
 714 }
 715 
 716 /* INTx domain operations structure */
 717 static const struct irq_domain_ops intx_domain_ops = {
 718         .map = mobiveil_pcie_intx_map,
 719 };
 720 
 721 static struct irq_chip mobiveil_msi_irq_chip = {
 722         .name = "Mobiveil PCIe MSI",
 723         .irq_mask = pci_msi_mask_irq,
 724         .irq_unmask = pci_msi_unmask_irq,
 725 };
 726 
 727 static struct msi_domain_info mobiveil_msi_domain_info = {
 728         .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 729                    MSI_FLAG_PCI_MSIX),
 730         .chip   = &mobiveil_msi_irq_chip,
 731 };
 732 
 733 static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 734 {
 735         struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
 736         phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
 737 
 738         msg->address_lo = lower_32_bits(addr);
 739         msg->address_hi = upper_32_bits(addr);
 740         msg->data = data->hwirq;
 741 
 742         dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
 743                 (int)data->hwirq, msg->address_hi, msg->address_lo);
 744 }
 745 
 746 static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
 747                                      const struct cpumask *mask, bool force)
 748 {
 749         return -EINVAL;
 750 }
 751 
 752 static struct irq_chip mobiveil_msi_bottom_irq_chip = {
 753         .name                   = "Mobiveil MSI",
 754         .irq_compose_msi_msg    = mobiveil_compose_msi_msg,
 755         .irq_set_affinity       = mobiveil_msi_set_affinity,
 756 };
 757 
 758 static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
 759                                          unsigned int virq,
 760                                          unsigned int nr_irqs, void *args)
 761 {
 762         struct mobiveil_pcie *pcie = domain->host_data;
 763         struct mobiveil_msi *msi = &pcie->msi;
 764         unsigned long bit;
 765 
 766         WARN_ON(nr_irqs != 1);
 767         mutex_lock(&msi->lock);
 768 
 769         bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
 770         if (bit >= msi->num_of_vectors) {
 771                 mutex_unlock(&msi->lock);
 772                 return -ENOSPC;
 773         }
 774 
 775         set_bit(bit, msi->msi_irq_in_use);
 776 
 777         mutex_unlock(&msi->lock);
 778 
 779         irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
 780                             domain->host_data, handle_level_irq, NULL, NULL);
 781         return 0;
 782 }
 783 
 784 static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
 785                                          unsigned int virq,
 786                                          unsigned int nr_irqs)
 787 {
 788         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 789         struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
 790         struct mobiveil_msi *msi = &pcie->msi;
 791 
 792         mutex_lock(&msi->lock);
 793 
 794         if (!test_bit(d->hwirq, msi->msi_irq_in_use))
 795                 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
 796                         d->hwirq);
 797         else
 798                 __clear_bit(d->hwirq, msi->msi_irq_in_use);
 799 
 800         mutex_unlock(&msi->lock);
 801 }
 802 static const struct irq_domain_ops msi_domain_ops = {
 803         .alloc  = mobiveil_irq_msi_domain_alloc,
 804         .free   = mobiveil_irq_msi_domain_free,
 805 };
 806 
 807 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
 808 {
 809         struct device *dev = &pcie->pdev->dev;
 810         struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
 811         struct mobiveil_msi *msi = &pcie->msi;
 812 
 813         mutex_init(&pcie->msi.lock);
 814         msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
 815                                                 &msi_domain_ops, pcie);
 816         if (!msi->dev_domain) {
 817                 dev_err(dev, "failed to create IRQ domain\n");
 818                 return -ENOMEM;
 819         }
 820 
 821         msi->msi_domain = pci_msi_create_irq_domain(fwnode,
 822                                                     &mobiveil_msi_domain_info,
 823                                                     msi->dev_domain);
 824         if (!msi->msi_domain) {
 825                 dev_err(dev, "failed to create MSI domain\n");
 826                 irq_domain_remove(msi->dev_domain);
 827                 return -ENOMEM;
 828         }
 829 
 830         return 0;
 831 }
 832 
 833 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
 834 {
 835         struct device *dev = &pcie->pdev->dev;
 836         struct device_node *node = dev->of_node;
 837         int ret;
 838 
 839         /* setup INTx */
 840         pcie->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
 841                                                   &intx_domain_ops, pcie);
 842 
 843         if (!pcie->intx_domain) {
 844                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 845                 return -ENOMEM;
 846         }
 847 
 848         raw_spin_lock_init(&pcie->intx_mask_lock);
 849 
 850         /* setup MSI */
 851         ret = mobiveil_allocate_msi_domains(pcie);
 852         if (ret)
 853                 return ret;
 854 
 855         return 0;
 856 }
 857 
 858 static int mobiveil_pcie_probe(struct platform_device *pdev)
 859 {
 860         struct mobiveil_pcie *pcie;
 861         struct pci_bus *bus;
 862         struct pci_bus *child;
 863         struct pci_host_bridge *bridge;
 864         struct device *dev = &pdev->dev;
 865         resource_size_t iobase;
 866         int ret;
 867 
 868         /* allocate the PCIe port */
 869         bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
 870         if (!bridge)
 871                 return -ENOMEM;
 872 
 873         pcie = pci_host_bridge_priv(bridge);
 874 
 875         pcie->pdev = pdev;
 876 
 877         ret = mobiveil_pcie_parse_dt(pcie);
 878         if (ret) {
 879                 dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
 880                 return ret;
 881         }
 882 
 883         INIT_LIST_HEAD(&pcie->resources);
 884 
 885         /* parse the host bridge base addresses from the device tree file */
 886         ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
 887                                                     &pcie->resources, &iobase);
 888         if (ret) {
 889                 dev_err(dev, "Getting bridge resources failed\n");
 890                 return ret;
 891         }
 892 
 893         /*
 894          * configure all inbound and outbound windows and prepare the RC for
 895          * config access
 896          */
 897         ret = mobiveil_host_init(pcie);
 898         if (ret) {
 899                 dev_err(dev, "Failed to initialize host\n");
 900                 goto error;
 901         }
 902 
 903         /* initialize the IRQ domains */
 904         ret = mobiveil_pcie_init_irq_domain(pcie);
 905         if (ret) {
 906                 dev_err(dev, "Failed creating IRQ Domain\n");
 907                 goto error;
 908         }
 909 
 910         irq_set_chained_handler_and_data(pcie->irq, mobiveil_pcie_isr, pcie);
 911 
 912         ret = devm_request_pci_bus_resources(dev, &pcie->resources);
 913         if (ret)
 914                 goto error;
 915 
 916         /* Initialize bridge */
 917         list_splice_init(&pcie->resources, &bridge->windows);
 918         bridge->dev.parent = dev;
 919         bridge->sysdata = pcie;
 920         bridge->busnr = pcie->root_bus_nr;
 921         bridge->ops = &mobiveil_pcie_ops;
 922         bridge->map_irq = of_irq_parse_and_map_pci;
 923         bridge->swizzle_irq = pci_common_swizzle;
 924 
 925         ret = mobiveil_bringup_link(pcie);
 926         if (ret) {
 927                 dev_info(dev, "link bring-up failed\n");
 928                 goto error;
 929         }
 930 
 931         /* setup the kernel resources for the newly added PCIe root bus */
 932         ret = pci_scan_root_bus_bridge(bridge);
 933         if (ret)
 934                 goto error;
 935 
 936         bus = bridge->bus;
 937 
 938         pci_assign_unassigned_bus_resources(bus);
 939         list_for_each_entry(child, &bus->children, node)
 940                 pcie_bus_configure_settings(child);
 941         pci_bus_add_devices(bus);
 942 
 943         return 0;
 944 error:
 945         pci_free_resource_list(&pcie->resources);
 946         return ret;
 947 }
 948 
 949 static const struct of_device_id mobiveil_pcie_of_match[] = {
 950         {.compatible = "mbvl,gpex40-pcie",},
 951         {},
 952 };
 953 
 954 MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
 955 
 956 static struct platform_driver mobiveil_pcie_driver = {
 957         .probe = mobiveil_pcie_probe,
 958         .driver = {
 959                 .name = "mobiveil-pcie",
 960                 .of_match_table = mobiveil_pcie_of_match,
 961                 .suppress_bind_attrs = true,
 962         },
 963 };
 964 
 965 builtin_platform_driver(mobiveil_pcie_driver);
 966 
 967 MODULE_LICENSE("GPL v2");
 968 MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
 969 MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/pci/controller/pcie-mobiveil.c

DEFINITIONS
