This source file includes following definitions.
- get_pci_domain_busn_res
- no_pci_devices
- release_pcibus_dev
- pcibus_class_init
- pci_size
- decode_bar
- __pci_read_base
- pci_read_bases
- pci_read_bridge_windows
- pci_read_bridge_io
- pci_read_bridge_mmio
- pci_read_bridge_mmio_pref
- pci_read_bridge_bases
- pci_alloc_bus
- devm_pci_release_host_bridge_dev
- pci_release_host_bridge_dev
- pci_init_host_bridge
- pci_alloc_host_bridge
- devm_pci_alloc_host_bridge
- pci_free_host_bridge
- pcie_update_link_speed
- agp_speed
- pci_set_bus_speed
- pci_host_bridge_msi_domain
- pci_set_bus_msi_domain
- pci_register_host_bridge
- pci_bridge_child_ext_cfg_accessible
- pci_alloc_child_bus
- pci_add_new_bus
- pci_enable_crs
- pci_ea_fixed_busnrs
- pci_scan_bridge_extend
- pci_scan_bridge
- pci_read_irq
- set_pcie_port_type
- set_pcie_hotplug_bridge
- set_pcie_thunderbolt
- set_pcie_untrusted
- pci_ext_cfg_is_aliased
- pci_cfg_space_size_ext
- pci_cfg_space_size
- pci_class
- pci_subsystem_ids
- pci_hdr_type
- pci_msi_setup_pci_dev
- pci_intx_mask_broken
- early_dump_pci_device
- pci_setup_device
- pci_configure_mps
- pci_configure_extended_tags
- pcie_relaxed_ordering_enabled
- pci_configure_relaxed_ordering
- pci_configure_ltr
- pci_configure_eetlp_prefix
- pci_configure_serr
- pci_configure_device
- pci_release_capabilities
- pci_release_dev
- pci_alloc_dev
- pci_bus_crs_vendor_id
- pci_bus_wait_crs
- pci_bus_generic_read_dev_vendor_id
- pci_bus_read_dev_vendor_id
- pci_scan_device
- pcie_report_downtraining
- pci_init_capabilities
- pci_dev_msi_domain
- pci_set_msi_domain
- pci_device_add
- pci_scan_single_device
- next_fn
- only_one_child
- pci_scan_slot
- pcie_find_smpss
- pcie_write_mps
- pcie_write_mrrs
- pcie_bus_configure_set
- pcie_bus_configure_settings
- pcibios_fixup_bus
- pci_scan_child_bus_extend
- pci_scan_child_bus
- pcibios_root_bridge_prepare
- pcibios_add_bus
- pcibios_remove_bus
- pci_create_root_bus
- pci_host_probe
- pci_bus_insert_busn_res
- pci_bus_update_busn_res_end
- pci_bus_release_busn_res
- pci_scan_root_bus_bridge
- pci_scan_root_bus
- pci_scan_bus
- pci_rescan_bus_bridge_resize
- pci_rescan_bus
- pci_lock_rescan_remove
- pci_unlock_rescan_remove
- pci_sort_bf_cmp
- pci_sort_breadthfirst
- pci_hp_add_bridge
1
2
3
4
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/of_device.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci_hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/cpumask.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/hypervisor.h>
19 #include <linux/irqdomain.h>
20 #include <linux/pm_runtime.h>
21 #include "pci.h"
22
23 #define CARDBUS_LATENCY_TIMER 176
24 #define CARDBUS_RESERVE_BUSNR 3
25
26 static struct resource busn_resource = {
27 .name = "PCI busn",
28 .start = 0,
29 .end = 255,
30 .flags = IORESOURCE_BUS,
31 };
32
33
34 LIST_HEAD(pci_root_buses);
35 EXPORT_SYMBOL(pci_root_buses);
36
37 static LIST_HEAD(pci_domain_busn_res_list);
38
39 struct pci_domain_busn_res {
40 struct list_head list;
41 struct resource res;
42 int domain_nr;
43 };
44
45 static struct resource *get_pci_domain_busn_res(int domain_nr)
46 {
47 struct pci_domain_busn_res *r;
48
49 list_for_each_entry(r, &pci_domain_busn_res_list, list)
50 if (r->domain_nr == domain_nr)
51 return &r->res;
52
53 r = kzalloc(sizeof(*r), GFP_KERNEL);
54 if (!r)
55 return NULL;
56
57 r->domain_nr = domain_nr;
58 r->res.start = 0;
59 r->res.end = 0xff;
60 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
61
62 list_add_tail(&r->list, &pci_domain_busn_res_list);
63
64 return &r->res;
65 }
66
67
68
69
70
71
72 int no_pci_devices(void)
73 {
74 struct device *dev;
75 int no_devices;
76
77 dev = bus_find_next_device(&pci_bus_type, NULL);
78 no_devices = (dev == NULL);
79 put_device(dev);
80 return no_devices;
81 }
82 EXPORT_SYMBOL(no_pci_devices);
83
84
85
86
87 static void release_pcibus_dev(struct device *dev)
88 {
89 struct pci_bus *pci_bus = to_pci_bus(dev);
90
91 put_device(pci_bus->bridge);
92 pci_bus_remove_resources(pci_bus);
93 pci_release_bus_of_node(pci_bus);
94 kfree(pci_bus);
95 }
96
97 static struct class pcibus_class = {
98 .name = "pci_bus",
99 .dev_release = &release_pcibus_dev,
100 .dev_groups = pcibus_groups,
101 };
102
103 static int __init pcibus_class_init(void)
104 {
105 return class_register(&pcibus_class);
106 }
107 postcore_initcall(pcibus_class_init);
108
109 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
110 {
111 u64 size = mask & maxbase;
112 if (!size)
113 return 0;
114
115
116
117
118
119 size = size & ~(size-1);
120
121
122
123
124
125 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
126 return 0;
127
128 return size;
129 }
130
131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132 {
133 u32 mem_type;
134 unsigned long flags;
135
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
139 return flags;
140 }
141
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
146
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 switch (mem_type) {
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152
153 break;
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
156 break;
157 default:
158
159 break;
160 }
161 return flags;
162 }
163
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165
166
167
168
169
170
171
172
173
174
175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
177 {
178 u32 l = 0, sz = 0, mask;
179 u64 l64, sz64, mask64;
180 u16 orig_cmd;
181 struct pci_bus_region region, inverted_region;
182
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
184
185
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 }
192 }
193
194 res->name = pci_name(dev);
195
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
200
201
202
203
204
205
206
207 if (sz == 0xffffffff)
208 sz = 0;
209
210
211
212
213
214 if (l == 0xffffffff)
215 l = 0;
216
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
224 } else {
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
228 }
229 } else {
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = PCI_ROM_ADDRESS_MASK;
235 }
236
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
242
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
246 }
247
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
250
251 if (!sz64)
252 goto fail;
253
254 sz64 = pci_size(l64, sz64, mask64);
255 if (!sz64) {
256 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
257 pos);
258 goto fail;
259 }
260
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 res->start = 0;
266 res->end = 0;
267 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
269 goto out;
270 }
271
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273
274 res->flags |= IORESOURCE_UNSET;
275 res->start = 0;
276 res->end = sz64 - 1;
277 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
279 goto out;
280 }
281 }
282
283 region.start = l64;
284 region.end = l64 + sz64 - 1;
285
286 pcibios_bus_to_resource(dev->bus, res, ®ion);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
288
289
290
291
292
293
294
295
296
297
298
299
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
302 res->start = 0;
303 res->end = region.end - region.start;
304 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
306 }
307
308 goto out;
309
310
311 fail:
312 res->flags = 0;
313 out:
314 if (res->flags)
315 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
316
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
318 }
319
320 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321 {
322 unsigned int pos, reg;
323
324 if (dev->non_compliant_bars)
325 return;
326
327
328 if (dev->is_virtfn)
329 return;
330
331 for (pos = 0; pos < howmany; pos++) {
332 struct resource *res = &dev->resource[pos];
333 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
334 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
335 }
336
337 if (rom) {
338 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
339 dev->rom_base_reg = rom;
340 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
341 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
342 __pci_read_base(dev, pci_bar_mem32, res, rom);
343 }
344 }
345
346 static void pci_read_bridge_windows(struct pci_dev *bridge)
347 {
348 u16 io;
349 u32 pmem, tmp;
350
351 pci_read_config_word(bridge, PCI_IO_BASE, &io);
352 if (!io) {
353 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
354 pci_read_config_word(bridge, PCI_IO_BASE, &io);
355 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
356 }
357 if (io)
358 bridge->io_window = 1;
359
360
361
362
363
364
365 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
366 return;
367
368 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
369 if (!pmem) {
370 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
371 0xffe0fff0);
372 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
373 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
374 }
375 if (!pmem)
376 return;
377
378 bridge->pref_window = 1;
379
380 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
381
382
383
384
385
386
387 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
388 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
389 0xffffffff);
390 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
391 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
392 if (tmp)
393 bridge->pref_64_window = 1;
394 }
395 }
396
397 static void pci_read_bridge_io(struct pci_bus *child)
398 {
399 struct pci_dev *dev = child->self;
400 u8 io_base_lo, io_limit_lo;
401 unsigned long io_mask, io_granularity, base, limit;
402 struct pci_bus_region region;
403 struct resource *res;
404
405 io_mask = PCI_IO_RANGE_MASK;
406 io_granularity = 0x1000;
407 if (dev->io_window_1k) {
408
409 io_mask = PCI_IO_1K_RANGE_MASK;
410 io_granularity = 0x400;
411 }
412
413 res = child->resource[0];
414 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
415 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
416 base = (io_base_lo & io_mask) << 8;
417 limit = (io_limit_lo & io_mask) << 8;
418
419 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
420 u16 io_base_hi, io_limit_hi;
421
422 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
423 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
424 base |= ((unsigned long) io_base_hi << 16);
425 limit |= ((unsigned long) io_limit_hi << 16);
426 }
427
428 if (base <= limit) {
429 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
430 region.start = base;
431 region.end = limit + io_granularity - 1;
432 pcibios_bus_to_resource(dev->bus, res, ®ion);
433 pci_info(dev, " bridge window %pR\n", res);
434 }
435 }
436
437 static void pci_read_bridge_mmio(struct pci_bus *child)
438 {
439 struct pci_dev *dev = child->self;
440 u16 mem_base_lo, mem_limit_lo;
441 unsigned long base, limit;
442 struct pci_bus_region region;
443 struct resource *res;
444
445 res = child->resource[1];
446 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
447 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
448 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
449 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
450 if (base <= limit) {
451 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
452 region.start = base;
453 region.end = limit + 0xfffff;
454 pcibios_bus_to_resource(dev->bus, res, ®ion);
455 pci_info(dev, " bridge window %pR\n", res);
456 }
457 }
458
459 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
460 {
461 struct pci_dev *dev = child->self;
462 u16 mem_base_lo, mem_limit_lo;
463 u64 base64, limit64;
464 pci_bus_addr_t base, limit;
465 struct pci_bus_region region;
466 struct resource *res;
467
468 res = child->resource[2];
469 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
470 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
471 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
472 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
473
474 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
475 u32 mem_base_hi, mem_limit_hi;
476
477 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
478 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
479
480
481
482
483
484
485 if (mem_base_hi <= mem_limit_hi) {
486 base64 |= (u64) mem_base_hi << 32;
487 limit64 |= (u64) mem_limit_hi << 32;
488 }
489 }
490
491 base = (pci_bus_addr_t) base64;
492 limit = (pci_bus_addr_t) limit64;
493
494 if (base != base64) {
495 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
496 (unsigned long long) base64);
497 return;
498 }
499
500 if (base <= limit) {
501 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
502 IORESOURCE_MEM | IORESOURCE_PREFETCH;
503 if (res->flags & PCI_PREF_RANGE_TYPE_64)
504 res->flags |= IORESOURCE_MEM_64;
505 region.start = base;
506 region.end = limit + 0xfffff;
507 pcibios_bus_to_resource(dev->bus, res, ®ion);
508 pci_info(dev, " bridge window %pR\n", res);
509 }
510 }
511
512 void pci_read_bridge_bases(struct pci_bus *child)
513 {
514 struct pci_dev *dev = child->self;
515 struct resource *res;
516 int i;
517
518 if (pci_is_root_bus(child))
519 return;
520
521 pci_info(dev, "PCI bridge to %pR%s\n",
522 &child->busn_res,
523 dev->transparent ? " (subtractive decode)" : "");
524
525 pci_bus_remove_resources(child);
526 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
527 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
528
529 pci_read_bridge_io(child);
530 pci_read_bridge_mmio(child);
531 pci_read_bridge_mmio_pref(child);
532
533 if (dev->transparent) {
534 pci_bus_for_each_resource(child->parent, res, i) {
535 if (res && res->flags) {
536 pci_bus_add_resource(child, res,
537 PCI_SUBTRACTIVE_DECODE);
538 pci_info(dev, " bridge window %pR (subtractive decode)\n",
539 res);
540 }
541 }
542 }
543 }
544
545 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
546 {
547 struct pci_bus *b;
548
549 b = kzalloc(sizeof(*b), GFP_KERNEL);
550 if (!b)
551 return NULL;
552
553 INIT_LIST_HEAD(&b->node);
554 INIT_LIST_HEAD(&b->children);
555 INIT_LIST_HEAD(&b->devices);
556 INIT_LIST_HEAD(&b->slots);
557 INIT_LIST_HEAD(&b->resources);
558 b->max_bus_speed = PCI_SPEED_UNKNOWN;
559 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
560 #ifdef CONFIG_PCI_DOMAINS_GENERIC
561 if (parent)
562 b->domain_nr = parent->domain_nr;
563 #endif
564 return b;
565 }
566
567 static void devm_pci_release_host_bridge_dev(struct device *dev)
568 {
569 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
570
571 if (bridge->release_fn)
572 bridge->release_fn(bridge);
573
574 pci_free_resource_list(&bridge->windows);
575 pci_free_resource_list(&bridge->dma_ranges);
576 }
577
578 static void pci_release_host_bridge_dev(struct device *dev)
579 {
580 devm_pci_release_host_bridge_dev(dev);
581 kfree(to_pci_host_bridge(dev));
582 }
583
584 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
585 {
586 INIT_LIST_HEAD(&bridge->windows);
587 INIT_LIST_HEAD(&bridge->dma_ranges);
588
589
590
591
592
593
594
595 bridge->native_aer = 1;
596 bridge->native_pcie_hotplug = 1;
597 bridge->native_shpc_hotplug = 1;
598 bridge->native_pme = 1;
599 bridge->native_ltr = 1;
600 }
601
602 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
603 {
604 struct pci_host_bridge *bridge;
605
606 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
607 if (!bridge)
608 return NULL;
609
610 pci_init_host_bridge(bridge);
611 bridge->dev.release = pci_release_host_bridge_dev;
612
613 return bridge;
614 }
615 EXPORT_SYMBOL(pci_alloc_host_bridge);
616
617 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
618 size_t priv)
619 {
620 struct pci_host_bridge *bridge;
621
622 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
623 if (!bridge)
624 return NULL;
625
626 pci_init_host_bridge(bridge);
627 bridge->dev.release = devm_pci_release_host_bridge_dev;
628
629 return bridge;
630 }
631 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
632
633 void pci_free_host_bridge(struct pci_host_bridge *bridge)
634 {
635 pci_free_resource_list(&bridge->windows);
636 pci_free_resource_list(&bridge->dma_ranges);
637
638 kfree(bridge);
639 }
640 EXPORT_SYMBOL(pci_free_host_bridge);
641
642 static const unsigned char pcix_bus_speed[] = {
643 PCI_SPEED_UNKNOWN,
644 PCI_SPEED_66MHz_PCIX,
645 PCI_SPEED_100MHz_PCIX,
646 PCI_SPEED_133MHz_PCIX,
647 PCI_SPEED_UNKNOWN,
648 PCI_SPEED_66MHz_PCIX_ECC,
649 PCI_SPEED_100MHz_PCIX_ECC,
650 PCI_SPEED_133MHz_PCIX_ECC,
651 PCI_SPEED_UNKNOWN,
652 PCI_SPEED_66MHz_PCIX_266,
653 PCI_SPEED_100MHz_PCIX_266,
654 PCI_SPEED_133MHz_PCIX_266,
655 PCI_SPEED_UNKNOWN,
656 PCI_SPEED_66MHz_PCIX_533,
657 PCI_SPEED_100MHz_PCIX_533,
658 PCI_SPEED_133MHz_PCIX_533
659 };
660
661 const unsigned char pcie_link_speed[] = {
662 PCI_SPEED_UNKNOWN,
663 PCIE_SPEED_2_5GT,
664 PCIE_SPEED_5_0GT,
665 PCIE_SPEED_8_0GT,
666 PCIE_SPEED_16_0GT,
667 PCIE_SPEED_32_0GT,
668 PCI_SPEED_UNKNOWN,
669 PCI_SPEED_UNKNOWN,
670 PCI_SPEED_UNKNOWN,
671 PCI_SPEED_UNKNOWN,
672 PCI_SPEED_UNKNOWN,
673 PCI_SPEED_UNKNOWN,
674 PCI_SPEED_UNKNOWN,
675 PCI_SPEED_UNKNOWN,
676 PCI_SPEED_UNKNOWN,
677 PCI_SPEED_UNKNOWN
678 };
679
680 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
681 {
682 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
683 }
684 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
685
686 static unsigned char agp_speeds[] = {
687 AGP_UNKNOWN,
688 AGP_1X,
689 AGP_2X,
690 AGP_4X,
691 AGP_8X
692 };
693
694 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
695 {
696 int index = 0;
697
698 if (agpstat & 4)
699 index = 3;
700 else if (agpstat & 2)
701 index = 2;
702 else if (agpstat & 1)
703 index = 1;
704 else
705 goto out;
706
707 if (agp3) {
708 index += 2;
709 if (index == 5)
710 index = 0;
711 }
712
713 out:
714 return agp_speeds[index];
715 }
716
717 static void pci_set_bus_speed(struct pci_bus *bus)
718 {
719 struct pci_dev *bridge = bus->self;
720 int pos;
721
722 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
723 if (!pos)
724 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
725 if (pos) {
726 u32 agpstat, agpcmd;
727
728 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
729 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
730
731 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
732 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
733 }
734
735 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
736 if (pos) {
737 u16 status;
738 enum pci_bus_speed max;
739
740 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
741 &status);
742
743 if (status & PCI_X_SSTATUS_533MHZ) {
744 max = PCI_SPEED_133MHz_PCIX_533;
745 } else if (status & PCI_X_SSTATUS_266MHZ) {
746 max = PCI_SPEED_133MHz_PCIX_266;
747 } else if (status & PCI_X_SSTATUS_133MHZ) {
748 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
749 max = PCI_SPEED_133MHz_PCIX_ECC;
750 else
751 max = PCI_SPEED_133MHz_PCIX;
752 } else {
753 max = PCI_SPEED_66MHz_PCIX;
754 }
755
756 bus->max_bus_speed = max;
757 bus->cur_bus_speed = pcix_bus_speed[
758 (status & PCI_X_SSTATUS_FREQ) >> 6];
759
760 return;
761 }
762
763 if (pci_is_pcie(bridge)) {
764 u32 linkcap;
765 u16 linksta;
766
767 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
768 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
769 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
770
771 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
772 pcie_update_link_speed(bus, linksta);
773 }
774 }
775
776 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
777 {
778 struct irq_domain *d;
779
780
781
782
783
784 d = pci_host_bridge_of_msi_domain(bus);
785 if (!d)
786 d = pci_host_bridge_acpi_msi_domain(bus);
787
788 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
789
790
791
792
793 if (!d) {
794 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
795
796 if (fwnode)
797 d = irq_find_matching_fwnode(fwnode,
798 DOMAIN_BUS_PCI_MSI);
799 }
800 #endif
801
802 return d;
803 }
804
805 static void pci_set_bus_msi_domain(struct pci_bus *bus)
806 {
807 struct irq_domain *d;
808 struct pci_bus *b;
809
810
811
812
813
814
815 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
816 if (b->self)
817 d = dev_get_msi_domain(&b->self->dev);
818 }
819
820 if (!d)
821 d = pci_host_bridge_msi_domain(b);
822
823 dev_set_msi_domain(&bus->dev, d);
824 }
825
826 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
827 {
828 struct device *parent = bridge->dev.parent;
829 struct resource_entry *window, *n;
830 struct pci_bus *bus, *b;
831 resource_size_t offset;
832 LIST_HEAD(resources);
833 struct resource *res;
834 char addr[64], *fmt;
835 const char *name;
836 int err;
837
838 bus = pci_alloc_bus(NULL);
839 if (!bus)
840 return -ENOMEM;
841
842 bridge->bus = bus;
843
844
845 list_splice_init(&bridge->windows, &resources);
846 bus->sysdata = bridge->sysdata;
847 bus->msi = bridge->msi;
848 bus->ops = bridge->ops;
849 bus->number = bus->busn_res.start = bridge->busnr;
850 #ifdef CONFIG_PCI_DOMAINS_GENERIC
851 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
852 #endif
853
854 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
855 if (b) {
856
857 dev_dbg(&b->dev, "bus already known\n");
858 err = -EEXIST;
859 goto free;
860 }
861
862 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
863 bridge->busnr);
864
865 err = pcibios_root_bridge_prepare(bridge);
866 if (err)
867 goto free;
868
869 err = device_register(&bridge->dev);
870 if (err)
871 put_device(&bridge->dev);
872
873 bus->bridge = get_device(&bridge->dev);
874 device_enable_async_suspend(bus->bridge);
875 pci_set_bus_of_node(bus);
876 pci_set_bus_msi_domain(bus);
877
878 if (!parent)
879 set_dev_node(bus->bridge, pcibus_to_node(bus));
880
881 bus->dev.class = &pcibus_class;
882 bus->dev.parent = bus->bridge;
883
884 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
885 name = dev_name(&bus->dev);
886
887 err = device_register(&bus->dev);
888 if (err)
889 goto unregister;
890
891 pcibios_add_bus(bus);
892
893
894 pci_create_legacy_files(bus);
895
896 if (parent)
897 dev_info(parent, "PCI host bridge to bus %s\n", name);
898 else
899 pr_info("PCI host bridge to bus %s\n", name);
900
901
902 resource_list_for_each_entry_safe(window, n, &resources) {
903 list_move_tail(&window->node, &bridge->windows);
904 offset = window->offset;
905 res = window->res;
906
907 if (res->flags & IORESOURCE_BUS)
908 pci_bus_insert_busn_res(bus, bus->number, res->end);
909 else
910 pci_bus_add_resource(bus, res, 0);
911
912 if (offset) {
913 if (resource_type(res) == IORESOURCE_IO)
914 fmt = " (bus address [%#06llx-%#06llx])";
915 else
916 fmt = " (bus address [%#010llx-%#010llx])";
917
918 snprintf(addr, sizeof(addr), fmt,
919 (unsigned long long)(res->start - offset),
920 (unsigned long long)(res->end - offset));
921 } else
922 addr[0] = '\0';
923
924 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
925 }
926
927 down_write(&pci_bus_sem);
928 list_add_tail(&bus->node, &pci_root_buses);
929 up_write(&pci_bus_sem);
930
931 return 0;
932
933 unregister:
934 put_device(&bridge->dev);
935 device_unregister(&bridge->dev);
936
937 free:
938 kfree(bus);
939 return err;
940 }
941
942 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
943 {
944 int pos;
945 u32 status;
946
947
948
949
950
951 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
952 return false;
953
954
955
956
957
958
959 if (pci_is_pcie(bridge) &&
960 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
961 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
962 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
963 return true;
964
965
966
967
968
969
970
971
972
973 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
974 if (!pos)
975 return false;
976
977 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
978 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
979 }
980
981 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
982 struct pci_dev *bridge, int busnr)
983 {
984 struct pci_bus *child;
985 int i;
986 int ret;
987
988
989 child = pci_alloc_bus(parent);
990 if (!child)
991 return NULL;
992
993 child->parent = parent;
994 child->ops = parent->ops;
995 child->msi = parent->msi;
996 child->sysdata = parent->sysdata;
997 child->bus_flags = parent->bus_flags;
998
999
1000
1001
1002
1003 child->dev.class = &pcibus_class;
1004 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1005
1006
1007 child->number = child->busn_res.start = busnr;
1008 child->primary = parent->busn_res.start;
1009 child->busn_res.end = 0xff;
1010
1011 if (!bridge) {
1012 child->dev.parent = parent->bridge;
1013 goto add_dev;
1014 }
1015
1016 child->self = bridge;
1017 child->bridge = get_device(&bridge->dev);
1018 child->dev.parent = child->bridge;
1019 pci_set_bus_of_node(child);
1020 pci_set_bus_speed(child);
1021
1022
1023
1024
1025
1026
1027 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1028 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1029 pci_info(child, "extended config space not accessible\n");
1030 }
1031
1032
1033 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1034 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1035 child->resource[i]->name = child->name;
1036 }
1037 bridge->subordinate = child;
1038
1039 add_dev:
1040 pci_set_bus_msi_domain(child);
1041 ret = device_register(&child->dev);
1042 WARN_ON(ret < 0);
1043
1044 pcibios_add_bus(child);
1045
1046 if (child->ops->add_bus) {
1047 ret = child->ops->add_bus(child);
1048 if (WARN_ON(ret < 0))
1049 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1050 }
1051
1052
1053 pci_create_legacy_files(child);
1054
1055 return child;
1056 }
1057
1058 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1059 int busnr)
1060 {
1061 struct pci_bus *child;
1062
1063 child = pci_alloc_child_bus(parent, dev, busnr);
1064 if (child) {
1065 down_write(&pci_bus_sem);
1066 list_add_tail(&child->node, &parent->children);
1067 up_write(&pci_bus_sem);
1068 }
1069 return child;
1070 }
1071 EXPORT_SYMBOL(pci_add_new_bus);
1072
1073 static void pci_enable_crs(struct pci_dev *pdev)
1074 {
1075 u16 root_cap = 0;
1076
1077
1078 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1079 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1080 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1081 PCI_EXP_RTCTL_CRSSVE);
1082 }
1083
1084 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1085 unsigned int available_buses);
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1098 {
1099 int ea, offset;
1100 u32 dw;
1101 u8 ea_sec, ea_sub;
1102
1103 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1104 return false;
1105
1106
1107 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1108 if (!ea)
1109 return false;
1110
1111 offset = ea + PCI_EA_FIRST_ENT;
1112 pci_read_config_dword(dev, offset, &dw);
1113 ea_sec = dw & PCI_EA_SEC_BUS_MASK;
1114 ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1115 if (ea_sec == 0 || ea_sub < ea_sec)
1116 return false;
1117
1118 *sec = ea_sec;
1119 *sub = ea_sub;
1120 return true;
1121 }
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1147 int max, unsigned int available_buses,
1148 int pass)
1149 {
1150 struct pci_bus *child;
1151 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1152 u32 buses, i, j = 0;
1153 u16 bctl;
1154 u8 primary, secondary, subordinate;
1155 int broken = 0;
1156 bool fixed_buses;
1157 u8 fixed_sec, fixed_sub;
1158 int next_busnr;
1159
1160
1161
1162
1163
1164 pm_runtime_get_sync(&dev->dev);
1165
1166 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1167 primary = buses & 0xFF;
1168 secondary = (buses >> 8) & 0xFF;
1169 subordinate = (buses >> 16) & 0xFF;
1170
1171 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1172 secondary, subordinate, pass);
1173
1174 if (!primary && (primary != bus->number) && secondary && subordinate) {
1175 pci_warn(dev, "Primary bus is hard wired to 0\n");
1176 primary = bus->number;
1177 }
1178
1179
1180 if (!pass &&
1181 (primary != bus->number || secondary <= bus->number ||
1182 secondary > subordinate)) {
1183 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1184 secondary, subordinate);
1185 broken = 1;
1186 }
1187
1188
1189
1190
1191
1192 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1193 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1194 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1195
1196 pci_enable_crs(dev);
1197
1198 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1199 !is_cardbus && !broken) {
1200 unsigned int cmax;
1201
1202
1203
1204
1205
1206 if (pass)
1207 goto out;
1208
1209
1210
1211
1212
1213
1214
1215 child = pci_find_bus(pci_domain_nr(bus), secondary);
1216 if (!child) {
1217 child = pci_add_new_bus(bus, dev, secondary);
1218 if (!child)
1219 goto out;
1220 child->primary = primary;
1221 pci_bus_insert_busn_res(child, secondary, subordinate);
1222 child->bridge_ctl = bctl;
1223 }
1224
1225 cmax = pci_scan_child_bus(child);
1226 if (cmax > subordinate)
1227 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1228 subordinate, cmax);
1229
1230
1231 if (subordinate > max)
1232 max = subordinate;
1233 } else {
1234
1235
1236
1237
1238
1239 if (!pass) {
1240 if (pcibios_assign_all_busses() || broken || is_cardbus)
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1251 buses & ~0xffffff);
1252 goto out;
1253 }
1254
1255
1256 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1257
1258
1259 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1260 if (fixed_buses)
1261 next_busnr = fixed_sec;
1262 else
1263 next_busnr = max + 1;
1264
1265
1266
1267
1268
1269
1270 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1271 if (!child) {
1272 child = pci_add_new_bus(bus, dev, next_busnr);
1273 if (!child)
1274 goto out;
1275 pci_bus_insert_busn_res(child, next_busnr,
1276 bus->busn_res.end);
1277 }
1278 max++;
1279 if (available_buses)
1280 available_buses--;
1281
1282 buses = (buses & 0xff000000)
1283 | ((unsigned int)(child->primary) << 0)
1284 | ((unsigned int)(child->busn_res.start) << 8)
1285 | ((unsigned int)(child->busn_res.end) << 16);
1286
1287
1288
1289
1290
1291 if (is_cardbus) {
1292 buses &= ~0xff000000;
1293 buses |= CARDBUS_LATENCY_TIMER << 24;
1294 }
1295
1296
1297 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1298
1299 if (!is_cardbus) {
1300 child->bridge_ctl = bctl;
1301 max = pci_scan_child_bus_extend(child, available_buses);
1302 } else {
1303
1304
1305
1306
1307
1308
1309 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1310 struct pci_bus *parent = bus;
1311 if (pci_find_bus(pci_domain_nr(bus),
1312 max+i+1))
1313 break;
1314 while (parent->parent) {
1315 if ((!pcibios_assign_all_busses()) &&
1316 (parent->busn_res.end > max) &&
1317 (parent->busn_res.end <= max+i)) {
1318 j = 1;
1319 }
1320 parent = parent->parent;
1321 }
1322 if (j) {
1323
1324
1325
1326
1327
1328
1329 i /= 2;
1330 break;
1331 }
1332 }
1333 max += i;
1334 }
1335
1336
1337
1338
1339
1340
1341 if (fixed_buses)
1342 max = fixed_sub;
1343 pci_bus_update_busn_res_end(child, max);
1344 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1345 }
1346
1347 sprintf(child->name,
1348 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1349 pci_domain_nr(bus), child->number);
1350
1351
1352 while (bus->parent) {
1353 if ((child->busn_res.end > bus->busn_res.end) ||
1354 (child->number > bus->busn_res.end) ||
1355 (child->number < bus->number) ||
1356 (child->busn_res.end < bus->number)) {
1357 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1358 &child->busn_res);
1359 break;
1360 }
1361 bus = bus->parent;
1362 }
1363
1364 out:
1365 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1366
1367 pm_runtime_put(&dev->dev);
1368
1369 return max;
1370 }
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1392 {
1393 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1394 }
1395 EXPORT_SYMBOL(pci_scan_bridge);
1396
1397
1398
1399
1400
1401 static void pci_read_irq(struct pci_dev *dev)
1402 {
1403 unsigned char irq;
1404
1405
1406 if (dev->is_virtfn) {
1407 dev->pin = 0;
1408 dev->irq = 0;
1409 return;
1410 }
1411
1412 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1413 dev->pin = irq;
1414 if (irq)
1415 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1416 dev->irq = irq;
1417 }
1418
1419 void set_pcie_port_type(struct pci_dev *pdev)
1420 {
1421 int pos;
1422 u16 reg16;
1423 int type;
1424 struct pci_dev *parent;
1425
1426 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1427 if (!pos)
1428 return;
1429
1430 pdev->pcie_cap = pos;
1431 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1432 pdev->pcie_flags_reg = reg16;
1433 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1434 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1435
1436 parent = pci_upstream_bridge(pdev);
1437 if (!parent)
1438 return;
1439
1440
1441
1442
1443
1444
1445 type = pci_pcie_type(pdev);
1446 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1447
1448
1449
1450
1451
1452 if (pcie_downstream_port(parent)) {
1453 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1454 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1455 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1456 }
1457 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1458
1459
1460
1461
1462
1463 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1464 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1465 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1466 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1467 }
1468 }
1469 }
1470
1471 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1472 {
1473 u32 reg32;
1474
1475 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1476 if (reg32 & PCI_EXP_SLTCAP_HPC)
1477 pdev->is_hotplug_bridge = 1;
1478 }
1479
1480 static void set_pcie_thunderbolt(struct pci_dev *dev)
1481 {
1482 int vsec = 0;
1483 u32 header;
1484
1485 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1486 PCI_EXT_CAP_ID_VNDR))) {
1487 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1488
1489
1490 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1491 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1492 dev->is_thunderbolt = 1;
1493 return;
1494 }
1495 }
1496 }
1497
1498 static void set_pcie_untrusted(struct pci_dev *dev)
1499 {
1500 struct pci_dev *parent;
1501
1502
1503
1504
1505
1506 parent = pci_upstream_bridge(dev);
1507 if (parent && parent->untrusted)
1508 dev->untrusted = true;
1509 }
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1528 {
1529 #ifdef CONFIG_PCI_QUIRKS
1530 int pos;
1531 u32 header, tmp;
1532
1533 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1534
1535 for (pos = PCI_CFG_SPACE_SIZE;
1536 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1537 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1538 || header != tmp)
1539 return false;
1540 }
1541
1542 return true;
1543 #else
1544 return false;
1545 #endif
1546 }
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1560 {
1561 u32 status;
1562 int pos = PCI_CFG_SPACE_SIZE;
1563
1564 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1565 return PCI_CFG_SPACE_SIZE;
1566 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1567 return PCI_CFG_SPACE_SIZE;
1568
1569 return PCI_CFG_SPACE_EXP_SIZE;
1570 }
1571
1572 int pci_cfg_space_size(struct pci_dev *dev)
1573 {
1574 int pos;
1575 u32 status;
1576 u16 class;
1577
1578 #ifdef CONFIG_PCI_IOV
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589 if (dev->is_virtfn)
1590 return PCI_CFG_SPACE_EXP_SIZE;
1591 #endif
1592
1593 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1594 return PCI_CFG_SPACE_SIZE;
1595
1596 class = dev->class >> 8;
1597 if (class == PCI_CLASS_BRIDGE_HOST)
1598 return pci_cfg_space_size_ext(dev);
1599
1600 if (pci_is_pcie(dev))
1601 return pci_cfg_space_size_ext(dev);
1602
1603 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1604 if (!pos)
1605 return PCI_CFG_SPACE_SIZE;
1606
1607 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1608 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1609 return pci_cfg_space_size_ext(dev);
1610
1611 return PCI_CFG_SPACE_SIZE;
1612 }
1613
1614 static u32 pci_class(struct pci_dev *dev)
1615 {
1616 u32 class;
1617
1618 #ifdef CONFIG_PCI_IOV
1619 if (dev->is_virtfn)
1620 return dev->physfn->sriov->class;
1621 #endif
1622 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1623 return class;
1624 }
1625
1626 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1627 {
1628 #ifdef CONFIG_PCI_IOV
1629 if (dev->is_virtfn) {
1630 *vendor = dev->physfn->sriov->subsystem_vendor;
1631 *device = dev->physfn->sriov->subsystem_device;
1632 return;
1633 }
1634 #endif
1635 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1636 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1637 }
1638
1639 static u8 pci_hdr_type(struct pci_dev *dev)
1640 {
1641 u8 hdr_type;
1642
1643 #ifdef CONFIG_PCI_IOV
1644 if (dev->is_virtfn)
1645 return dev->physfn->sriov->hdr_type;
1646 #endif
1647 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1648 return hdr_type;
1649 }
1650
1651 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1652
1653 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1654 {
1655
1656
1657
1658
1659
1660 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1661 if (dev->msi_cap)
1662 pci_msi_set_enable(dev, 0);
1663
1664 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1665 if (dev->msix_cap)
1666 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1667 }
1668
1669
1670
1671
1672
1673
1674
1675
1676 static int pci_intx_mask_broken(struct pci_dev *dev)
1677 {
1678 u16 orig, toggle, new;
1679
1680 pci_read_config_word(dev, PCI_COMMAND, &orig);
1681 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1682 pci_write_config_word(dev, PCI_COMMAND, toggle);
1683 pci_read_config_word(dev, PCI_COMMAND, &new);
1684
1685 pci_write_config_word(dev, PCI_COMMAND, orig);
1686
1687
1688
1689
1690
1691
1692 if (new != toggle)
1693 return 1;
1694 return 0;
1695 }
1696
1697 static void early_dump_pci_device(struct pci_dev *pdev)
1698 {
1699 u32 value[256 / 4];
1700 int i;
1701
1702 pci_info(pdev, "config space:\n");
1703
1704 for (i = 0; i < 256; i += 4)
1705 pci_read_config_dword(pdev, i, &value[i / 4]);
1706
1707 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1708 value, 256, false);
1709 }
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721 int pci_setup_device(struct pci_dev *dev)
1722 {
1723 u32 class;
1724 u16 cmd;
1725 u8 hdr_type;
1726 int pos = 0;
1727 struct pci_bus_region region;
1728 struct resource *res;
1729
1730 hdr_type = pci_hdr_type(dev);
1731
1732 dev->sysdata = dev->bus->sysdata;
1733 dev->dev.parent = dev->bus->bridge;
1734 dev->dev.bus = &pci_bus_type;
1735 dev->hdr_type = hdr_type & 0x7f;
1736 dev->multifunction = !!(hdr_type & 0x80);
1737 dev->error_state = pci_channel_io_normal;
1738 set_pcie_port_type(dev);
1739
1740 pci_dev_assign_slot(dev);
1741
1742
1743
1744
1745
1746 dev->dma_mask = 0xffffffff;
1747
1748 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1749 dev->bus->number, PCI_SLOT(dev->devfn),
1750 PCI_FUNC(dev->devfn));
1751
1752 class = pci_class(dev);
1753
1754 dev->revision = class & 0xff;
1755 dev->class = class >> 8;
1756
1757 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1758 dev->vendor, dev->device, dev->hdr_type, dev->class);
1759
1760 if (pci_early_dump)
1761 early_dump_pci_device(dev);
1762
1763
1764 dev->cfg_size = pci_cfg_space_size(dev);
1765
1766
1767 set_pcie_thunderbolt(dev);
1768
1769 set_pcie_untrusted(dev);
1770
1771
1772 dev->current_state = PCI_UNKNOWN;
1773
1774
1775 pci_fixup_device(pci_fixup_early, dev);
1776
1777
1778 class = dev->class >> 8;
1779
1780 if (dev->non_compliant_bars) {
1781 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1782 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1783 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1784 cmd &= ~PCI_COMMAND_IO;
1785 cmd &= ~PCI_COMMAND_MEMORY;
1786 pci_write_config_word(dev, PCI_COMMAND, cmd);
1787 }
1788 }
1789
1790 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1791
1792 switch (dev->hdr_type) {
1793 case PCI_HEADER_TYPE_NORMAL:
1794 if (class == PCI_CLASS_BRIDGE_PCI)
1795 goto bad;
1796 pci_read_irq(dev);
1797 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1798
1799 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1800
1801
1802
1803
1804
1805
1806
1807 if (class == PCI_CLASS_STORAGE_IDE) {
1808 u8 progif;
1809 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1810 if ((progif & 1) == 0) {
1811 region.start = 0x1F0;
1812 region.end = 0x1F7;
1813 res = &dev->resource[0];
1814 res->flags = LEGACY_IO_RESOURCE;
1815 pcibios_bus_to_resource(dev->bus, res, ®ion);
1816 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1817 res);
1818 region.start = 0x3F6;
1819 region.end = 0x3F6;
1820 res = &dev->resource[1];
1821 res->flags = LEGACY_IO_RESOURCE;
1822 pcibios_bus_to_resource(dev->bus, res, ®ion);
1823 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1824 res);
1825 }
1826 if ((progif & 4) == 0) {
1827 region.start = 0x170;
1828 region.end = 0x177;
1829 res = &dev->resource[2];
1830 res->flags = LEGACY_IO_RESOURCE;
1831 pcibios_bus_to_resource(dev->bus, res, ®ion);
1832 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1833 res);
1834 region.start = 0x376;
1835 region.end = 0x376;
1836 res = &dev->resource[3];
1837 res->flags = LEGACY_IO_RESOURCE;
1838 pcibios_bus_to_resource(dev->bus, res, ®ion);
1839 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1840 res);
1841 }
1842 }
1843 break;
1844
1845 case PCI_HEADER_TYPE_BRIDGE:
1846
1847
1848
1849
1850
1851 pci_read_irq(dev);
1852 dev->transparent = ((dev->class & 0xff) == 1);
1853 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1854 pci_read_bridge_windows(dev);
1855 set_pcie_hotplug_bridge(dev);
1856 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1857 if (pos) {
1858 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1859 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1860 }
1861 break;
1862
1863 case PCI_HEADER_TYPE_CARDBUS:
1864 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1865 goto bad;
1866 pci_read_irq(dev);
1867 pci_read_bases(dev, 1, 0);
1868 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1869 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1870 break;
1871
1872 default:
1873 pci_err(dev, "unknown header type %02x, ignoring device\n",
1874 dev->hdr_type);
1875 return -EIO;
1876
1877 bad:
1878 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1879 dev->class, dev->hdr_type);
1880 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1881 }
1882
1883
1884 return 0;
1885 }
1886
1887 static void pci_configure_mps(struct pci_dev *dev)
1888 {
1889 struct pci_dev *bridge = pci_upstream_bridge(dev);
1890 int mps, mpss, p_mps, rc;
1891
1892 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1893 return;
1894
1895
1896 if (dev->is_virtfn)
1897 return;
1898
1899 mps = pcie_get_mps(dev);
1900 p_mps = pcie_get_mps(bridge);
1901
1902 if (mps == p_mps)
1903 return;
1904
1905 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1906 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1907 mps, pci_name(bridge), p_mps);
1908 return;
1909 }
1910
1911
1912
1913
1914
1915 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1916 return;
1917
1918 mpss = 128 << dev->pcie_mpss;
1919 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1920 pcie_set_mps(bridge, mpss);
1921 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1922 mpss, p_mps, 128 << bridge->pcie_mpss);
1923 p_mps = pcie_get_mps(bridge);
1924 }
1925
1926 rc = pcie_set_mps(dev, p_mps);
1927 if (rc) {
1928 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1929 p_mps);
1930 return;
1931 }
1932
1933 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1934 p_mps, mps, mpss);
1935 }
1936
1937 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1938 {
1939 struct pci_host_bridge *host;
1940 u32 cap;
1941 u16 ctl;
1942 int ret;
1943
1944 if (!pci_is_pcie(dev))
1945 return 0;
1946
1947 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1948 if (ret)
1949 return 0;
1950
1951 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1952 return 0;
1953
1954 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1955 if (ret)
1956 return 0;
1957
1958 host = pci_find_host_bridge(dev->bus);
1959 if (!host)
1960 return 0;
1961
1962
1963
1964
1965
1966 if (host->no_ext_tags) {
1967 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1968 pci_info(dev, "disabling Extended Tags\n");
1969 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1970 PCI_EXP_DEVCTL_EXT_TAG);
1971 }
1972 return 0;
1973 }
1974
1975 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1976 pci_info(dev, "enabling Extended Tags\n");
1977 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1978 PCI_EXP_DEVCTL_EXT_TAG);
1979 }
1980 return 0;
1981 }
1982
1983
1984
1985
1986
1987
1988
1989 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1990 {
1991 u16 v;
1992
1993 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1994
1995 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1996 }
1997 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1998
1999 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2000 {
2001 struct pci_dev *root;
2002
2003
2004 if (dev->is_virtfn)
2005 return;
2006
2007 if (!pcie_relaxed_ordering_enabled(dev))
2008 return;
2009
2010
2011
2012
2013
2014 root = pci_find_pcie_root_port(dev);
2015 if (!root)
2016 return;
2017
2018 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2019 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2020 PCI_EXP_DEVCTL_RELAX_EN);
2021 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2022 }
2023 }
2024
2025 static void pci_configure_ltr(struct pci_dev *dev)
2026 {
2027 #ifdef CONFIG_PCIEASPM
2028 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2029 struct pci_dev *bridge;
2030 u32 cap, ctl;
2031
2032 if (!pci_is_pcie(dev))
2033 return;
2034
2035 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2036 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2037 return;
2038
2039 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2040 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2041 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2042 dev->ltr_path = 1;
2043 return;
2044 }
2045
2046 bridge = pci_upstream_bridge(dev);
2047 if (bridge && bridge->ltr_path)
2048 dev->ltr_path = 1;
2049
2050 return;
2051 }
2052
2053 if (!host->native_ltr)
2054 return;
2055
2056
2057
2058
2059
2060
2061 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2062 ((bridge = pci_upstream_bridge(dev)) &&
2063 bridge->ltr_path)) {
2064 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2065 PCI_EXP_DEVCTL2_LTR_EN);
2066 dev->ltr_path = 1;
2067 }
2068 #endif
2069 }
2070
2071 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2072 {
2073 #ifdef CONFIG_PCI_PASID
2074 struct pci_dev *bridge;
2075 int pcie_type;
2076 u32 cap;
2077
2078 if (!pci_is_pcie(dev))
2079 return;
2080
2081 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2082 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2083 return;
2084
2085 pcie_type = pci_pcie_type(dev);
2086 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2087 pcie_type == PCI_EXP_TYPE_RC_END)
2088 dev->eetlp_prefix_path = 1;
2089 else {
2090 bridge = pci_upstream_bridge(dev);
2091 if (bridge && bridge->eetlp_prefix_path)
2092 dev->eetlp_prefix_path = 1;
2093 }
2094 #endif
2095 }
2096
2097 static void pci_configure_serr(struct pci_dev *dev)
2098 {
2099 u16 control;
2100
2101 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2102
2103
2104
2105
2106
2107 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2108 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2109 control |= PCI_BRIDGE_CTL_SERR;
2110 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2111 }
2112 }
2113 }
2114
2115 static void pci_configure_device(struct pci_dev *dev)
2116 {
2117 pci_configure_mps(dev);
2118 pci_configure_extended_tags(dev, NULL);
2119 pci_configure_relaxed_ordering(dev);
2120 pci_configure_ltr(dev);
2121 pci_configure_eetlp_prefix(dev);
2122 pci_configure_serr(dev);
2123
2124 pci_acpi_program_hp_params(dev);
2125 }
2126
2127 static void pci_release_capabilities(struct pci_dev *dev)
2128 {
2129 pci_aer_exit(dev);
2130 pci_vpd_release(dev);
2131 pci_iov_release(dev);
2132 pci_free_cap_save_buffers(dev);
2133 }
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143 static void pci_release_dev(struct device *dev)
2144 {
2145 struct pci_dev *pci_dev;
2146
2147 pci_dev = to_pci_dev(dev);
2148 pci_release_capabilities(pci_dev);
2149 pci_release_of_node(pci_dev);
2150 pcibios_release_device(pci_dev);
2151 pci_bus_put(pci_dev->bus);
2152 kfree(pci_dev->driver_override);
2153 bitmap_free(pci_dev->dma_alias_mask);
2154 kfree(pci_dev);
2155 }
2156
2157 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2158 {
2159 struct pci_dev *dev;
2160
2161 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2162 if (!dev)
2163 return NULL;
2164
2165 INIT_LIST_HEAD(&dev->bus_list);
2166 dev->dev.type = &pci_dev_type;
2167 dev->bus = pci_bus_get(bus);
2168
2169 return dev;
2170 }
2171 EXPORT_SYMBOL(pci_alloc_dev);
2172
2173 static bool pci_bus_crs_vendor_id(u32 l)
2174 {
2175 return (l & 0xffff) == 0x0001;
2176 }
2177
2178 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2179 int timeout)
2180 {
2181 int delay = 1;
2182
2183 if (!pci_bus_crs_vendor_id(*l))
2184 return true;
2185
2186 if (!timeout)
2187 return false;
2188
2189
2190
2191
2192
2193
2194 while (pci_bus_crs_vendor_id(*l)) {
2195 if (delay > timeout) {
2196 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2197 pci_domain_nr(bus), bus->number,
2198 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2199
2200 return false;
2201 }
2202 if (delay >= 1000)
2203 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2204 pci_domain_nr(bus), bus->number,
2205 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2206
2207 msleep(delay);
2208 delay *= 2;
2209
2210 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2211 return false;
2212 }
2213
2214 if (delay >= 1000)
2215 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2216 pci_domain_nr(bus), bus->number,
2217 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2218
2219 return true;
2220 }
2221
2222 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2223 int timeout)
2224 {
2225 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2226 return false;
2227
2228
2229 if (*l == 0xffffffff || *l == 0x00000000 ||
2230 *l == 0x0000ffff || *l == 0xffff0000)
2231 return false;
2232
2233 if (pci_bus_crs_vendor_id(*l))
2234 return pci_bus_wait_crs(bus, devfn, l, timeout);
2235
2236 return true;
2237 }
2238
2239 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2240 int timeout)
2241 {
2242 #ifdef CONFIG_PCI_QUIRKS
2243 struct pci_dev *bridge = bus->self;
2244
2245
2246
2247
2248
2249 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2250 bridge->device == 0x80b5)
2251 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2252 #endif
2253
2254 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2255 }
2256 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2257
2258
2259
2260
2261
2262 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2263 {
2264 struct pci_dev *dev;
2265 u32 l;
2266
2267 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2268 return NULL;
2269
2270 dev = pci_alloc_dev(bus);
2271 if (!dev)
2272 return NULL;
2273
2274 dev->devfn = devfn;
2275 dev->vendor = l & 0xffff;
2276 dev->device = (l >> 16) & 0xffff;
2277
2278 pci_set_of_node(dev);
2279
2280 if (pci_setup_device(dev)) {
2281 pci_bus_put(dev->bus);
2282 kfree(dev);
2283 return NULL;
2284 }
2285
2286 return dev;
2287 }
2288
2289 void pcie_report_downtraining(struct pci_dev *dev)
2290 {
2291 if (!pci_is_pcie(dev))
2292 return;
2293
2294
2295 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2296 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2297 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2298 return;
2299
2300
2301 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2302 return;
2303
2304
2305 __pcie_print_link_status(dev, false);
2306 }
2307
2308 static void pci_init_capabilities(struct pci_dev *dev)
2309 {
2310
2311 pci_ea_init(dev);
2312
2313
2314 pci_msi_setup_pci_dev(dev);
2315
2316
2317 pci_allocate_cap_save_buffers(dev);
2318
2319
2320 pci_pm_init(dev);
2321
2322
2323 pci_vpd_init(dev);
2324
2325
2326 pci_configure_ari(dev);
2327
2328
2329 pci_iov_init(dev);
2330
2331
2332 pci_ats_init(dev);
2333
2334
2335 pci_enable_acs(dev);
2336
2337
2338 pci_ptm_init(dev);
2339
2340
2341 pci_aer_init(dev);
2342
2343 pcie_report_downtraining(dev);
2344
2345 if (pci_probe_reset_function(dev) == 0)
2346 dev->reset_fn = 1;
2347 }
2348
2349
2350
2351
2352
2353
2354 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2355 {
2356 struct irq_domain *d;
2357
2358
2359
2360
2361
2362 d = dev_get_msi_domain(&dev->dev);
2363 if (d)
2364 return d;
2365
2366
2367
2368
2369
2370 d = pci_msi_get_device_domain(dev);
2371 if (d)
2372 return d;
2373
2374 return NULL;
2375 }
2376
2377 static void pci_set_msi_domain(struct pci_dev *dev)
2378 {
2379 struct irq_domain *d;
2380
2381
2382
2383
2384
2385
2386 d = pci_dev_msi_domain(dev);
2387 if (!d)
2388 d = dev_get_msi_domain(&dev->bus->dev);
2389
2390 dev_set_msi_domain(&dev->dev, d);
2391 }
2392
2393 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2394 {
2395 int ret;
2396
2397 pci_configure_device(dev);
2398
2399 device_initialize(&dev->dev);
2400 dev->dev.release = pci_release_dev;
2401
2402 set_dev_node(&dev->dev, pcibus_to_node(bus));
2403 dev->dev.dma_mask = &dev->dma_mask;
2404 dev->dev.dma_parms = &dev->dma_parms;
2405 dev->dev.coherent_dma_mask = 0xffffffffull;
2406
2407 dma_set_max_seg_size(&dev->dev, 65536);
2408 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2409
2410
2411 pci_fixup_device(pci_fixup_header, dev);
2412
2413
2414 pci_reassigndev_resource_alignment(dev);
2415
2416
2417 dev->state_saved = false;
2418
2419
2420 pci_init_capabilities(dev);
2421
2422
2423
2424
2425
2426 down_write(&pci_bus_sem);
2427 list_add_tail(&dev->bus_list, &bus->devices);
2428 up_write(&pci_bus_sem);
2429
2430 ret = pcibios_add_device(dev);
2431 WARN_ON(ret < 0);
2432
2433
2434 pci_set_msi_domain(dev);
2435
2436
2437 dev->match_driver = false;
2438 ret = device_add(&dev->dev);
2439 WARN_ON(ret < 0);
2440 }
2441
2442 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2443 {
2444 struct pci_dev *dev;
2445
2446 dev = pci_get_slot(bus, devfn);
2447 if (dev) {
2448 pci_dev_put(dev);
2449 return dev;
2450 }
2451
2452 dev = pci_scan_device(bus, devfn);
2453 if (!dev)
2454 return NULL;
2455
2456 pci_device_add(dev, bus);
2457
2458 return dev;
2459 }
2460 EXPORT_SYMBOL(pci_scan_single_device);
2461
2462 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2463 {
2464 int pos;
2465 u16 cap = 0;
2466 unsigned next_fn;
2467
2468 if (pci_ari_enabled(bus)) {
2469 if (!dev)
2470 return 0;
2471 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2472 if (!pos)
2473 return 0;
2474
2475 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2476 next_fn = PCI_ARI_CAP_NFN(cap);
2477 if (next_fn <= fn)
2478 return 0;
2479
2480 return next_fn;
2481 }
2482
2483
2484 if (!dev || dev->multifunction)
2485 return (fn + 1) % 8;
2486
2487 return 0;
2488 }
2489
2490 static int only_one_child(struct pci_bus *bus)
2491 {
2492 struct pci_dev *bridge = bus->self;
2493
2494
2495
2496
2497
2498 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2499 return 0;
2500
2501
2502
2503
2504
2505
2506 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2507 return 1;
2508
2509 return 0;
2510 }
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523 int pci_scan_slot(struct pci_bus *bus, int devfn)
2524 {
2525 unsigned fn, nr = 0;
2526 struct pci_dev *dev;
2527
2528 if (only_one_child(bus) && (devfn > 0))
2529 return 0;
2530
2531 dev = pci_scan_single_device(bus, devfn);
2532 if (!dev)
2533 return 0;
2534 if (!pci_dev_is_added(dev))
2535 nr++;
2536
2537 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2538 dev = pci_scan_single_device(bus, devfn + fn);
2539 if (dev) {
2540 if (!pci_dev_is_added(dev))
2541 nr++;
2542 dev->multifunction = 1;
2543 }
2544 }
2545
2546
2547 if (bus->self && nr)
2548 pcie_aspm_init_link_state(bus->self);
2549
2550 return nr;
2551 }
2552 EXPORT_SYMBOL(pci_scan_slot);
2553
2554 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2555 {
2556 u8 *smpss = data;
2557
2558 if (!pci_is_pcie(dev))
2559 return 0;
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576 if (dev->is_hotplug_bridge &&
2577 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2578 *smpss = 0;
2579
2580 if (*smpss > dev->pcie_mpss)
2581 *smpss = dev->pcie_mpss;
2582
2583 return 0;
2584 }
2585
2586 static void pcie_write_mps(struct pci_dev *dev, int mps)
2587 {
2588 int rc;
2589
2590 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2591 mps = 128 << dev->pcie_mpss;
2592
2593 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2594 dev->bus->self)
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609 mps = min(mps, pcie_get_mps(dev->bus->self));
2610 }
2611
2612 rc = pcie_set_mps(dev, mps);
2613 if (rc)
2614 pci_err(dev, "Failed attempting to set the MPS\n");
2615 }
2616
2617 static void pcie_write_mrrs(struct pci_dev *dev)
2618 {
2619 int rc, mrrs;
2620
2621
2622
2623
2624
2625 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2626 return;
2627
2628
2629
2630
2631
2632
2633
2634 mrrs = pcie_get_mps(dev);
2635
2636
2637
2638
2639
2640
2641
2642 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2643 rc = pcie_set_readrq(dev, mrrs);
2644 if (!rc)
2645 break;
2646
2647 pci_warn(dev, "Failed attempting to set the MRRS\n");
2648 mrrs /= 2;
2649 }
2650
2651 if (mrrs < 128)
2652 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2653 }
2654
2655 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2656 {
2657 int mps, orig_mps;
2658
2659 if (!pci_is_pcie(dev))
2660 return 0;
2661
2662 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2663 pcie_bus_config == PCIE_BUS_DEFAULT)
2664 return 0;
2665
2666 mps = 128 << *(u8 *)data;
2667 orig_mps = pcie_get_mps(dev);
2668
2669 pcie_write_mps(dev, mps);
2670 pcie_write_mrrs(dev);
2671
2672 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2673 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2674 orig_mps, pcie_get_readrq(dev));
2675
2676 return 0;
2677 }
2678
2679
2680
2681
2682
2683
2684 void pcie_bus_configure_settings(struct pci_bus *bus)
2685 {
2686 u8 smpss = 0;
2687
2688 if (!bus->self)
2689 return;
2690
2691 if (!pci_is_pcie(bus->self))
2692 return;
2693
2694
2695
2696
2697
2698
2699 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2700 smpss = 0;
2701
2702 if (pcie_bus_config == PCIE_BUS_SAFE) {
2703 smpss = bus->self->pcie_mpss;
2704
2705 pcie_find_smpss(bus->self, &smpss);
2706 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2707 }
2708
2709 pcie_bus_configure_set(bus->self, &smpss);
2710 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2711 }
2712 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2713
2714
2715
2716
2717
2718 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2719 {
2720
2721 }
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2736 unsigned int available_buses)
2737 {
2738 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2739 unsigned int start = bus->busn_res.start;
2740 unsigned int devfn, fn, cmax, max = start;
2741 struct pci_dev *dev;
2742 int nr_devs;
2743
2744 dev_dbg(&bus->dev, "scanning bus\n");
2745
2746
2747 for (devfn = 0; devfn < 256; devfn += 8) {
2748 nr_devs = pci_scan_slot(bus, devfn);
2749
2750
2751
2752
2753
2754
2755 if (jailhouse_paravirt() && nr_devs == 0) {
2756 for (fn = 1; fn < 8; fn++) {
2757 dev = pci_scan_single_device(bus, devfn + fn);
2758 if (dev)
2759 dev->multifunction = 1;
2760 }
2761 }
2762 }
2763
2764
2765 used_buses = pci_iov_bus_range(bus);
2766 max += used_buses;
2767
2768
2769
2770
2771
2772 if (!bus->is_added) {
2773 dev_dbg(&bus->dev, "fixups for bus\n");
2774 pcibios_fixup_bus(bus);
2775 bus->is_added = 1;
2776 }
2777
2778
2779
2780
2781
2782
2783 for_each_pci_bridge(dev, bus) {
2784 if (dev->is_hotplug_bridge)
2785 hotplug_bridges++;
2786 else
2787 normal_bridges++;
2788 }
2789
2790
2791
2792
2793
2794
2795 for_each_pci_bridge(dev, bus) {
2796 cmax = max;
2797 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2798
2799
2800
2801
2802
2803 used_buses++;
2804 if (cmax - max > 1)
2805 used_buses += cmax - max - 1;
2806 }
2807
2808
2809 for_each_pci_bridge(dev, bus) {
2810 unsigned int buses = 0;
2811
2812 if (!hotplug_bridges && normal_bridges == 1) {
2813
2814
2815
2816
2817
2818
2819
2820 buses = available_buses;
2821 } else if (dev->is_hotplug_bridge) {
2822
2823
2824
2825
2826
2827 buses = available_buses / hotplug_bridges;
2828 buses = min(buses, available_buses - used_buses + 1);
2829 }
2830
2831 cmax = max;
2832 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2833
2834 if (max - cmax > 1)
2835 used_buses += max - cmax - 1;
2836 }
2837
2838
2839
2840
2841
2842
2843 if (bus->self && bus->self->is_hotplug_bridge) {
2844 used_buses = max_t(unsigned int, available_buses,
2845 pci_hotplug_bus_size - 1);
2846 if (max - start < used_buses) {
2847 max = start + used_buses;
2848
2849
2850 if (max > bus->busn_res.end)
2851 max = bus->busn_res.end;
2852
2853 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2854 &bus->busn_res, max - start);
2855 }
2856 }
2857
2858
2859
2860
2861
2862
2863
2864
2865 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2866 return max;
2867 }
2868
2869
2870
2871
2872
2873
2874
2875
2876 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2877 {
2878 return pci_scan_child_bus_extend(bus, 0);
2879 }
2880 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2881
2882
2883
2884
2885
2886
2887
2888
2889 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2890 {
2891 return 0;
2892 }
2893
2894 void __weak pcibios_add_bus(struct pci_bus *bus)
2895 {
2896 }
2897
2898 void __weak pcibios_remove_bus(struct pci_bus *bus)
2899 {
2900 }
2901
2902 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2903 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2904 {
2905 int error;
2906 struct pci_host_bridge *bridge;
2907
2908 bridge = pci_alloc_host_bridge(0);
2909 if (!bridge)
2910 return NULL;
2911
2912 bridge->dev.parent = parent;
2913
2914 list_splice_init(resources, &bridge->windows);
2915 bridge->sysdata = sysdata;
2916 bridge->busnr = bus;
2917 bridge->ops = ops;
2918
2919 error = pci_register_host_bridge(bridge);
2920 if (error < 0)
2921 goto err_out;
2922
2923 return bridge->bus;
2924
2925 err_out:
2926 kfree(bridge);
2927 return NULL;
2928 }
2929 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2930
2931 int pci_host_probe(struct pci_host_bridge *bridge)
2932 {
2933 struct pci_bus *bus, *child;
2934 int ret;
2935
2936 ret = pci_scan_root_bus_bridge(bridge);
2937 if (ret < 0) {
2938 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2939 return ret;
2940 }
2941
2942 bus = bridge->bus;
2943
2944
2945
2946
2947
2948
2949 if (pci_has_flag(PCI_PROBE_ONLY)) {
2950 pci_bus_claim_resources(bus);
2951 } else {
2952 pci_bus_size_bridges(bus);
2953 pci_bus_assign_resources(bus);
2954
2955 list_for_each_entry(child, &bus->children, node)
2956 pcie_bus_configure_settings(child);
2957 }
2958
2959 pci_bus_add_devices(bus);
2960 return 0;
2961 }
2962 EXPORT_SYMBOL_GPL(pci_host_probe);
2963
2964 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2965 {
2966 struct resource *res = &b->busn_res;
2967 struct resource *parent_res, *conflict;
2968
2969 res->start = bus;
2970 res->end = bus_max;
2971 res->flags = IORESOURCE_BUS;
2972
2973 if (!pci_is_root_bus(b))
2974 parent_res = &b->parent->busn_res;
2975 else {
2976 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2977 res->flags |= IORESOURCE_PCI_FIXED;
2978 }
2979
2980 conflict = request_resource_conflict(parent_res, res);
2981
2982 if (conflict)
2983 dev_info(&b->dev,
2984 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2985 res, pci_is_root_bus(b) ? "domain " : "",
2986 parent_res, conflict->name, conflict);
2987
2988 return conflict == NULL;
2989 }
2990
2991 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2992 {
2993 struct resource *res = &b->busn_res;
2994 struct resource old_res = *res;
2995 resource_size_t size;
2996 int ret;
2997
2998 if (res->start > bus_max)
2999 return -EINVAL;
3000
3001 size = bus_max - res->start + 1;
3002 ret = adjust_resource(res, res->start, size);
3003 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3004 &old_res, ret ? "can not be" : "is", bus_max);
3005
3006 if (!ret && !res->parent)
3007 pci_bus_insert_busn_res(b, res->start, res->end);
3008
3009 return ret;
3010 }
3011
3012 void pci_bus_release_busn_res(struct pci_bus *b)
3013 {
3014 struct resource *res = &b->busn_res;
3015 int ret;
3016
3017 if (!res->flags || !res->parent)
3018 return;
3019
3020 ret = release_resource(res);
3021 dev_info(&b->dev, "busn_res: %pR %s released\n",
3022 res, ret ? "can not be" : "is");
3023 }
3024
3025 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3026 {
3027 struct resource_entry *window;
3028 bool found = false;
3029 struct pci_bus *b;
3030 int max, bus, ret;
3031
3032 if (!bridge)
3033 return -EINVAL;
3034
3035 resource_list_for_each_entry(window, &bridge->windows)
3036 if (window->res->flags & IORESOURCE_BUS) {
3037 found = true;
3038 break;
3039 }
3040
3041 ret = pci_register_host_bridge(bridge);
3042 if (ret < 0)
3043 return ret;
3044
3045 b = bridge->bus;
3046 bus = bridge->busnr;
3047
3048 if (!found) {
3049 dev_info(&b->dev,
3050 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3051 bus);
3052 pci_bus_insert_busn_res(b, bus, 255);
3053 }
3054
3055 max = pci_scan_child_bus(b);
3056
3057 if (!found)
3058 pci_bus_update_busn_res_end(b, max);
3059
3060 return 0;
3061 }
3062 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3063
3064 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3065 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3066 {
3067 struct resource_entry *window;
3068 bool found = false;
3069 struct pci_bus *b;
3070 int max;
3071
3072 resource_list_for_each_entry(window, resources)
3073 if (window->res->flags & IORESOURCE_BUS) {
3074 found = true;
3075 break;
3076 }
3077
3078 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3079 if (!b)
3080 return NULL;
3081
3082 if (!found) {
3083 dev_info(&b->dev,
3084 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3085 bus);
3086 pci_bus_insert_busn_res(b, bus, 255);
3087 }
3088
3089 max = pci_scan_child_bus(b);
3090
3091 if (!found)
3092 pci_bus_update_busn_res_end(b, max);
3093
3094 return b;
3095 }
3096 EXPORT_SYMBOL(pci_scan_root_bus);
3097
3098 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3099 void *sysdata)
3100 {
3101 LIST_HEAD(resources);
3102 struct pci_bus *b;
3103
3104 pci_add_resource(&resources, &ioport_resource);
3105 pci_add_resource(&resources, &iomem_resource);
3106 pci_add_resource(&resources, &busn_resource);
3107 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3108 if (b) {
3109 pci_scan_child_bus(b);
3110 } else {
3111 pci_free_resource_list(&resources);
3112 }
3113 return b;
3114 }
3115 EXPORT_SYMBOL(pci_scan_bus);
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3129 {
3130 unsigned int max;
3131 struct pci_bus *bus = bridge->subordinate;
3132
3133 max = pci_scan_child_bus(bus);
3134
3135 pci_assign_unassigned_bridge_resources(bridge);
3136
3137 pci_bus_add_devices(bus);
3138
3139 return max;
3140 }
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151 unsigned int pci_rescan_bus(struct pci_bus *bus)
3152 {
3153 unsigned int max;
3154
3155 max = pci_scan_child_bus(bus);
3156 pci_assign_unassigned_bus_resources(bus);
3157 pci_bus_add_devices(bus);
3158
3159 return max;
3160 }
3161 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3162
3163
3164
3165
3166
3167 static DEFINE_MUTEX(pci_rescan_remove_lock);
3168
3169 void pci_lock_rescan_remove(void)
3170 {
3171 mutex_lock(&pci_rescan_remove_lock);
3172 }
3173 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3174
3175 void pci_unlock_rescan_remove(void)
3176 {
3177 mutex_unlock(&pci_rescan_remove_lock);
3178 }
3179 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3180
3181 static int __init pci_sort_bf_cmp(const struct device *d_a,
3182 const struct device *d_b)
3183 {
3184 const struct pci_dev *a = to_pci_dev(d_a);
3185 const struct pci_dev *b = to_pci_dev(d_b);
3186
3187 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3188 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3189
3190 if (a->bus->number < b->bus->number) return -1;
3191 else if (a->bus->number > b->bus->number) return 1;
3192
3193 if (a->devfn < b->devfn) return -1;
3194 else if (a->devfn > b->devfn) return 1;
3195
3196 return 0;
3197 }
3198
3199 void __init pci_sort_breadthfirst(void)
3200 {
3201 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3202 }
3203
3204 int pci_hp_add_bridge(struct pci_dev *dev)
3205 {
3206 struct pci_bus *parent = dev->bus;
3207 int busnr, start = parent->busn_res.start;
3208 unsigned int available_buses = 0;
3209 int end = parent->busn_res.end;
3210
3211 for (busnr = start; busnr <= end; busnr++) {
3212 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3213 break;
3214 }
3215 if (busnr-- > end) {
3216 pci_err(dev, "No bus number available for hot-added bridge\n");
3217 return -1;
3218 }
3219
3220
3221 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3222
3223
3224
3225
3226
3227 available_buses = end - busnr;
3228
3229
3230 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3231
3232 if (!dev->subordinate)
3233 return -1;
3234
3235 return 0;
3236 }
3237 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);