1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * ecc.h: Definitions and defines for the external cache/memory 4 * controller on the sun4m. 5 * 6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 7 */ 8 9 #ifndef _SPARC_ECC_H 10 #define _SPARC_ECC_H 11 12 /* These registers are accessed through the SRMMU passthrough ASI 0x20 */ 13 #define ECC_ENABLE 0x00000000 /* ECC enable register */ 14 #define ECC_FSTATUS 0x00000008 /* ECC fault status register */ 15 #define ECC_FADDR 0x00000010 /* ECC fault address register */ 16 #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */ 17 #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */ 18 #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */ 19 20 /* ECC MBus Arbiter Enable register: 21 * 22 * ---------------------------------------- 23 * | |SBUS|MOD3|MOD2|MOD1|RSV| 24 * ---------------------------------------- 25 * 31 5 4 3 2 1 0 26 * 27 * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on 28 * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on 29 * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on 30 * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on 31 */ 32 33 #define ECC_MBAE_SBUS 0x00000010 34 #define ECC_MBAE_MOD3 0x00000008 35 #define ECC_MBAE_MOD2 0x00000004 36 #define ECC_MBAE_MOD1 0x00000002 37 38 /* ECC Fault Control Register layout: 39 * 40 * ----------------------------- 41 * | RESV | ECHECK | EINT | 42 * ----------------------------- 43 * 31 2 1 0 44 * 45 * ECHECK: Enable ECC checking. 0=off 1=on 46 * EINT: Enable Interrupts for correctable errors. 0=off 1=on 47 */ 48 #define ECC_FCR_CHECK 0x00000002 49 #define ECC_FCR_INTENAB 0x00000001 50 51 /* ECC Fault Address Register Zero layout: 52 * 53 * ----------------------------------------------------- 54 * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR | 55 * ----------------------------------------------------- 56 * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0 57 * 58 * MID: ModuleID of the faulting processor. ie. who did it? 59 * S: Supervisor/Privileged access? 0=no 1=yes 60 * VA: Bits 19-12 of the virtual faulting address, these are the 61 * superset bits in the virtual cache and can be used for 62 * a flush operation if necessary. 63 * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot 64 * mode bit. 65 * AT: Did this fault happen during an atomic instruction? 0=no 66 * 1=yes. This means either an 'ldstub' or 'swap' instruction 67 * was in progress (but not finished) when this fault happened. 68 * This indicated whether the bus was locked when the fault 69 * occurred. 70 * C: Did the pte for this access indicate that it was cacheable? 71 * 0=no 1=yes 72 * SZ: The size of the transaction. 73 * TYP: The transaction type. 74 * PADDR: Bits 35-32 of the physical address for the fault. 75 */ 76 #define ECC_FADDR0_MIDMASK 0xf0000000 77 #define ECC_FADDR0_S 0x08000000 78 #define ECC_FADDR0_VADDR 0x003fc000 79 #define ECC_FADDR0_BMODE 0x00002000 80 #define ECC_FADDR0_ATOMIC 0x00001000 81 #define ECC_FADDR0_CACHE 0x00000800 82 #define ECC_FADDR0_SIZE 0x00000700 83 #define ECC_FADDR0_TYPE 0x000000f0 84 #define ECC_FADDR0_PADDR 0x0000000f 85 86 /* ECC Fault Address Register One layout: 87 * 88 * ------------------------------------- 89 * | Physical Address 31-0 | 90 * ------------------------------------- 91 * 31 0 92 * 93 * You get the upper 4 bits of the physical address from the 94 * PADDR field in ECC Fault Address Zero register. 95 */ 96 97 /* ECC Fault Status Register layout: 98 * 99 * ---------------------------------------------- 100 * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C| 101 * ---------------------------------------------- 102 * 31-18 17 16 15-8 7-4 3 2 1 0 103 * 104 * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only) 105 * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes) 106 * SYNDROME: Controller is mentally unstable. 107 * DWORD: 108 * UNC: Uncorrectable error. 0=no 1=yes 109 * TIMEO: Timeout occurred. 0=no 1=yes 110 * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only) 111 * C: Correctable error? 0=no 1=yes 112 */ 113 114 #define ECC_FSR_C2ERR 0x00020000 115 #define ECC_FSR_MULT 0x00010000 116 #define ECC_FSR_SYND 0x0000ff00 117 #define ECC_FSR_DWORD 0x000000f0 118 #define ECC_FSR_UNC 0x00000008 119 #define ECC_FSR_TIMEO 0x00000004 120 #define ECC_FSR_BADSLOT 0x00000002 121 #define ECC_FSR_C 0x00000001 122 123 #endif /* !(_SPARC_ECC_H) */