drivers/rapidio/devices/tsi721.c

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This source file includes following definitions.
tsi721_lcread
tsi721_lcwrite
tsi721_maint_dma
tsi721_cread_dma
tsi721_cwrite_dma
tsi721_pw_handler
tsi721_pw_dpc
tsi721_pw_enable
tsi721_dsend
tsi721_dbell_handler
tsi721_db_dpc
tsi721_irqhandler
tsi721_interrupts_init
tsi721_omsg_msix
tsi721_imsg_msix
tsi721_srio_msix
tsi721_sr2pc_ch_msix
tsi721_request_msix
tsi721_enable_msix
tsi721_request_irq
tsi721_free_irq
tsi721_obw_alloc
tsi721_map_outb_win
tsi721_unmap_outb_win
tsi721_init_pc2sr_mapping
tsi721_rio_map_inb_mem
tsi721_rio_unmap_inb_mem
tsi721_init_sr2pc_mapping
tsi721_close_sr2pc_mapping
tsi721_port_write_init
tsi721_port_write_free
tsi721_doorbell_init
tsi721_doorbell_free
tsi721_bdma_maint_init
tsi721_bdma_maint_free
tsi721_imsg_interrupt_enable
tsi721_imsg_interrupt_disable
tsi721_omsg_interrupt_enable
tsi721_omsg_interrupt_disable
tsi721_add_outb_message
tsi721_omsg_handler
tsi721_open_outb_mbox
tsi721_close_outb_mbox
tsi721_imsg_handler
tsi721_open_inb_mbox
tsi721_close_inb_mbox
tsi721_add_inb_buffer
tsi721_get_inb_message
tsi721_messages_init
tsi721_query_mport
tsi721_disable_ints
tsi721_mport_release
tsi721_setup_mport
tsi721_probe
tsi721_remove
tsi721_shutdown
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
   4  *
   5  * Copyright 2011 Integrated Device Technology, Inc.
   6  * Alexandre Bounine <alexandre.bounine@idt.com>
   7  * Chul Kim <chul.kim@idt.com>
   8  */
   9 
  10 #include <linux/io.h>
  11 #include <linux/errno.h>
  12 #include <linux/init.h>
  13 #include <linux/ioport.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/pci.h>
  17 #include <linux/rio.h>
  18 #include <linux/rio_drv.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kfifo.h>
  22 #include <linux/delay.h>
  23 
  24 #include "tsi721.h"
  25 
  26 #ifdef DEBUG
  27 u32 tsi_dbg_level;
  28 module_param_named(dbg_level, tsi_dbg_level, uint, S_IWUSR | S_IRUGO);
  29 MODULE_PARM_DESC(dbg_level, "Debugging output level (default 0 = none)");
  30 #endif
  31 
  32 static int pcie_mrrs = -1;
  33 module_param(pcie_mrrs, int, S_IRUGO);
  34 MODULE_PARM_DESC(pcie_mrrs, "PCIe MRRS override value (0...5)");
  35 
  36 static u8 mbox_sel = 0x0f;
  37 module_param(mbox_sel, byte, S_IRUGO);
  38 MODULE_PARM_DESC(mbox_sel,
  39                  "RIO Messaging MBOX Selection Mask (default: 0x0f = all)");
  40 
  41 static DEFINE_SPINLOCK(tsi721_maint_lock);
  42 
  43 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch);
  44 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch);
  45 
  46 /**
  47  * tsi721_lcread - read from local SREP config space
  48  * @mport: RapidIO master port info
  49  * @index: ID of RapdiIO interface
  50  * @offset: Offset into configuration space
  51  * @len: Length (in bytes) of the maintenance transaction
  52  * @data: Value to be read into
  53  *
  54  * Generates a local SREP space read. Returns %0 on
  55  * success or %-EINVAL on failure.
  56  */
  57 static int tsi721_lcread(struct rio_mport *mport, int index, u32 offset,
  58                          int len, u32 *data)
  59 {
  60         struct tsi721_device *priv = mport->priv;
  61 
  62         if (len != sizeof(u32))
  63                 return -EINVAL; /* only 32-bit access is supported */
  64 
  65         *data = ioread32(priv->regs + offset);
  66 
  67         return 0;
  68 }
  69 
  70 /**
  71  * tsi721_lcwrite - write into local SREP config space
  72  * @mport: RapidIO master port info
  73  * @index: ID of RapdiIO interface
  74  * @offset: Offset into configuration space
  75  * @len: Length (in bytes) of the maintenance transaction
  76  * @data: Value to be written
  77  *
  78  * Generates a local write into SREP configuration space. Returns %0 on
  79  * success or %-EINVAL on failure.
  80  */
  81 static int tsi721_lcwrite(struct rio_mport *mport, int index, u32 offset,
  82                           int len, u32 data)
  83 {
  84         struct tsi721_device *priv = mport->priv;
  85 
  86         if (len != sizeof(u32))
  87                 return -EINVAL; /* only 32-bit access is supported */
  88 
  89         iowrite32(data, priv->regs + offset);
  90 
  91         return 0;
  92 }
  93 
  94 /**
  95  * tsi721_maint_dma - Helper function to generate RapidIO maintenance
  96  *                    transactions using designated Tsi721 DMA channel.
  97  * @priv: pointer to tsi721 private data
  98  * @sys_size: RapdiIO transport system size
  99  * @destid: Destination ID of transaction
 100  * @hopcount: Number of hops to target device
 101  * @offset: Offset into configuration space
 102  * @len: Length (in bytes) of the maintenance transaction
 103  * @data: Location to be read from or write into
 104  * @do_wr: Operation flag (1 == MAINT_WR)
 105  *
 106  * Generates a RapidIO maintenance transaction (Read or Write).
 107  * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
 108  */
 109 static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
 110                         u16 destid, u8 hopcount, u32 offset, int len,
 111                         u32 *data, int do_wr)
 112 {
 113         void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id);
 114         struct tsi721_dma_desc *bd_ptr;
 115         u32 rd_count, swr_ptr, ch_stat;
 116         unsigned long flags;
 117         int i, err = 0;
 118         u32 op = do_wr ? MAINT_WR : MAINT_RD;
 119 
 120         if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
 121                 return -EINVAL;
 122 
 123         spin_lock_irqsave(&tsi721_maint_lock, flags);
 124 
 125         bd_ptr = priv->mdma.bd_base;
 126 
 127         rd_count = ioread32(regs + TSI721_DMAC_DRDCNT);
 128 
 129         /* Initialize DMA descriptor */
 130         bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
 131         bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04);
 132         bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset);
 133         bd_ptr[0].raddr_hi = 0;
 134         if (do_wr)
 135                 bd_ptr[0].data[0] = cpu_to_be32p(data);
 136         else
 137                 bd_ptr[0].data[0] = 0xffffffff;
 138 
 139         mb();
 140 
 141         /* Start DMA operation */
 142         iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT);
 143         ioread32(regs + TSI721_DMAC_DWRCNT);
 144         i = 0;
 145 
 146         /* Wait until DMA transfer is finished */
 147         while ((ch_stat = ioread32(regs + TSI721_DMAC_STS))
 148                                                         & TSI721_DMAC_STS_RUN) {
 149                 udelay(1);
 150                 if (++i >= 5000000) {
 151                         tsi_debug(MAINT, &priv->pdev->dev,
 152                                 "DMA[%d] read timeout ch_status=%x",
 153                                 priv->mdma.ch_id, ch_stat);
 154                         if (!do_wr)
 155                                 *data = 0xffffffff;
 156                         err = -EIO;
 157                         goto err_out;
 158                 }
 159         }
 160 
 161         if (ch_stat & TSI721_DMAC_STS_ABORT) {
 162                 /* If DMA operation aborted due to error,
 163                  * reinitialize DMA channel
 164                  */
 165                 tsi_debug(MAINT, &priv->pdev->dev, "DMA ABORT ch_stat=%x",
 166                           ch_stat);
 167                 tsi_debug(MAINT, &priv->pdev->dev,
 168                           "OP=%d : destid=%x hc=%x off=%x",
 169                           do_wr ? MAINT_WR : MAINT_RD,
 170                           destid, hopcount, offset);
 171                 iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
 172                 iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
 173                 udelay(10);
 174                 iowrite32(0, regs + TSI721_DMAC_DWRCNT);
 175                 udelay(1);
 176                 if (!do_wr)
 177                         *data = 0xffffffff;
 178                 err = -EIO;
 179                 goto err_out;
 180         }
 181 
 182         if (!do_wr)
 183                 *data = be32_to_cpu(bd_ptr[0].data[0]);
 184 
 185         /*
 186          * Update descriptor status FIFO RD pointer.
 187          * NOTE: Skipping check and clear FIFO entries because we are waiting
 188          * for transfer to be completed.
 189          */
 190         swr_ptr = ioread32(regs + TSI721_DMAC_DSWP);
 191         iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP);
 192 
 193 err_out:
 194         spin_unlock_irqrestore(&tsi721_maint_lock, flags);
 195 
 196         return err;
 197 }
 198 
 199 /**
 200  * tsi721_cread_dma - Generate a RapidIO maintenance read transaction
 201  *                    using Tsi721 BDMA engine.
 202  * @mport: RapidIO master port control structure
 203  * @index: ID of RapdiIO interface
 204  * @destid: Destination ID of transaction
 205  * @hopcount: Number of hops to target device
 206  * @offset: Offset into configuration space
 207  * @len: Length (in bytes) of the maintenance transaction
 208  * @val: Location to be read into
 209  *
 210  * Generates a RapidIO maintenance read transaction.
 211  * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
 212  */
 213 static int tsi721_cread_dma(struct rio_mport *mport, int index, u16 destid,
 214                         u8 hopcount, u32 offset, int len, u32 *data)
 215 {
 216         struct tsi721_device *priv = mport->priv;
 217 
 218         return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
 219                                 offset, len, data, 0);
 220 }
 221 
 222 /**
 223  * tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction
 224  *                     using Tsi721 BDMA engine
 225  * @mport: RapidIO master port control structure
 226  * @index: ID of RapdiIO interface
 227  * @destid: Destination ID of transaction
 228  * @hopcount: Number of hops to target device
 229  * @offset: Offset into configuration space
 230  * @len: Length (in bytes) of the maintenance transaction
 231  * @val: Value to be written
 232  *
 233  * Generates a RapidIO maintenance write transaction.
 234  * Returns %0 on success and %-EINVAL or %-EFAULT on failure.
 235  */
 236 static int tsi721_cwrite_dma(struct rio_mport *mport, int index, u16 destid,
 237                          u8 hopcount, u32 offset, int len, u32 data)
 238 {
 239         struct tsi721_device *priv = mport->priv;
 240         u32 temp = data;
 241 
 242         return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
 243                                 offset, len, &temp, 1);
 244 }
 245 
 246 /**
 247  * tsi721_pw_handler - Tsi721 inbound port-write interrupt handler
 248  * @priv:  tsi721 device private structure
 249  *
 250  * Handles inbound port-write interrupts. Copies PW message from an internal
 251  * buffer into PW message FIFO and schedules deferred routine to process
 252  * queued messages.
 253  */
 254 static int
 255 tsi721_pw_handler(struct tsi721_device *priv)
 256 {
 257         u32 pw_stat;
 258         u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)];
 259 
 260 
 261         pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT);
 262 
 263         if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) {
 264                 pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0));
 265                 pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1));
 266                 pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2));
 267                 pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3));
 268 
 269                 /* Queue PW message (if there is room in FIFO),
 270                  * otherwise discard it.
 271                  */
 272                 spin_lock(&priv->pw_fifo_lock);
 273                 if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE)
 274                         kfifo_in(&priv->pw_fifo, pw_buf,
 275                                                 TSI721_RIO_PW_MSG_SIZE);
 276                 else
 277                         priv->pw_discard_count++;
 278                 spin_unlock(&priv->pw_fifo_lock);
 279         }
 280 
 281         /* Clear pending PW interrupts */
 282         iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
 283                   priv->regs + TSI721_RIO_PW_RX_STAT);
 284 
 285         schedule_work(&priv->pw_work);
 286 
 287         return 0;
 288 }
 289 
 290 static void tsi721_pw_dpc(struct work_struct *work)
 291 {
 292         struct tsi721_device *priv = container_of(work, struct tsi721_device,
 293                                                     pw_work);
 294         union rio_pw_msg pwmsg;
 295 
 296         /*
 297          * Process port-write messages
 298          */
 299         while (kfifo_out_spinlocked(&priv->pw_fifo, (unsigned char *)&pwmsg,
 300                          TSI721_RIO_PW_MSG_SIZE, &priv->pw_fifo_lock)) {
 301                 /* Pass the port-write message to RIO core for processing */
 302                 rio_inb_pwrite_handler(&priv->mport, &pwmsg);
 303         }
 304 }
 305 
 306 /**
 307  * tsi721_pw_enable - enable/disable port-write interface init
 308  * @mport: Master port implementing the port write unit
 309  * @enable:    1=enable; 0=disable port-write message handling
 310  */
 311 static int tsi721_pw_enable(struct rio_mport *mport, int enable)
 312 {
 313         struct tsi721_device *priv = mport->priv;
 314         u32 rval;
 315 
 316         rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE);
 317 
 318         if (enable)
 319                 rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX;
 320         else
 321                 rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX;
 322 
 323         /* Clear pending PW interrupts */
 324         iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
 325                   priv->regs + TSI721_RIO_PW_RX_STAT);
 326         /* Update enable bits */
 327         iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);
 328 
 329         return 0;
 330 }
 331 
 332 /**
 333  * tsi721_dsend - Send a RapidIO doorbell
 334  * @mport: RapidIO master port info
 335  * @index: ID of RapidIO interface
 336  * @destid: Destination ID of target device
 337  * @data: 16-bit info field of RapidIO doorbell
 338  *
 339  * Sends a RapidIO doorbell message. Always returns %0.
 340  */
 341 static int tsi721_dsend(struct rio_mport *mport, int index,
 342                         u16 destid, u16 data)
 343 {
 344         struct tsi721_device *priv = mport->priv;
 345         u32 offset;
 346 
 347         offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) |
 348                  (destid << 2);
 349 
 350         tsi_debug(DBELL, &priv->pdev->dev,
 351                   "Send Doorbell 0x%04x to destID 0x%x", data, destid);
 352         iowrite16be(data, priv->odb_base + offset);
 353 
 354         return 0;
 355 }
 356 
 357 /**
 358  * tsi721_dbell_handler - Tsi721 doorbell interrupt handler
 359  * @priv: tsi721 device-specific data structure
 360  *
 361  * Handles inbound doorbell interrupts. Copies doorbell entry from an internal
 362  * buffer into DB message FIFO and schedules deferred  routine to process
 363  * queued DBs.
 364  */
 365 static int
 366 tsi721_dbell_handler(struct tsi721_device *priv)
 367 {
 368         u32 regval;
 369 
 370         /* Disable IDB interrupts */
 371         regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 372         regval &= ~TSI721_SR_CHINT_IDBQRCV;
 373         iowrite32(regval,
 374                 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 375 
 376         schedule_work(&priv->idb_work);
 377 
 378         return 0;
 379 }
 380 
 381 static void tsi721_db_dpc(struct work_struct *work)
 382 {
 383         struct tsi721_device *priv = container_of(work, struct tsi721_device,
 384                                                     idb_work);
 385         struct rio_mport *mport;
 386         struct rio_dbell *dbell;
 387         int found = 0;
 388         u32 wr_ptr, rd_ptr;
 389         u64 *idb_entry;
 390         u32 regval;
 391         union {
 392                 u64 msg;
 393                 u8  bytes[8];
 394         } idb;
 395 
 396         /*
 397          * Process queued inbound doorbells
 398          */
 399         mport = &priv->mport;
 400 
 401         wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
 402         rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE;
 403 
 404         while (wr_ptr != rd_ptr) {
 405                 idb_entry = (u64 *)(priv->idb_base +
 406                                         (TSI721_IDB_ENTRY_SIZE * rd_ptr));
 407                 rd_ptr++;
 408                 rd_ptr %= IDB_QSIZE;
 409                 idb.msg = *idb_entry;
 410                 *idb_entry = 0;
 411 
 412                 /* Process one doorbell */
 413                 list_for_each_entry(dbell, &mport->dbells, node) {
 414                         if ((dbell->res->start <= DBELL_INF(idb.bytes)) &&
 415                             (dbell->res->end >= DBELL_INF(idb.bytes))) {
 416                                 found = 1;
 417                                 break;
 418                         }
 419                 }
 420 
 421                 if (found) {
 422                         dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes),
 423                                     DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
 424                 } else {
 425                         tsi_debug(DBELL, &priv->pdev->dev,
 426                                   "spurious IDB sid %2.2x tid %2.2x info %4.4x",
 427                                   DBELL_SID(idb.bytes), DBELL_TID(idb.bytes),
 428                                   DBELL_INF(idb.bytes));
 429                 }
 430 
 431                 wr_ptr = ioread32(priv->regs +
 432                                   TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
 433         }
 434 
 435         iowrite32(rd_ptr & (IDB_QSIZE - 1),
 436                 priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
 437 
 438         /* Re-enable IDB interrupts */
 439         regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 440         regval |= TSI721_SR_CHINT_IDBQRCV;
 441         iowrite32(regval,
 442                 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 443 
 444         wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
 445         if (wr_ptr != rd_ptr)
 446                 schedule_work(&priv->idb_work);
 447 }
 448 
 449 /**
 450  * tsi721_irqhandler - Tsi721 interrupt handler
 451  * @irq: Linux interrupt number
 452  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 453  *
 454  * Handles Tsi721 interrupts signaled using MSI and INTA. Checks reported
 455  * interrupt events and calls an event-specific handler(s).
 456  */
 457 static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
 458 {
 459         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 460         u32 dev_int;
 461         u32 dev_ch_int;
 462         u32 intval;
 463         u32 ch_inte;
 464 
 465         /* For MSI mode disable all device-level interrupts */
 466         if (priv->flags & TSI721_USING_MSI)
 467                 iowrite32(0, priv->regs + TSI721_DEV_INTE);
 468 
 469         dev_int = ioread32(priv->regs + TSI721_DEV_INT);
 470         if (!dev_int)
 471                 return IRQ_NONE;
 472 
 473         dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT);
 474 
 475         if (dev_int & TSI721_DEV_INT_SR2PC_CH) {
 476                 /* Service SR2PC Channel interrupts */
 477                 if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) {
 478                         /* Service Inbound Doorbell interrupt */
 479                         intval = ioread32(priv->regs +
 480                                                 TSI721_SR_CHINT(IDB_QUEUE));
 481                         if (intval & TSI721_SR_CHINT_IDBQRCV)
 482                                 tsi721_dbell_handler(priv);
 483                         else
 484                                 tsi_info(&priv->pdev->dev,
 485                                         "Unsupported SR_CH_INT %x", intval);
 486 
 487                         /* Clear interrupts */
 488                         iowrite32(intval,
 489                                 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 490                         ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 491                 }
 492         }
 493 
 494         if (dev_int & TSI721_DEV_INT_SMSG_CH) {
 495                 int ch;
 496 
 497                 /*
 498                  * Service channel interrupts from Messaging Engine
 499                  */
 500 
 501                 if (dev_ch_int & TSI721_INT_IMSG_CHAN_M) { /* Inbound Msg */
 502                         /* Disable signaled OB MSG Channel interrupts */
 503                         ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
 504                         ch_inte &= ~(dev_ch_int & TSI721_INT_IMSG_CHAN_M);
 505                         iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
 506 
 507                         /*
 508                          * Process Inbound Message interrupt for each MBOX
 509                          */
 510                         for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) {
 511                                 if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch)))
 512                                         continue;
 513                                 tsi721_imsg_handler(priv, ch);
 514                         }
 515                 }
 516 
 517                 if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */
 518                         /* Disable signaled OB MSG Channel interrupts */
 519                         ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
 520                         ch_inte &= ~(dev_ch_int & TSI721_INT_OMSG_CHAN_M);
 521                         iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
 522 
 523                         /*
 524                          * Process Outbound Message interrupts for each MBOX
 525                          */
 526 
 527                         for (ch = 0; ch < RIO_MAX_MBOX; ch++) {
 528                                 if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch)))
 529                                         continue;
 530                                 tsi721_omsg_handler(priv, ch);
 531                         }
 532                 }
 533         }
 534 
 535         if (dev_int & TSI721_DEV_INT_SRIO) {
 536                 /* Service SRIO MAC interrupts */
 537                 intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
 538                 if (intval & TSI721_RIO_EM_INT_STAT_PW_RX)
 539                         tsi721_pw_handler(priv);
 540         }
 541 
 542 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 543         if (dev_int & TSI721_DEV_INT_BDMA_CH) {
 544                 int ch;
 545 
 546                 if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) {
 547                         tsi_debug(DMA, &priv->pdev->dev,
 548                                   "IRQ from DMA channel 0x%08x", dev_ch_int);
 549 
 550                         for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) {
 551                                 if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch)))
 552                                         continue;
 553                                 tsi721_bdma_handler(&priv->bdma[ch]);
 554                         }
 555                 }
 556         }
 557 #endif
 558 
 559         /* For MSI mode re-enable device-level interrupts */
 560         if (priv->flags & TSI721_USING_MSI) {
 561                 dev_int = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
 562                         TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
 563                 iowrite32(dev_int, priv->regs + TSI721_DEV_INTE);
 564         }
 565 
 566         return IRQ_HANDLED;
 567 }
 568 
 569 static void tsi721_interrupts_init(struct tsi721_device *priv)
 570 {
 571         u32 intr;
 572 
 573         /* Enable IDB interrupts */
 574         iowrite32(TSI721_SR_CHINT_ALL,
 575                 priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 576         iowrite32(TSI721_SR_CHINT_IDBQRCV,
 577                 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
 578 
 579         /* Enable SRIO MAC interrupts */
 580         iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
 581                 priv->regs + TSI721_RIO_EM_DEV_INT_EN);
 582 
 583         /* Enable interrupts from channels in use */
 584 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 585         intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) |
 586                 (TSI721_INT_BDMA_CHAN_M &
 587                  ~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT));
 588 #else
 589         intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE);
 590 #endif
 591         iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE);
 592 
 593         if (priv->flags & TSI721_USING_MSIX)
 594                 intr = TSI721_DEV_INT_SRIO;
 595         else
 596                 intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
 597                         TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
 598 
 599         iowrite32(intr, priv->regs + TSI721_DEV_INTE);
 600         ioread32(priv->regs + TSI721_DEV_INTE);
 601 }
 602 
 603 #ifdef CONFIG_PCI_MSI
 604 /**
 605  * tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging
 606  * @irq: Linux interrupt number
 607  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 608  *
 609  * Handles outbound messaging interrupts signaled using MSI-X.
 610  */
 611 static irqreturn_t tsi721_omsg_msix(int irq, void *ptr)
 612 {
 613         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 614         int mbox;
 615 
 616         mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX;
 617         tsi721_omsg_handler(priv, mbox);
 618         return IRQ_HANDLED;
 619 }
 620 
 621 /**
 622  * tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging
 623  * @irq: Linux interrupt number
 624  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 625  *
 626  * Handles inbound messaging interrupts signaled using MSI-X.
 627  */
 628 static irqreturn_t tsi721_imsg_msix(int irq, void *ptr)
 629 {
 630         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 631         int mbox;
 632 
 633         mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX;
 634         tsi721_imsg_handler(priv, mbox + 4);
 635         return IRQ_HANDLED;
 636 }
 637 
 638 /**
 639  * tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler
 640  * @irq: Linux interrupt number
 641  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 642  *
 643  * Handles Tsi721 interrupts from SRIO MAC.
 644  */
 645 static irqreturn_t tsi721_srio_msix(int irq, void *ptr)
 646 {
 647         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 648         u32 srio_int;
 649 
 650         /* Service SRIO MAC interrupts */
 651         srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
 652         if (srio_int & TSI721_RIO_EM_INT_STAT_PW_RX)
 653                 tsi721_pw_handler(priv);
 654 
 655         return IRQ_HANDLED;
 656 }
 657 
 658 /**
 659  * tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler
 660  * @irq: Linux interrupt number
 661  * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
 662  *
 663  * Handles Tsi721 interrupts from SR2PC Channel.
 664  * NOTE: At this moment services only one SR2PC channel associated with inbound
 665  * doorbells.
 666  */
 667 static irqreturn_t tsi721_sr2pc_ch_msix(int irq, void *ptr)
 668 {
 669         struct tsi721_device *priv = (struct tsi721_device *)ptr;
 670         u32 sr_ch_int;
 671 
 672         /* Service Inbound DB interrupt from SR2PC channel */
 673         sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 674         if (sr_ch_int & TSI721_SR_CHINT_IDBQRCV)
 675                 tsi721_dbell_handler(priv);
 676 
 677         /* Clear interrupts */
 678         iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 679         /* Read back to ensure that interrupt was cleared */
 680         sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
 681 
 682         return IRQ_HANDLED;
 683 }
 684 
 685 /**
 686  * tsi721_request_msix - register interrupt service for MSI-X mode.
 687  * @priv: tsi721 device-specific data structure
 688  *
 689  * Registers MSI-X interrupt service routines for interrupts that are active
 690  * immediately after mport initialization. Messaging interrupt service routines
 691  * should be registered during corresponding open requests.
 692  */
 693 static int tsi721_request_msix(struct tsi721_device *priv)
 694 {
 695         int err = 0;
 696 
 697         err = request_irq(priv->msix[TSI721_VECT_IDB].vector,
 698                         tsi721_sr2pc_ch_msix, 0,
 699                         priv->msix[TSI721_VECT_IDB].irq_name, (void *)priv);
 700         if (err)
 701                 return err;
 702 
 703         err = request_irq(priv->msix[TSI721_VECT_PWRX].vector,
 704                         tsi721_srio_msix, 0,
 705                         priv->msix[TSI721_VECT_PWRX].irq_name, (void *)priv);
 706         if (err) {
 707                 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv);
 708                 return err;
 709         }
 710 
 711         return 0;
 712 }
 713 
 714 /**
 715  * tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721.
 716  * @priv: pointer to tsi721 private data
 717  *
 718  * Configures MSI-X support for Tsi721. Supports only an exact number
 719  * of requested vectors.
 720  */
 721 static int tsi721_enable_msix(struct tsi721_device *priv)
 722 {
 723         struct msix_entry entries[TSI721_VECT_MAX];
 724         int err;
 725         int i;
 726 
 727         entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);
 728         entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT;
 729 
 730         /*
 731          * Initialize MSI-X entries for Messaging Engine:
 732          * this driver supports four RIO mailboxes (inbound and outbound)
 733          * NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore
 734          * offset +4 is added to IB MBOX number.
 735          */
 736         for (i = 0; i < RIO_MAX_MBOX; i++) {
 737                 entries[TSI721_VECT_IMB0_RCV + i].entry =
 738                                         TSI721_MSIX_IMSG_DQ_RCV(i + 4);
 739                 entries[TSI721_VECT_IMB0_INT + i].entry =
 740                                         TSI721_MSIX_IMSG_INT(i + 4);
 741                 entries[TSI721_VECT_OMB0_DONE + i].entry =
 742                                         TSI721_MSIX_OMSG_DONE(i);
 743                 entries[TSI721_VECT_OMB0_INT + i].entry =
 744                                         TSI721_MSIX_OMSG_INT(i);
 745         }
 746 
 747 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 748         /*
 749          * Initialize MSI-X entries for Block DMA Engine:
 750          * this driver supports XXX DMA channels
 751          * (one is reserved for SRIO maintenance transactions)
 752          */
 753         for (i = 0; i < TSI721_DMA_CHNUM; i++) {
 754                 entries[TSI721_VECT_DMA0_DONE + i].entry =
 755                                         TSI721_MSIX_DMACH_DONE(i);
 756                 entries[TSI721_VECT_DMA0_INT + i].entry =
 757                                         TSI721_MSIX_DMACH_INT(i);
 758         }
 759 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
 760 
 761         err = pci_enable_msix_exact(priv->pdev, entries, ARRAY_SIZE(entries));
 762         if (err) {
 763                 tsi_err(&priv->pdev->dev,
 764                         "Failed to enable MSI-X (err=%d)", err);
 765                 return err;
 766         }
 767 
 768         /*
 769          * Copy MSI-X vector information into tsi721 private structure
 770          */
 771         priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector;
 772         snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX,
 773                  DRV_NAME "-idb@pci:%s", pci_name(priv->pdev));
 774         priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector;
 775         snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX,
 776                  DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev));
 777 
 778         for (i = 0; i < RIO_MAX_MBOX; i++) {
 779                 priv->msix[TSI721_VECT_IMB0_RCV + i].vector =
 780                                 entries[TSI721_VECT_IMB0_RCV + i].vector;
 781                 snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name,
 782                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s",
 783                          i, pci_name(priv->pdev));
 784 
 785                 priv->msix[TSI721_VECT_IMB0_INT + i].vector =
 786                                 entries[TSI721_VECT_IMB0_INT + i].vector;
 787                 snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name,
 788                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s",
 789                          i, pci_name(priv->pdev));
 790 
 791                 priv->msix[TSI721_VECT_OMB0_DONE + i].vector =
 792                                 entries[TSI721_VECT_OMB0_DONE + i].vector;
 793                 snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name,
 794                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s",
 795                          i, pci_name(priv->pdev));
 796 
 797                 priv->msix[TSI721_VECT_OMB0_INT + i].vector =
 798                                 entries[TSI721_VECT_OMB0_INT + i].vector;
 799                 snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name,
 800                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s",
 801                          i, pci_name(priv->pdev));
 802         }
 803 
 804 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
 805         for (i = 0; i < TSI721_DMA_CHNUM; i++) {
 806                 priv->msix[TSI721_VECT_DMA0_DONE + i].vector =
 807                                 entries[TSI721_VECT_DMA0_DONE + i].vector;
 808                 snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name,
 809                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s",
 810                          i, pci_name(priv->pdev));
 811 
 812                 priv->msix[TSI721_VECT_DMA0_INT + i].vector =
 813                                 entries[TSI721_VECT_DMA0_INT + i].vector;
 814                 snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name,
 815                          IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s",
 816                          i, pci_name(priv->pdev));
 817         }
 818 #endif /* CONFIG_RAPIDIO_DMA_ENGINE */
 819 
 820         return 0;
 821 }
 822 #endif /* CONFIG_PCI_MSI */
 823 
 824 static int tsi721_request_irq(struct tsi721_device *priv)
 825 {
 826         int err;
 827 
 828 #ifdef CONFIG_PCI_MSI
 829         if (priv->flags & TSI721_USING_MSIX)
 830                 err = tsi721_request_msix(priv);
 831         else
 832 #endif
 833                 err = request_irq(priv->pdev->irq, tsi721_irqhandler,
 834                           (priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED,
 835                           DRV_NAME, (void *)priv);
 836 
 837         if (err)
 838                 tsi_err(&priv->pdev->dev,
 839                         "Unable to allocate interrupt, err=%d", err);
 840 
 841         return err;
 842 }
 843 
 844 static void tsi721_free_irq(struct tsi721_device *priv)
 845 {
 846 #ifdef CONFIG_PCI_MSI
 847         if (priv->flags & TSI721_USING_MSIX) {
 848                 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv);
 849                 free_irq(priv->msix[TSI721_VECT_PWRX].vector, (void *)priv);
 850         } else
 851 #endif
 852         free_irq(priv->pdev->irq, (void *)priv);
 853 }
 854 
 855 static int
 856 tsi721_obw_alloc(struct tsi721_device *priv, struct tsi721_obw_bar *pbar,
 857                  u32 size, int *win_id)
 858 {
 859         u64 win_base;
 860         u64 bar_base;
 861         u64 bar_end;
 862         u32 align;
 863         struct tsi721_ob_win *win;
 864         struct tsi721_ob_win *new_win = NULL;
 865         int new_win_idx = -1;
 866         int i = 0;
 867 
 868         bar_base = pbar->base;
 869         bar_end =  bar_base + pbar->size;
 870         win_base = bar_base;
 871         align = size/TSI721_PC2SR_ZONES;
 872 
 873         while (i < TSI721_IBWIN_NUM) {
 874                 for (i = 0; i < TSI721_IBWIN_NUM; i++) {
 875                         if (!priv->ob_win[i].active) {
 876                                 if (new_win == NULL) {
 877                                         new_win = &priv->ob_win[i];
 878                                         new_win_idx = i;
 879                                 }
 880                                 continue;
 881                         }
 882 
 883                         /*
 884                          * If this window belongs to the current BAR check it
 885                          * for overlap
 886                          */
 887                         win = &priv->ob_win[i];
 888 
 889                         if (win->base >= bar_base && win->base < bar_end) {
 890                                 if (win_base < (win->base + win->size) &&
 891                                                 (win_base + size) > win->base) {
 892                                         /* Overlap detected */
 893                                         win_base = win->base + win->size;
 894                                         win_base = ALIGN(win_base, align);
 895                                         break;
 896                                 }
 897                         }
 898                 }
 899         }
 900 
 901         if (win_base + size > bar_end)
 902                 return -ENOMEM;
 903 
 904         if (!new_win) {
 905                 tsi_err(&priv->pdev->dev, "OBW count tracking failed");
 906                 return -EIO;
 907         }
 908 
 909         new_win->active = true;
 910         new_win->base = win_base;
 911         new_win->size = size;
 912         new_win->pbar = pbar;
 913         priv->obwin_cnt--;
 914         pbar->free -= size;
 915         *win_id = new_win_idx;
 916         return 0;
 917 }
 918 
 919 static int tsi721_map_outb_win(struct rio_mport *mport, u16 destid, u64 rstart,
 920                         u32 size, u32 flags, dma_addr_t *laddr)
 921 {
 922         struct tsi721_device *priv = mport->priv;
 923         int i;
 924         struct tsi721_obw_bar *pbar;
 925         struct tsi721_ob_win *ob_win;
 926         int obw = -1;
 927         u32 rval;
 928         u64 rio_addr;
 929         u32 zsize;
 930         int ret = -ENOMEM;
 931 
 932         tsi_debug(OBW, &priv->pdev->dev,
 933                   "did=%d ra=0x%llx sz=0x%x", destid, rstart, size);
 934 
 935         if (!is_power_of_2(size) || (size < 0x8000) || (rstart & (size - 1)))
 936                 return -EINVAL;
 937 
 938         if (priv->obwin_cnt == 0)
 939                 return -EBUSY;
 940 
 941         for (i = 0; i < 2; i++) {
 942                 if (priv->p2r_bar[i].free >= size) {
 943                         pbar = &priv->p2r_bar[i];
 944                         ret = tsi721_obw_alloc(priv, pbar, size, &obw);
 945                         if (!ret)
 946                                 break;
 947                 }
 948         }
 949 
 950         if (ret)
 951                 return ret;
 952 
 953         WARN_ON(obw == -1);
 954         ob_win = &priv->ob_win[obw];
 955         ob_win->destid = destid;
 956         ob_win->rstart = rstart;
 957         tsi_debug(OBW, &priv->pdev->dev,
 958                   "allocated OBW%d @%llx", obw, ob_win->base);
 959 
 960         /*
 961          * Configure Outbound Window
 962          */
 963 
 964         zsize = size/TSI721_PC2SR_ZONES;
 965         rio_addr = rstart;
 966 
 967         /*
 968          * Program Address Translation Zones:
 969          *  This implementation uses all 8 zones associated wit window.
 970          */
 971         for (i = 0; i < TSI721_PC2SR_ZONES; i++) {
 972 
 973                 while (ioread32(priv->regs + TSI721_ZONE_SEL) &
 974                         TSI721_ZONE_SEL_GO) {
 975                         udelay(1);
 976                 }
 977 
 978                 rval = (u32)(rio_addr & TSI721_LUT_DATA0_ADD) |
 979                         TSI721_LUT_DATA0_NREAD | TSI721_LUT_DATA0_NWR;
 980                 iowrite32(rval, priv->regs + TSI721_LUT_DATA0);
 981                 rval = (u32)(rio_addr >> 32);
 982                 iowrite32(rval, priv->regs + TSI721_LUT_DATA1);
 983                 rval = destid;
 984                 iowrite32(rval, priv->regs + TSI721_LUT_DATA2);
 985 
 986                 rval = TSI721_ZONE_SEL_GO | (obw << 3) | i;
 987                 iowrite32(rval, priv->regs + TSI721_ZONE_SEL);
 988 
 989                 rio_addr += zsize;
 990         }
 991 
 992         iowrite32(TSI721_OBWIN_SIZE(size) << 8,
 993                   priv->regs + TSI721_OBWINSZ(obw));
 994         iowrite32((u32)(ob_win->base >> 32), priv->regs + TSI721_OBWINUB(obw));
 995         iowrite32((u32)(ob_win->base & TSI721_OBWINLB_BA) | TSI721_OBWINLB_WEN,
 996                   priv->regs + TSI721_OBWINLB(obw));
 997 
 998         *laddr = ob_win->base;
 999         return 0;
1000 }
1001 
1002 static void tsi721_unmap_outb_win(struct rio_mport *mport,
1003                                   u16 destid, u64 rstart)
1004 {
1005         struct tsi721_device *priv = mport->priv;
1006         struct tsi721_ob_win *ob_win;
1007         int i;
1008 
1009         tsi_debug(OBW, &priv->pdev->dev, "did=%d ra=0x%llx", destid, rstart);
1010 
1011         for (i = 0; i < TSI721_OBWIN_NUM; i++) {
1012                 ob_win = &priv->ob_win[i];
1013 
1014                 if (ob_win->active &&
1015                     ob_win->destid == destid && ob_win->rstart == rstart) {
1016                         tsi_debug(OBW, &priv->pdev->dev,
1017                                   "free OBW%d @%llx", i, ob_win->base);
1018                         ob_win->active = false;
1019                         iowrite32(0, priv->regs + TSI721_OBWINLB(i));
1020                         ob_win->pbar->free += ob_win->size;
1021                         priv->obwin_cnt++;
1022                         break;
1023                 }
1024         }
1025 }
1026 
1027 /**
1028  * tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO)
1029  * translation regions.
1030  * @priv: pointer to tsi721 private data
1031  *
1032  * Disables SREP translation regions.
1033  */
1034 static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv)
1035 {
1036         int i, z;
1037         u32 rval;
1038 
1039         /* Disable all PC2SR translation windows */
1040         for (i = 0; i < TSI721_OBWIN_NUM; i++)
1041                 iowrite32(0, priv->regs + TSI721_OBWINLB(i));
1042 
1043         /* Initialize zone lookup tables to avoid ECC errors on reads */
1044         iowrite32(0, priv->regs + TSI721_LUT_DATA0);
1045         iowrite32(0, priv->regs + TSI721_LUT_DATA1);
1046         iowrite32(0, priv->regs + TSI721_LUT_DATA2);
1047 
1048         for (i = 0; i < TSI721_OBWIN_NUM; i++) {
1049                 for (z = 0; z < TSI721_PC2SR_ZONES; z++) {
1050                         while (ioread32(priv->regs + TSI721_ZONE_SEL) &
1051                                 TSI721_ZONE_SEL_GO) {
1052                                 udelay(1);
1053                         }
1054                         rval = TSI721_ZONE_SEL_GO | (i << 3) | z;
1055                         iowrite32(rval, priv->regs + TSI721_ZONE_SEL);
1056                 }
1057         }
1058 
1059         if (priv->p2r_bar[0].size == 0 && priv->p2r_bar[1].size == 0) {
1060                 priv->obwin_cnt = 0;
1061                 return;
1062         }
1063 
1064         priv->p2r_bar[0].free = priv->p2r_bar[0].size;
1065         priv->p2r_bar[1].free = priv->p2r_bar[1].size;
1066 
1067         for (i = 0; i < TSI721_OBWIN_NUM; i++)
1068                 priv->ob_win[i].active = false;
1069 
1070         priv->obwin_cnt = TSI721_OBWIN_NUM;
1071 }
1072 
1073 /**
1074  * tsi721_rio_map_inb_mem -- Mapping inbound memory region.
1075  * @mport: RapidIO master port
1076  * @lstart: Local memory space start address.
1077  * @rstart: RapidIO space start address.
1078  * @size: The mapping region size.
1079  * @flags: Flags for mapping. 0 for using default flags.
1080  *
1081  * Return: 0 -- Success.
1082  *
1083  * This function will create the inbound mapping
1084  * from rstart to lstart.
1085  */
1086 static int tsi721_rio_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
1087                 u64 rstart, u64 size, u32 flags)
1088 {
1089         struct tsi721_device *priv = mport->priv;
1090         int i, avail = -1;
1091         u32 regval;
1092         struct tsi721_ib_win *ib_win;
1093         bool direct = (lstart == rstart);
1094         u64 ibw_size;
1095         dma_addr_t loc_start;
1096         u64 ibw_start;
1097         struct tsi721_ib_win_mapping *map = NULL;
1098         int ret = -EBUSY;
1099 
1100         /* Max IBW size supported by HW is 16GB */
1101         if (size > 0x400000000UL)
1102                 return -EINVAL;
1103 
1104         if (direct) {
1105                 /* Calculate minimal acceptable window size and base address */
1106 
1107                 ibw_size = roundup_pow_of_two(size);
1108                 ibw_start = lstart & ~(ibw_size - 1);
1109 
1110                 tsi_debug(IBW, &priv->pdev->dev,
1111                         "Direct (RIO_0x%llx -> PCIe_%pad), size=0x%llx, ibw_start = 0x%llx",
1112                         rstart, &lstart, size, ibw_start);
1113 
1114                 while ((lstart + size) > (ibw_start + ibw_size)) {
1115                         ibw_size *= 2;
1116                         ibw_start = lstart & ~(ibw_size - 1);
1117                         /* Check for crossing IBW max size 16GB */
1118                         if (ibw_size > 0x400000000UL)
1119                                 return -EBUSY;
1120                 }
1121 
1122                 loc_start = ibw_start;
1123 
1124                 map = kzalloc(sizeof(struct tsi721_ib_win_mapping), GFP_ATOMIC);
1125                 if (map == NULL)
1126                         return -ENOMEM;
1127 
1128         } else {
1129                 tsi_debug(IBW, &priv->pdev->dev,
1130                         "Translated (RIO_0x%llx -> PCIe_%pad), size=0x%llx",
1131                         rstart, &lstart, size);
1132 
1133                 if (!is_power_of_2(size) || size < 0x1000 ||
1134                     ((u64)lstart & (size - 1)) || (rstart & (size - 1)))
1135                         return -EINVAL;
1136                 if (priv->ibwin_cnt == 0)
1137                         return -EBUSY;
1138                 ibw_start = rstart;
1139                 ibw_size = size;
1140                 loc_start = lstart;
1141         }
1142 
1143         /*
1144          * Scan for overlapping with active regions and mark the first available
1145          * IB window at the same time.
1146          */
1147         for (i = 0; i < TSI721_IBWIN_NUM; i++) {
1148                 ib_win = &priv->ib_win[i];
1149 
1150                 if (!ib_win->active) {
1151                         if (avail == -1) {
1152                                 avail = i;
1153                                 ret = 0;
1154                         }
1155                 } else if (ibw_start < (ib_win->rstart + ib_win->size) &&
1156                            (ibw_start + ibw_size) > ib_win->rstart) {
1157                         /* Return error if address translation involved */
1158                         if (!direct || ib_win->xlat) {
1159                                 ret = -EFAULT;
1160                                 break;
1161                         }
1162 
1163                         /*
1164                          * Direct mappings usually are larger than originally
1165                          * requested fragments - check if this new request fits
1166                          * into it.
1167                          */
1168                         if (rstart >= ib_win->rstart &&
1169                             (rstart + size) <= (ib_win->rstart +
1170                                                         ib_win->size)) {
1171                                 /* We are in - no further mapping required */
1172                                 map->lstart = lstart;
1173                                 list_add_tail(&map->node, &ib_win->mappings);
1174                                 return 0;
1175                         }
1176 
1177                         ret = -EFAULT;
1178                         break;
1179                 }
1180         }
1181 
1182         if (ret)
1183                 goto out;
1184         i = avail;
1185 
1186         /* Sanity check: available IB window must be disabled at this point */
1187         regval = ioread32(priv->regs + TSI721_IBWIN_LB(i));
1188         if (WARN_ON(regval & TSI721_IBWIN_LB_WEN)) {
1189                 ret = -EIO;
1190                 goto out;
1191         }
1192 
1193         ib_win = &priv->ib_win[i];
1194         ib_win->active = true;
1195         ib_win->rstart = ibw_start;
1196         ib_win->lstart = loc_start;
1197         ib_win->size = ibw_size;
1198         ib_win->xlat = (lstart != rstart);
1199         INIT_LIST_HEAD(&ib_win->mappings);
1200 
1201         /*
1202          * When using direct IBW mapping and have larger than requested IBW size
1203          * we can have multiple local memory blocks mapped through the same IBW
1204          * To handle this situation we maintain list of "clients" for such IBWs.
1205          */
1206         if (direct) {
1207                 map->lstart = lstart;
1208                 list_add_tail(&map->node, &ib_win->mappings);
1209         }
1210 
1211         iowrite32(TSI721_IBWIN_SIZE(ibw_size) << 8,
1212                         priv->regs + TSI721_IBWIN_SZ(i));
1213 
1214         iowrite32(((u64)loc_start >> 32), priv->regs + TSI721_IBWIN_TUA(i));
1215         iowrite32(((u64)loc_start & TSI721_IBWIN_TLA_ADD),
1216                   priv->regs + TSI721_IBWIN_TLA(i));
1217 
1218         iowrite32(ibw_start >> 32, priv->regs + TSI721_IBWIN_UB(i));
1219         iowrite32((ibw_start & TSI721_IBWIN_LB_BA) | TSI721_IBWIN_LB_WEN,
1220                 priv->regs + TSI721_IBWIN_LB(i));
1221 
1222         priv->ibwin_cnt--;
1223 
1224         tsi_debug(IBW, &priv->pdev->dev,
1225                 "Configured IBWIN%d (RIO_0x%llx -> PCIe_%pad), size=0x%llx",
1226                 i, ibw_start, &loc_start, ibw_size);
1227 
1228         return 0;
1229 out:
1230         kfree(map);
1231         return ret;
1232 }
1233 
1234 /**
1235  * tsi721_rio_unmap_inb_mem -- Unmapping inbound memory region.
1236  * @mport: RapidIO master port
1237  * @lstart: Local memory space start address.
1238  */
1239 static void tsi721_rio_unmap_inb_mem(struct rio_mport *mport,
1240                                 dma_addr_t lstart)
1241 {
1242         struct tsi721_device *priv = mport->priv;
1243         struct tsi721_ib_win *ib_win;
1244         int i;
1245 
1246         tsi_debug(IBW, &priv->pdev->dev,
1247                 "Unmap IBW mapped to PCIe_%pad", &lstart);
1248 
1249         /* Search for matching active inbound translation window */
1250         for (i = 0; i < TSI721_IBWIN_NUM; i++) {
1251                 ib_win = &priv->ib_win[i];
1252 
1253                 /* Address translating IBWs must to be an exact march */
1254                 if (!ib_win->active ||
1255                     (ib_win->xlat && lstart != ib_win->lstart))
1256                         continue;
1257 
1258                 if (lstart >= ib_win->lstart &&
1259                     lstart < (ib_win->lstart + ib_win->size)) {
1260 
1261                         if (!ib_win->xlat) {
1262                                 struct tsi721_ib_win_mapping *map;
1263                                 int found = 0;
1264 
1265                                 list_for_each_entry(map,
1266                                                     &ib_win->mappings, node) {
1267                                         if (map->lstart == lstart) {
1268                                                 list_del(&map->node);
1269                                                 kfree(map);
1270                                                 found = 1;
1271                                                 break;
1272                                         }
1273                                 }
1274 
1275                                 if (!found)
1276                                         continue;
1277 
1278                                 if (!list_empty(&ib_win->mappings))
1279                                         break;
1280                         }
1281 
1282                         tsi_debug(IBW, &priv->pdev->dev, "Disable IBWIN_%d", i);
1283                         iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1284                         ib_win->active = false;
1285                         priv->ibwin_cnt++;
1286                         break;
1287                 }
1288         }
1289 
1290         if (i == TSI721_IBWIN_NUM)
1291                 tsi_debug(IBW, &priv->pdev->dev,
1292                         "IB window mapped to %pad not found", &lstart);
1293 }
1294 
1295 /**
1296  * tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe)
1297  * translation regions.
1298  * @priv: pointer to tsi721 private data
1299  *
1300  * Disables inbound windows.
1301  */
1302 static void tsi721_init_sr2pc_mapping(struct tsi721_device *priv)
1303 {
1304         int i;
1305 
1306         /* Disable all SR2PC inbound windows */
1307         for (i = 0; i < TSI721_IBWIN_NUM; i++)
1308                 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1309         priv->ibwin_cnt = TSI721_IBWIN_NUM;
1310 }
1311 
1312 /*
1313  * tsi721_close_sr2pc_mapping - closes all active inbound (SRIO->PCIe)
1314  * translation regions.
1315  * @priv: pointer to tsi721 device private data
1316  */
1317 static void tsi721_close_sr2pc_mapping(struct tsi721_device *priv)
1318 {
1319         struct tsi721_ib_win *ib_win;
1320         int i;
1321 
1322         /* Disable all active SR2PC inbound windows */
1323         for (i = 0; i < TSI721_IBWIN_NUM; i++) {
1324                 ib_win = &priv->ib_win[i];
1325                 if (ib_win->active) {
1326                         iowrite32(0, priv->regs + TSI721_IBWIN_LB(i));
1327                         ib_win->active = false;
1328                 }
1329         }
1330 }
1331 
1332 /**
1333  * tsi721_port_write_init - Inbound port write interface init
1334  * @priv: pointer to tsi721 private data
1335  *
1336  * Initializes inbound port write handler.
1337  * Returns %0 on success or %-ENOMEM on failure.
1338  */
1339 static int tsi721_port_write_init(struct tsi721_device *priv)
1340 {
1341         priv->pw_discard_count = 0;
1342         INIT_WORK(&priv->pw_work, tsi721_pw_dpc);
1343         spin_lock_init(&priv->pw_fifo_lock);
1344         if (kfifo_alloc(&priv->pw_fifo,
1345                         TSI721_RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1346                 tsi_err(&priv->pdev->dev, "PW FIFO allocation failed");
1347                 return -ENOMEM;
1348         }
1349 
1350         /* Use reliable port-write capture mode */
1351         iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL);
1352         return 0;
1353 }
1354 
1355 static void tsi721_port_write_free(struct tsi721_device *priv)
1356 {
1357         kfifo_free(&priv->pw_fifo);
1358 }
1359 
1360 static int tsi721_doorbell_init(struct tsi721_device *priv)
1361 {
1362         /* Outbound Doorbells do not require any setup.
1363          * Tsi721 uses dedicated PCI BAR1 to generate doorbells.
1364          * That BAR1 was mapped during the probe routine.
1365          */
1366 
1367         /* Initialize Inbound Doorbell processing DPC and queue */
1368         priv->db_discard_count = 0;
1369         INIT_WORK(&priv->idb_work, tsi721_db_dpc);
1370 
1371         /* Allocate buffer for inbound doorbells queue */
1372         priv->idb_base = dma_alloc_coherent(&priv->pdev->dev,
1373                                             IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
1374                                             &priv->idb_dma, GFP_KERNEL);
1375         if (!priv->idb_base)
1376                 return -ENOMEM;
1377 
1378         tsi_debug(DBELL, &priv->pdev->dev,
1379                   "Allocated IDB buffer @ %p (phys = %pad)",
1380                   priv->idb_base, &priv->idb_dma);
1381 
1382         iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE),
1383                 priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE));
1384         iowrite32(((u64)priv->idb_dma >> 32),
1385                 priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE));
1386         iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR),
1387                 priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE));
1388         /* Enable accepting all inbound doorbells */
1389         iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));
1390 
1391         iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));
1392 
1393         iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
1394 
1395         return 0;
1396 }
1397 
1398 static void tsi721_doorbell_free(struct tsi721_device *priv)
1399 {
1400         if (priv->idb_base == NULL)
1401                 return;
1402 
1403         /* Free buffer allocated for inbound doorbell queue */
1404         dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
1405                           priv->idb_base, priv->idb_dma);
1406         priv->idb_base = NULL;
1407 }
1408 
1409 /**
1410  * tsi721_bdma_maint_init - Initialize maintenance request BDMA channel.
1411  * @priv: pointer to tsi721 private data
1412  *
1413  * Initialize BDMA channel allocated for RapidIO maintenance read/write
1414  * request generation
1415  * Returns %0 on success or %-ENOMEM on failure.
1416  */
1417 static int tsi721_bdma_maint_init(struct tsi721_device *priv)
1418 {
1419         struct tsi721_dma_desc *bd_ptr;
1420         u64             *sts_ptr;
1421         dma_addr_t      bd_phys, sts_phys;
1422         int             sts_size;
1423         int             bd_num = 2;
1424         void __iomem    *regs;
1425 
1426         tsi_debug(MAINT, &priv->pdev->dev,
1427                   "Init BDMA_%d Maintenance requests", TSI721_DMACH_MAINT);
1428 
1429         /*
1430          * Initialize DMA channel for maintenance requests
1431          */
1432 
1433         priv->mdma.ch_id = TSI721_DMACH_MAINT;
1434         regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT);
1435 
1436         /* Allocate space for DMA descriptors */
1437         bd_ptr = dma_alloc_coherent(&priv->pdev->dev,
1438                                     bd_num * sizeof(struct tsi721_dma_desc),
1439                                     &bd_phys, GFP_KERNEL);
1440         if (!bd_ptr)
1441                 return -ENOMEM;
1442 
1443         priv->mdma.bd_num = bd_num;
1444         priv->mdma.bd_phys = bd_phys;
1445         priv->mdma.bd_base = bd_ptr;
1446 
1447         tsi_debug(MAINT, &priv->pdev->dev, "DMA descriptors @ %p (phys = %pad)",
1448                   bd_ptr, &bd_phys);
1449 
1450         /* Allocate space for descriptor status FIFO */
1451         sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
1452                                         bd_num : TSI721_DMA_MINSTSSZ;
1453         sts_size = roundup_pow_of_two(sts_size);
1454         sts_ptr = dma_alloc_coherent(&priv->pdev->dev,
1455                                      sts_size * sizeof(struct tsi721_dma_sts),
1456                                      &sts_phys, GFP_KERNEL);
1457         if (!sts_ptr) {
1458                 /* Free space allocated for DMA descriptors */
1459                 dma_free_coherent(&priv->pdev->dev,
1460                                   bd_num * sizeof(struct tsi721_dma_desc),
1461                                   bd_ptr, bd_phys);
1462                 priv->mdma.bd_base = NULL;
1463                 return -ENOMEM;
1464         }
1465 
1466         priv->mdma.sts_phys = sts_phys;
1467         priv->mdma.sts_base = sts_ptr;
1468         priv->mdma.sts_size = sts_size;
1469 
1470         tsi_debug(MAINT, &priv->pdev->dev,
1471                 "desc status FIFO @ %p (phys = %pad) size=0x%x",
1472                 sts_ptr, &sts_phys, sts_size);
1473 
1474         /* Initialize DMA descriptors ring */
1475         bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29);
1476         bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys &
1477                                                  TSI721_DMAC_DPTRL_MASK);
1478         bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
1479 
1480         /* Setup DMA descriptor pointers */
1481         iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH);
1482         iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
1483                 regs + TSI721_DMAC_DPTRL);
1484 
1485         /* Setup descriptor status FIFO */
1486         iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH);
1487         iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
1488                 regs + TSI721_DMAC_DSBL);
1489         iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
1490                 regs + TSI721_DMAC_DSSZ);
1491 
1492         /* Clear interrupt bits */
1493         iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
1494 
1495         ioread32(regs + TSI721_DMAC_INT);
1496 
1497         /* Toggle DMA channel initialization */
1498         iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1499         ioread32(regs + TSI721_DMAC_CTL);
1500         udelay(10);
1501 
1502         return 0;
1503 }
1504 
1505 static int tsi721_bdma_maint_free(struct tsi721_device *priv)
1506 {
1507         u32 ch_stat;
1508         struct tsi721_bdma_maint *mdma = &priv->mdma;
1509         void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id);
1510 
1511         if (mdma->bd_base == NULL)
1512                 return 0;
1513 
1514         /* Check if DMA channel still running */
1515         ch_stat = ioread32(regs + TSI721_DMAC_STS);
1516         if (ch_stat & TSI721_DMAC_STS_RUN)
1517                 return -EFAULT;
1518 
1519         /* Put DMA channel into init state */
1520         iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
1521 
1522         /* Free space allocated for DMA descriptors */
1523         dma_free_coherent(&priv->pdev->dev,
1524                 mdma->bd_num * sizeof(struct tsi721_dma_desc),
1525                 mdma->bd_base, mdma->bd_phys);
1526         mdma->bd_base = NULL;
1527 
1528         /* Free space allocated for status FIFO */
1529         dma_free_coherent(&priv->pdev->dev,
1530                 mdma->sts_size * sizeof(struct tsi721_dma_sts),
1531                 mdma->sts_base, mdma->sts_phys);
1532         mdma->sts_base = NULL;
1533         return 0;
1534 }
1535 
1536 /* Enable Inbound Messaging Interrupts */
1537 static void
1538 tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,
1539                                   u32 inte_mask)
1540 {
1541         u32 rval;
1542 
1543         if (!inte_mask)
1544                 return;
1545 
1546         /* Clear pending Inbound Messaging interrupts */
1547         iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1548 
1549         /* Enable Inbound Messaging interrupts */
1550         rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1551         iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch));
1552 
1553         if (priv->flags & TSI721_USING_MSIX)
1554                 return; /* Finished if we are in MSI-X mode */
1555 
1556         /*
1557          * For MSI and INTA interrupt signalling we need to enable next levels
1558          */
1559 
1560         /* Enable Device Channel Interrupt */
1561         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1562         iowrite32(rval | TSI721_INT_IMSG_CHAN(ch),
1563                   priv->regs + TSI721_DEV_CHAN_INTE);
1564 }
1565 
1566 /* Disable Inbound Messaging Interrupts */
1567 static void
1568 tsi721_imsg_interrupt_disable(struct tsi721_device *priv, int ch,
1569                                    u32 inte_mask)
1570 {
1571         u32 rval;
1572 
1573         if (!inte_mask)
1574                 return;
1575 
1576         /* Clear pending Inbound Messaging interrupts */
1577         iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch));
1578 
1579         /* Disable Inbound Messaging interrupts */
1580         rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch));
1581         rval &= ~inte_mask;
1582         iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch));
1583 
1584         if (priv->flags & TSI721_USING_MSIX)
1585                 return; /* Finished if we are in MSI-X mode */
1586 
1587         /*
1588          * For MSI and INTA interrupt signalling we need to disable next levels
1589          */
1590 
1591         /* Disable Device Channel Interrupt */
1592         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1593         rval &= ~TSI721_INT_IMSG_CHAN(ch);
1594         iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1595 }
1596 
1597 /* Enable Outbound Messaging interrupts */
1598 static void
1599 tsi721_omsg_interrupt_enable(struct tsi721_device *priv, int ch,
1600                                   u32 inte_mask)
1601 {
1602         u32 rval;
1603 
1604         if (!inte_mask)
1605                 return;
1606 
1607         /* Clear pending Outbound Messaging interrupts */
1608         iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1609 
1610         /* Enable Outbound Messaging channel interrupts */
1611         rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1612         iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch));
1613 
1614         if (priv->flags & TSI721_USING_MSIX)
1615                 return; /* Finished if we are in MSI-X mode */
1616 
1617         /*
1618          * For MSI and INTA interrupt signalling we need to enable next levels
1619          */
1620 
1621         /* Enable Device Channel Interrupt */
1622         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1623         iowrite32(rval | TSI721_INT_OMSG_CHAN(ch),
1624                   priv->regs + TSI721_DEV_CHAN_INTE);
1625 }
1626 
1627 /* Disable Outbound Messaging interrupts */
1628 static void
1629 tsi721_omsg_interrupt_disable(struct tsi721_device *priv, int ch,
1630                                    u32 inte_mask)
1631 {
1632         u32 rval;
1633 
1634         if (!inte_mask)
1635                 return;
1636 
1637         /* Clear pending Outbound Messaging interrupts */
1638         iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch));
1639 
1640         /* Disable Outbound Messaging interrupts */
1641         rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch));
1642         rval &= ~inte_mask;
1643         iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch));
1644 
1645         if (priv->flags & TSI721_USING_MSIX)
1646                 return; /* Finished if we are in MSI-X mode */
1647 
1648         /*
1649          * For MSI and INTA interrupt signalling we need to disable next levels
1650          */
1651 
1652         /* Disable Device Channel Interrupt */
1653         rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1654         rval &= ~TSI721_INT_OMSG_CHAN(ch);
1655         iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE);
1656 }
1657 
1658 /**
1659  * tsi721_add_outb_message - Add message to the Tsi721 outbound message queue
1660  * @mport: Master port with outbound message queue
1661  * @rdev: Target of outbound message
1662  * @mbox: Outbound mailbox
1663  * @buffer: Message to add to outbound queue
1664  * @len: Length of message
1665  */
1666 static int
1667 tsi721_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
1668                         void *buffer, size_t len)
1669 {
1670         struct tsi721_device *priv = mport->priv;
1671         struct tsi721_omsg_desc *desc;
1672         u32 tx_slot;
1673         unsigned long flags;
1674 
1675         if (!priv->omsg_init[mbox] ||
1676             len > TSI721_MSG_MAX_SIZE || len < 8)
1677                 return -EINVAL;
1678 
1679         spin_lock_irqsave(&priv->omsg_ring[mbox].lock, flags);
1680 
1681         tx_slot = priv->omsg_ring[mbox].tx_slot;
1682 
1683         /* Copy copy message into transfer buffer */
1684         memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len);
1685 
1686         if (len & 0x7)
1687                 len += 8;
1688 
1689         /* Build descriptor associated with buffer */
1690         desc = priv->omsg_ring[mbox].omd_base;
1691         desc[tx_slot].type_id = cpu_to_le32((DTYPE4 << 29) | rdev->destid);
1692 #ifdef TSI721_OMSG_DESC_INT
1693         /* Request IOF_DONE interrupt generation for each N-th frame in queue */
1694         if (tx_slot % 4 == 0)
1695                 desc[tx_slot].type_id |= cpu_to_le32(TSI721_OMD_IOF);
1696 #endif
1697         desc[tx_slot].msg_info =
1698                 cpu_to_le32((mport->sys_size << 26) | (mbox << 22) |
1699                             (0xe << 12) | (len & 0xff8));
1700         desc[tx_slot].bufptr_lo =
1701                 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] &
1702                             0xffffffff);
1703         desc[tx_slot].bufptr_hi =
1704                 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32);
1705 
1706         priv->omsg_ring[mbox].wr_count++;
1707 
1708         /* Go to next descriptor */
1709         if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) {
1710                 priv->omsg_ring[mbox].tx_slot = 0;
1711                 /* Move through the ring link descriptor at the end */
1712                 priv->omsg_ring[mbox].wr_count++;
1713         }
1714 
1715         mb();
1716 
1717         /* Set new write count value */
1718         iowrite32(priv->omsg_ring[mbox].wr_count,
1719                 priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1720         ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
1721 
1722         spin_unlock_irqrestore(&priv->omsg_ring[mbox].lock, flags);
1723 
1724         return 0;
1725 }
1726 
1727 /**
1728  * tsi721_omsg_handler - Outbound Message Interrupt Handler
1729  * @priv: pointer to tsi721 private data
1730  * @ch:   number of OB MSG channel to service
1731  *
1732  * Services channel interrupts from outbound messaging engine.
1733  */
1734 static void tsi721_omsg_handler(struct tsi721_device *priv, int ch)
1735 {
1736         u32 omsg_int;
1737         struct rio_mport *mport = &priv->mport;
1738         void *dev_id = NULL;
1739         u32 tx_slot = 0xffffffff;
1740         int do_callback = 0;
1741 
1742         spin_lock(&priv->omsg_ring[ch].lock);
1743 
1744         omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch));
1745 
1746         if (omsg_int & TSI721_OBDMAC_INT_ST_FULL)
1747                 tsi_info(&priv->pdev->dev,
1748                         "OB MBOX%d: Status FIFO is full", ch);
1749 
1750         if (omsg_int & (TSI721_OBDMAC_INT_DONE | TSI721_OBDMAC_INT_IOF_DONE)) {
1751                 u32 srd_ptr;
1752                 u64 *sts_ptr, last_ptr = 0, prev_ptr = 0;
1753                 int i, j;
1754 
1755                 /*
1756                  * Find last successfully processed descriptor
1757                  */
1758 
1759                 /* Check and clear descriptor status FIFO entries */
1760                 srd_ptr = priv->omsg_ring[ch].sts_rdptr;
1761                 sts_ptr = priv->omsg_ring[ch].sts_base;
1762                 j = srd_ptr * 8;
1763                 while (sts_ptr[j]) {
1764                         for (i = 0; i < 8 && sts_ptr[j]; i++, j++) {
1765                                 prev_ptr = last_ptr;
1766                                 last_ptr = le64_to_cpu(sts_ptr[j]);
1767                                 sts_ptr[j] = 0;
1768                         }
1769 
1770                         ++srd_ptr;
1771                         srd_ptr %= priv->omsg_ring[ch].sts_size;
1772                         j = srd_ptr * 8;
1773                 }
1774 
1775                 if (last_ptr == 0)
1776                         goto no_sts_update;
1777 
1778                 priv->omsg_ring[ch].sts_rdptr = srd_ptr;
1779                 iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch));
1780 
1781                 if (!mport->outb_msg[ch].mcback)
1782                         goto no_sts_update;
1783 
1784                 /* Inform upper layer about transfer completion */
1785 
1786                 tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/
1787                                                 sizeof(struct tsi721_omsg_desc);
1788 
1789                 /*
1790                  * Check if this is a Link Descriptor (LD).
1791                  * If yes, ignore LD and use descriptor processed
1792                  * before LD.
1793                  */
1794                 if (tx_slot == priv->omsg_ring[ch].size) {
1795                         if (prev_ptr)
1796                                 tx_slot = (prev_ptr -
1797                                         (u64)priv->omsg_ring[ch].omd_phys)/
1798                                                 sizeof(struct tsi721_omsg_desc);
1799                         else
1800                                 goto no_sts_update;
1801                 }
1802 
1803                 if (tx_slot >= priv->omsg_ring[ch].size)
1804                         tsi_debug(OMSG, &priv->pdev->dev,
1805                                   "OB_MSG tx_slot=%x > size=%x",
1806                                   tx_slot, priv->omsg_ring[ch].size);
1807                 WARN_ON(tx_slot >= priv->omsg_ring[ch].size);
1808 
1809                 /* Move slot index to the next message to be sent */
1810                 ++tx_slot;
1811                 if (tx_slot == priv->omsg_ring[ch].size)
1812                         tx_slot = 0;
1813 
1814                 dev_id = priv->omsg_ring[ch].dev_id;
1815                 do_callback = 1;
1816         }
1817 
1818 no_sts_update:
1819 
1820         if (omsg_int & TSI721_OBDMAC_INT_ERROR) {
1821                 /*
1822                 * Outbound message operation aborted due to error,
1823                 * reinitialize OB MSG channel
1824                 */
1825 
1826                 tsi_debug(OMSG, &priv->pdev->dev, "OB MSG ABORT ch_stat=%x",
1827                           ioread32(priv->regs + TSI721_OBDMAC_STS(ch)));
1828 
1829                 iowrite32(TSI721_OBDMAC_INT_ERROR,
1830                                 priv->regs + TSI721_OBDMAC_INT(ch));
1831                 iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT,
1832                                 priv->regs + TSI721_OBDMAC_CTL(ch));
1833                 ioread32(priv->regs + TSI721_OBDMAC_CTL(ch));
1834 
1835                 /* Inform upper level to clear all pending tx slots */
1836                 dev_id = priv->omsg_ring[ch].dev_id;
1837                 tx_slot = priv->omsg_ring[ch].tx_slot;
1838                 do_callback = 1;
1839 
1840                 /* Synch tx_slot tracking */
1841                 iowrite32(priv->omsg_ring[ch].tx_slot,
1842                         priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1843                 ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch));
1844                 priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot;
1845                 priv->omsg_ring[ch].sts_rdptr = 0;
1846         }
1847 
1848         /* Clear channel interrupts */
1849         iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch));
1850 
1851         if (!(priv->flags & TSI721_USING_MSIX)) {
1852                 u32 ch_inte;
1853 
1854                 /* Re-enable channel interrupts */
1855                 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
1856                 ch_inte |= TSI721_INT_OMSG_CHAN(ch);
1857                 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
1858         }
1859 
1860         spin_unlock(&priv->omsg_ring[ch].lock);
1861 
1862         if (mport->outb_msg[ch].mcback && do_callback)
1863                 mport->outb_msg[ch].mcback(mport, dev_id, ch, tx_slot);
1864 }
1865 
1866 /**
1867  * tsi721_open_outb_mbox - Initialize Tsi721 outbound mailbox
1868  * @mport: Master port implementing Outbound Messaging Engine
1869  * @dev_id: Device specific pointer to pass on event
1870  * @mbox: Mailbox to open
1871  * @entries: Number of entries in the outbound mailbox ring
1872  */
1873 static int tsi721_open_outb_mbox(struct rio_mport *mport, void *dev_id,
1874                                  int mbox, int entries)
1875 {
1876         struct tsi721_device *priv = mport->priv;
1877         struct tsi721_omsg_desc *bd_ptr;
1878         int i, rc = 0;
1879 
1880         if ((entries < TSI721_OMSGD_MIN_RING_SIZE) ||
1881             (entries > (TSI721_OMSGD_RING_SIZE)) ||
1882             (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
1883                 rc = -EINVAL;
1884                 goto out;
1885         }
1886 
1887         if ((mbox_sel & (1 << mbox)) == 0) {
1888                 rc = -ENODEV;
1889                 goto out;
1890         }
1891 
1892         priv->omsg_ring[mbox].dev_id = dev_id;
1893         priv->omsg_ring[mbox].size = entries;
1894         priv->omsg_ring[mbox].sts_rdptr = 0;
1895         spin_lock_init(&priv->omsg_ring[mbox].lock);
1896 
1897         /* Outbound Msg Buffer allocation based on
1898            the number of maximum descriptor entries */
1899         for (i = 0; i < entries; i++) {
1900                 priv->omsg_ring[mbox].omq_base[i] =
1901                         dma_alloc_coherent(
1902                                 &priv->pdev->dev, TSI721_MSG_BUFFER_SIZE,
1903                                 &priv->omsg_ring[mbox].omq_phys[i],
1904                                 GFP_KERNEL);
1905                 if (priv->omsg_ring[mbox].omq_base[i] == NULL) {
1906                         tsi_debug(OMSG, &priv->pdev->dev,
1907                                   "ENOMEM for OB_MSG_%d data buffer", mbox);
1908                         rc = -ENOMEM;
1909                         goto out_buf;
1910                 }
1911         }
1912 
1913         /* Outbound message descriptor allocation */
1914         priv->omsg_ring[mbox].omd_base = dma_alloc_coherent(
1915                                 &priv->pdev->dev,
1916                                 (entries + 1) * sizeof(struct tsi721_omsg_desc),
1917                                 &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL);
1918         if (priv->omsg_ring[mbox].omd_base == NULL) {
1919                 tsi_debug(OMSG, &priv->pdev->dev,
1920                         "ENOMEM for OB_MSG_%d descriptor memory", mbox);
1921                 rc = -ENOMEM;
1922                 goto out_buf;
1923         }
1924 
1925         priv->omsg_ring[mbox].tx_slot = 0;
1926 
1927         /* Outbound message descriptor status FIFO allocation */
1928         priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1);
1929         priv->omsg_ring[mbox].sts_base = dma_alloc_coherent(&priv->pdev->dev,
1930                                                             priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
1931                                                             &priv->omsg_ring[mbox].sts_phys,
1932                                                             GFP_KERNEL);
1933         if (priv->omsg_ring[mbox].sts_base == NULL) {
1934                 tsi_debug(OMSG, &priv->pdev->dev,
1935                         "ENOMEM for OB_MSG_%d status FIFO", mbox);
1936                 rc = -ENOMEM;
1937                 goto out_desc;
1938         }
1939 
1940         /*
1941          * Configure Outbound Messaging Engine
1942          */
1943 
1944         /* Setup Outbound Message descriptor pointer */
1945         iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32),
1946                         priv->regs + TSI721_OBDMAC_DPTRH(mbox));
1947         iowrite32(((u64)priv->omsg_ring[mbox].omd_phys &
1948                                         TSI721_OBDMAC_DPTRL_MASK),
1949                         priv->regs + TSI721_OBDMAC_DPTRL(mbox));
1950 
1951         /* Setup Outbound Message descriptor status FIFO */
1952         iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32),
1953                         priv->regs + TSI721_OBDMAC_DSBH(mbox));
1954         iowrite32(((u64)priv->omsg_ring[mbox].sts_phys &
1955                                         TSI721_OBDMAC_DSBL_MASK),
1956                         priv->regs + TSI721_OBDMAC_DSBL(mbox));
1957         iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size),
1958                 priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox));
1959 
1960         /* Enable interrupts */
1961 
1962 #ifdef CONFIG_PCI_MSI
1963         if (priv->flags & TSI721_USING_MSIX) {
1964                 int idx = TSI721_VECT_OMB0_DONE + mbox;
1965 
1966                 /* Request interrupt service if we are in MSI-X mode */
1967                 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0,
1968                                  priv->msix[idx].irq_name, (void *)priv);
1969 
1970                 if (rc) {
1971                         tsi_debug(OMSG, &priv->pdev->dev,
1972                                 "Unable to get MSI-X IRQ for OBOX%d-DONE",
1973                                 mbox);
1974                         goto out_stat;
1975                 }
1976 
1977                 idx = TSI721_VECT_OMB0_INT + mbox;
1978                 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0,
1979                                  priv->msix[idx].irq_name, (void *)priv);
1980 
1981                 if (rc) {
1982                         tsi_debug(OMSG, &priv->pdev->dev,
1983                                 "Unable to get MSI-X IRQ for MBOX%d-INT", mbox);
1984                         idx = TSI721_VECT_OMB0_DONE + mbox;
1985                         free_irq(priv->msix[idx].vector, (void *)priv);
1986                         goto out_stat;
1987                 }
1988         }
1989 #endif /* CONFIG_PCI_MSI */
1990 
1991         tsi721_omsg_interrupt_enable(priv, mbox, TSI721_OBDMAC_INT_ALL);
1992 
1993         /* Initialize Outbound Message descriptors ring */
1994         bd_ptr = priv->omsg_ring[mbox].omd_base;
1995         bd_ptr[entries].type_id = cpu_to_le32(DTYPE5 << 29);
1996         bd_ptr[entries].msg_info = 0;
1997         bd_ptr[entries].next_lo =
1998                 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys &
1999                 TSI721_OBDMAC_DPTRL_MASK);
2000         bd_ptr[entries].next_hi =
2001                 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32);
2002         priv->omsg_ring[mbox].wr_count = 0;
2003         mb();
2004 
2005         /* Initialize Outbound Message engine */
2006         iowrite32(TSI721_OBDMAC_CTL_RETRY_THR | TSI721_OBDMAC_CTL_INIT,
2007                   priv->regs + TSI721_OBDMAC_CTL(mbox));
2008         ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox));
2009         udelay(10);
2010 
2011         priv->omsg_init[mbox] = 1;
2012 
2013         return 0;
2014 
2015 #ifdef CONFIG_PCI_MSI
2016 out_stat:
2017         dma_free_coherent(&priv->pdev->dev,
2018                 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
2019                 priv->omsg_ring[mbox].sts_base,
2020                 priv->omsg_ring[mbox].sts_phys);
2021 
2022         priv->omsg_ring[mbox].sts_base = NULL;
2023 #endif /* CONFIG_PCI_MSI */
2024 
2025 out_desc:
2026         dma_free_coherent(&priv->pdev->dev,
2027                 (entries + 1) * sizeof(struct tsi721_omsg_desc),
2028                 priv->omsg_ring[mbox].omd_base,
2029                 priv->omsg_ring[mbox].omd_phys);
2030 
2031         priv->omsg_ring[mbox].omd_base = NULL;
2032 
2033 out_buf:
2034         for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
2035                 if (priv->omsg_ring[mbox].omq_base[i]) {
2036                         dma_free_coherent(&priv->pdev->dev,
2037                                 TSI721_MSG_BUFFER_SIZE,
2038                                 priv->omsg_ring[mbox].omq_base[i],
2039                                 priv->omsg_ring[mbox].omq_phys[i]);
2040 
2041                         priv->omsg_ring[mbox].omq_base[i] = NULL;
2042                 }
2043         }
2044 
2045 out:
2046         return rc;
2047 }
2048 
2049 /**
2050  * tsi721_close_outb_mbox - Close Tsi721 outbound mailbox
2051  * @mport: Master port implementing the outbound message unit
2052  * @mbox: Mailbox to close
2053  */
2054 static void tsi721_close_outb_mbox(struct rio_mport *mport, int mbox)
2055 {
2056         struct tsi721_device *priv = mport->priv;
2057         u32 i;
2058 
2059         if (!priv->omsg_init[mbox])
2060                 return;
2061         priv->omsg_init[mbox] = 0;
2062 
2063         /* Disable Interrupts */
2064 
2065         tsi721_omsg_interrupt_disable(priv, mbox, TSI721_OBDMAC_INT_ALL);
2066 
2067 #ifdef CONFIG_PCI_MSI
2068         if (priv->flags & TSI721_USING_MSIX) {
2069                 free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector,
2070                          (void *)priv);
2071                 free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector,
2072                          (void *)priv);
2073         }
2074 #endif /* CONFIG_PCI_MSI */
2075 
2076         /* Free OMSG Descriptor Status FIFO */
2077         dma_free_coherent(&priv->pdev->dev,
2078                 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts),
2079                 priv->omsg_ring[mbox].sts_base,
2080                 priv->omsg_ring[mbox].sts_phys);
2081 
2082         priv->omsg_ring[mbox].sts_base = NULL;
2083 
2084         /* Free OMSG descriptors */
2085         dma_free_coherent(&priv->pdev->dev,
2086                 (priv->omsg_ring[mbox].size + 1) *
2087                         sizeof(struct tsi721_omsg_desc),
2088                 priv->omsg_ring[mbox].omd_base,
2089                 priv->omsg_ring[mbox].omd_phys);
2090 
2091         priv->omsg_ring[mbox].omd_base = NULL;
2092 
2093         /* Free message buffers */
2094         for (i = 0; i < priv->omsg_ring[mbox].size; i++) {
2095                 if (priv->omsg_ring[mbox].omq_base[i]) {
2096                         dma_free_coherent(&priv->pdev->dev,
2097                                 TSI721_MSG_BUFFER_SIZE,
2098                                 priv->omsg_ring[mbox].omq_base[i],
2099                                 priv->omsg_ring[mbox].omq_phys[i]);
2100 
2101                         priv->omsg_ring[mbox].omq_base[i] = NULL;
2102                 }
2103         }
2104 }
2105 
2106 /**
2107  * tsi721_imsg_handler - Inbound Message Interrupt Handler
2108  * @priv: pointer to tsi721 private data
2109  * @ch: inbound message channel number to service
2110  *
2111  * Services channel interrupts from inbound messaging engine.
2112  */
2113 static void tsi721_imsg_handler(struct tsi721_device *priv, int ch)
2114 {
2115         u32 mbox = ch - 4;
2116         u32 imsg_int;
2117         struct rio_mport *mport = &priv->mport;
2118 
2119         spin_lock(&priv->imsg_ring[mbox].lock);
2120 
2121         imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch));
2122 
2123         if (imsg_int & TSI721_IBDMAC_INT_SRTO)
2124                 tsi_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout", mbox);
2125 
2126         if (imsg_int & TSI721_IBDMAC_INT_PC_ERROR)
2127                 tsi_info(&priv->pdev->dev, "IB MBOX%d PCIe error", mbox);
2128 
2129         if (imsg_int & TSI721_IBDMAC_INT_FQ_LOW)
2130                 tsi_info(&priv->pdev->dev, "IB MBOX%d IB free queue low", mbox);
2131 
2132         /* Clear IB channel interrupts */
2133         iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch));
2134 
2135         /* If an IB Msg is received notify the upper layer */
2136         if (imsg_int & TSI721_IBDMAC_INT_DQ_RCV &&
2137                 mport->inb_msg[mbox].mcback)
2138                 mport->inb_msg[mbox].mcback(mport,
2139                                 priv->imsg_ring[mbox].dev_id, mbox, -1);
2140 
2141         if (!(priv->flags & TSI721_USING_MSIX)) {
2142                 u32 ch_inte;
2143 
2144                 /* Re-enable channel interrupts */
2145                 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
2146                 ch_inte |= TSI721_INT_IMSG_CHAN(ch);
2147                 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
2148         }
2149 
2150         spin_unlock(&priv->imsg_ring[mbox].lock);
2151 }
2152 
2153 /**
2154  * tsi721_open_inb_mbox - Initialize Tsi721 inbound mailbox
2155  * @mport: Master port implementing the Inbound Messaging Engine
2156  * @dev_id: Device specific pointer to pass on event
2157  * @mbox: Mailbox to open
2158  * @entries: Number of entries in the inbound mailbox ring
2159  */
2160 static int tsi721_open_inb_mbox(struct rio_mport *mport, void *dev_id,
2161                                 int mbox, int entries)
2162 {
2163         struct tsi721_device *priv = mport->priv;
2164         int ch = mbox + 4;
2165         int i;
2166         u64 *free_ptr;
2167         int rc = 0;
2168 
2169         if ((entries < TSI721_IMSGD_MIN_RING_SIZE) ||
2170             (entries > TSI721_IMSGD_RING_SIZE) ||
2171             (!is_power_of_2(entries)) || mbox >= RIO_MAX_MBOX) {
2172                 rc = -EINVAL;
2173                 goto out;
2174         }
2175 
2176         if ((mbox_sel & (1 << mbox)) == 0) {
2177                 rc = -ENODEV;
2178                 goto out;
2179         }
2180 
2181         /* Initialize IB Messaging Ring */
2182         priv->imsg_ring[mbox].dev_id = dev_id;
2183         priv->imsg_ring[mbox].size = entries;
2184         priv->imsg_ring[mbox].rx_slot = 0;
2185         priv->imsg_ring[mbox].desc_rdptr = 0;
2186         priv->imsg_ring[mbox].fq_wrptr = 0;
2187         for (i = 0; i < priv->imsg_ring[mbox].size; i++)
2188                 priv->imsg_ring[mbox].imq_base[i] = NULL;
2189         spin_lock_init(&priv->imsg_ring[mbox].lock);
2190 
2191         /* Allocate buffers for incoming messages */
2192         priv->imsg_ring[mbox].buf_base =
2193                 dma_alloc_coherent(&priv->pdev->dev,
2194                                    entries * TSI721_MSG_BUFFER_SIZE,
2195                                    &priv->imsg_ring[mbox].buf_phys,
2196                                    GFP_KERNEL);
2197 
2198         if (priv->imsg_ring[mbox].buf_base == NULL) {
2199                 tsi_err(&priv->pdev->dev,
2200                         "Failed to allocate buffers for IB MBOX%d", mbox);
2201                 rc = -ENOMEM;
2202                 goto out;
2203         }
2204 
2205         /* Allocate memory for circular free list */
2206         priv->imsg_ring[mbox].imfq_base =
2207                 dma_alloc_coherent(&priv->pdev->dev,
2208                                    entries * 8,
2209                                    &priv->imsg_ring[mbox].imfq_phys,
2210                                    GFP_KERNEL);
2211 
2212         if (priv->imsg_ring[mbox].imfq_base == NULL) {
2213                 tsi_err(&priv->pdev->dev,
2214                         "Failed to allocate free queue for IB MBOX%d", mbox);
2215                 rc = -ENOMEM;
2216                 goto out_buf;
2217         }
2218 
2219         /* Allocate memory for Inbound message descriptors */
2220         priv->imsg_ring[mbox].imd_base =
2221                 dma_alloc_coherent(&priv->pdev->dev,
2222                                    entries * sizeof(struct tsi721_imsg_desc),
2223                                    &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL);
2224 
2225         if (priv->imsg_ring[mbox].imd_base == NULL) {
2226                 tsi_err(&priv->pdev->dev,
2227                         "Failed to allocate descriptor memory for IB MBOX%d",
2228                         mbox);
2229                 rc = -ENOMEM;
2230                 goto out_dma;
2231         }
2232 
2233         /* Fill free buffer pointer list */
2234         free_ptr = priv->imsg_ring[mbox].imfq_base;
2235         for (i = 0; i < entries; i++)
2236                 free_ptr[i] = cpu_to_le64(
2237                                 (u64)(priv->imsg_ring[mbox].buf_phys) +
2238                                 i * 0x1000);
2239 
2240         mb();
2241 
2242         /*
2243          * For mapping of inbound SRIO Messages into appropriate queues we need
2244          * to set Inbound Device ID register in the messaging engine. We do it
2245          * once when first inbound mailbox is requested.
2246          */
2247         if (!(priv->flags & TSI721_IMSGID_SET)) {
2248                 iowrite32((u32)priv->mport.host_deviceid,
2249                         priv->regs + TSI721_IB_DEVID);
2250                 priv->flags |= TSI721_IMSGID_SET;
2251         }
2252 
2253         /*
2254          * Configure Inbound Messaging channel (ch = mbox + 4)
2255          */
2256 
2257         /* Setup Inbound Message free queue */
2258         iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32),
2259                 priv->regs + TSI721_IBDMAC_FQBH(ch));
2260         iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys &
2261                         TSI721_IBDMAC_FQBL_MASK),
2262                 priv->regs+TSI721_IBDMAC_FQBL(ch));
2263         iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2264                 priv->regs + TSI721_IBDMAC_FQSZ(ch));
2265 
2266         /* Setup Inbound Message descriptor queue */
2267         iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32),
2268                 priv->regs + TSI721_IBDMAC_DQBH(ch));
2269         iowrite32(((u32)priv->imsg_ring[mbox].imd_phys &
2270                    (u32)TSI721_IBDMAC_DQBL_MASK),
2271                 priv->regs+TSI721_IBDMAC_DQBL(ch));
2272         iowrite32(TSI721_DMAC_DSSZ_SIZE(entries),
2273                 priv->regs + TSI721_IBDMAC_DQSZ(ch));
2274 
2275         /* Enable interrupts */
2276 
2277 #ifdef CONFIG_PCI_MSI
2278         if (priv->flags & TSI721_USING_MSIX) {
2279                 int idx = TSI721_VECT_IMB0_RCV + mbox;
2280 
2281                 /* Request interrupt service if we are in MSI-X mode */
2282                 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0,
2283                                  priv->msix[idx].irq_name, (void *)priv);
2284 
2285                 if (rc) {
2286                         tsi_debug(IMSG, &priv->pdev->dev,
2287                                 "Unable to get MSI-X IRQ for IBOX%d-DONE",
2288                                 mbox);
2289                         goto out_desc;
2290                 }
2291 
2292                 idx = TSI721_VECT_IMB0_INT + mbox;
2293                 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0,
2294                                  priv->msix[idx].irq_name, (void *)priv);
2295 
2296                 if (rc) {
2297                         tsi_debug(IMSG, &priv->pdev->dev,
2298                                 "Unable to get MSI-X IRQ for IBOX%d-INT", mbox);
2299                         free_irq(
2300                                 priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2301                                 (void *)priv);
2302                         goto out_desc;
2303                 }
2304         }
2305 #endif /* CONFIG_PCI_MSI */
2306 
2307         tsi721_imsg_interrupt_enable(priv, ch, TSI721_IBDMAC_INT_ALL);
2308 
2309         /* Initialize Inbound Message Engine */
2310         iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch));
2311         ioread32(priv->regs + TSI721_IBDMAC_CTL(ch));
2312         udelay(10);
2313         priv->imsg_ring[mbox].fq_wrptr = entries - 1;
2314         iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch));
2315 
2316         priv->imsg_init[mbox] = 1;
2317         return 0;
2318 
2319 #ifdef CONFIG_PCI_MSI
2320 out_desc:
2321         dma_free_coherent(&priv->pdev->dev,
2322                 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2323                 priv->imsg_ring[mbox].imd_base,
2324                 priv->imsg_ring[mbox].imd_phys);
2325 
2326         priv->imsg_ring[mbox].imd_base = NULL;
2327 #endif /* CONFIG_PCI_MSI */
2328 
2329 out_dma:
2330         dma_free_coherent(&priv->pdev->dev,
2331                 priv->imsg_ring[mbox].size * 8,
2332                 priv->imsg_ring[mbox].imfq_base,
2333                 priv->imsg_ring[mbox].imfq_phys);
2334 
2335         priv->imsg_ring[mbox].imfq_base = NULL;
2336 
2337 out_buf:
2338         dma_free_coherent(&priv->pdev->dev,
2339                 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2340                 priv->imsg_ring[mbox].buf_base,
2341                 priv->imsg_ring[mbox].buf_phys);
2342 
2343         priv->imsg_ring[mbox].buf_base = NULL;
2344 
2345 out:
2346         return rc;
2347 }
2348 
2349 /**
2350  * tsi721_close_inb_mbox - Shut down Tsi721 inbound mailbox
2351  * @mport: Master port implementing the Inbound Messaging Engine
2352  * @mbox: Mailbox to close
2353  */
2354 static void tsi721_close_inb_mbox(struct rio_mport *mport, int mbox)
2355 {
2356         struct tsi721_device *priv = mport->priv;
2357         u32 rx_slot;
2358         int ch = mbox + 4;
2359 
2360         if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */
2361                 return;
2362         priv->imsg_init[mbox] = 0;
2363 
2364         /* Disable Inbound Messaging Engine */
2365 
2366         /* Disable Interrupts */
2367         tsi721_imsg_interrupt_disable(priv, ch, TSI721_OBDMAC_INT_MASK);
2368 
2369 #ifdef CONFIG_PCI_MSI
2370         if (priv->flags & TSI721_USING_MSIX) {
2371                 free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector,
2372                                 (void *)priv);
2373                 free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector,
2374                                 (void *)priv);
2375         }
2376 #endif /* CONFIG_PCI_MSI */
2377 
2378         /* Clear Inbound Buffer Queue */
2379         for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++)
2380                 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2381 
2382         /* Free memory allocated for message buffers */
2383         dma_free_coherent(&priv->pdev->dev,
2384                 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE,
2385                 priv->imsg_ring[mbox].buf_base,
2386                 priv->imsg_ring[mbox].buf_phys);
2387 
2388         priv->imsg_ring[mbox].buf_base = NULL;
2389 
2390         /* Free memory allocated for free pointr list */
2391         dma_free_coherent(&priv->pdev->dev,
2392                 priv->imsg_ring[mbox].size * 8,
2393                 priv->imsg_ring[mbox].imfq_base,
2394                 priv->imsg_ring[mbox].imfq_phys);
2395 
2396         priv->imsg_ring[mbox].imfq_base = NULL;
2397 
2398         /* Free memory allocated for RX descriptors */
2399         dma_free_coherent(&priv->pdev->dev,
2400                 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc),
2401                 priv->imsg_ring[mbox].imd_base,
2402                 priv->imsg_ring[mbox].imd_phys);
2403 
2404         priv->imsg_ring[mbox].imd_base = NULL;
2405 }
2406 
2407 /**
2408  * tsi721_add_inb_buffer - Add buffer to the Tsi721 inbound message queue
2409  * @mport: Master port implementing the Inbound Messaging Engine
2410  * @mbox: Inbound mailbox number
2411  * @buf: Buffer to add to inbound queue
2412  */
2413 static int tsi721_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
2414 {
2415         struct tsi721_device *priv = mport->priv;
2416         u32 rx_slot;
2417         int rc = 0;
2418 
2419         rx_slot = priv->imsg_ring[mbox].rx_slot;
2420         if (priv->imsg_ring[mbox].imq_base[rx_slot]) {
2421                 tsi_err(&priv->pdev->dev,
2422                         "Error adding inbound buffer %d, buffer exists",
2423                         rx_slot);
2424                 rc = -EINVAL;
2425                 goto out;
2426         }
2427 
2428         priv->imsg_ring[mbox].imq_base[rx_slot] = buf;
2429 
2430         if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size)
2431                 priv->imsg_ring[mbox].rx_slot = 0;
2432 
2433 out:
2434         return rc;
2435 }
2436 
2437 /**
2438  * tsi721_get_inb_message - Fetch inbound message from the Tsi721 MSG Queue
2439  * @mport: Master port implementing the Inbound Messaging Engine
2440  * @mbox: Inbound mailbox number
2441  *
2442  * Returns pointer to the message on success or NULL on failure.
2443  */
2444 static void *tsi721_get_inb_message(struct rio_mport *mport, int mbox)
2445 {
2446         struct tsi721_device *priv = mport->priv;
2447         struct tsi721_imsg_desc *desc;
2448         u32 rx_slot;
2449         void *rx_virt = NULL;
2450         u64 rx_phys;
2451         void *buf = NULL;
2452         u64 *free_ptr;
2453         int ch = mbox + 4;
2454         int msg_size;
2455 
2456         if (!priv->imsg_init[mbox])
2457                 return NULL;
2458 
2459         desc = priv->imsg_ring[mbox].imd_base;
2460         desc += priv->imsg_ring[mbox].desc_rdptr;
2461 
2462         if (!(le32_to_cpu(desc->msg_info) & TSI721_IMD_HO))
2463                 goto out;
2464 
2465         rx_slot = priv->imsg_ring[mbox].rx_slot;
2466         while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) {
2467                 if (++rx_slot == priv->imsg_ring[mbox].size)
2468                         rx_slot = 0;
2469         }
2470 
2471         rx_phys = ((u64)le32_to_cpu(desc->bufptr_hi) << 32) |
2472                         le32_to_cpu(desc->bufptr_lo);
2473 
2474         rx_virt = priv->imsg_ring[mbox].buf_base +
2475                   (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys);
2476 
2477         buf = priv->imsg_ring[mbox].imq_base[rx_slot];
2478         msg_size = le32_to_cpu(desc->msg_info) & TSI721_IMD_BCOUNT;
2479         if (msg_size == 0)
2480                 msg_size = RIO_MAX_MSG_SIZE;
2481 
2482         memcpy(buf, rx_virt, msg_size);
2483         priv->imsg_ring[mbox].imq_base[rx_slot] = NULL;
2484 
2485         desc->msg_info &= cpu_to_le32(~TSI721_IMD_HO);
2486         if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size)
2487                 priv->imsg_ring[mbox].desc_rdptr = 0;
2488 
2489         iowrite32(priv->imsg_ring[mbox].desc_rdptr,
2490                 priv->regs + TSI721_IBDMAC_DQRP(ch));
2491 
2492         /* Return free buffer into the pointer list */
2493         free_ptr = priv->imsg_ring[mbox].imfq_base;
2494         free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys);
2495 
2496         if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size)
2497                 priv->imsg_ring[mbox].fq_wrptr = 0;
2498 
2499         iowrite32(priv->imsg_ring[mbox].fq_wrptr,
2500                 priv->regs + TSI721_IBDMAC_FQWP(ch));
2501 out:
2502         return buf;
2503 }
2504 
2505 /**
2506  * tsi721_messages_init - Initialization of Messaging Engine
2507  * @priv: pointer to tsi721 private data
2508  *
2509  * Configures Tsi721 messaging engine.
2510  */
2511 static int tsi721_messages_init(struct tsi721_device *priv)
2512 {
2513         int     ch;
2514 
2515         iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG);
2516         iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT);
2517         iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT);
2518 
2519         /* Set SRIO Message Request/Response Timeout */
2520         iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO);
2521 
2522         /* Initialize Inbound Messaging Engine Registers */
2523         for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++) {
2524                 /* Clear interrupt bits */
2525                 iowrite32(TSI721_IBDMAC_INT_MASK,
2526                         priv->regs + TSI721_IBDMAC_INT(ch));
2527                 /* Clear Status */
2528                 iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch));
2529 
2530                 iowrite32(TSI721_SMSG_ECC_COR_LOG_MASK,
2531                                 priv->regs + TSI721_SMSG_ECC_COR_LOG(ch));
2532                 iowrite32(TSI721_SMSG_ECC_NCOR_MASK,
2533                                 priv->regs + TSI721_SMSG_ECC_NCOR(ch));
2534         }
2535 
2536         return 0;
2537 }
2538 
2539 /**
2540  * tsi721_query_mport - Fetch inbound message from the Tsi721 MSG Queue
2541  * @mport: Master port implementing the Inbound Messaging Engine
2542  * @mbox: Inbound mailbox number
2543  *
2544  * Returns pointer to the message on success or NULL on failure.
2545  */
2546 static int tsi721_query_mport(struct rio_mport *mport,
2547                               struct rio_mport_attr *attr)
2548 {
2549         struct tsi721_device *priv = mport->priv;
2550         u32 rval;
2551 
2552         rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_ERR_STS_CSR(0, 0));
2553         if (rval & RIO_PORT_N_ERR_STS_PORT_OK) {
2554                 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL2_CSR(0, 0));
2555                 attr->link_speed = (rval & RIO_PORT_N_CTL2_SEL_BAUD) >> 28;
2556                 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL_CSR(0, 0));
2557                 attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27;
2558         } else
2559                 attr->link_speed = RIO_LINK_DOWN;
2560 
2561 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
2562         attr->flags = RIO_MPORT_DMA | RIO_MPORT_DMA_SG;
2563         attr->dma_max_sge = 0;
2564         attr->dma_max_size = TSI721_BDMA_MAX_BCOUNT;
2565         attr->dma_align = 0;
2566 #else
2567         attr->flags = 0;
2568 #endif
2569         return 0;
2570 }
2571 
2572 /**
2573  * tsi721_disable_ints - disables all device interrupts
2574  * @priv: pointer to tsi721 private data
2575  */
2576 static void tsi721_disable_ints(struct tsi721_device *priv)
2577 {
2578         int ch;
2579 
2580         /* Disable all device level interrupts */
2581         iowrite32(0, priv->regs + TSI721_DEV_INTE);
2582 
2583         /* Disable all Device Channel interrupts */
2584         iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE);
2585 
2586         /* Disable all Inbound Msg Channel interrupts */
2587         for (ch = 0; ch < TSI721_IMSG_CHNUM; ch++)
2588                 iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch));
2589 
2590         /* Disable all Outbound Msg Channel interrupts */
2591         for (ch = 0; ch < TSI721_OMSG_CHNUM; ch++)
2592                 iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch));
2593 
2594         /* Disable all general messaging interrupts */
2595         iowrite32(0, priv->regs + TSI721_SMSG_INTE);
2596 
2597         /* Disable all BDMA Channel interrupts */
2598         for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)
2599                 iowrite32(0,
2600                         priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE);
2601 
2602         /* Disable all general BDMA interrupts */
2603         iowrite32(0, priv->regs + TSI721_BDMA_INTE);
2604 
2605         /* Disable all SRIO Channel interrupts */
2606         for (ch = 0; ch < TSI721_SRIO_MAXCH; ch++)
2607                 iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch));
2608 
2609         /* Disable all general SR2PC interrupts */
2610         iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE);
2611 
2612         /* Disable all PC2SR interrupts */
2613         iowrite32(0, priv->regs + TSI721_PC2SR_INTE);
2614 
2615         /* Disable all I2C interrupts */
2616         iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE);
2617 
2618         /* Disable SRIO MAC interrupts */
2619         iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE);
2620         iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN);
2621 }
2622 
2623 static struct rio_ops tsi721_rio_ops = {
2624         .lcread                 = tsi721_lcread,
2625         .lcwrite                = tsi721_lcwrite,
2626         .cread                  = tsi721_cread_dma,
2627         .cwrite                 = tsi721_cwrite_dma,
2628         .dsend                  = tsi721_dsend,
2629         .open_inb_mbox          = tsi721_open_inb_mbox,
2630         .close_inb_mbox         = tsi721_close_inb_mbox,
2631         .open_outb_mbox         = tsi721_open_outb_mbox,
2632         .close_outb_mbox        = tsi721_close_outb_mbox,
2633         .add_outb_message       = tsi721_add_outb_message,
2634         .add_inb_buffer         = tsi721_add_inb_buffer,
2635         .get_inb_message        = tsi721_get_inb_message,
2636         .map_inb                = tsi721_rio_map_inb_mem,
2637         .unmap_inb              = tsi721_rio_unmap_inb_mem,
2638         .pwenable               = tsi721_pw_enable,
2639         .query_mport            = tsi721_query_mport,
2640         .map_outb               = tsi721_map_outb_win,
2641         .unmap_outb             = tsi721_unmap_outb_win,
2642 };
2643 
2644 static void tsi721_mport_release(struct device *dev)
2645 {
2646         struct rio_mport *mport = to_rio_mport(dev);
2647 
2648         tsi_debug(EXIT, dev, "%s id=%d", mport->name, mport->id);
2649 }
2650 
2651 /**
2652  * tsi721_setup_mport - Setup Tsi721 as RapidIO subsystem master port
2653  * @priv: pointer to tsi721 private data
2654  *
2655  * Configures Tsi721 as RapidIO master port.
2656  */
2657 static int tsi721_setup_mport(struct tsi721_device *priv)
2658 {
2659         struct pci_dev *pdev = priv->pdev;
2660         int err = 0;
2661         struct rio_mport *mport = &priv->mport;
2662 
2663         err = rio_mport_initialize(mport);
2664         if (err)
2665                 return err;
2666 
2667         mport->ops = &tsi721_rio_ops;
2668         mport->index = 0;
2669         mport->sys_size = 0; /* small system */
2670         mport->priv = (void *)priv;
2671         mport->phys_efptr = 0x100;
2672         mport->phys_rmap = 1;
2673         mport->dev.parent = &pdev->dev;
2674         mport->dev.release = tsi721_mport_release;
2675 
2676         INIT_LIST_HEAD(&mport->dbells);
2677 
2678         rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
2679         rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3);
2680         rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3);
2681         snprintf(mport->name, RIO_MAX_MPORT_NAME, "%s(%s)",
2682                  dev_driver_string(&pdev->dev), dev_name(&pdev->dev));
2683 
2684         /* Hook up interrupt handler */
2685 
2686 #ifdef CONFIG_PCI_MSI
2687         if (!tsi721_enable_msix(priv))
2688                 priv->flags |= TSI721_USING_MSIX;
2689         else if (!pci_enable_msi(pdev))
2690                 priv->flags |= TSI721_USING_MSI;
2691         else
2692                 tsi_debug(MPORT, &pdev->dev,
2693                          "MSI/MSI-X is not available. Using legacy INTx.");
2694 #endif /* CONFIG_PCI_MSI */
2695 
2696         err = tsi721_request_irq(priv);
2697 
2698         if (err) {
2699                 tsi_err(&pdev->dev, "Unable to get PCI IRQ %02X (err=0x%x)",
2700                         pdev->irq, err);
2701                 return err;
2702         }
2703 
2704 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
2705         err = tsi721_register_dma(priv);
2706         if (err)
2707                 goto err_exit;
2708 #endif
2709         /* Enable SRIO link */
2710         iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
2711                   TSI721_DEVCTL_SRBOOT_CMPL,
2712                   priv->regs + TSI721_DEVCTL);
2713 
2714         if (mport->host_deviceid >= 0)
2715                 iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
2716                           RIO_PORT_GEN_DISCOVERED,
2717                           priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2718         else
2719                 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
2720 
2721         err = rio_register_mport(mport);
2722         if (err) {
2723                 tsi721_unregister_dma(priv);
2724                 goto err_exit;
2725         }
2726 
2727         return 0;
2728 
2729 err_exit:
2730         tsi721_free_irq(priv);
2731         return err;
2732 }
2733 
2734 static int tsi721_probe(struct pci_dev *pdev,
2735                                   const struct pci_device_id *id)
2736 {
2737         struct tsi721_device *priv;
2738         int err;
2739 
2740         priv = kzalloc(sizeof(struct tsi721_device), GFP_KERNEL);
2741         if (!priv) {
2742                 err = -ENOMEM;
2743                 goto err_exit;
2744         }
2745 
2746         err = pci_enable_device(pdev);
2747         if (err) {
2748                 tsi_err(&pdev->dev, "Failed to enable PCI device");
2749                 goto err_clean;
2750         }
2751 
2752         priv->pdev = pdev;
2753 
2754 #ifdef DEBUG
2755         {
2756                 int i;
2757 
2758                 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
2759                         tsi_debug(INIT, &pdev->dev, "res%d %pR",
2760                                   i, &pdev->resource[i]);
2761                 }
2762         }
2763 #endif
2764         /*
2765          * Verify BAR configuration
2766          */
2767 
2768         /* BAR_0 (registers) must be 512KB+ in 32-bit address space */
2769         if (!(pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM) ||
2770             pci_resource_flags(pdev, BAR_0) & IORESOURCE_MEM_64 ||
2771             pci_resource_len(pdev, BAR_0) < TSI721_REG_SPACE_SIZE) {
2772                 tsi_err(&pdev->dev, "Missing or misconfigured CSR BAR0");
2773                 err = -ENODEV;
2774                 goto err_disable_pdev;
2775         }
2776 
2777         /* BAR_1 (outbound doorbells) must be 16MB+ in 32-bit address space */
2778         if (!(pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM) ||
2779             pci_resource_flags(pdev, BAR_1) & IORESOURCE_MEM_64 ||
2780             pci_resource_len(pdev, BAR_1) < TSI721_DB_WIN_SIZE) {
2781                 tsi_err(&pdev->dev, "Missing or misconfigured Doorbell BAR1");
2782                 err = -ENODEV;
2783                 goto err_disable_pdev;
2784         }
2785 
2786         /*
2787          * BAR_2 and BAR_4 (outbound translation) must be in 64-bit PCIe address
2788          * space.
2789          * NOTE: BAR_2 and BAR_4 are not used by this version of driver.
2790          * It may be a good idea to keep them disabled using HW configuration
2791          * to save PCI memory space.
2792          */
2793 
2794         priv->p2r_bar[0].size = priv->p2r_bar[1].size = 0;
2795 
2796         if (pci_resource_flags(pdev, BAR_2) & IORESOURCE_MEM_64) {
2797                 if (pci_resource_flags(pdev, BAR_2) & IORESOURCE_PREFETCH)
2798                         tsi_debug(INIT, &pdev->dev,
2799                                  "Prefetchable OBW BAR2 will not be used");
2800                 else {
2801                         priv->p2r_bar[0].base = pci_resource_start(pdev, BAR_2);
2802                         priv->p2r_bar[0].size = pci_resource_len(pdev, BAR_2);
2803                 }
2804         }
2805 
2806         if (pci_resource_flags(pdev, BAR_4) & IORESOURCE_MEM_64) {
2807                 if (pci_resource_flags(pdev, BAR_4) & IORESOURCE_PREFETCH)
2808                         tsi_debug(INIT, &pdev->dev,
2809                                  "Prefetchable OBW BAR4 will not be used");
2810                 else {
2811                         priv->p2r_bar[1].base = pci_resource_start(pdev, BAR_4);
2812                         priv->p2r_bar[1].size = pci_resource_len(pdev, BAR_4);
2813                 }
2814         }
2815 
2816         err = pci_request_regions(pdev, DRV_NAME);
2817         if (err) {
2818                 tsi_err(&pdev->dev, "Unable to obtain PCI resources");
2819                 goto err_disable_pdev;
2820         }
2821 
2822         pci_set_master(pdev);
2823 
2824         priv->regs = pci_ioremap_bar(pdev, BAR_0);
2825         if (!priv->regs) {
2826                 tsi_err(&pdev->dev, "Unable to map device registers space");
2827                 err = -ENOMEM;
2828                 goto err_free_res;
2829         }
2830 
2831         priv->odb_base = pci_ioremap_bar(pdev, BAR_1);
2832         if (!priv->odb_base) {
2833                 tsi_err(&pdev->dev, "Unable to map outbound doorbells space");
2834                 err = -ENOMEM;
2835                 goto err_unmap_bars;
2836         }
2837 
2838         /* Configure DMA attributes. */
2839         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2840                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2841                 if (err) {
2842                         tsi_err(&pdev->dev, "Unable to set DMA mask");
2843                         goto err_unmap_bars;
2844                 }
2845 
2846                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2847                         tsi_info(&pdev->dev, "Unable to set consistent DMA mask");
2848         } else {
2849                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2850                 if (err)
2851                         tsi_info(&pdev->dev, "Unable to set consistent DMA mask");
2852         }
2853 
2854         BUG_ON(!pci_is_pcie(pdev));
2855 
2856         /* Clear "no snoop" and "relaxed ordering" bits. */
2857         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
2858                 PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
2859 
2860         /* Override PCIe Maximum Read Request Size setting if requested */
2861         if (pcie_mrrs >= 0) {
2862                 if (pcie_mrrs <= 5)
2863                         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
2864                                         PCI_EXP_DEVCTL_READRQ, pcie_mrrs << 12);
2865                 else
2866                         tsi_info(&pdev->dev,
2867                                  "Invalid MRRS override value %d", pcie_mrrs);
2868         }
2869 
2870         /* Set PCIe completion timeout to 1-10ms */
2871         pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL2,
2872                                            PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0x2);
2873 
2874         /*
2875          * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
2876          */
2877         pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0x01);
2878         pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXTBL,
2879                                                 TSI721_MSIXTBL_OFFSET);
2880         pci_write_config_dword(pdev, TSI721_PCIECFG_MSIXPBA,
2881                                                 TSI721_MSIXPBA_OFFSET);
2882         pci_write_config_dword(pdev, TSI721_PCIECFG_EPCTL, 0);
2883         /* End of FIXUP */
2884 
2885         tsi721_disable_ints(priv);
2886 
2887         tsi721_init_pc2sr_mapping(priv);
2888         tsi721_init_sr2pc_mapping(priv);
2889 
2890         if (tsi721_bdma_maint_init(priv)) {
2891                 tsi_err(&pdev->dev, "BDMA initialization failed");
2892                 err = -ENOMEM;
2893                 goto err_unmap_bars;
2894         }
2895 
2896         err = tsi721_doorbell_init(priv);
2897         if (err)
2898                 goto err_free_bdma;
2899 
2900         tsi721_port_write_init(priv);
2901 
2902         err = tsi721_messages_init(priv);
2903         if (err)
2904                 goto err_free_consistent;
2905 
2906         err = tsi721_setup_mport(priv);
2907         if (err)
2908                 goto err_free_consistent;
2909 
2910         pci_set_drvdata(pdev, priv);
2911         tsi721_interrupts_init(priv);
2912 
2913         return 0;
2914 
2915 err_free_consistent:
2916         tsi721_port_write_free(priv);
2917         tsi721_doorbell_free(priv);
2918 err_free_bdma:
2919         tsi721_bdma_maint_free(priv);
2920 err_unmap_bars:
2921         if (priv->regs)
2922                 iounmap(priv->regs);
2923         if (priv->odb_base)
2924                 iounmap(priv->odb_base);
2925 err_free_res:
2926         pci_release_regions(pdev);
2927         pci_clear_master(pdev);
2928 err_disable_pdev:
2929         pci_disable_device(pdev);
2930 err_clean:
2931         kfree(priv);
2932 err_exit:
2933         return err;
2934 }
2935 
2936 static void tsi721_remove(struct pci_dev *pdev)
2937 {
2938         struct tsi721_device *priv = pci_get_drvdata(pdev);
2939 
2940         tsi_debug(EXIT, &pdev->dev, "enter");
2941 
2942         tsi721_disable_ints(priv);
2943         tsi721_free_irq(priv);
2944         flush_scheduled_work();
2945         rio_unregister_mport(&priv->mport);
2946 
2947         tsi721_unregister_dma(priv);
2948         tsi721_bdma_maint_free(priv);
2949         tsi721_doorbell_free(priv);
2950         tsi721_port_write_free(priv);
2951         tsi721_close_sr2pc_mapping(priv);
2952 
2953         if (priv->regs)
2954                 iounmap(priv->regs);
2955         if (priv->odb_base)
2956                 iounmap(priv->odb_base);
2957 #ifdef CONFIG_PCI_MSI
2958         if (priv->flags & TSI721_USING_MSIX)
2959                 pci_disable_msix(priv->pdev);
2960         else if (priv->flags & TSI721_USING_MSI)
2961                 pci_disable_msi(priv->pdev);
2962 #endif
2963         pci_release_regions(pdev);
2964         pci_clear_master(pdev);
2965         pci_disable_device(pdev);
2966         pci_set_drvdata(pdev, NULL);
2967         kfree(priv);
2968         tsi_debug(EXIT, &pdev->dev, "exit");
2969 }
2970 
2971 static void tsi721_shutdown(struct pci_dev *pdev)
2972 {
2973         struct tsi721_device *priv = pci_get_drvdata(pdev);
2974 
2975         tsi_debug(EXIT, &pdev->dev, "enter");
2976 
2977         tsi721_disable_ints(priv);
2978         tsi721_dma_stop_all(priv);
2979         pci_clear_master(pdev);
2980         pci_disable_device(pdev);
2981 }
2982 
2983 static const struct pci_device_id tsi721_pci_tbl[] = {
2984         { PCI_DEVICE(PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_TSI721) },
2985         { 0, }  /* terminate list */
2986 };
2987 
2988 MODULE_DEVICE_TABLE(pci, tsi721_pci_tbl);
2989 
2990 static struct pci_driver tsi721_driver = {
2991         .name           = "tsi721",
2992         .id_table       = tsi721_pci_tbl,
2993         .probe          = tsi721_probe,
2994         .remove         = tsi721_remove,
2995         .shutdown       = tsi721_shutdown,
2996 };
2997 
2998 module_pci_driver(tsi721_driver);
2999 
3000 MODULE_DESCRIPTION("IDT Tsi721 PCIExpress-to-SRIO bridge driver");
3001 MODULE_AUTHOR("Integrated Device Technology, Inc.");
3002 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/rapidio/devices/tsi721.c

DEFINITIONS
