1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/bitops.h>
3 #include <linux/serial_core.h>
4 #include <linux/io.h>
5 #include <linux/gpio.h>
6
7 #define SCI_MAJOR 204
8 #define SCI_MINOR_START 8
9
10
11 /*
12 * SCI register subset common for all port types.
13 * Not all registers will exist on all parts.
14 */
15 enum {
16 SCSMR, /* Serial Mode Register */
17 SCBRR, /* Bit Rate Register */
18 SCSCR, /* Serial Control Register */
19 SCxSR, /* Serial Status Register */
20 SCFCR, /* FIFO Control Register */
21 SCFDR, /* FIFO Data Count Register */
22 SCxTDR, /* Transmit (FIFO) Data Register */
23 SCxRDR, /* Receive (FIFO) Data Register */
24 SCLSR, /* Line Status Register */
25 SCTFDR, /* Transmit FIFO Data Count Register */
26 SCRFDR, /* Receive FIFO Data Count Register */
27 SCSPTR, /* Serial Port Register */
28 HSSRR, /* Sampling Rate Register */
29 SCPCR, /* Serial Port Control Register */
30 SCPDR, /* Serial Port Data Register */
31 SCDL, /* BRG Frequency Division Register */
32 SCCKS, /* BRG Clock Select Register */
33 HSRTRGR, /* Rx FIFO Data Count Trigger Register */
34 HSTTRGR, /* Tx FIFO Data Count Trigger Register */
35
36 SCIx_NR_REGS,
37 };
38
39
40 /* SCSMR (Serial Mode Register) */
41 #define SCSMR_C_A BIT(7) /* Communication Mode */
42 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */
43 #define SCSMR_ASYNC 0 /* - Asynchronous mode */
44 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */
45 #define SCSMR_PE BIT(5) /* Parity Enable */
46 #define SCSMR_ODD BIT(4) /* Odd Parity */
47 #define SCSMR_STOP BIT(3) /* Stop Bit Length */
48 #define SCSMR_CKS 0x0003 /* Clock Select */
49
50 /* Serial Mode Register, SCIFA/SCIFB only bits */
51 #define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */
52 #define SCSMR_SRC_MASK 0x0700 /* Sampling Control */
53 #define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */
54 #define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */
55 #define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */
56 #define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */
57 #define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */
58 #define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */
59 #define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */
60 #define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */
61
62 /* Serial Control Register, SCIFA/SCIFB only bits */
63 #define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
64 #define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
65
66 /* Serial Control Register, HSCIF-only bits */
67 #define HSSCR_TOT_SHIFT 14
68
69 /* SCxSR (Serial Status Register) on SCI */
70 #define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
71 #define SCI_RDRF BIT(6) /* Receive Data Register Full */
72 #define SCI_ORER BIT(5) /* Overrun Error */
73 #define SCI_FER BIT(4) /* Framing Error */
74 #define SCI_PER BIT(3) /* Parity Error */
75 #define SCI_TEND BIT(2) /* Transmit End */
76 #define SCI_RESERVED 0x03 /* All reserved bits */
77
78 #define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
79
80 #define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF))
81 #define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
82 #define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
83 #define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
84
85 /* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
86 #define SCIF_ER BIT(7) /* Receive Error */
87 #define SCIF_TEND BIT(6) /* Transmission End */
88 #define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
89 #define SCIF_BRK BIT(4) /* Break Detect */
90 #define SCIF_FER BIT(3) /* Framing Error */
91 #define SCIF_PER BIT(2) /* Parity Error */
92 #define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
93 #define SCIF_DR BIT(0) /* Receive Data Ready */
94 /* SCIF only (optional) */
95 #define SCIF_PERC 0xf000 /* Number of Parity Errors */
96 #define SCIF_FERC 0x0f00 /* Number of Framing Errors */
97 /*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
98 #define SCIFA_ORER BIT(9) /* Overrun Error */
99
100 #define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)
101
102 #define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF))
103 #define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
104 #define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE))
105 #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))
106
107 /* SCFCR (FIFO Control Register) */
108 #define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */
109 #define SCFCR_RTRG0 BIT(6)
110 #define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */
111 #define SCFCR_TTRG0 BIT(4)
112 #define SCFCR_MCE BIT(3) /* Modem Control Enable */
113 #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
114 #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
115 #define SCFCR_LOOP BIT(0) /* Loopback Test */
116
117 /* SCLSR (Line Status Register) on (H)SCIF */
118 #define SCLSR_TO BIT(2) /* Timeout */
119 #define SCLSR_ORER BIT(0) /* Overrun Error */
120
121 /* SCSPTR (Serial Port Register), optional */
122 #define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */
123 #define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */
124 #define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */
125 #define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */
126 #define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */
127 #define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */
128 #define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
129 #define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
130
131 /* HSSRR HSCIF */
132 #define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
133 #define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */
134
135 #define HSCIF_SRHP_SHIFT 8
136 #define HSCIF_SRHP_MASK 0x0f00
137
138 /* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
139 #define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */
140 #define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */
141 #define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */
142 #define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */
143 #define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */
144
145 /* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
146 #define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */
147 #define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */
148 #define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */
149 #define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */
150 #define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */
151
152 /*
153 * BRG Clock Select Register (Some SCIF and HSCIF)
154 * The Baud Rate Generator for external clock can provide a clock source for
155 * the sampling clock. It outputs either its frequency divided clock, or the
156 * (undivided) (H)SCK external clock.
157 */
158 #define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */
159 #define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
160
161 #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
162 #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF)
163 #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
164 #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
165 #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
166 #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
167
168 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)
169
170 #define SCxSR_RDxF_CLEAR(port) \
171 (((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
172 #define SCxSR_ERROR_CLEAR(port) \
173 (to_sci_port(port)->params->error_clear)
174 #define SCxSR_TDxE_CLEAR(port) \
175 (((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
176 #define SCxSR_BREAK_CLEAR(port) \
177 (((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)