This source file includes following definitions.
- sa1100_mctrl_check
- sa1100_timeout
- sa1100_stop_tx
- sa1100_start_tx
- sa1100_stop_rx
- sa1100_enable_ms
- sa1100_rx_chars
- sa1100_tx_chars
- sa1100_int
- sa1100_tx_empty
- sa1100_get_mctrl
- sa1100_set_mctrl
- sa1100_break_ctl
- sa1100_startup
- sa1100_shutdown
- sa1100_set_termios
- sa1100_type
- sa1100_release_port
- sa1100_request_port
- sa1100_config_port
- sa1100_verify_port
- sa1100_init_ports
- sa1100_register_uart_fns
- sa1100_register_uart
- sa1100_console_putchar
- sa1100_console_write
- sa1100_console_get_options
- sa1100_console_setup
- sa1100_rs_console_init
- sa1100_serial_suspend
- sa1100_serial_resume
- sa1100_serial_add_one_port
- sa1100_serial_probe
- sa1100_serial_remove
- sa1100_serial_init
- sa1100_serial_exit
1
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3
4
5
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7
8
9
10 #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
11 #define SUPPORT_SYSRQ
12 #endif
13
14 #include <linux/module.h>
15 #include <linux/ioport.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/platform_data/sa11x0-serial.h>
20 #include <linux/platform_device.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24 #include <linux/serial.h>
25 #include <linux/io.h>
26
27 #include <asm/irq.h>
28 #include <mach/hardware.h>
29 #include <mach/irqs.h>
30
31 #include "serial_mctrl_gpio.h"
32
33
34 #define SERIAL_SA1100_MAJOR 204
35 #define MINOR_START 5
36
37 #define NR_PORTS 3
38
39 #define SA1100_ISR_PASS_LIMIT 256
40
41
42
43
44 #define SM_TO_UTSR0(x) ((x) & 0xff)
45 #define SM_TO_UTSR1(x) ((x) >> 8)
46 #define UTSR0_TO_SM(x) ((x))
47 #define UTSR1_TO_SM(x) ((x) << 8)
48
49 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
50 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
51 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
52 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
53 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
54 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
55 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
56
57 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
58 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
59 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
60 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
61 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
62 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
63 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
64
65
66
67
68 #define UART_PORT_SIZE 0x24
69
70
71
72
73
74
75
76 #define MCTRL_TIMEOUT (250*HZ/1000)
77
78 struct sa1100_port {
79 struct uart_port port;
80 struct timer_list timer;
81 unsigned int old_status;
82 struct mctrl_gpios *gpios;
83 };
84
85
86
87
88 static void sa1100_mctrl_check(struct sa1100_port *sport)
89 {
90 unsigned int status, changed;
91
92 status = sport->port.ops->get_mctrl(&sport->port);
93 changed = status ^ sport->old_status;
94
95 if (changed == 0)
96 return;
97
98 sport->old_status = status;
99
100 if (changed & TIOCM_RI)
101 sport->port.icount.rng++;
102 if (changed & TIOCM_DSR)
103 sport->port.icount.dsr++;
104 if (changed & TIOCM_CAR)
105 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
106 if (changed & TIOCM_CTS)
107 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
108
109 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
110 }
111
112
113
114
115
116 static void sa1100_timeout(struct timer_list *t)
117 {
118 struct sa1100_port *sport = from_timer(sport, t, timer);
119 unsigned long flags;
120
121 if (sport->port.state) {
122 spin_lock_irqsave(&sport->port.lock, flags);
123 sa1100_mctrl_check(sport);
124 spin_unlock_irqrestore(&sport->port.lock, flags);
125
126 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
127 }
128 }
129
130
131
132
133 static void sa1100_stop_tx(struct uart_port *port)
134 {
135 struct sa1100_port *sport =
136 container_of(port, struct sa1100_port, port);
137 u32 utcr3;
138
139 utcr3 = UART_GET_UTCR3(sport);
140 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
141 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
142 }
143
144
145
146
147 static void sa1100_start_tx(struct uart_port *port)
148 {
149 struct sa1100_port *sport =
150 container_of(port, struct sa1100_port, port);
151 u32 utcr3;
152
153 utcr3 = UART_GET_UTCR3(sport);
154 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
155 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
156 }
157
158
159
160
161 static void sa1100_stop_rx(struct uart_port *port)
162 {
163 struct sa1100_port *sport =
164 container_of(port, struct sa1100_port, port);
165 u32 utcr3;
166
167 utcr3 = UART_GET_UTCR3(sport);
168 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
169 }
170
171
172
173
174 static void sa1100_enable_ms(struct uart_port *port)
175 {
176 struct sa1100_port *sport =
177 container_of(port, struct sa1100_port, port);
178
179 mod_timer(&sport->timer, jiffies);
180
181 mctrl_gpio_enable_ms(sport->gpios);
182 }
183
184 static void
185 sa1100_rx_chars(struct sa1100_port *sport)
186 {
187 unsigned int status, ch, flg;
188
189 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
190 UTSR0_TO_SM(UART_GET_UTSR0(sport));
191 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
192 ch = UART_GET_CHAR(sport);
193
194 sport->port.icount.rx++;
195
196 flg = TTY_NORMAL;
197
198
199
200
201
202 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
203 if (status & UTSR1_TO_SM(UTSR1_PRE))
204 sport->port.icount.parity++;
205 else if (status & UTSR1_TO_SM(UTSR1_FRE))
206 sport->port.icount.frame++;
207 if (status & UTSR1_TO_SM(UTSR1_ROR))
208 sport->port.icount.overrun++;
209
210 status &= sport->port.read_status_mask;
211
212 if (status & UTSR1_TO_SM(UTSR1_PRE))
213 flg = TTY_PARITY;
214 else if (status & UTSR1_TO_SM(UTSR1_FRE))
215 flg = TTY_FRAME;
216
217 #ifdef SUPPORT_SYSRQ
218 sport->port.sysrq = 0;
219 #endif
220 }
221
222 if (uart_handle_sysrq_char(&sport->port, ch))
223 goto ignore_char;
224
225 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
226
227 ignore_char:
228 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
229 UTSR0_TO_SM(UART_GET_UTSR0(sport));
230 }
231
232 spin_unlock(&sport->port.lock);
233 tty_flip_buffer_push(&sport->port.state->port);
234 spin_lock(&sport->port.lock);
235 }
236
237 static void sa1100_tx_chars(struct sa1100_port *sport)
238 {
239 struct circ_buf *xmit = &sport->port.state->xmit;
240
241 if (sport->port.x_char) {
242 UART_PUT_CHAR(sport, sport->port.x_char);
243 sport->port.icount.tx++;
244 sport->port.x_char = 0;
245 return;
246 }
247
248
249
250
251
252 sa1100_mctrl_check(sport);
253
254 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
255 sa1100_stop_tx(&sport->port);
256 return;
257 }
258
259
260
261
262
263 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
264 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
265 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
266 sport->port.icount.tx++;
267 if (uart_circ_empty(xmit))
268 break;
269 }
270
271 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
272 uart_write_wakeup(&sport->port);
273
274 if (uart_circ_empty(xmit))
275 sa1100_stop_tx(&sport->port);
276 }
277
278 static irqreturn_t sa1100_int(int irq, void *dev_id)
279 {
280 struct sa1100_port *sport = dev_id;
281 unsigned int status, pass_counter = 0;
282
283 spin_lock(&sport->port.lock);
284 status = UART_GET_UTSR0(sport);
285 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
286 do {
287 if (status & (UTSR0_RFS | UTSR0_RID)) {
288
289 if (status & UTSR0_RID)
290 UART_PUT_UTSR0(sport, UTSR0_RID);
291 sa1100_rx_chars(sport);
292 }
293
294
295 if (status & (UTSR0_RBB | UTSR0_REB))
296 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
297
298 if (status & UTSR0_RBB)
299 sport->port.icount.brk++;
300
301 if (status & UTSR0_REB)
302 uart_handle_break(&sport->port);
303
304 if (status & UTSR0_TFS)
305 sa1100_tx_chars(sport);
306 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
307 break;
308 status = UART_GET_UTSR0(sport);
309 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
310 ~UTSR0_TFS;
311 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
312 spin_unlock(&sport->port.lock);
313
314 return IRQ_HANDLED;
315 }
316
317
318
319
320 static unsigned int sa1100_tx_empty(struct uart_port *port)
321 {
322 struct sa1100_port *sport =
323 container_of(port, struct sa1100_port, port);
324
325 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
326 }
327
328 static unsigned int sa1100_get_mctrl(struct uart_port *port)
329 {
330 struct sa1100_port *sport =
331 container_of(port, struct sa1100_port, port);
332 int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
333
334 mctrl_gpio_get(sport->gpios, &ret);
335
336 return ret;
337 }
338
339 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
340 {
341 struct sa1100_port *sport =
342 container_of(port, struct sa1100_port, port);
343
344 mctrl_gpio_set(sport->gpios, mctrl);
345 }
346
347
348
349
350 static void sa1100_break_ctl(struct uart_port *port, int break_state)
351 {
352 struct sa1100_port *sport =
353 container_of(port, struct sa1100_port, port);
354 unsigned long flags;
355 unsigned int utcr3;
356
357 spin_lock_irqsave(&sport->port.lock, flags);
358 utcr3 = UART_GET_UTCR3(sport);
359 if (break_state == -1)
360 utcr3 |= UTCR3_BRK;
361 else
362 utcr3 &= ~UTCR3_BRK;
363 UART_PUT_UTCR3(sport, utcr3);
364 spin_unlock_irqrestore(&sport->port.lock, flags);
365 }
366
367 static int sa1100_startup(struct uart_port *port)
368 {
369 struct sa1100_port *sport =
370 container_of(port, struct sa1100_port, port);
371 int retval;
372
373
374
375
376 retval = request_irq(sport->port.irq, sa1100_int, 0,
377 "sa11x0-uart", sport);
378 if (retval)
379 return retval;
380
381
382
383
384 UART_PUT_UTSR0(sport, -1);
385 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
386
387
388
389
390 spin_lock_irq(&sport->port.lock);
391 sa1100_enable_ms(&sport->port);
392 spin_unlock_irq(&sport->port.lock);
393
394 return 0;
395 }
396
397 static void sa1100_shutdown(struct uart_port *port)
398 {
399 struct sa1100_port *sport =
400 container_of(port, struct sa1100_port, port);
401
402
403
404
405 del_timer_sync(&sport->timer);
406
407
408
409
410 free_irq(sport->port.irq, sport);
411
412
413
414
415 UART_PUT_UTCR3(sport, 0);
416 }
417
418 static void
419 sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
420 struct ktermios *old)
421 {
422 struct sa1100_port *sport =
423 container_of(port, struct sa1100_port, port);
424 unsigned long flags;
425 unsigned int utcr0, old_utcr3, baud, quot;
426 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
427
428
429
430
431 while ((termios->c_cflag & CSIZE) != CS7 &&
432 (termios->c_cflag & CSIZE) != CS8) {
433 termios->c_cflag &= ~CSIZE;
434 termios->c_cflag |= old_csize;
435 old_csize = CS8;
436 }
437
438 if ((termios->c_cflag & CSIZE) == CS8)
439 utcr0 = UTCR0_DSS;
440 else
441 utcr0 = 0;
442
443 if (termios->c_cflag & CSTOPB)
444 utcr0 |= UTCR0_SBS;
445 if (termios->c_cflag & PARENB) {
446 utcr0 |= UTCR0_PE;
447 if (!(termios->c_cflag & PARODD))
448 utcr0 |= UTCR0_OES;
449 }
450
451
452
453
454 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
455 quot = uart_get_divisor(port, baud);
456
457 spin_lock_irqsave(&sport->port.lock, flags);
458
459 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
460 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
461 if (termios->c_iflag & INPCK)
462 sport->port.read_status_mask |=
463 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
464 if (termios->c_iflag & (BRKINT | PARMRK))
465 sport->port.read_status_mask |=
466 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
467
468
469
470
471 sport->port.ignore_status_mask = 0;
472 if (termios->c_iflag & IGNPAR)
473 sport->port.ignore_status_mask |=
474 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
475 if (termios->c_iflag & IGNBRK) {
476 sport->port.ignore_status_mask |=
477 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
478
479
480
481
482 if (termios->c_iflag & IGNPAR)
483 sport->port.ignore_status_mask |=
484 UTSR1_TO_SM(UTSR1_ROR);
485 }
486
487 del_timer_sync(&sport->timer);
488
489
490
491
492 uart_update_timeout(port, termios->c_cflag, baud);
493
494
495
496
497 old_utcr3 = UART_GET_UTCR3(sport);
498 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
499
500 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
501 barrier();
502
503
504 UART_PUT_UTCR3(sport, 0);
505
506
507 UART_PUT_UTCR0(sport, utcr0);
508
509
510 quot -= 1;
511 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
512 UART_PUT_UTCR2(sport, (quot & 0xff));
513
514 UART_PUT_UTSR0(sport, -1);
515
516 UART_PUT_UTCR3(sport, old_utcr3);
517
518 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
519 sa1100_enable_ms(&sport->port);
520
521 spin_unlock_irqrestore(&sport->port.lock, flags);
522 }
523
524 static const char *sa1100_type(struct uart_port *port)
525 {
526 struct sa1100_port *sport =
527 container_of(port, struct sa1100_port, port);
528
529 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
530 }
531
532
533
534
535 static void sa1100_release_port(struct uart_port *port)
536 {
537 struct sa1100_port *sport =
538 container_of(port, struct sa1100_port, port);
539
540 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
541 }
542
543
544
545
546 static int sa1100_request_port(struct uart_port *port)
547 {
548 struct sa1100_port *sport =
549 container_of(port, struct sa1100_port, port);
550
551 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
552 "sa11x0-uart") != NULL ? 0 : -EBUSY;
553 }
554
555
556
557
558 static void sa1100_config_port(struct uart_port *port, int flags)
559 {
560 struct sa1100_port *sport =
561 container_of(port, struct sa1100_port, port);
562
563 if (flags & UART_CONFIG_TYPE &&
564 sa1100_request_port(&sport->port) == 0)
565 sport->port.type = PORT_SA1100;
566 }
567
568
569
570
571
572
573 static int
574 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
575 {
576 struct sa1100_port *sport =
577 container_of(port, struct sa1100_port, port);
578 int ret = 0;
579
580 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
581 ret = -EINVAL;
582 if (sport->port.irq != ser->irq)
583 ret = -EINVAL;
584 if (ser->io_type != SERIAL_IO_MEM)
585 ret = -EINVAL;
586 if (sport->port.uartclk / 16 != ser->baud_base)
587 ret = -EINVAL;
588 if ((void *)sport->port.mapbase != ser->iomem_base)
589 ret = -EINVAL;
590 if (sport->port.iobase != ser->port)
591 ret = -EINVAL;
592 if (ser->hub6 != 0)
593 ret = -EINVAL;
594 return ret;
595 }
596
597 static struct uart_ops sa1100_pops = {
598 .tx_empty = sa1100_tx_empty,
599 .set_mctrl = sa1100_set_mctrl,
600 .get_mctrl = sa1100_get_mctrl,
601 .stop_tx = sa1100_stop_tx,
602 .start_tx = sa1100_start_tx,
603 .stop_rx = sa1100_stop_rx,
604 .enable_ms = sa1100_enable_ms,
605 .break_ctl = sa1100_break_ctl,
606 .startup = sa1100_startup,
607 .shutdown = sa1100_shutdown,
608 .set_termios = sa1100_set_termios,
609 .type = sa1100_type,
610 .release_port = sa1100_release_port,
611 .request_port = sa1100_request_port,
612 .config_port = sa1100_config_port,
613 .verify_port = sa1100_verify_port,
614 };
615
616 static struct sa1100_port sa1100_ports[NR_PORTS];
617
618
619
620
621
622
623
624
625
626
627
628
629
630 static void __init sa1100_init_ports(void)
631 {
632 static int first = 1;
633 int i;
634
635 if (!first)
636 return;
637 first = 0;
638
639 for (i = 0; i < NR_PORTS; i++) {
640 sa1100_ports[i].port.uartclk = 3686400;
641 sa1100_ports[i].port.ops = &sa1100_pops;
642 sa1100_ports[i].port.fifosize = 8;
643 sa1100_ports[i].port.line = i;
644 sa1100_ports[i].port.iotype = UPIO_MEM;
645 timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0);
646 }
647
648
649
650
651
652 PPDR |= PPC_TXD1 | PPC_TXD3;
653 PPSR |= PPC_TXD1 | PPC_TXD3;
654 }
655
656 void sa1100_register_uart_fns(struct sa1100_port_fns *fns)
657 {
658 if (fns->get_mctrl)
659 sa1100_pops.get_mctrl = fns->get_mctrl;
660 if (fns->set_mctrl)
661 sa1100_pops.set_mctrl = fns->set_mctrl;
662
663 sa1100_pops.pm = fns->pm;
664
665
666
667
668 }
669
670 void __init sa1100_register_uart(int idx, int port)
671 {
672 if (idx >= NR_PORTS) {
673 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
674 return;
675 }
676
677 switch (port) {
678 case 1:
679 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
680 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
681 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
682 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
683 break;
684
685 case 2:
686 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
687 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
688 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
689 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
690 break;
691
692 case 3:
693 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
694 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
695 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
696 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
697 break;
698
699 default:
700 printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
701 }
702 }
703
704
705 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
706 static void sa1100_console_putchar(struct uart_port *port, int ch)
707 {
708 struct sa1100_port *sport =
709 container_of(port, struct sa1100_port, port);
710
711 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
712 barrier();
713 UART_PUT_CHAR(sport, ch);
714 }
715
716
717
718
719 static void
720 sa1100_console_write(struct console *co, const char *s, unsigned int count)
721 {
722 struct sa1100_port *sport = &sa1100_ports[co->index];
723 unsigned int old_utcr3, status;
724
725
726
727
728 old_utcr3 = UART_GET_UTCR3(sport);
729 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
730 UTCR3_TXE);
731
732 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
733
734
735
736
737
738 do {
739 status = UART_GET_UTSR1(sport);
740 } while (status & UTSR1_TBY);
741 UART_PUT_UTCR3(sport, old_utcr3);
742 }
743
744
745
746
747
748 static void __init
749 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
750 int *parity, int *bits)
751 {
752 unsigned int utcr3;
753
754 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
755 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
756
757 unsigned int utcr0, quot;
758
759 utcr0 = UART_GET_UTCR0(sport);
760
761 *parity = 'n';
762 if (utcr0 & UTCR0_PE) {
763 if (utcr0 & UTCR0_OES)
764 *parity = 'e';
765 else
766 *parity = 'o';
767 }
768
769 if (utcr0 & UTCR0_DSS)
770 *bits = 8;
771 else
772 *bits = 7;
773
774 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
775 quot &= 0xfff;
776 *baud = sport->port.uartclk / (16 * (quot + 1));
777 }
778 }
779
780 static int __init
781 sa1100_console_setup(struct console *co, char *options)
782 {
783 struct sa1100_port *sport;
784 int baud = 9600;
785 int bits = 8;
786 int parity = 'n';
787 int flow = 'n';
788
789
790
791
792
793
794 if (co->index == -1 || co->index >= NR_PORTS)
795 co->index = 0;
796 sport = &sa1100_ports[co->index];
797
798 if (options)
799 uart_parse_options(options, &baud, &parity, &bits, &flow);
800 else
801 sa1100_console_get_options(sport, &baud, &parity, &bits);
802
803 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
804 }
805
806 static struct uart_driver sa1100_reg;
807 static struct console sa1100_console = {
808 .name = "ttySA",
809 .write = sa1100_console_write,
810 .device = uart_console_device,
811 .setup = sa1100_console_setup,
812 .flags = CON_PRINTBUFFER,
813 .index = -1,
814 .data = &sa1100_reg,
815 };
816
817 static int __init sa1100_rs_console_init(void)
818 {
819 sa1100_init_ports();
820 register_console(&sa1100_console);
821 return 0;
822 }
823 console_initcall(sa1100_rs_console_init);
824
825 #define SA1100_CONSOLE &sa1100_console
826 #else
827 #define SA1100_CONSOLE NULL
828 #endif
829
830 static struct uart_driver sa1100_reg = {
831 .owner = THIS_MODULE,
832 .driver_name = "ttySA",
833 .dev_name = "ttySA",
834 .major = SERIAL_SA1100_MAJOR,
835 .minor = MINOR_START,
836 .nr = NR_PORTS,
837 .cons = SA1100_CONSOLE,
838 };
839
840 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
841 {
842 struct sa1100_port *sport = platform_get_drvdata(dev);
843
844 if (sport)
845 uart_suspend_port(&sa1100_reg, &sport->port);
846
847 return 0;
848 }
849
850 static int sa1100_serial_resume(struct platform_device *dev)
851 {
852 struct sa1100_port *sport = platform_get_drvdata(dev);
853
854 if (sport)
855 uart_resume_port(&sa1100_reg, &sport->port);
856
857 return 0;
858 }
859
860 static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)
861 {
862 sport->port.dev = &dev->dev;
863
864
865
866
867 sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);
868 if (IS_ERR(sport->gpios)) {
869 int err = PTR_ERR(sport->gpios);
870
871 dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n",
872 err);
873
874 if (err == -EPROBE_DEFER)
875 return err;
876
877 sport->gpios = NULL;
878 }
879
880 platform_set_drvdata(dev, sport);
881
882 return uart_add_one_port(&sa1100_reg, &sport->port);
883 }
884
885 static int sa1100_serial_probe(struct platform_device *dev)
886 {
887 struct resource *res = dev->resource;
888 int i;
889
890 for (i = 0; i < dev->num_resources; i++, res++)
891 if (res->flags & IORESOURCE_MEM)
892 break;
893
894 if (i < dev->num_resources) {
895 for (i = 0; i < NR_PORTS; i++) {
896 if (sa1100_ports[i].port.mapbase != res->start)
897 continue;
898
899 sa1100_serial_add_one_port(&sa1100_ports[i], dev);
900 break;
901 }
902 }
903
904 return 0;
905 }
906
907 static int sa1100_serial_remove(struct platform_device *pdev)
908 {
909 struct sa1100_port *sport = platform_get_drvdata(pdev);
910
911 if (sport)
912 uart_remove_one_port(&sa1100_reg, &sport->port);
913
914 return 0;
915 }
916
917 static struct platform_driver sa11x0_serial_driver = {
918 .probe = sa1100_serial_probe,
919 .remove = sa1100_serial_remove,
920 .suspend = sa1100_serial_suspend,
921 .resume = sa1100_serial_resume,
922 .driver = {
923 .name = "sa11x0-uart",
924 },
925 };
926
927 static int __init sa1100_serial_init(void)
928 {
929 int ret;
930
931 printk(KERN_INFO "Serial: SA11x0 driver\n");
932
933 sa1100_init_ports();
934
935 ret = uart_register_driver(&sa1100_reg);
936 if (ret == 0) {
937 ret = platform_driver_register(&sa11x0_serial_driver);
938 if (ret)
939 uart_unregister_driver(&sa1100_reg);
940 }
941 return ret;
942 }
943
944 static void __exit sa1100_serial_exit(void)
945 {
946 platform_driver_unregister(&sa11x0_serial_driver);
947 uart_unregister_driver(&sa1100_reg);
948 }
949
950 module_init(sa1100_serial_init);
951 module_exit(sa1100_serial_exit);
952
953 MODULE_AUTHOR("Deep Blue Solutions Ltd");
954 MODULE_DESCRIPTION("SA1100 generic serial port driver");
955 MODULE_LICENSE("GPL");
956 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
957 MODULE_ALIAS("platform:sa11x0-uart");