root/drivers/tty/serial/icom.h

INCLUDED FROM

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * icom.h
   4  *
   5  * Copyright (C) 2001 Michael Anderson, IBM Corporation
   6  *
   7  * Serial device driver include file.
   8  */
   9 
  10 #include <linux/serial_core.h>
  11 
  12 #define BAUD_TABLE_LIMIT        ((sizeof(icom_acfg_baud)/sizeof(int)) - 1)
  13 static int icom_acfg_baud[] = {
  14         300,
  15         600,
  16         900,
  17         1200,
  18         1800,
  19         2400,
  20         3600,
  21         4800,
  22         7200,
  23         9600,
  24         14400,
  25         19200,
  26         28800,
  27         38400,
  28         57600,
  29         76800,
  30         115200,
  31         153600,
  32         230400,
  33         307200,
  34         460800,
  35 };
  36 
  37 struct icom_regs {
  38         u32 control;            /* Adapter Control Register     */
  39         u32 interrupt;          /* Adapter Interrupt Register   */
  40         u32 int_mask;           /* Adapter Interrupt Mask Reg   */
  41         u32 int_pri;            /* Adapter Interrupt Priority r */
  42         u32 int_reg_b;          /* Adapter non-masked Interrupt */
  43         u32 resvd01;
  44         u32 resvd02;
  45         u32 resvd03;
  46         u32 control_2;          /* Adapter Control Register 2   */
  47         u32 interrupt_2;        /* Adapter Interrupt Register 2 */
  48         u32 int_mask_2;         /* Adapter Interrupt Mask 2     */
  49         u32 int_pri_2;          /* Adapter Interrupt Prior 2    */
  50         u32 int_reg_2b;         /* Adapter non-masked 2         */
  51 };
  52 
  53 struct func_dram {
  54         u32 reserved[108];      /* 0-1B0   reserved by personality code */
  55         u32 RcvStatusAddr;      /* 1B0-1B3 Status Address for Next rcv */
  56         u8 RcvStnAddr;          /* 1B4     Receive Station Addr */
  57         u8 IdleState;           /* 1B5     Idle State */
  58         u8 IdleMonitor;         /* 1B6     Idle Monitor */
  59         u8 FlagFillIdleTimer;   /* 1B7     Flag Fill Idle Timer */
  60         u32 XmitStatusAddr;     /* 1B8-1BB Transmit Status Address */
  61         u8 StartXmitCmd;        /* 1BC     Start Xmit Command */
  62         u8 HDLCConfigReg;       /* 1BD     Reserved */
  63         u8 CauseCode;           /* 1BE     Cause code for fatal error */
  64         u8 xchar;               /* 1BF     High priority send */
  65         u32 reserved3;          /* 1C0-1C3 Reserved */
  66         u8 PrevCmdReg;          /* 1C4     Reserved */
  67         u8 CmdReg;              /* 1C5     Command Register */
  68         u8 async_config2;       /* 1C6     Async Config Byte 2 */
  69         u8 async_config3;       /* 1C7     Async Config Byte 3 */
  70         u8 dce_resvd[20];       /* 1C8-1DB DCE Rsvd           */
  71         u8 dce_resvd21;         /* 1DC     DCE Rsvd (21st byte */
  72         u8 misc_flags;          /* 1DD     misc flags         */
  73 #define V2_HARDWARE     0x40
  74 #define ICOM_HDW_ACTIVE 0x01
  75         u8 call_length;         /* 1DE     Phone #/CFI buff ln */
  76         u8 call_length2;        /* 1DF     Upper byte (unused) */
  77         u32 call_addr;          /* 1E0-1E3 Phn #/CFI buff addr */
  78         u16 timer_value;        /* 1E4-1E5 general timer value */
  79         u8 timer_command;       /* 1E6     general timer cmd  */
  80         u8 dce_command;         /* 1E7     dce command reg    */
  81         u8 dce_cmd_status;      /* 1E8     dce command stat   */
  82         u8 x21_r1_ioff;         /* 1E9     dce ready counter  */
  83         u8 x21_r0_ioff;         /* 1EA     dce not ready ctr  */
  84         u8 x21_ralt_ioff;       /* 1EB     dce CNR counter    */
  85         u8 x21_r1_ion;          /* 1EC     dce ready I on ctr */
  86         u8 rsvd_ier;            /* 1ED     Rsvd for IER (if ne */
  87         u8 ier;                 /* 1EE     Interrupt Enable   */
  88         u8 isr;                 /* 1EF     Input Signal Reg   */
  89         u8 osr;                 /* 1F0     Output Signal Reg  */
  90         u8 reset;               /* 1F1     Reset/Reload Reg   */
  91         u8 disable;             /* 1F2     Disable Reg        */
  92         u8 sync;                /* 1F3     Sync Reg           */
  93         u8 error_stat;          /* 1F4     Error Status       */
  94         u8 cable_id;            /* 1F5     Cable ID           */
  95         u8 cs_length;           /* 1F6     CS Load Length     */
  96         u8 mac_length;          /* 1F7     Mac Load Length    */
  97         u32 cs_load_addr;       /* 1F8-1FB Call Load PCI Addr */
  98         u32 mac_load_addr;      /* 1FC-1FF Mac Load PCI Addr  */
  99 };
 100 
 101 /*
 102  * adapter defines and structures
 103  */
 104 #define ICOM_CONTROL_START_A         0x00000008
 105 #define ICOM_CONTROL_STOP_A          0x00000004
 106 #define ICOM_CONTROL_START_B         0x00000002
 107 #define ICOM_CONTROL_STOP_B          0x00000001
 108 #define ICOM_CONTROL_START_C         0x00000008
 109 #define ICOM_CONTROL_STOP_C          0x00000004
 110 #define ICOM_CONTROL_START_D         0x00000002
 111 #define ICOM_CONTROL_STOP_D          0x00000001
 112 #define ICOM_IRAM_OFFSET             0x1000
 113 #define ICOM_IRAM_SIZE               0x0C00
 114 #define ICOM_DCE_IRAM_OFFSET         0x0A00
 115 #define ICOM_CABLE_ID_VALID          0x01
 116 #define ICOM_CABLE_ID_MASK           0xF0
 117 #define ICOM_DISABLE                 0x80
 118 #define CMD_XMIT_RCV_ENABLE          0xC0
 119 #define CMD_XMIT_ENABLE              0x40
 120 #define CMD_RCV_DISABLE              0x00
 121 #define CMD_RCV_ENABLE               0x80
 122 #define CMD_RESTART                  0x01
 123 #define CMD_HOLD_XMIT                0x02
 124 #define CMD_SND_BREAK                0x04
 125 #define RS232_CABLE                  0x06
 126 #define V24_CABLE                    0x0E
 127 #define V35_CABLE                    0x0C
 128 #define V36_CABLE                    0x02
 129 #define NO_CABLE                     0x00
 130 #define START_DOWNLOAD               0x80
 131 #define ICOM_INT_MASK_PRC_A          0x00003FFF
 132 #define ICOM_INT_MASK_PRC_B          0x3FFF0000
 133 #define ICOM_INT_MASK_PRC_C          0x00003FFF
 134 #define ICOM_INT_MASK_PRC_D          0x3FFF0000
 135 #define INT_RCV_COMPLETED            0x1000
 136 #define INT_XMIT_COMPLETED           0x2000
 137 #define INT_IDLE_DETECT              0x0800
 138 #define INT_RCV_DISABLED             0x0400
 139 #define INT_XMIT_DISABLED            0x0200
 140 #define INT_RCV_XMIT_SHUTDOWN        0x0100
 141 #define INT_FATAL_ERROR              0x0080
 142 #define INT_CABLE_PULL               0x0020
 143 #define INT_SIGNAL_CHANGE            0x0010
 144 #define HDLC_PPP_PURE_ASYNC          0x02
 145 #define HDLC_FF_FILL                 0x00
 146 #define HDLC_HDW_FLOW                0x01
 147 #define START_XMIT                   0x80
 148 #define ICOM_ACFG_DRIVE1             0x20
 149 #define ICOM_ACFG_NO_PARITY          0x00
 150 #define ICOM_ACFG_PARITY_ENAB        0x02
 151 #define ICOM_ACFG_PARITY_ODD         0x01
 152 #define ICOM_ACFG_8BPC               0x00
 153 #define ICOM_ACFG_7BPC               0x04
 154 #define ICOM_ACFG_6BPC               0x08
 155 #define ICOM_ACFG_5BPC               0x0C
 156 #define ICOM_ACFG_1STOP_BIT          0x00
 157 #define ICOM_ACFG_2STOP_BIT          0x10
 158 #define ICOM_DTR                     0x80
 159 #define ICOM_RTS                     0x40
 160 #define ICOM_RI                      0x08
 161 #define ICOM_DSR                     0x80
 162 #define ICOM_DCD                     0x20
 163 #define ICOM_CTS                     0x40
 164 
 165 #define NUM_XBUFFS 1
 166 #define NUM_RBUFFS 2
 167 #define RCV_BUFF_SZ 0x0200
 168 #define XMIT_BUFF_SZ 0x1000
 169 struct statusArea {
 170     /**********************************************/
 171         /* Transmit Status Area                       */
 172     /**********************************************/
 173         struct xmit_status_area{
 174                 u32 leNext;     /* Next entry in Little Endian on Adapter */
 175                 u32 leNextASD;
 176                 u32 leBuffer;   /* Buffer for entry in LE for Adapter */
 177                 u16 leLengthASD;
 178                 u16 leOffsetASD;
 179                 u16 leLength;   /* Length of data in segment */
 180                 u16 flags;
 181 #define SA_FLAGS_DONE           0x0080  /* Done with Segment */
 182 #define SA_FLAGS_CONTINUED      0x8000  /* More Segments */
 183 #define SA_FLAGS_IDLE           0x4000  /* Mark IDLE after frm */
 184 #define SA_FLAGS_READY_TO_XMIT  0x0800
 185 #define SA_FLAGS_STAT_MASK      0x007F
 186         } xmit[NUM_XBUFFS];
 187 
 188     /**********************************************/
 189         /* Receive Status Area                        */
 190     /**********************************************/
 191         struct {
 192                 u32 leNext;     /* Next entry in Little Endian on Adapter */
 193                 u32 leNextASD;
 194                 u32 leBuffer;   /* Buffer for entry in LE for Adapter */
 195                 u16 WorkingLength;      /* size of segment */
 196                 u16 reserv01;
 197                 u16 leLength;   /* Length of data in segment */
 198                 u16 flags;
 199 #define SA_FL_RCV_DONE           0x0010 /* Data ready */
 200 #define SA_FLAGS_OVERRUN         0x0040
 201 #define SA_FLAGS_PARITY_ERROR    0x0080
 202 #define SA_FLAGS_FRAME_ERROR     0x0001
 203 #define SA_FLAGS_FRAME_TRUNC     0x0002
 204 #define SA_FLAGS_BREAK_DET       0x0004 /* set conditionally by device driver, not hardware */
 205 #define SA_FLAGS_RCV_MASK        0xFFE6
 206         } rcv[NUM_RBUFFS];
 207 };
 208 
 209 struct icom_adapter;
 210 
 211 
 212 #define ICOM_MAJOR       243
 213 #define ICOM_MINOR_START 0
 214 
 215 struct icom_port {
 216         struct uart_port uart_port;
 217         u8 imbed_modem;
 218 #define ICOM_UNKNOWN            1
 219 #define ICOM_RVX                2
 220 #define ICOM_IMBED_MODEM        3
 221         unsigned char cable_id;
 222         unsigned char read_status_mask;
 223         unsigned char ignore_status_mask;
 224         void __iomem * int_reg;
 225         struct icom_regs __iomem *global_reg;
 226         struct func_dram __iomem *dram;
 227         int port;
 228         struct statusArea *statStg;
 229         dma_addr_t statStg_pci;
 230         u32 *xmitRestart;
 231         dma_addr_t xmitRestart_pci;
 232         unsigned char *xmit_buf;
 233         dma_addr_t xmit_buf_pci;
 234         unsigned char *recv_buf;
 235         dma_addr_t recv_buf_pci;
 236         int next_rcv;
 237         int put_length;
 238         int status;
 239 #define ICOM_PORT_ACTIVE        1       /* Port exists. */
 240 #define ICOM_PORT_OFF           0       /* Port does not exist. */
 241         int load_in_progress;
 242         struct icom_adapter *adapter;
 243 };
 244 
 245 struct icom_adapter {
 246         void __iomem * base_addr;
 247         unsigned long base_addr_pci;
 248         struct pci_dev *pci_dev;
 249         struct icom_port port_info[4];
 250         int index;
 251         int version;
 252 #define ADAPTER_V1      0x0001
 253 #define ADAPTER_V2      0x0002
 254         u32 subsystem_id;
 255 #define FOUR_PORT_MODEL                         0x0252
 256 #define V2_TWO_PORTS_RVX                        0x021A
 257 #define V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM      0x0251
 258         int numb_ports;
 259         struct list_head icom_adapter_entry;
 260         struct kref kref;
 261 };
 262 
 263 /* prototype */
 264 extern void iCom_sercons_init(void);
 265 
 266 struct lookup_proc_table {
 267         u32     __iomem *global_control_reg;
 268         unsigned long   processor_id;
 269 };
 270 
 271 struct lookup_int_table {
 272         u32     __iomem *global_int_mask;
 273         unsigned long   processor_id;
 274 };