This source file includes following definitions.
- earlycon_map
- earlycon_init
- parse_options
- register_earlycon
- setup_earlycon
- param_setup_earlycon
- of_setup_earlycon
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11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/console.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/serial_core.h>
18 #include <linux/sizes.h>
19 #include <linux/of.h>
20 #include <linux/of_fdt.h>
21 #include <linux/acpi.h>
22
23 #ifdef CONFIG_FIX_EARLYCON_MEM
24 #include <asm/fixmap.h>
25 #endif
26
27 #include <asm/serial.h>
28
29 static struct console early_con = {
30 .name = "uart",
31 .flags = CON_PRINTBUFFER | CON_BOOT,
32 .index = 0,
33 };
34
35 static struct earlycon_device early_console_dev = {
36 .con = &early_con,
37 };
38
39 static void __iomem * __init earlycon_map(resource_size_t paddr, size_t size)
40 {
41 void __iomem *base;
42 #ifdef CONFIG_FIX_EARLYCON_MEM
43 set_fixmap_io(FIX_EARLYCON_MEM_BASE, paddr & PAGE_MASK);
44 base = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
45 base += paddr & ~PAGE_MASK;
46 #else
47 base = ioremap(paddr, size);
48 #endif
49 if (!base)
50 pr_err("%s: Couldn't map %pa\n", __func__, &paddr);
51
52 return base;
53 }
54
55 static void __init earlycon_init(struct earlycon_device *device,
56 const char *name)
57 {
58 struct console *earlycon = device->con;
59 struct uart_port *port = &device->port;
60 const char *s;
61 size_t len;
62
63
64 for (s = name + strlen(name);
65 s > name && s[-1] >= '0' && s[-1] <= '9';
66 s--)
67 ;
68 if (*s)
69 earlycon->index = simple_strtoul(s, NULL, 10);
70 len = s - name;
71 strlcpy(earlycon->name, name, min(len + 1, sizeof(earlycon->name)));
72 earlycon->data = &early_console_dev;
73
74 if (port->iotype == UPIO_MEM || port->iotype == UPIO_MEM16 ||
75 port->iotype == UPIO_MEM32 || port->iotype == UPIO_MEM32BE)
76 pr_info("%s%d at MMIO%s %pa (options '%s')\n",
77 earlycon->name, earlycon->index,
78 (port->iotype == UPIO_MEM) ? "" :
79 (port->iotype == UPIO_MEM16) ? "16" :
80 (port->iotype == UPIO_MEM32) ? "32" : "32be",
81 &port->mapbase, device->options);
82 else
83 pr_info("%s%d at I/O port 0x%lx (options '%s')\n",
84 earlycon->name, earlycon->index,
85 port->iobase, device->options);
86 }
87
88 static int __init parse_options(struct earlycon_device *device, char *options)
89 {
90 struct uart_port *port = &device->port;
91 int length;
92 resource_size_t addr;
93
94 if (uart_parse_earlycon(options, &port->iotype, &addr, &options))
95 return -EINVAL;
96
97 switch (port->iotype) {
98 case UPIO_MEM:
99 port->mapbase = addr;
100 break;
101 case UPIO_MEM16:
102 port->regshift = 1;
103 port->mapbase = addr;
104 break;
105 case UPIO_MEM32:
106 case UPIO_MEM32BE:
107 port->regshift = 2;
108 port->mapbase = addr;
109 break;
110 case UPIO_PORT:
111 port->iobase = addr;
112 break;
113 default:
114 return -EINVAL;
115 }
116
117 if (options) {
118 device->baud = simple_strtoul(options, NULL, 0);
119 length = min(strcspn(options, " ") + 1,
120 (size_t)(sizeof(device->options)));
121 strlcpy(device->options, options, length);
122 }
123
124 return 0;
125 }
126
127 static int __init register_earlycon(char *buf, const struct earlycon_id *match)
128 {
129 int err;
130 struct uart_port *port = &early_console_dev.port;
131
132
133 if (buf && !parse_options(&early_console_dev, buf))
134 buf = NULL;
135
136 spin_lock_init(&port->lock);
137 port->uartclk = BASE_BAUD * 16;
138 if (port->mapbase)
139 port->membase = earlycon_map(port->mapbase, 64);
140
141 earlycon_init(&early_console_dev, match->name);
142 err = match->setup(&early_console_dev, buf);
143 if (err < 0)
144 return err;
145 if (!early_console_dev.con->write)
146 return -ENODEV;
147
148 register_console(early_console_dev.con);
149 return 0;
150 }
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170 int __init setup_earlycon(char *buf)
171 {
172 const struct earlycon_id **p_match;
173
174 if (!buf || !buf[0])
175 return -EINVAL;
176
177 if (early_con.flags & CON_ENABLED)
178 return -EALREADY;
179
180 for (p_match = __earlycon_table; p_match < __earlycon_table_end;
181 p_match++) {
182 const struct earlycon_id *match = *p_match;
183 size_t len = strlen(match->name);
184
185 if (strncmp(buf, match->name, len))
186 continue;
187
188 if (buf[len]) {
189 if (buf[len] != ',')
190 continue;
191 buf += len + 1;
192 } else
193 buf = NULL;
194
195 return register_earlycon(buf, match);
196 }
197
198 return -ENOENT;
199 }
200
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204
205 bool earlycon_acpi_spcr_enable __initdata;
206
207
208 static int __init param_setup_earlycon(char *buf)
209 {
210 int err;
211
212
213 if (!buf || !buf[0]) {
214 if (IS_ENABLED(CONFIG_ACPI_SPCR_TABLE)) {
215 earlycon_acpi_spcr_enable = true;
216 return 0;
217 } else if (!buf) {
218 return early_init_dt_scan_chosen_stdout();
219 }
220 }
221
222 err = setup_earlycon(buf);
223 if (err == -ENOENT || err == -EALREADY)
224 return 0;
225 return err;
226 }
227 early_param("earlycon", param_setup_earlycon);
228
229 #ifdef CONFIG_OF_EARLY_FLATTREE
230
231 int __init of_setup_earlycon(const struct earlycon_id *match,
232 unsigned long node,
233 const char *options)
234 {
235 int err;
236 struct uart_port *port = &early_console_dev.port;
237 const __be32 *val;
238 bool big_endian;
239 u64 addr;
240
241 spin_lock_init(&port->lock);
242 port->iotype = UPIO_MEM;
243 addr = of_flat_dt_translate_address(node);
244 if (addr == OF_BAD_ADDR) {
245 pr_warn("[%s] bad address\n", match->name);
246 return -ENXIO;
247 }
248 port->mapbase = addr;
249
250 val = of_get_flat_dt_prop(node, "reg-offset", NULL);
251 if (val)
252 port->mapbase += be32_to_cpu(*val);
253 port->membase = earlycon_map(port->mapbase, SZ_4K);
254
255 val = of_get_flat_dt_prop(node, "reg-shift", NULL);
256 if (val)
257 port->regshift = be32_to_cpu(*val);
258 big_endian = of_get_flat_dt_prop(node, "big-endian", NULL) != NULL ||
259 (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) &&
260 of_get_flat_dt_prop(node, "native-endian", NULL) != NULL);
261 val = of_get_flat_dt_prop(node, "reg-io-width", NULL);
262 if (val) {
263 switch (be32_to_cpu(*val)) {
264 case 1:
265 port->iotype = UPIO_MEM;
266 break;
267 case 2:
268 port->iotype = UPIO_MEM16;
269 break;
270 case 4:
271 port->iotype = (big_endian) ? UPIO_MEM32BE : UPIO_MEM32;
272 break;
273 default:
274 pr_warn("[%s] unsupported reg-io-width\n", match->name);
275 return -EINVAL;
276 }
277 }
278
279 val = of_get_flat_dt_prop(node, "current-speed", NULL);
280 if (val)
281 early_console_dev.baud = be32_to_cpu(*val);
282
283 val = of_get_flat_dt_prop(node, "clock-frequency", NULL);
284 if (val)
285 port->uartclk = be32_to_cpu(*val);
286
287 if (options) {
288 early_console_dev.baud = simple_strtoul(options, NULL, 0);
289 strlcpy(early_console_dev.options, options,
290 sizeof(early_console_dev.options));
291 }
292 earlycon_init(&early_console_dev, match->name);
293 err = match->setup(&early_console_dev, options);
294 if (err < 0)
295 return err;
296 if (!early_console_dev.con->write)
297 return -ENODEV;
298
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300 register_console(early_console_dev.con);
301 return 0;
302 }
303
304 #endif