drivers/tty/serial/imx.c

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This source file includes following definitions.
imx_uart_writel
imx_uart_readl
imx_uart_uts_reg
imx_uart_is_imx1
imx_uart_is_imx21
imx_uart_is_imx53
imx_uart_is_imx6q
imx_uart_ucrs_save
imx_uart_ucrs_restore
imx_uart_rts_active
imx_uart_rts_inactive
imx_uart_start_rx
imx_uart_stop_tx
imx_uart_stop_rx
imx_uart_enable_ms
imx_uart_transmit_buffer
imx_uart_dma_tx_callback
imx_uart_dma_tx
imx_uart_start_tx
__imx_uart_rtsint
imx_uart_rtsint
imx_uart_txint
__imx_uart_rxint
imx_uart_rxint
imx_uart_get_hwmctrl
imx_uart_mctrl_check
imx_uart_int
imx_uart_tx_empty
imx_uart_get_mctrl
imx_uart_set_mctrl
imx_uart_break_ctl
imx_uart_timeout
imx_uart_dma_rx_callback
imx_uart_start_rx_dma
imx_uart_clear_rx_errors
imx_uart_setup_ufcr
imx_uart_dma_exit
imx_uart_dma_init
imx_uart_enable_dma
imx_uart_disable_dma
imx_uart_startup
imx_uart_shutdown
imx_uart_flush_buffer
imx_uart_set_termios
imx_uart_type
imx_uart_config_port
imx_uart_verify_port
imx_uart_poll_init
imx_uart_poll_get_char
imx_uart_poll_put_char
imx_uart_rs485_config
imx_uart_console_putchar
imx_uart_console_write
imx_uart_console_get_options
imx_uart_console_setup
imx_uart_console_early_putchar
imx_uart_console_early_write
imx_console_early_setup
imx_uart_probe_dt
imx_uart_probe_dt
imx_uart_probe_pdata
imx_uart_probe
imx_uart_remove
imx_uart_restore_context
imx_uart_save_context
imx_uart_enable_wakeup
imx_uart_suspend_noirq
imx_uart_resume_noirq
imx_uart_suspend
imx_uart_resume
imx_uart_freeze
imx_uart_thaw
imx_uart_init
imx_uart_exit
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Motorola/Freescale IMX serial ports
   4  *
   5  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   6  *
   7  * Author: Sascha Hauer <sascha@saschahauer.de>
   8  * Copyright (C) 2004 Pengutronix
   9  */
  10 
  11 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14 
  15 #include <linux/module.h>
  16 #include <linux/ioport.h>
  17 #include <linux/init.h>
  18 #include <linux/console.h>
  19 #include <linux/sysrq.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/serial.h>
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/rational.h>
  29 #include <linux/slab.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/io.h>
  33 #include <linux/dma-mapping.h>
  34 
  35 #include <asm/irq.h>
  36 #include <linux/platform_data/serial-imx.h>
  37 #include <linux/platform_data/dma-imx.h>
  38 
  39 #include "serial_mctrl_gpio.h"
  40 
  41 /* Register definitions */
  42 #define URXD0 0x0  /* Receiver Register */
  43 #define URTX0 0x40 /* Transmitter Register */
  44 #define UCR1  0x80 /* Control Register 1 */
  45 #define UCR2  0x84 /* Control Register 2 */
  46 #define UCR3  0x88 /* Control Register 3 */
  47 #define UCR4  0x8c /* Control Register 4 */
  48 #define UFCR  0x90 /* FIFO Control Register */
  49 #define USR1  0x94 /* Status Register 1 */
  50 #define USR2  0x98 /* Status Register 2 */
  51 #define UESC  0x9c /* Escape Character Register */
  52 #define UTIM  0xa0 /* Escape Timer Register */
  53 #define UBIR  0xa4 /* BRM Incremental Register */
  54 #define UBMR  0xa8 /* BRM Modulator Register */
  55 #define UBRC  0xac /* Baud Rate Count Register */
  56 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  57 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  58 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  59 
  60 /* UART Control Register Bit Fields.*/
  61 #define URXD_DUMMY_READ (1<<16)
  62 #define URXD_CHARRDY    (1<<15)
  63 #define URXD_ERR        (1<<14)
  64 #define URXD_OVRRUN     (1<<13)
  65 #define URXD_FRMERR     (1<<12)
  66 #define URXD_BRK        (1<<11)
  67 #define URXD_PRERR      (1<<10)
  68 #define URXD_RX_DATA    (0xFF<<0)
  69 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  70 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  71 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  72 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  73 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  74 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  75 #define UCR1_RXDMAEN    (1<<8)  /* Recv ready DMA enable */
  76 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  77 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  78 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  79 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  80 #define UCR1_TXDMAEN    (1<<3)  /* Transmitter ready DMA enable */
  81 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  82 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  83 #define UCR1_DOZE       (1<<1)  /* Doze */
  84 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  85 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  86 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  87 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  88 #define UCR2_CTS        (1<<12) /* Clear to send */
  89 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  90 #define UCR2_PREN       (1<<8)  /* Parity enable */
  91 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
  92 #define UCR2_STPB       (1<<6)  /* Stop */
  93 #define UCR2_WS         (1<<5)  /* Word size */
  94 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
  95 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
  96 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
  97 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
  98 #define UCR2_SRST       (1<<0)  /* SW reset */
  99 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 100 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 101 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 102 #define UCR3_DSR        (1<<10) /* Data set ready */
 103 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 104 #define UCR3_RI         (1<<8)  /* Ring indicator */
 105 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 106 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 107 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 108 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 109 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 110 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 111 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 112 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 113 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 114 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 115 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 116 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 117 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 118 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 119 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 120 #define UCR4_IRSC       (1<<5)  /* IR special case */
 121 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 122 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 123 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 124 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 125 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 126 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 127 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 128 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 129 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 130 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 131 #define USR1_RTSS       (1<<14) /* RTS pin status */
 132 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 133 #define USR1_RTSD       (1<<12) /* RTS delta */
 134 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 135 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 136 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 137 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 138 #define USR1_DTRD       (1<<7)   /* DTR Delta */
 139 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 140 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 141 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 142 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 143 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 144 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 145 #define USR2_IDLE        (1<<12) /* Idle condition */
 146 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 147 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 148 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 149 #define USR2_WAKE        (1<<7)  /* Wake */
 150 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 151 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 152 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 153 #define USR2_BRCD        (1<<2)  /* Break condition */
 154 #define USR2_ORE        (1<<1)   /* Overrun error */
 155 #define USR2_RDR        (1<<0)   /* Recv data ready */
 156 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 157 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 158 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 159 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 160 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 161 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 162 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 163 
 164 /* We've been assigned a range on the "Low-density serial ports" major */
 165 #define SERIAL_IMX_MAJOR        207
 166 #define MINOR_START             16
 167 #define DEV_NAME                "ttymxc"
 168 
 169 /*
 170  * This determines how often we check the modem status signals
 171  * for any change.  They generally aren't connected to an IRQ
 172  * so we have to poll them.  We also check immediately before
 173  * filling the TX fifo incase CTS has been dropped.
 174  */
 175 #define MCTRL_TIMEOUT   (250*HZ/1000)
 176 
 177 #define DRIVER_NAME "IMX-uart"
 178 
 179 #define UART_NR 8
 180 
 181 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 182 enum imx_uart_type {
 183         IMX1_UART,
 184         IMX21_UART,
 185         IMX53_UART,
 186         IMX6Q_UART,
 187 };
 188 
 189 /* device type dependent stuff */
 190 struct imx_uart_data {
 191         unsigned uts_reg;
 192         enum imx_uart_type devtype;
 193 };
 194 
 195 struct imx_port {
 196         struct uart_port        port;
 197         struct timer_list       timer;
 198         unsigned int            old_status;
 199         unsigned int            have_rtscts:1;
 200         unsigned int            have_rtsgpio:1;
 201         unsigned int            dte_mode:1;
 202         struct clk              *clk_ipg;
 203         struct clk              *clk_per;
 204         const struct imx_uart_data *devdata;
 205 
 206         struct mctrl_gpios *gpios;
 207 
 208         /* shadow registers */
 209         unsigned int ucr1;
 210         unsigned int ucr2;
 211         unsigned int ucr3;
 212         unsigned int ucr4;
 213         unsigned int ufcr;
 214 
 215         /* DMA fields */
 216         unsigned int            dma_is_enabled:1;
 217         unsigned int            dma_is_rxing:1;
 218         unsigned int            dma_is_txing:1;
 219         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 220         struct scatterlist      rx_sgl, tx_sgl[2];
 221         void                    *rx_buf;
 222         struct circ_buf         rx_ring;
 223         unsigned int            rx_periods;
 224         dma_cookie_t            rx_cookie;
 225         unsigned int            tx_bytes;
 226         unsigned int            dma_tx_nents;
 227         unsigned int            saved_reg[10];
 228         bool                    context_saved;
 229 };
 230 
 231 struct imx_port_ucrs {
 232         unsigned int    ucr1;
 233         unsigned int    ucr2;
 234         unsigned int    ucr3;
 235 };
 236 
 237 static struct imx_uart_data imx_uart_devdata[] = {
 238         [IMX1_UART] = {
 239                 .uts_reg = IMX1_UTS,
 240                 .devtype = IMX1_UART,
 241         },
 242         [IMX21_UART] = {
 243                 .uts_reg = IMX21_UTS,
 244                 .devtype = IMX21_UART,
 245         },
 246         [IMX53_UART] = {
 247                 .uts_reg = IMX21_UTS,
 248                 .devtype = IMX53_UART,
 249         },
 250         [IMX6Q_UART] = {
 251                 .uts_reg = IMX21_UTS,
 252                 .devtype = IMX6Q_UART,
 253         },
 254 };
 255 
 256 static const struct platform_device_id imx_uart_devtype[] = {
 257         {
 258                 .name = "imx1-uart",
 259                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 260         }, {
 261                 .name = "imx21-uart",
 262                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 263         }, {
 264                 .name = "imx53-uart",
 265                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
 266         }, {
 267                 .name = "imx6q-uart",
 268                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 269         }, {
 270                 /* sentinel */
 271         }
 272 };
 273 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 274 
 275 static const struct of_device_id imx_uart_dt_ids[] = {
 276         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 277         { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
 278         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 279         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 280         { /* sentinel */ }
 281 };
 282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 283 
 284 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
 285 {
 286         switch (offset) {
 287         case UCR1:
 288                 sport->ucr1 = val;
 289                 break;
 290         case UCR2:
 291                 sport->ucr2 = val;
 292                 break;
 293         case UCR3:
 294                 sport->ucr3 = val;
 295                 break;
 296         case UCR4:
 297                 sport->ucr4 = val;
 298                 break;
 299         case UFCR:
 300                 sport->ufcr = val;
 301                 break;
 302         default:
 303                 break;
 304         }
 305         writel(val, sport->port.membase + offset);
 306 }
 307 
 308 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
 309 {
 310         switch (offset) {
 311         case UCR1:
 312                 return sport->ucr1;
 313                 break;
 314         case UCR2:
 315                 /*
 316                  * UCR2_SRST is the only bit in the cached registers that might
 317                  * differ from the value that was last written. As it only
 318                  * automatically becomes one after being cleared, reread
 319                  * conditionally.
 320                  */
 321                 if (!(sport->ucr2 & UCR2_SRST))
 322                         sport->ucr2 = readl(sport->port.membase + offset);
 323                 return sport->ucr2;
 324                 break;
 325         case UCR3:
 326                 return sport->ucr3;
 327                 break;
 328         case UCR4:
 329                 return sport->ucr4;
 330                 break;
 331         case UFCR:
 332                 return sport->ufcr;
 333                 break;
 334         default:
 335                 return readl(sport->port.membase + offset);
 336         }
 337 }
 338 
 339 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
 340 {
 341         return sport->devdata->uts_reg;
 342 }
 343 
 344 static inline int imx_uart_is_imx1(struct imx_port *sport)
 345 {
 346         return sport->devdata->devtype == IMX1_UART;
 347 }
 348 
 349 static inline int imx_uart_is_imx21(struct imx_port *sport)
 350 {
 351         return sport->devdata->devtype == IMX21_UART;
 352 }
 353 
 354 static inline int imx_uart_is_imx53(struct imx_port *sport)
 355 {
 356         return sport->devdata->devtype == IMX53_UART;
 357 }
 358 
 359 static inline int imx_uart_is_imx6q(struct imx_port *sport)
 360 {
 361         return sport->devdata->devtype == IMX6Q_UART;
 362 }
 363 /*
 364  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 365  */
 366 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 367 static void imx_uart_ucrs_save(struct imx_port *sport,
 368                                struct imx_port_ucrs *ucr)
 369 {
 370         /* save control registers */
 371         ucr->ucr1 = imx_uart_readl(sport, UCR1);
 372         ucr->ucr2 = imx_uart_readl(sport, UCR2);
 373         ucr->ucr3 = imx_uart_readl(sport, UCR3);
 374 }
 375 
 376 static void imx_uart_ucrs_restore(struct imx_port *sport,
 377                                   struct imx_port_ucrs *ucr)
 378 {
 379         /* restore control registers */
 380         imx_uart_writel(sport, ucr->ucr1, UCR1);
 381         imx_uart_writel(sport, ucr->ucr2, UCR2);
 382         imx_uart_writel(sport, ucr->ucr3, UCR3);
 383 }
 384 #endif
 385 
 386 /* called with port.lock taken and irqs caller dependent */
 387 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
 388 {
 389         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 390 
 391         sport->port.mctrl |= TIOCM_RTS;
 392         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 393 }
 394 
 395 /* called with port.lock taken and irqs caller dependent */
 396 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
 397 {
 398         *ucr2 &= ~UCR2_CTSC;
 399         *ucr2 |= UCR2_CTS;
 400 
 401         sport->port.mctrl &= ~TIOCM_RTS;
 402         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 403 }
 404 
 405 /* called with port.lock taken and irqs off */
 406 static void imx_uart_start_rx(struct uart_port *port)
 407 {
 408         struct imx_port *sport = (struct imx_port *)port;
 409         unsigned int ucr1, ucr2;
 410 
 411         ucr1 = imx_uart_readl(sport, UCR1);
 412         ucr2 = imx_uart_readl(sport, UCR2);
 413 
 414         ucr2 |= UCR2_RXEN;
 415 
 416         if (sport->dma_is_enabled) {
 417                 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
 418         } else {
 419                 ucr1 |= UCR1_RRDYEN;
 420                 ucr2 |= UCR2_ATEN;
 421         }
 422 
 423         /* Write UCR2 first as it includes RXEN */
 424         imx_uart_writel(sport, ucr2, UCR2);
 425         imx_uart_writel(sport, ucr1, UCR1);
 426 }
 427 
 428 /* called with port.lock taken and irqs off */
 429 static void imx_uart_stop_tx(struct uart_port *port)
 430 {
 431         struct imx_port *sport = (struct imx_port *)port;
 432         u32 ucr1;
 433 
 434         /*
 435          * We are maybe in the SMP context, so if the DMA TX thread is running
 436          * on other cpu, we have to wait for it to finish.
 437          */
 438         if (sport->dma_is_txing)
 439                 return;
 440 
 441         ucr1 = imx_uart_readl(sport, UCR1);
 442         imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
 443 
 444         /* in rs485 mode disable transmitter if shifter is empty */
 445         if (port->rs485.flags & SER_RS485_ENABLED &&
 446             imx_uart_readl(sport, USR2) & USR2_TXDC) {
 447                 u32 ucr2 = imx_uart_readl(sport, UCR2), ucr4;
 448                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 449                         imx_uart_rts_active(sport, &ucr2);
 450                 else
 451                         imx_uart_rts_inactive(sport, &ucr2);
 452                 imx_uart_writel(sport, ucr2, UCR2);
 453 
 454                 imx_uart_start_rx(port);
 455 
 456                 ucr4 = imx_uart_readl(sport, UCR4);
 457                 ucr4 &= ~UCR4_TCEN;
 458                 imx_uart_writel(sport, ucr4, UCR4);
 459         }
 460 }
 461 
 462 /* called with port.lock taken and irqs off */
 463 static void imx_uart_stop_rx(struct uart_port *port)
 464 {
 465         struct imx_port *sport = (struct imx_port *)port;
 466         u32 ucr1, ucr2;
 467 
 468         ucr1 = imx_uart_readl(sport, UCR1);
 469         ucr2 = imx_uart_readl(sport, UCR2);
 470 
 471         if (sport->dma_is_enabled) {
 472                 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
 473         } else {
 474                 ucr1 &= ~UCR1_RRDYEN;
 475                 ucr2 &= ~UCR2_ATEN;
 476         }
 477         imx_uart_writel(sport, ucr1, UCR1);
 478 
 479         ucr2 &= ~UCR2_RXEN;
 480         imx_uart_writel(sport, ucr2, UCR2);
 481 }
 482 
 483 /* called with port.lock taken and irqs off */
 484 static void imx_uart_enable_ms(struct uart_port *port)
 485 {
 486         struct imx_port *sport = (struct imx_port *)port;
 487 
 488         mod_timer(&sport->timer, jiffies);
 489 
 490         mctrl_gpio_enable_ms(sport->gpios);
 491 }
 492 
 493 static void imx_uart_dma_tx(struct imx_port *sport);
 494 
 495 /* called with port.lock taken and irqs off */
 496 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
 497 {
 498         struct circ_buf *xmit = &sport->port.state->xmit;
 499 
 500         if (sport->port.x_char) {
 501                 /* Send next char */
 502                 imx_uart_writel(sport, sport->port.x_char, URTX0);
 503                 sport->port.icount.tx++;
 504                 sport->port.x_char = 0;
 505                 return;
 506         }
 507 
 508         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 509                 imx_uart_stop_tx(&sport->port);
 510                 return;
 511         }
 512 
 513         if (sport->dma_is_enabled) {
 514                 u32 ucr1;
 515                 /*
 516                  * We've just sent a X-char Ensure the TX DMA is enabled
 517                  * and the TX IRQ is disabled.
 518                  **/
 519                 ucr1 = imx_uart_readl(sport, UCR1);
 520                 ucr1 &= ~UCR1_TRDYEN;
 521                 if (sport->dma_is_txing) {
 522                         ucr1 |= UCR1_TXDMAEN;
 523                         imx_uart_writel(sport, ucr1, UCR1);
 524                 } else {
 525                         imx_uart_writel(sport, ucr1, UCR1);
 526                         imx_uart_dma_tx(sport);
 527                 }
 528 
 529                 return;
 530         }
 531 
 532         while (!uart_circ_empty(xmit) &&
 533                !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
 534                 /* send xmit->buf[xmit->tail]
 535                  * out the port here */
 536                 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
 537                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 538                 sport->port.icount.tx++;
 539         }
 540 
 541         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 542                 uart_write_wakeup(&sport->port);
 543 
 544         if (uart_circ_empty(xmit))
 545                 imx_uart_stop_tx(&sport->port);
 546 }
 547 
 548 static void imx_uart_dma_tx_callback(void *data)
 549 {
 550         struct imx_port *sport = data;
 551         struct scatterlist *sgl = &sport->tx_sgl[0];
 552         struct circ_buf *xmit = &sport->port.state->xmit;
 553         unsigned long flags;
 554         u32 ucr1;
 555 
 556         spin_lock_irqsave(&sport->port.lock, flags);
 557 
 558         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 559 
 560         ucr1 = imx_uart_readl(sport, UCR1);
 561         ucr1 &= ~UCR1_TXDMAEN;
 562         imx_uart_writel(sport, ucr1, UCR1);
 563 
 564         /* update the stat */
 565         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 566         sport->port.icount.tx += sport->tx_bytes;
 567 
 568         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 569 
 570         sport->dma_is_txing = 0;
 571 
 572         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 573                 uart_write_wakeup(&sport->port);
 574 
 575         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 576                 imx_uart_dma_tx(sport);
 577         else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
 578                 u32 ucr4 = imx_uart_readl(sport, UCR4);
 579                 ucr4 |= UCR4_TCEN;
 580                 imx_uart_writel(sport, ucr4, UCR4);
 581         }
 582 
 583         spin_unlock_irqrestore(&sport->port.lock, flags);
 584 }
 585 
 586 /* called with port.lock taken and irqs off */
 587 static void imx_uart_dma_tx(struct imx_port *sport)
 588 {
 589         struct circ_buf *xmit = &sport->port.state->xmit;
 590         struct scatterlist *sgl = sport->tx_sgl;
 591         struct dma_async_tx_descriptor *desc;
 592         struct dma_chan *chan = sport->dma_chan_tx;
 593         struct device *dev = sport->port.dev;
 594         u32 ucr1, ucr4;
 595         int ret;
 596 
 597         if (sport->dma_is_txing)
 598                 return;
 599 
 600         ucr4 = imx_uart_readl(sport, UCR4);
 601         ucr4 &= ~UCR4_TCEN;
 602         imx_uart_writel(sport, ucr4, UCR4);
 603 
 604         sport->tx_bytes = uart_circ_chars_pending(xmit);
 605 
 606         if (xmit->tail < xmit->head || xmit->head == 0) {
 607                 sport->dma_tx_nents = 1;
 608                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 609         } else {
 610                 sport->dma_tx_nents = 2;
 611                 sg_init_table(sgl, 2);
 612                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 613                                 UART_XMIT_SIZE - xmit->tail);
 614                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 615         }
 616 
 617         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 618         if (ret == 0) {
 619                 dev_err(dev, "DMA mapping error for TX.\n");
 620                 return;
 621         }
 622         desc = dmaengine_prep_slave_sg(chan, sgl, ret,
 623                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 624         if (!desc) {
 625                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 626                              DMA_TO_DEVICE);
 627                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 628                 return;
 629         }
 630         desc->callback = imx_uart_dma_tx_callback;
 631         desc->callback_param = sport;
 632 
 633         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 634                         uart_circ_chars_pending(xmit));
 635 
 636         ucr1 = imx_uart_readl(sport, UCR1);
 637         ucr1 |= UCR1_TXDMAEN;
 638         imx_uart_writel(sport, ucr1, UCR1);
 639 
 640         /* fire it */
 641         sport->dma_is_txing = 1;
 642         dmaengine_submit(desc);
 643         dma_async_issue_pending(chan);
 644         return;
 645 }
 646 
 647 /* called with port.lock taken and irqs off */
 648 static void imx_uart_start_tx(struct uart_port *port)
 649 {
 650         struct imx_port *sport = (struct imx_port *)port;
 651         u32 ucr1;
 652 
 653         if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
 654                 return;
 655 
 656         if (port->rs485.flags & SER_RS485_ENABLED) {
 657                 u32 ucr2;
 658 
 659                 ucr2 = imx_uart_readl(sport, UCR2);
 660                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 661                         imx_uart_rts_active(sport, &ucr2);
 662                 else
 663                         imx_uart_rts_inactive(sport, &ucr2);
 664                 imx_uart_writel(sport, ucr2, UCR2);
 665 
 666                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 667                         imx_uart_stop_rx(port);
 668 
 669                 /*
 670                  * Enable transmitter and shifter empty irq only if DMA is off.
 671                  * In the DMA case this is done in the tx-callback.
 672                  */
 673                 if (!sport->dma_is_enabled) {
 674                         u32 ucr4 = imx_uart_readl(sport, UCR4);
 675                         ucr4 |= UCR4_TCEN;
 676                         imx_uart_writel(sport, ucr4, UCR4);
 677                 }
 678         }
 679 
 680         if (!sport->dma_is_enabled) {
 681                 ucr1 = imx_uart_readl(sport, UCR1);
 682                 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
 683         }
 684 
 685         if (sport->dma_is_enabled) {
 686                 if (sport->port.x_char) {
 687                         /* We have X-char to send, so enable TX IRQ and
 688                          * disable TX DMA to let TX interrupt to send X-char */
 689                         ucr1 = imx_uart_readl(sport, UCR1);
 690                         ucr1 &= ~UCR1_TXDMAEN;
 691                         ucr1 |= UCR1_TRDYEN;
 692                         imx_uart_writel(sport, ucr1, UCR1);
 693                         return;
 694                 }
 695 
 696                 if (!uart_circ_empty(&port->state->xmit) &&
 697                     !uart_tx_stopped(port))
 698                         imx_uart_dma_tx(sport);
 699                 return;
 700         }
 701 }
 702 
 703 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
 704 {
 705         struct imx_port *sport = dev_id;
 706         u32 usr1;
 707 
 708         imx_uart_writel(sport, USR1_RTSD, USR1);
 709         usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
 710         uart_handle_cts_change(&sport->port, !!usr1);
 711         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 712 
 713         return IRQ_HANDLED;
 714 }
 715 
 716 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
 717 {
 718         struct imx_port *sport = dev_id;
 719         irqreturn_t ret;
 720 
 721         spin_lock(&sport->port.lock);
 722 
 723         ret = __imx_uart_rtsint(irq, dev_id);
 724 
 725         spin_unlock(&sport->port.lock);
 726 
 727         return ret;
 728 }
 729 
 730 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
 731 {
 732         struct imx_port *sport = dev_id;
 733 
 734         spin_lock(&sport->port.lock);
 735         imx_uart_transmit_buffer(sport);
 736         spin_unlock(&sport->port.lock);
 737         return IRQ_HANDLED;
 738 }
 739 
 740 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
 741 {
 742         struct imx_port *sport = dev_id;
 743         unsigned int rx, flg, ignored = 0;
 744         struct tty_port *port = &sport->port.state->port;
 745 
 746         while (imx_uart_readl(sport, USR2) & USR2_RDR) {
 747                 u32 usr2;
 748 
 749                 flg = TTY_NORMAL;
 750                 sport->port.icount.rx++;
 751 
 752                 rx = imx_uart_readl(sport, URXD0);
 753 
 754                 usr2 = imx_uart_readl(sport, USR2);
 755                 if (usr2 & USR2_BRCD) {
 756                         imx_uart_writel(sport, USR2_BRCD, USR2);
 757                         if (uart_handle_break(&sport->port))
 758                                 continue;
 759                 }
 760 
 761                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 762                         continue;
 763 
 764                 if (unlikely(rx & URXD_ERR)) {
 765                         if (rx & URXD_BRK)
 766                                 sport->port.icount.brk++;
 767                         else if (rx & URXD_PRERR)
 768                                 sport->port.icount.parity++;
 769                         else if (rx & URXD_FRMERR)
 770                                 sport->port.icount.frame++;
 771                         if (rx & URXD_OVRRUN)
 772                                 sport->port.icount.overrun++;
 773 
 774                         if (rx & sport->port.ignore_status_mask) {
 775                                 if (++ignored > 100)
 776                                         goto out;
 777                                 continue;
 778                         }
 779 
 780                         rx &= (sport->port.read_status_mask | 0xFF);
 781 
 782                         if (rx & URXD_BRK)
 783                                 flg = TTY_BREAK;
 784                         else if (rx & URXD_PRERR)
 785                                 flg = TTY_PARITY;
 786                         else if (rx & URXD_FRMERR)
 787                                 flg = TTY_FRAME;
 788                         if (rx & URXD_OVRRUN)
 789                                 flg = TTY_OVERRUN;
 790 
 791 #ifdef SUPPORT_SYSRQ
 792                         sport->port.sysrq = 0;
 793 #endif
 794                 }
 795 
 796                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 797                         goto out;
 798 
 799                 if (tty_insert_flip_char(port, rx, flg) == 0)
 800                         sport->port.icount.buf_overrun++;
 801         }
 802 
 803 out:
 804         tty_flip_buffer_push(port);
 805 
 806         return IRQ_HANDLED;
 807 }
 808 
 809 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
 810 {
 811         struct imx_port *sport = dev_id;
 812         irqreturn_t ret;
 813 
 814         spin_lock(&sport->port.lock);
 815 
 816         ret = __imx_uart_rxint(irq, dev_id);
 817 
 818         spin_unlock(&sport->port.lock);
 819 
 820         return ret;
 821 }
 822 
 823 static void imx_uart_clear_rx_errors(struct imx_port *sport);
 824 
 825 /*
 826  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 827  */
 828 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
 829 {
 830         unsigned int tmp = TIOCM_DSR;
 831         unsigned usr1 = imx_uart_readl(sport, USR1);
 832         unsigned usr2 = imx_uart_readl(sport, USR2);
 833 
 834         if (usr1 & USR1_RTSS)
 835                 tmp |= TIOCM_CTS;
 836 
 837         /* in DCE mode DCDIN is always 0 */
 838         if (!(usr2 & USR2_DCDIN))
 839                 tmp |= TIOCM_CAR;
 840 
 841         if (sport->dte_mode)
 842                 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
 843                         tmp |= TIOCM_RI;
 844 
 845         return tmp;
 846 }
 847 
 848 /*
 849  * Handle any change of modem status signal since we were last called.
 850  */
 851 static void imx_uart_mctrl_check(struct imx_port *sport)
 852 {
 853         unsigned int status, changed;
 854 
 855         status = imx_uart_get_hwmctrl(sport);
 856         changed = status ^ sport->old_status;
 857 
 858         if (changed == 0)
 859                 return;
 860 
 861         sport->old_status = status;
 862 
 863         if (changed & TIOCM_RI && status & TIOCM_RI)
 864                 sport->port.icount.rng++;
 865         if (changed & TIOCM_DSR)
 866                 sport->port.icount.dsr++;
 867         if (changed & TIOCM_CAR)
 868                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 869         if (changed & TIOCM_CTS)
 870                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 871 
 872         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 873 }
 874 
 875 static irqreturn_t imx_uart_int(int irq, void *dev_id)
 876 {
 877         struct imx_port *sport = dev_id;
 878         unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
 879         irqreturn_t ret = IRQ_NONE;
 880 
 881         spin_lock(&sport->port.lock);
 882 
 883         usr1 = imx_uart_readl(sport, USR1);
 884         usr2 = imx_uart_readl(sport, USR2);
 885         ucr1 = imx_uart_readl(sport, UCR1);
 886         ucr2 = imx_uart_readl(sport, UCR2);
 887         ucr3 = imx_uart_readl(sport, UCR3);
 888         ucr4 = imx_uart_readl(sport, UCR4);
 889 
 890         /*
 891          * Even if a condition is true that can trigger an irq only handle it if
 892          * the respective irq source is enabled. This prevents some undesired
 893          * actions, for example if a character that sits in the RX FIFO and that
 894          * should be fetched via DMA is tried to be fetched using PIO. Or the
 895          * receiver is currently off and so reading from URXD0 results in an
 896          * exception. So just mask the (raw) status bits for disabled irqs.
 897          */
 898         if ((ucr1 & UCR1_RRDYEN) == 0)
 899                 usr1 &= ~USR1_RRDY;
 900         if ((ucr2 & UCR2_ATEN) == 0)
 901                 usr1 &= ~USR1_AGTIM;
 902         if ((ucr1 & UCR1_TRDYEN) == 0)
 903                 usr1 &= ~USR1_TRDY;
 904         if ((ucr4 & UCR4_TCEN) == 0)
 905                 usr2 &= ~USR2_TXDC;
 906         if ((ucr3 & UCR3_DTRDEN) == 0)
 907                 usr1 &= ~USR1_DTRD;
 908         if ((ucr1 & UCR1_RTSDEN) == 0)
 909                 usr1 &= ~USR1_RTSD;
 910         if ((ucr3 & UCR3_AWAKEN) == 0)
 911                 usr1 &= ~USR1_AWAKE;
 912         if ((ucr4 & UCR4_OREN) == 0)
 913                 usr2 &= ~USR2_ORE;
 914 
 915         if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
 916                 __imx_uart_rxint(irq, dev_id);
 917                 ret = IRQ_HANDLED;
 918         }
 919 
 920         if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
 921                 imx_uart_transmit_buffer(sport);
 922                 ret = IRQ_HANDLED;
 923         }
 924 
 925         if (usr1 & USR1_DTRD) {
 926                 imx_uart_writel(sport, USR1_DTRD, USR1);
 927 
 928                 imx_uart_mctrl_check(sport);
 929 
 930                 ret = IRQ_HANDLED;
 931         }
 932 
 933         if (usr1 & USR1_RTSD) {
 934                 __imx_uart_rtsint(irq, dev_id);
 935                 ret = IRQ_HANDLED;
 936         }
 937 
 938         if (usr1 & USR1_AWAKE) {
 939                 imx_uart_writel(sport, USR1_AWAKE, USR1);
 940                 ret = IRQ_HANDLED;
 941         }
 942 
 943         if (usr2 & USR2_ORE) {
 944                 sport->port.icount.overrun++;
 945                 imx_uart_writel(sport, USR2_ORE, USR2);
 946                 ret = IRQ_HANDLED;
 947         }
 948 
 949         spin_unlock(&sport->port.lock);
 950 
 951         return ret;
 952 }
 953 
 954 /*
 955  * Return TIOCSER_TEMT when transmitter is not busy.
 956  */
 957 static unsigned int imx_uart_tx_empty(struct uart_port *port)
 958 {
 959         struct imx_port *sport = (struct imx_port *)port;
 960         unsigned int ret;
 961 
 962         ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 963 
 964         /* If the TX DMA is working, return 0. */
 965         if (sport->dma_is_txing)
 966                 ret = 0;
 967 
 968         return ret;
 969 }
 970 
 971 /* called with port.lock taken and irqs off */
 972 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
 973 {
 974         struct imx_port *sport = (struct imx_port *)port;
 975         unsigned int ret = imx_uart_get_hwmctrl(sport);
 976 
 977         mctrl_gpio_get(sport->gpios, &ret);
 978 
 979         return ret;
 980 }
 981 
 982 /* called with port.lock taken and irqs off */
 983 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 984 {
 985         struct imx_port *sport = (struct imx_port *)port;
 986         u32 ucr3, uts;
 987 
 988         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 989                 u32 ucr2;
 990 
 991                 /*
 992                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 993                  * setting if RTS is raised.
 994                  */
 995                 ucr2 = imx_uart_readl(sport, UCR2);
 996                 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
 997                 if (mctrl & TIOCM_RTS) {
 998                         ucr2 |= UCR2_CTS;
 999                         /*
1000                          * UCR2_IRTS is unset if and only if the port is
1001                          * configured for CRTSCTS, so we use inverted UCR2_IRTS
1002                          * to get the state to restore to.
1003                          */
1004                         if (!(ucr2 & UCR2_IRTS))
1005                                 ucr2 |= UCR2_CTSC;
1006                 }
1007                 imx_uart_writel(sport, ucr2, UCR2);
1008         }
1009 
1010         ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1011         if (!(mctrl & TIOCM_DTR))
1012                 ucr3 |= UCR3_DSR;
1013         imx_uart_writel(sport, ucr3, UCR3);
1014 
1015         uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1016         if (mctrl & TIOCM_LOOP)
1017                 uts |= UTS_LOOP;
1018         imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1019 
1020         mctrl_gpio_set(sport->gpios, mctrl);
1021 }
1022 
1023 /*
1024  * Interrupts always disabled.
1025  */
1026 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1027 {
1028         struct imx_port *sport = (struct imx_port *)port;
1029         unsigned long flags;
1030         u32 ucr1;
1031 
1032         spin_lock_irqsave(&sport->port.lock, flags);
1033 
1034         ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1035 
1036         if (break_state != 0)
1037                 ucr1 |= UCR1_SNDBRK;
1038 
1039         imx_uart_writel(sport, ucr1, UCR1);
1040 
1041         spin_unlock_irqrestore(&sport->port.lock, flags);
1042 }
1043 
1044 /*
1045  * This is our per-port timeout handler, for checking the
1046  * modem status signals.
1047  */
1048 static void imx_uart_timeout(struct timer_list *t)
1049 {
1050         struct imx_port *sport = from_timer(sport, t, timer);
1051         unsigned long flags;
1052 
1053         if (sport->port.state) {
1054                 spin_lock_irqsave(&sport->port.lock, flags);
1055                 imx_uart_mctrl_check(sport);
1056                 spin_unlock_irqrestore(&sport->port.lock, flags);
1057 
1058                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1059         }
1060 }
1061 
1062 #define RX_BUF_SIZE     (PAGE_SIZE)
1063 
1064 /*
1065  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1066  *   [1] the RX DMA buffer is full.
1067  *   [2] the aging timer expires
1068  *
1069  * Condition [2] is triggered when a character has been sitting in the FIFO
1070  * for at least 8 byte durations.
1071  */
1072 static void imx_uart_dma_rx_callback(void *data)
1073 {
1074         struct imx_port *sport = data;
1075         struct dma_chan *chan = sport->dma_chan_rx;
1076         struct scatterlist *sgl = &sport->rx_sgl;
1077         struct tty_port *port = &sport->port.state->port;
1078         struct dma_tx_state state;
1079         struct circ_buf *rx_ring = &sport->rx_ring;
1080         enum dma_status status;
1081         unsigned int w_bytes = 0;
1082         unsigned int r_bytes;
1083         unsigned int bd_size;
1084 
1085         status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1086 
1087         if (status == DMA_ERROR) {
1088                 imx_uart_clear_rx_errors(sport);
1089                 return;
1090         }
1091 
1092         if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1093 
1094                 /*
1095                  * The state-residue variable represents the empty space
1096                  * relative to the entire buffer. Taking this in consideration
1097                  * the head is always calculated base on the buffer total
1098                  * length - DMA transaction residue. The UART script from the
1099                  * SDMA firmware will jump to the next buffer descriptor,
1100                  * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1101                  * Taking this in consideration the tail is always at the
1102                  * beginning of the buffer descriptor that contains the head.
1103                  */
1104 
1105                 /* Calculate the head */
1106                 rx_ring->head = sg_dma_len(sgl) - state.residue;
1107 
1108                 /* Calculate the tail. */
1109                 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1110                 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1111 
1112                 if (rx_ring->head <= sg_dma_len(sgl) &&
1113                     rx_ring->head > rx_ring->tail) {
1114 
1115                         /* Move data from tail to head */
1116                         r_bytes = rx_ring->head - rx_ring->tail;
1117 
1118                         /* CPU claims ownership of RX DMA buffer */
1119                         dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1120                                 DMA_FROM_DEVICE);
1121 
1122                         w_bytes = tty_insert_flip_string(port,
1123                                 sport->rx_buf + rx_ring->tail, r_bytes);
1124 
1125                         /* UART retrieves ownership of RX DMA buffer */
1126                         dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1127                                 DMA_FROM_DEVICE);
1128 
1129                         if (w_bytes != r_bytes)
1130                                 sport->port.icount.buf_overrun++;
1131 
1132                         sport->port.icount.rx += w_bytes;
1133                 } else  {
1134                         WARN_ON(rx_ring->head > sg_dma_len(sgl));
1135                         WARN_ON(rx_ring->head <= rx_ring->tail);
1136                 }
1137         }
1138 
1139         if (w_bytes) {
1140                 tty_flip_buffer_push(port);
1141                 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1142         }
1143 }
1144 
1145 /* RX DMA buffer periods */
1146 #define RX_DMA_PERIODS 4
1147 
1148 static int imx_uart_start_rx_dma(struct imx_port *sport)
1149 {
1150         struct scatterlist *sgl = &sport->rx_sgl;
1151         struct dma_chan *chan = sport->dma_chan_rx;
1152         struct device *dev = sport->port.dev;
1153         struct dma_async_tx_descriptor *desc;
1154         int ret;
1155 
1156         sport->rx_ring.head = 0;
1157         sport->rx_ring.tail = 0;
1158         sport->rx_periods = RX_DMA_PERIODS;
1159 
1160         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1161         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1162         if (ret == 0) {
1163                 dev_err(dev, "DMA mapping error for RX.\n");
1164                 return -EINVAL;
1165         }
1166 
1167         desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1168                 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1169                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1170 
1171         if (!desc) {
1172                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1173                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1174                 return -EINVAL;
1175         }
1176         desc->callback = imx_uart_dma_rx_callback;
1177         desc->callback_param = sport;
1178 
1179         dev_dbg(dev, "RX: prepare for the DMA.\n");
1180         sport->dma_is_rxing = 1;
1181         sport->rx_cookie = dmaengine_submit(desc);
1182         dma_async_issue_pending(chan);
1183         return 0;
1184 }
1185 
1186 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1187 {
1188         struct tty_port *port = &sport->port.state->port;
1189         u32 usr1, usr2;
1190 
1191         usr1 = imx_uart_readl(sport, USR1);
1192         usr2 = imx_uart_readl(sport, USR2);
1193 
1194         if (usr2 & USR2_BRCD) {
1195                 sport->port.icount.brk++;
1196                 imx_uart_writel(sport, USR2_BRCD, USR2);
1197                 uart_handle_break(&sport->port);
1198                 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1199                         sport->port.icount.buf_overrun++;
1200                 tty_flip_buffer_push(port);
1201         } else {
1202                 if (usr1 & USR1_FRAMERR) {
1203                         sport->port.icount.frame++;
1204                         imx_uart_writel(sport, USR1_FRAMERR, USR1);
1205                 } else if (usr1 & USR1_PARITYERR) {
1206                         sport->port.icount.parity++;
1207                         imx_uart_writel(sport, USR1_PARITYERR, USR1);
1208                 }
1209         }
1210 
1211         if (usr2 & USR2_ORE) {
1212                 sport->port.icount.overrun++;
1213                 imx_uart_writel(sport, USR2_ORE, USR2);
1214         }
1215 
1216 }
1217 
1218 #define TXTL_DEFAULT 2 /* reset default */
1219 #define RXTL_DEFAULT 1 /* reset default */
1220 #define TXTL_DMA 8 /* DMA burst setting */
1221 #define RXTL_DMA 9 /* DMA burst setting */
1222 
1223 static void imx_uart_setup_ufcr(struct imx_port *sport,
1224                                 unsigned char txwl, unsigned char rxwl)
1225 {
1226         unsigned int val;
1227 
1228         /* set receiver / transmitter trigger level */
1229         val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1230         val |= txwl << UFCR_TXTL_SHF | rxwl;
1231         imx_uart_writel(sport, val, UFCR);
1232 }
1233 
1234 static void imx_uart_dma_exit(struct imx_port *sport)
1235 {
1236         if (sport->dma_chan_rx) {
1237                 dmaengine_terminate_sync(sport->dma_chan_rx);
1238                 dma_release_channel(sport->dma_chan_rx);
1239                 sport->dma_chan_rx = NULL;
1240                 sport->rx_cookie = -EINVAL;
1241                 kfree(sport->rx_buf);
1242                 sport->rx_buf = NULL;
1243         }
1244 
1245         if (sport->dma_chan_tx) {
1246                 dmaengine_terminate_sync(sport->dma_chan_tx);
1247                 dma_release_channel(sport->dma_chan_tx);
1248                 sport->dma_chan_tx = NULL;
1249         }
1250 }
1251 
1252 static int imx_uart_dma_init(struct imx_port *sport)
1253 {
1254         struct dma_slave_config slave_config = {};
1255         struct device *dev = sport->port.dev;
1256         int ret;
1257 
1258         /* Prepare for RX : */
1259         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1260         if (!sport->dma_chan_rx) {
1261                 dev_dbg(dev, "cannot get the DMA channel.\n");
1262                 ret = -EINVAL;
1263                 goto err;
1264         }
1265 
1266         slave_config.direction = DMA_DEV_TO_MEM;
1267         slave_config.src_addr = sport->port.mapbase + URXD0;
1268         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1269         /* one byte less than the watermark level to enable the aging timer */
1270         slave_config.src_maxburst = RXTL_DMA - 1;
1271         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1272         if (ret) {
1273                 dev_err(dev, "error in RX dma configuration.\n");
1274                 goto err;
1275         }
1276 
1277         sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1278         if (!sport->rx_buf) {
1279                 ret = -ENOMEM;
1280                 goto err;
1281         }
1282         sport->rx_ring.buf = sport->rx_buf;
1283 
1284         /* Prepare for TX : */
1285         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1286         if (!sport->dma_chan_tx) {
1287                 dev_err(dev, "cannot get the TX DMA channel!\n");
1288                 ret = -EINVAL;
1289                 goto err;
1290         }
1291 
1292         slave_config.direction = DMA_MEM_TO_DEV;
1293         slave_config.dst_addr = sport->port.mapbase + URTX0;
1294         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1295         slave_config.dst_maxburst = TXTL_DMA;
1296         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1297         if (ret) {
1298                 dev_err(dev, "error in TX dma configuration.");
1299                 goto err;
1300         }
1301 
1302         return 0;
1303 err:
1304         imx_uart_dma_exit(sport);
1305         return ret;
1306 }
1307 
1308 static void imx_uart_enable_dma(struct imx_port *sport)
1309 {
1310         u32 ucr1;
1311 
1312         imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1313 
1314         /* set UCR1 */
1315         ucr1 = imx_uart_readl(sport, UCR1);
1316         ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1317         imx_uart_writel(sport, ucr1, UCR1);
1318 
1319         sport->dma_is_enabled = 1;
1320 }
1321 
1322 static void imx_uart_disable_dma(struct imx_port *sport)
1323 {
1324         u32 ucr1;
1325 
1326         /* clear UCR1 */
1327         ucr1 = imx_uart_readl(sport, UCR1);
1328         ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1329         imx_uart_writel(sport, ucr1, UCR1);
1330 
1331         imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1332 
1333         sport->dma_is_enabled = 0;
1334 }
1335 
1336 /* half the RX buffer size */
1337 #define CTSTL 16
1338 
1339 static int imx_uart_startup(struct uart_port *port)
1340 {
1341         struct imx_port *sport = (struct imx_port *)port;
1342         int retval, i;
1343         unsigned long flags;
1344         int dma_is_inited = 0;
1345         u32 ucr1, ucr2, ucr4;
1346 
1347         retval = clk_prepare_enable(sport->clk_per);
1348         if (retval)
1349                 return retval;
1350         retval = clk_prepare_enable(sport->clk_ipg);
1351         if (retval) {
1352                 clk_disable_unprepare(sport->clk_per);
1353                 return retval;
1354         }
1355 
1356         imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1357 
1358         /* disable the DREN bit (Data Ready interrupt enable) before
1359          * requesting IRQs
1360          */
1361         ucr4 = imx_uart_readl(sport, UCR4);
1362 
1363         /* set the trigger level for CTS */
1364         ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1365         ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1366 
1367         imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1368 
1369         /* Can we enable the DMA support? */
1370         if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1371                 dma_is_inited = 1;
1372 
1373         spin_lock_irqsave(&sport->port.lock, flags);
1374         /* Reset fifo's and state machines */
1375         i = 100;
1376 
1377         ucr2 = imx_uart_readl(sport, UCR2);
1378         ucr2 &= ~UCR2_SRST;
1379         imx_uart_writel(sport, ucr2, UCR2);
1380 
1381         while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1382                 udelay(1);
1383 
1384         /*
1385          * Finally, clear and enable interrupts
1386          */
1387         imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1388         imx_uart_writel(sport, USR2_ORE, USR2);
1389 
1390         ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1391         ucr1 |= UCR1_UARTEN;
1392         if (sport->have_rtscts)
1393                 ucr1 |= UCR1_RTSDEN;
1394 
1395         imx_uart_writel(sport, ucr1, UCR1);
1396 
1397         ucr4 = imx_uart_readl(sport, UCR4) & ~UCR4_OREN;
1398         if (!sport->dma_is_enabled)
1399                 ucr4 |= UCR4_OREN;
1400         imx_uart_writel(sport, ucr4, UCR4);
1401 
1402         ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1403         ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1404         if (!sport->have_rtscts)
1405                 ucr2 |= UCR2_IRTS;
1406         /*
1407          * make sure the edge sensitive RTS-irq is disabled,
1408          * we're using RTSD instead.
1409          */
1410         if (!imx_uart_is_imx1(sport))
1411                 ucr2 &= ~UCR2_RTSEN;
1412         imx_uart_writel(sport, ucr2, UCR2);
1413 
1414         if (!imx_uart_is_imx1(sport)) {
1415                 u32 ucr3;
1416 
1417                 ucr3 = imx_uart_readl(sport, UCR3);
1418 
1419                 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1420 
1421                 if (sport->dte_mode)
1422                         /* disable broken interrupts */
1423                         ucr3 &= ~(UCR3_RI | UCR3_DCD);
1424 
1425                 imx_uart_writel(sport, ucr3, UCR3);
1426         }
1427 
1428         /*
1429          * Enable modem status interrupts
1430          */
1431         imx_uart_enable_ms(&sport->port);
1432 
1433         if (dma_is_inited) {
1434                 imx_uart_enable_dma(sport);
1435                 imx_uart_start_rx_dma(sport);
1436         } else {
1437                 ucr1 = imx_uart_readl(sport, UCR1);
1438                 ucr1 |= UCR1_RRDYEN;
1439                 imx_uart_writel(sport, ucr1, UCR1);
1440 
1441                 ucr2 = imx_uart_readl(sport, UCR2);
1442                 ucr2 |= UCR2_ATEN;
1443                 imx_uart_writel(sport, ucr2, UCR2);
1444         }
1445 
1446         spin_unlock_irqrestore(&sport->port.lock, flags);
1447 
1448         return 0;
1449 }
1450 
1451 static void imx_uart_shutdown(struct uart_port *port)
1452 {
1453         struct imx_port *sport = (struct imx_port *)port;
1454         unsigned long flags;
1455         u32 ucr1, ucr2, ucr4;
1456 
1457         if (sport->dma_is_enabled) {
1458                 dmaengine_terminate_sync(sport->dma_chan_tx);
1459                 if (sport->dma_is_txing) {
1460                         dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1461                                      sport->dma_tx_nents, DMA_TO_DEVICE);
1462                         sport->dma_is_txing = 0;
1463                 }
1464                 dmaengine_terminate_sync(sport->dma_chan_rx);
1465                 if (sport->dma_is_rxing) {
1466                         dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1467                                      1, DMA_FROM_DEVICE);
1468                         sport->dma_is_rxing = 0;
1469                 }
1470 
1471                 spin_lock_irqsave(&sport->port.lock, flags);
1472                 imx_uart_stop_tx(port);
1473                 imx_uart_stop_rx(port);
1474                 imx_uart_disable_dma(sport);
1475                 spin_unlock_irqrestore(&sport->port.lock, flags);
1476                 imx_uart_dma_exit(sport);
1477         }
1478 
1479         mctrl_gpio_disable_ms(sport->gpios);
1480 
1481         spin_lock_irqsave(&sport->port.lock, flags);
1482         ucr2 = imx_uart_readl(sport, UCR2);
1483         ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1484         imx_uart_writel(sport, ucr2, UCR2);
1485 
1486         ucr4 = imx_uart_readl(sport, UCR4);
1487         ucr4 &= ~UCR4_OREN;
1488         imx_uart_writel(sport, ucr4, UCR4);
1489         spin_unlock_irqrestore(&sport->port.lock, flags);
1490 
1491         /*
1492          * Stop our timer.
1493          */
1494         del_timer_sync(&sport->timer);
1495 
1496         /*
1497          * Disable all interrupts, port and break condition.
1498          */
1499 
1500         spin_lock_irqsave(&sport->port.lock, flags);
1501         ucr1 = imx_uart_readl(sport, UCR1);
1502         ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1503 
1504         imx_uart_writel(sport, ucr1, UCR1);
1505         spin_unlock_irqrestore(&sport->port.lock, flags);
1506 
1507         clk_disable_unprepare(sport->clk_per);
1508         clk_disable_unprepare(sport->clk_ipg);
1509 }
1510 
1511 /* called with port.lock taken and irqs off */
1512 static void imx_uart_flush_buffer(struct uart_port *port)
1513 {
1514         struct imx_port *sport = (struct imx_port *)port;
1515         struct scatterlist *sgl = &sport->tx_sgl[0];
1516         u32 ucr2;
1517         int i = 100, ubir, ubmr, uts;
1518 
1519         if (!sport->dma_chan_tx)
1520                 return;
1521 
1522         sport->tx_bytes = 0;
1523         dmaengine_terminate_all(sport->dma_chan_tx);
1524         if (sport->dma_is_txing) {
1525                 u32 ucr1;
1526 
1527                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1528                              DMA_TO_DEVICE);
1529                 ucr1 = imx_uart_readl(sport, UCR1);
1530                 ucr1 &= ~UCR1_TXDMAEN;
1531                 imx_uart_writel(sport, ucr1, UCR1);
1532                 sport->dma_is_txing = 0;
1533         }
1534 
1535         /*
1536          * According to the Reference Manual description of the UART SRST bit:
1537          *
1538          * "Reset the transmit and receive state machines,
1539          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1540          * and UTS[6-3]".
1541          *
1542          * We don't need to restore the old values from USR1, USR2, URXD and
1543          * UTXD. UBRC is read only, so only save/restore the other three
1544          * registers.
1545          */
1546         ubir = imx_uart_readl(sport, UBIR);
1547         ubmr = imx_uart_readl(sport, UBMR);
1548         uts = imx_uart_readl(sport, IMX21_UTS);
1549 
1550         ucr2 = imx_uart_readl(sport, UCR2);
1551         ucr2 &= ~UCR2_SRST;
1552         imx_uart_writel(sport, ucr2, UCR2);
1553 
1554         while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1555                 udelay(1);
1556 
1557         /* Restore the registers */
1558         imx_uart_writel(sport, ubir, UBIR);
1559         imx_uart_writel(sport, ubmr, UBMR);
1560         imx_uart_writel(sport, uts, IMX21_UTS);
1561 }
1562 
1563 static void
1564 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1565                      struct ktermios *old)
1566 {
1567         struct imx_port *sport = (struct imx_port *)port;
1568         unsigned long flags;
1569         u32 ucr2, old_ucr2, ufcr;
1570         unsigned int baud, quot;
1571         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1572         unsigned long div;
1573         unsigned long num, denom, old_ubir, old_ubmr;
1574         uint64_t tdiv64;
1575 
1576         /*
1577          * We only support CS7 and CS8.
1578          */
1579         while ((termios->c_cflag & CSIZE) != CS7 &&
1580                (termios->c_cflag & CSIZE) != CS8) {
1581                 termios->c_cflag &= ~CSIZE;
1582                 termios->c_cflag |= old_csize;
1583                 old_csize = CS8;
1584         }
1585 
1586         del_timer_sync(&sport->timer);
1587 
1588         /*
1589          * Ask the core to calculate the divisor for us.
1590          */
1591         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1592         quot = uart_get_divisor(port, baud);
1593 
1594         spin_lock_irqsave(&sport->port.lock, flags);
1595 
1596         /*
1597          * Read current UCR2 and save it for future use, then clear all the bits
1598          * except those we will or may need to preserve.
1599          */
1600         old_ucr2 = imx_uart_readl(sport, UCR2);
1601         ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1602 
1603         ucr2 |= UCR2_SRST | UCR2_IRTS;
1604         if ((termios->c_cflag & CSIZE) == CS8)
1605                 ucr2 |= UCR2_WS;
1606 
1607         if (!sport->have_rtscts)
1608                 termios->c_cflag &= ~CRTSCTS;
1609 
1610         if (port->rs485.flags & SER_RS485_ENABLED) {
1611                 /*
1612                  * RTS is mandatory for rs485 operation, so keep
1613                  * it under manual control and keep transmitter
1614                  * disabled.
1615                  */
1616                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1617                         imx_uart_rts_active(sport, &ucr2);
1618                 else
1619                         imx_uart_rts_inactive(sport, &ucr2);
1620 
1621         } else if (termios->c_cflag & CRTSCTS) {
1622                 /*
1623                  * Only let receiver control RTS output if we were not requested
1624                  * to have RTS inactive (which then should take precedence).
1625                  */
1626                 if (ucr2 & UCR2_CTS)
1627                         ucr2 |= UCR2_CTSC;
1628         }
1629 
1630         if (termios->c_cflag & CRTSCTS)
1631                 ucr2 &= ~UCR2_IRTS;
1632 
1633         if (termios->c_cflag & CSTOPB)
1634                 ucr2 |= UCR2_STPB;
1635         if (termios->c_cflag & PARENB) {
1636                 ucr2 |= UCR2_PREN;
1637                 if (termios->c_cflag & PARODD)
1638                         ucr2 |= UCR2_PROE;
1639         }
1640 
1641         sport->port.read_status_mask = 0;
1642         if (termios->c_iflag & INPCK)
1643                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1644         if (termios->c_iflag & (BRKINT | PARMRK))
1645                 sport->port.read_status_mask |= URXD_BRK;
1646 
1647         /*
1648          * Characters to ignore
1649          */
1650         sport->port.ignore_status_mask = 0;
1651         if (termios->c_iflag & IGNPAR)
1652                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1653         if (termios->c_iflag & IGNBRK) {
1654                 sport->port.ignore_status_mask |= URXD_BRK;
1655                 /*
1656                  * If we're ignoring parity and break indicators,
1657                  * ignore overruns too (for real raw support).
1658                  */
1659                 if (termios->c_iflag & IGNPAR)
1660                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1661         }
1662 
1663         if ((termios->c_cflag & CREAD) == 0)
1664                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1665 
1666         /*
1667          * Update the per-port timeout.
1668          */
1669         uart_update_timeout(port, termios->c_cflag, baud);
1670 
1671         /* custom-baudrate handling */
1672         div = sport->port.uartclk / (baud * 16);
1673         if (baud == 38400 && quot != div)
1674                 baud = sport->port.uartclk / (quot * 16);
1675 
1676         div = sport->port.uartclk / (baud * 16);
1677         if (div > 7)
1678                 div = 7;
1679         if (!div)
1680                 div = 1;
1681 
1682         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1683                 1 << 16, 1 << 16, &num, &denom);
1684 
1685         tdiv64 = sport->port.uartclk;
1686         tdiv64 *= num;
1687         do_div(tdiv64, denom * 16 * div);
1688         tty_termios_encode_baud_rate(termios,
1689                                 (speed_t)tdiv64, (speed_t)tdiv64);
1690 
1691         num -= 1;
1692         denom -= 1;
1693 
1694         ufcr = imx_uart_readl(sport, UFCR);
1695         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1696         imx_uart_writel(sport, ufcr, UFCR);
1697 
1698         /*
1699          *  Two registers below should always be written both and in this
1700          *  particular order. One consequence is that we need to check if any of
1701          *  them changes and then update both. We do need the check for change
1702          *  as even writing the same values seem to "restart"
1703          *  transmission/receiving logic in the hardware, that leads to data
1704          *  breakage even when rate doesn't in fact change. E.g., user switches
1705          *  RTS/CTS handshake and suddenly gets broken bytes.
1706          */
1707         old_ubir = imx_uart_readl(sport, UBIR);
1708         old_ubmr = imx_uart_readl(sport, UBMR);
1709         if (old_ubir != num || old_ubmr != denom) {
1710                 imx_uart_writel(sport, num, UBIR);
1711                 imx_uart_writel(sport, denom, UBMR);
1712         }
1713 
1714         if (!imx_uart_is_imx1(sport))
1715                 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1716                                 IMX21_ONEMS);
1717 
1718         imx_uart_writel(sport, ucr2, UCR2);
1719 
1720         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1721                 imx_uart_enable_ms(&sport->port);
1722 
1723         spin_unlock_irqrestore(&sport->port.lock, flags);
1724 }
1725 
1726 static const char *imx_uart_type(struct uart_port *port)
1727 {
1728         struct imx_port *sport = (struct imx_port *)port;
1729 
1730         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1731 }
1732 
1733 /*
1734  * Configure/autoconfigure the port.
1735  */
1736 static void imx_uart_config_port(struct uart_port *port, int flags)
1737 {
1738         struct imx_port *sport = (struct imx_port *)port;
1739 
1740         if (flags & UART_CONFIG_TYPE)
1741                 sport->port.type = PORT_IMX;
1742 }
1743 
1744 /*
1745  * Verify the new serial_struct (for TIOCSSERIAL).
1746  * The only change we allow are to the flags and type, and
1747  * even then only between PORT_IMX and PORT_UNKNOWN
1748  */
1749 static int
1750 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1751 {
1752         struct imx_port *sport = (struct imx_port *)port;
1753         int ret = 0;
1754 
1755         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1756                 ret = -EINVAL;
1757         if (sport->port.irq != ser->irq)
1758                 ret = -EINVAL;
1759         if (ser->io_type != UPIO_MEM)
1760                 ret = -EINVAL;
1761         if (sport->port.uartclk / 16 != ser->baud_base)
1762                 ret = -EINVAL;
1763         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1764                 ret = -EINVAL;
1765         if (sport->port.iobase != ser->port)
1766                 ret = -EINVAL;
1767         if (ser->hub6 != 0)
1768                 ret = -EINVAL;
1769         return ret;
1770 }
1771 
1772 #if defined(CONFIG_CONSOLE_POLL)
1773 
1774 static int imx_uart_poll_init(struct uart_port *port)
1775 {
1776         struct imx_port *sport = (struct imx_port *)port;
1777         unsigned long flags;
1778         u32 ucr1, ucr2;
1779         int retval;
1780 
1781         retval = clk_prepare_enable(sport->clk_ipg);
1782         if (retval)
1783                 return retval;
1784         retval = clk_prepare_enable(sport->clk_per);
1785         if (retval)
1786                 clk_disable_unprepare(sport->clk_ipg);
1787 
1788         imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1789 
1790         spin_lock_irqsave(&sport->port.lock, flags);
1791 
1792         /*
1793          * Be careful about the order of enabling bits here. First enable the
1794          * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1795          * This prevents that a character that already sits in the RX fifo is
1796          * triggering an irq but the try to fetch it from there results in an
1797          * exception because UARTEN or RXEN is still off.
1798          */
1799         ucr1 = imx_uart_readl(sport, UCR1);
1800         ucr2 = imx_uart_readl(sport, UCR2);
1801 
1802         if (imx_uart_is_imx1(sport))
1803                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1804 
1805         ucr1 |= UCR1_UARTEN;
1806         ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1807 
1808         ucr2 |= UCR2_RXEN;
1809         ucr2 &= ~UCR2_ATEN;
1810 
1811         imx_uart_writel(sport, ucr1, UCR1);
1812         imx_uart_writel(sport, ucr2, UCR2);
1813 
1814         /* now enable irqs */
1815         imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1816         imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1817 
1818         spin_unlock_irqrestore(&sport->port.lock, flags);
1819 
1820         return 0;
1821 }
1822 
1823 static int imx_uart_poll_get_char(struct uart_port *port)
1824 {
1825         struct imx_port *sport = (struct imx_port *)port;
1826         if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1827                 return NO_POLL_CHAR;
1828 
1829         return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1830 }
1831 
1832 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1833 {
1834         struct imx_port *sport = (struct imx_port *)port;
1835         unsigned int status;
1836 
1837         /* drain */
1838         do {
1839                 status = imx_uart_readl(sport, USR1);
1840         } while (~status & USR1_TRDY);
1841 
1842         /* write */
1843         imx_uart_writel(sport, c, URTX0);
1844 
1845         /* flush */
1846         do {
1847                 status = imx_uart_readl(sport, USR2);
1848         } while (~status & USR2_TXDC);
1849 }
1850 #endif
1851 
1852 /* called with port.lock taken and irqs off or from .probe without locking */
1853 static int imx_uart_rs485_config(struct uart_port *port,
1854                                  struct serial_rs485 *rs485conf)
1855 {
1856         struct imx_port *sport = (struct imx_port *)port;
1857         u32 ucr2;
1858 
1859         /* unimplemented */
1860         rs485conf->delay_rts_before_send = 0;
1861         rs485conf->delay_rts_after_send = 0;
1862 
1863         /* RTS is required to control the transmitter */
1864         if (!sport->have_rtscts && !sport->have_rtsgpio)
1865                 rs485conf->flags &= ~SER_RS485_ENABLED;
1866 
1867         if (rs485conf->flags & SER_RS485_ENABLED) {
1868                 /* Enable receiver if low-active RTS signal is requested */
1869                 if (sport->have_rtscts &&  !sport->have_rtsgpio &&
1870                     !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1871                         rs485conf->flags |= SER_RS485_RX_DURING_TX;
1872 
1873                 /* disable transmitter */
1874                 ucr2 = imx_uart_readl(sport, UCR2);
1875                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1876                         imx_uart_rts_active(sport, &ucr2);
1877                 else
1878                         imx_uart_rts_inactive(sport, &ucr2);
1879                 imx_uart_writel(sport, ucr2, UCR2);
1880         }
1881 
1882         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1883         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1884             rs485conf->flags & SER_RS485_RX_DURING_TX)
1885                 imx_uart_start_rx(port);
1886 
1887         port->rs485 = *rs485conf;
1888 
1889         return 0;
1890 }
1891 
1892 static const struct uart_ops imx_uart_pops = {
1893         .tx_empty       = imx_uart_tx_empty,
1894         .set_mctrl      = imx_uart_set_mctrl,
1895         .get_mctrl      = imx_uart_get_mctrl,
1896         .stop_tx        = imx_uart_stop_tx,
1897         .start_tx       = imx_uart_start_tx,
1898         .stop_rx        = imx_uart_stop_rx,
1899         .enable_ms      = imx_uart_enable_ms,
1900         .break_ctl      = imx_uart_break_ctl,
1901         .startup        = imx_uart_startup,
1902         .shutdown       = imx_uart_shutdown,
1903         .flush_buffer   = imx_uart_flush_buffer,
1904         .set_termios    = imx_uart_set_termios,
1905         .type           = imx_uart_type,
1906         .config_port    = imx_uart_config_port,
1907         .verify_port    = imx_uart_verify_port,
1908 #if defined(CONFIG_CONSOLE_POLL)
1909         .poll_init      = imx_uart_poll_init,
1910         .poll_get_char  = imx_uart_poll_get_char,
1911         .poll_put_char  = imx_uart_poll_put_char,
1912 #endif
1913 };
1914 
1915 static struct imx_port *imx_uart_ports[UART_NR];
1916 
1917 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1918 static void imx_uart_console_putchar(struct uart_port *port, int ch)
1919 {
1920         struct imx_port *sport = (struct imx_port *)port;
1921 
1922         while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1923                 barrier();
1924 
1925         imx_uart_writel(sport, ch, URTX0);
1926 }
1927 
1928 /*
1929  * Interrupts are disabled on entering
1930  */
1931 static void
1932 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1933 {
1934         struct imx_port *sport = imx_uart_ports[co->index];
1935         struct imx_port_ucrs old_ucr;
1936         unsigned int ucr1;
1937         unsigned long flags = 0;
1938         int locked = 1;
1939         int retval;
1940 
1941         retval = clk_enable(sport->clk_per);
1942         if (retval)
1943                 return;
1944         retval = clk_enable(sport->clk_ipg);
1945         if (retval) {
1946                 clk_disable(sport->clk_per);
1947                 return;
1948         }
1949 
1950         if (sport->port.sysrq)
1951                 locked = 0;
1952         else if (oops_in_progress)
1953                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1954         else
1955                 spin_lock_irqsave(&sport->port.lock, flags);
1956 
1957         /*
1958          *      First, save UCR1/2/3 and then disable interrupts
1959          */
1960         imx_uart_ucrs_save(sport, &old_ucr);
1961         ucr1 = old_ucr.ucr1;
1962 
1963         if (imx_uart_is_imx1(sport))
1964                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1965         ucr1 |= UCR1_UARTEN;
1966         ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1967 
1968         imx_uart_writel(sport, ucr1, UCR1);
1969 
1970         imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
1971 
1972         uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
1973 
1974         /*
1975          *      Finally, wait for transmitter to become empty
1976          *      and restore UCR1/2/3
1977          */
1978         while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
1979 
1980         imx_uart_ucrs_restore(sport, &old_ucr);
1981 
1982         if (locked)
1983                 spin_unlock_irqrestore(&sport->port.lock, flags);
1984 
1985         clk_disable(sport->clk_ipg);
1986         clk_disable(sport->clk_per);
1987 }
1988 
1989 /*
1990  * If the port was already initialised (eg, by a boot loader),
1991  * try to determine the current setup.
1992  */
1993 static void __init
1994 imx_uart_console_get_options(struct imx_port *sport, int *baud,
1995                              int *parity, int *bits)
1996 {
1997 
1998         if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
1999                 /* ok, the port was enabled */
2000                 unsigned int ucr2, ubir, ubmr, uartclk;
2001                 unsigned int baud_raw;
2002                 unsigned int ucfr_rfdiv;
2003 
2004                 ucr2 = imx_uart_readl(sport, UCR2);
2005 
2006                 *parity = 'n';
2007                 if (ucr2 & UCR2_PREN) {
2008                         if (ucr2 & UCR2_PROE)
2009                                 *parity = 'o';
2010                         else
2011                                 *parity = 'e';
2012                 }
2013 
2014                 if (ucr2 & UCR2_WS)
2015                         *bits = 8;
2016                 else
2017                         *bits = 7;
2018 
2019                 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2020                 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2021 
2022                 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2023                 if (ucfr_rfdiv == 6)
2024                         ucfr_rfdiv = 7;
2025                 else
2026                         ucfr_rfdiv = 6 - ucfr_rfdiv;
2027 
2028                 uartclk = clk_get_rate(sport->clk_per);
2029                 uartclk /= ucfr_rfdiv;
2030 
2031                 {       /*
2032                          * The next code provides exact computation of
2033                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2034                          * without need of float support or long long division,
2035                          * which would be required to prevent 32bit arithmetic overflow
2036                          */
2037                         unsigned int mul = ubir + 1;
2038                         unsigned int div = 16 * (ubmr + 1);
2039                         unsigned int rem = uartclk % div;
2040 
2041                         baud_raw = (uartclk / div) * mul;
2042                         baud_raw += (rem * mul + div / 2) / div;
2043                         *baud = (baud_raw + 50) / 100 * 100;
2044                 }
2045 
2046                 if (*baud != baud_raw)
2047                         dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2048                                 baud_raw, *baud);
2049         }
2050 }
2051 
2052 static int __init
2053 imx_uart_console_setup(struct console *co, char *options)
2054 {
2055         struct imx_port *sport;
2056         int baud = 9600;
2057         int bits = 8;
2058         int parity = 'n';
2059         int flow = 'n';
2060         int retval;
2061 
2062         /*
2063          * Check whether an invalid uart number has been specified, and
2064          * if so, search for the first available port that does have
2065          * console support.
2066          */
2067         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2068                 co->index = 0;
2069         sport = imx_uart_ports[co->index];
2070         if (sport == NULL)
2071                 return -ENODEV;
2072 
2073         /* For setting the registers, we only need to enable the ipg clock. */
2074         retval = clk_prepare_enable(sport->clk_ipg);
2075         if (retval)
2076                 goto error_console;
2077 
2078         if (options)
2079                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2080         else
2081                 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2082 
2083         imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2084 
2085         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2086 
2087         clk_disable(sport->clk_ipg);
2088         if (retval) {
2089                 clk_unprepare(sport->clk_ipg);
2090                 goto error_console;
2091         }
2092 
2093         retval = clk_prepare(sport->clk_per);
2094         if (retval)
2095                 clk_unprepare(sport->clk_ipg);
2096 
2097 error_console:
2098         return retval;
2099 }
2100 
2101 static struct uart_driver imx_uart_uart_driver;
2102 static struct console imx_uart_console = {
2103         .name           = DEV_NAME,
2104         .write          = imx_uart_console_write,
2105         .device         = uart_console_device,
2106         .setup          = imx_uart_console_setup,
2107         .flags          = CON_PRINTBUFFER,
2108         .index          = -1,
2109         .data           = &imx_uart_uart_driver,
2110 };
2111 
2112 #define IMX_CONSOLE     &imx_uart_console
2113 
2114 #ifdef CONFIG_OF
2115 static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
2116 {
2117         struct imx_port *sport = (struct imx_port *)port;
2118 
2119         while (imx_uart_readl(sport, IMX21_UTS) & UTS_TXFULL)
2120                 cpu_relax();
2121 
2122         imx_uart_writel(sport, ch, URTX0);
2123 }
2124 
2125 static void imx_uart_console_early_write(struct console *con, const char *s,
2126                                          unsigned count)
2127 {
2128         struct earlycon_device *dev = con->data;
2129 
2130         uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
2131 }
2132 
2133 static int __init
2134 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2135 {
2136         if (!dev->port.membase)
2137                 return -ENODEV;
2138 
2139         dev->con->write = imx_uart_console_early_write;
2140 
2141         return 0;
2142 }
2143 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2144 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2145 #endif
2146 
2147 #else
2148 #define IMX_CONSOLE     NULL
2149 #endif
2150 
2151 static struct uart_driver imx_uart_uart_driver = {
2152         .owner          = THIS_MODULE,
2153         .driver_name    = DRIVER_NAME,
2154         .dev_name       = DEV_NAME,
2155         .major          = SERIAL_IMX_MAJOR,
2156         .minor          = MINOR_START,
2157         .nr             = ARRAY_SIZE(imx_uart_ports),
2158         .cons           = IMX_CONSOLE,
2159 };
2160 
2161 #ifdef CONFIG_OF
2162 /*
2163  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2164  * could successfully get all information from dt or a negative errno.
2165  */
2166 static int imx_uart_probe_dt(struct imx_port *sport,
2167                              struct platform_device *pdev)
2168 {
2169         struct device_node *np = pdev->dev.of_node;
2170         int ret;
2171 
2172         sport->devdata = of_device_get_match_data(&pdev->dev);
2173         if (!sport->devdata)
2174                 /* no device tree device */
2175                 return 1;
2176 
2177         ret = of_alias_get_id(np, "serial");
2178         if (ret < 0) {
2179                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2180                 return ret;
2181         }
2182         sport->port.line = ret;
2183 
2184         if (of_get_property(np, "uart-has-rtscts", NULL) ||
2185             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2186                 sport->have_rtscts = 1;
2187 
2188         if (of_get_property(np, "fsl,dte-mode", NULL))
2189                 sport->dte_mode = 1;
2190 
2191         if (of_get_property(np, "rts-gpios", NULL))
2192                 sport->have_rtsgpio = 1;
2193 
2194         return 0;
2195 }
2196 #else
2197 static inline int imx_uart_probe_dt(struct imx_port *sport,
2198                                     struct platform_device *pdev)
2199 {
2200         return 1;
2201 }
2202 #endif
2203 
2204 static void imx_uart_probe_pdata(struct imx_port *sport,
2205                                  struct platform_device *pdev)
2206 {
2207         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2208 
2209         sport->port.line = pdev->id;
2210         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2211 
2212         if (!pdata)
2213                 return;
2214 
2215         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2216                 sport->have_rtscts = 1;
2217 }
2218 
2219 static int imx_uart_probe(struct platform_device *pdev)
2220 {
2221         struct imx_port *sport;
2222         void __iomem *base;
2223         int ret = 0;
2224         u32 ucr1;
2225         struct resource *res;
2226         int txirq, rxirq, rtsirq;
2227 
2228         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2229         if (!sport)
2230                 return -ENOMEM;
2231 
2232         ret = imx_uart_probe_dt(sport, pdev);
2233         if (ret > 0)
2234                 imx_uart_probe_pdata(sport, pdev);
2235         else if (ret < 0)
2236                 return ret;
2237 
2238         if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2239                 dev_err(&pdev->dev, "serial%d out of range\n",
2240                         sport->port.line);
2241                 return -EINVAL;
2242         }
2243 
2244         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2245         base = devm_ioremap_resource(&pdev->dev, res);
2246         if (IS_ERR(base))
2247                 return PTR_ERR(base);
2248 
2249         rxirq = platform_get_irq(pdev, 0);
2250         txirq = platform_get_irq_optional(pdev, 1);
2251         rtsirq = platform_get_irq_optional(pdev, 2);
2252 
2253         sport->port.dev = &pdev->dev;
2254         sport->port.mapbase = res->start;
2255         sport->port.membase = base;
2256         sport->port.type = PORT_IMX,
2257         sport->port.iotype = UPIO_MEM;
2258         sport->port.irq = rxirq;
2259         sport->port.fifosize = 32;
2260         sport->port.ops = &imx_uart_pops;
2261         sport->port.rs485_config = imx_uart_rs485_config;
2262         sport->port.flags = UPF_BOOT_AUTOCONF;
2263         timer_setup(&sport->timer, imx_uart_timeout, 0);
2264 
2265         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2266         if (IS_ERR(sport->gpios))
2267                 return PTR_ERR(sport->gpios);
2268 
2269         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2270         if (IS_ERR(sport->clk_ipg)) {
2271                 ret = PTR_ERR(sport->clk_ipg);
2272                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2273                 return ret;
2274         }
2275 
2276         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2277         if (IS_ERR(sport->clk_per)) {
2278                 ret = PTR_ERR(sport->clk_per);
2279                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2280                 return ret;
2281         }
2282 
2283         sport->port.uartclk = clk_get_rate(sport->clk_per);
2284 
2285         /* For register access, we only need to enable the ipg clock. */
2286         ret = clk_prepare_enable(sport->clk_ipg);
2287         if (ret) {
2288                 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2289                 return ret;
2290         }
2291 
2292         /* initialize shadow register values */
2293         sport->ucr1 = readl(sport->port.membase + UCR1);
2294         sport->ucr2 = readl(sport->port.membase + UCR2);
2295         sport->ucr3 = readl(sport->port.membase + UCR3);
2296         sport->ucr4 = readl(sport->port.membase + UCR4);
2297         sport->ufcr = readl(sport->port.membase + UFCR);
2298 
2299         uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2300 
2301         if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2302             (!sport->have_rtscts && !sport->have_rtsgpio))
2303                 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2304 
2305         /*
2306          * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2307          * signal cannot be set low during transmission in case the
2308          * receiver is off (limitation of the i.MX UART IP).
2309          */
2310         if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2311             sport->have_rtscts && !sport->have_rtsgpio &&
2312             (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2313              !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2314                 dev_err(&pdev->dev,
2315                         "low-active RTS not possible when receiver is off, enabling receiver\n");
2316 
2317         imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2318 
2319         /* Disable interrupts before requesting them */
2320         ucr1 = imx_uart_readl(sport, UCR1);
2321         ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2322                  UCR1_TRDYEN | UCR1_RTSDEN);
2323         imx_uart_writel(sport, ucr1, UCR1);
2324 
2325         if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2326                 /*
2327                  * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2328                  * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2329                  * and DCD (when they are outputs) or enables the respective
2330                  * irqs. So set this bit early, i.e. before requesting irqs.
2331                  */
2332                 u32 ufcr = imx_uart_readl(sport, UFCR);
2333                 if (!(ufcr & UFCR_DCEDTE))
2334                         imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2335 
2336                 /*
2337                  * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2338                  * enabled later because they cannot be cleared
2339                  * (confirmed on i.MX25) which makes them unusable.
2340                  */
2341                 imx_uart_writel(sport,
2342                                 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2343                                 UCR3);
2344 
2345         } else {
2346                 u32 ucr3 = UCR3_DSR;
2347                 u32 ufcr = imx_uart_readl(sport, UFCR);
2348                 if (ufcr & UFCR_DCEDTE)
2349                         imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2350 
2351                 if (!imx_uart_is_imx1(sport))
2352                         ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2353                 imx_uart_writel(sport, ucr3, UCR3);
2354         }
2355 
2356         clk_disable_unprepare(sport->clk_ipg);
2357 
2358         /*
2359          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2360          * chips only have one interrupt.
2361          */
2362         if (txirq > 0) {
2363                 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2364                                        dev_name(&pdev->dev), sport);
2365                 if (ret) {
2366                         dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2367                                 ret);
2368                         return ret;
2369                 }
2370 
2371                 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2372                                        dev_name(&pdev->dev), sport);
2373                 if (ret) {
2374                         dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2375                                 ret);
2376                         return ret;
2377                 }
2378 
2379                 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2380                                        dev_name(&pdev->dev), sport);
2381                 if (ret) {
2382                         dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2383                                 ret);
2384                         return ret;
2385                 }
2386         } else {
2387                 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2388                                        dev_name(&pdev->dev), sport);
2389                 if (ret) {
2390                         dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2391                         return ret;
2392                 }
2393         }
2394 
2395         imx_uart_ports[sport->port.line] = sport;
2396 
2397         platform_set_drvdata(pdev, sport);
2398 
2399         return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2400 }
2401 
2402 static int imx_uart_remove(struct platform_device *pdev)
2403 {
2404         struct imx_port *sport = platform_get_drvdata(pdev);
2405 
2406         return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2407 }
2408 
2409 static void imx_uart_restore_context(struct imx_port *sport)
2410 {
2411         unsigned long flags;
2412 
2413         spin_lock_irqsave(&sport->port.lock, flags);
2414         if (!sport->context_saved) {
2415                 spin_unlock_irqrestore(&sport->port.lock, flags);
2416                 return;
2417         }
2418 
2419         imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2420         imx_uart_writel(sport, sport->saved_reg[5], UESC);
2421         imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2422         imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2423         imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2424         imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2425         imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2426         imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2427         imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2428         imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2429         sport->context_saved = false;
2430         spin_unlock_irqrestore(&sport->port.lock, flags);
2431 }
2432 
2433 static void imx_uart_save_context(struct imx_port *sport)
2434 {
2435         unsigned long flags;
2436 
2437         /* Save necessary regs */
2438         spin_lock_irqsave(&sport->port.lock, flags);
2439         sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2440         sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2441         sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2442         sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2443         sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2444         sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2445         sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2446         sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2447         sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2448         sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2449         sport->context_saved = true;
2450         spin_unlock_irqrestore(&sport->port.lock, flags);
2451 }
2452 
2453 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2454 {
2455         u32 ucr3;
2456 
2457         ucr3 = imx_uart_readl(sport, UCR3);
2458         if (on) {
2459                 imx_uart_writel(sport, USR1_AWAKE, USR1);
2460                 ucr3 |= UCR3_AWAKEN;
2461         } else {
2462                 ucr3 &= ~UCR3_AWAKEN;
2463         }
2464         imx_uart_writel(sport, ucr3, UCR3);
2465 
2466         if (sport->have_rtscts) {
2467                 u32 ucr1 = imx_uart_readl(sport, UCR1);
2468                 if (on)
2469                         ucr1 |= UCR1_RTSDEN;
2470                 else
2471                         ucr1 &= ~UCR1_RTSDEN;
2472                 imx_uart_writel(sport, ucr1, UCR1);
2473         }
2474 }
2475 
2476 static int imx_uart_suspend_noirq(struct device *dev)
2477 {
2478         struct imx_port *sport = dev_get_drvdata(dev);
2479 
2480         imx_uart_save_context(sport);
2481 
2482         clk_disable(sport->clk_ipg);
2483 
2484         pinctrl_pm_select_sleep_state(dev);
2485 
2486         return 0;
2487 }
2488 
2489 static int imx_uart_resume_noirq(struct device *dev)
2490 {
2491         struct imx_port *sport = dev_get_drvdata(dev);
2492         int ret;
2493 
2494         pinctrl_pm_select_default_state(dev);
2495 
2496         ret = clk_enable(sport->clk_ipg);
2497         if (ret)
2498                 return ret;
2499 
2500         imx_uart_restore_context(sport);
2501 
2502         return 0;
2503 }
2504 
2505 static int imx_uart_suspend(struct device *dev)
2506 {
2507         struct imx_port *sport = dev_get_drvdata(dev);
2508         int ret;
2509 
2510         uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2511         disable_irq(sport->port.irq);
2512 
2513         ret = clk_prepare_enable(sport->clk_ipg);
2514         if (ret)
2515                 return ret;
2516 
2517         /* enable wakeup from i.MX UART */
2518         imx_uart_enable_wakeup(sport, true);
2519 
2520         return 0;
2521 }
2522 
2523 static int imx_uart_resume(struct device *dev)
2524 {
2525         struct imx_port *sport = dev_get_drvdata(dev);
2526 
2527         /* disable wakeup from i.MX UART */
2528         imx_uart_enable_wakeup(sport, false);
2529 
2530         uart_resume_port(&imx_uart_uart_driver, &sport->port);
2531         enable_irq(sport->port.irq);
2532 
2533         clk_disable_unprepare(sport->clk_ipg);
2534 
2535         return 0;
2536 }
2537 
2538 static int imx_uart_freeze(struct device *dev)
2539 {
2540         struct imx_port *sport = dev_get_drvdata(dev);
2541 
2542         uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2543 
2544         return clk_prepare_enable(sport->clk_ipg);
2545 }
2546 
2547 static int imx_uart_thaw(struct device *dev)
2548 {
2549         struct imx_port *sport = dev_get_drvdata(dev);
2550 
2551         uart_resume_port(&imx_uart_uart_driver, &sport->port);
2552 
2553         clk_disable_unprepare(sport->clk_ipg);
2554 
2555         return 0;
2556 }
2557 
2558 static const struct dev_pm_ops imx_uart_pm_ops = {
2559         .suspend_noirq = imx_uart_suspend_noirq,
2560         .resume_noirq = imx_uart_resume_noirq,
2561         .freeze_noirq = imx_uart_suspend_noirq,
2562         .restore_noirq = imx_uart_resume_noirq,
2563         .suspend = imx_uart_suspend,
2564         .resume = imx_uart_resume,
2565         .freeze = imx_uart_freeze,
2566         .thaw = imx_uart_thaw,
2567         .restore = imx_uart_thaw,
2568 };
2569 
2570 static struct platform_driver imx_uart_platform_driver = {
2571         .probe = imx_uart_probe,
2572         .remove = imx_uart_remove,
2573 
2574         .id_table = imx_uart_devtype,
2575         .driver = {
2576                 .name = "imx-uart",
2577                 .of_match_table = imx_uart_dt_ids,
2578                 .pm = &imx_uart_pm_ops,
2579         },
2580 };
2581 
2582 static int __init imx_uart_init(void)
2583 {
2584         int ret = uart_register_driver(&imx_uart_uart_driver);
2585 
2586         if (ret)
2587                 return ret;
2588 
2589         ret = platform_driver_register(&imx_uart_platform_driver);
2590         if (ret != 0)
2591                 uart_unregister_driver(&imx_uart_uart_driver);
2592 
2593         return ret;
2594 }
2595 
2596 static void __exit imx_uart_exit(void)
2597 {
2598         platform_driver_unregister(&imx_uart_platform_driver);
2599         uart_unregister_driver(&imx_uart_uart_driver);
2600 }
2601 
2602 module_init(imx_uart_init);
2603 module_exit(imx_uart_exit);
2604 
2605 MODULE_AUTHOR("Sascha Hauer");
2606 MODULE_DESCRIPTION("IMX generic serial port driver");
2607 MODULE_LICENSE("GPL");
2608 MODULE_ALIAS("platform:imx-uart");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/imx.c

DEFINITIONS
