This source file includes following definitions.
- get_fifosize_arm
- get_fifosize_st
- get_fifosize_zte
- pl011_reg_to_offset
- pl011_read
- pl011_write
- pl011_fifo_to_tty
- pl011_sgbuf_init
- pl011_sgbuf_free
- pl011_dma_probe
- pl011_dma_remove
- pl011_dma_tx_callback
- pl011_dma_tx_refill
- pl011_dma_tx_irq
- pl011_dma_tx_stop
- pl011_dma_tx_start
- pl011_dma_flush_buffer
- pl011_dma_rx_trigger_dma
- pl011_dma_rx_chars
- pl011_dma_rx_irq
- pl011_dma_rx_callback
- pl011_dma_rx_stop
- pl011_dma_rx_poll
- pl011_dma_startup
- pl011_dma_shutdown
- pl011_dma_rx_available
- pl011_dma_rx_running
- pl011_dma_probe
- pl011_dma_remove
- pl011_dma_startup
- pl011_dma_shutdown
- pl011_dma_tx_irq
- pl011_dma_tx_stop
- pl011_dma_tx_start
- pl011_dma_rx_irq
- pl011_dma_rx_stop
- pl011_dma_rx_trigger_dma
- pl011_dma_rx_available
- pl011_dma_rx_running
- pl011_stop_tx
- pl011_start_tx_pio
- pl011_start_tx
- pl011_stop_rx
- pl011_enable_ms
- pl011_rx_chars
- pl011_tx_char
- pl011_tx_chars
- pl011_modem_status
- check_apply_cts_event_workaround
- pl011_int
- pl011_tx_empty
- pl011_get_mctrl
- pl011_set_mctrl
- pl011_break_ctl
- pl011_quiesce_irqs
- pl011_get_poll_char
- pl011_put_poll_char
- pl011_hwinit
- pl011_split_lcrh
- pl011_write_lcr_h
- pl011_allocate_irq
- pl011_enable_interrupts
- pl011_startup
- sbsa_uart_startup
- pl011_shutdown_channel
- pl011_disable_uart
- pl011_disable_interrupts
- pl011_shutdown
- sbsa_uart_shutdown
- pl011_setup_status_masks
- pl011_set_termios
- sbsa_uart_set_termios
- pl011_type
- pl011_release_port
- pl011_request_port
- pl011_config_port
- pl011_verify_port
- sbsa_uart_set_mctrl
- sbsa_uart_get_mctrl
- pl011_console_putchar
- pl011_console_write
- pl011_console_get_options
- pl011_console_setup
- pl011_console_match
- qdf2400_e44_putc
- qdf2400_e44_early_write
- pl011_putc
- pl011_early_write
- pl011_early_console_setup
- qdf2400_e44_early_console_setup
- pl011_probe_dt_alias
- pl011_unregister_port
- pl011_find_free_port
- pl011_setup_port
- pl011_register_port
- pl011_probe
- pl011_remove
- pl011_suspend
- pl011_resume
- sbsa_uart_probe
- sbsa_uart_remove
- pl011_init
- pl011_exit
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20 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/amba/bus.h>
35 #include <linux/amba/serial.h>
36 #include <linux/clk.h>
37 #include <linux/slab.h>
38 #include <linux/dmaengine.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/scatterlist.h>
41 #include <linux/delay.h>
42 #include <linux/types.h>
43 #include <linux/of.h>
44 #include <linux/of_device.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/sizes.h>
47 #include <linux/io.h>
48 #include <linux/acpi.h>
49
50 #include "amba-pl011.h"
51
52 #define UART_NR 14
53
54 #define SERIAL_AMBA_MAJOR 204
55 #define SERIAL_AMBA_MINOR 64
56 #define SERIAL_AMBA_NR UART_NR
57
58 #define AMBA_ISR_PASS_LIMIT 256
59
60 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
61 #define UART_DUMMY_DR_RX (1 << 16)
62
63 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
64 [REG_DR] = UART01x_DR,
65 [REG_FR] = UART01x_FR,
66 [REG_LCRH_RX] = UART011_LCRH,
67 [REG_LCRH_TX] = UART011_LCRH,
68 [REG_IBRD] = UART011_IBRD,
69 [REG_FBRD] = UART011_FBRD,
70 [REG_CR] = UART011_CR,
71 [REG_IFLS] = UART011_IFLS,
72 [REG_IMSC] = UART011_IMSC,
73 [REG_RIS] = UART011_RIS,
74 [REG_MIS] = UART011_MIS,
75 [REG_ICR] = UART011_ICR,
76 [REG_DMACR] = UART011_DMACR,
77 };
78
79
80 struct vendor_data {
81 const u16 *reg_offset;
82 unsigned int ifls;
83 unsigned int fr_busy;
84 unsigned int fr_dsr;
85 unsigned int fr_cts;
86 unsigned int fr_ri;
87 unsigned int inv_fr;
88 bool access_32b;
89 bool oversampling;
90 bool dma_threshold;
91 bool cts_event_workaround;
92 bool always_enabled;
93 bool fixed_options;
94
95 unsigned int (*get_fifosize)(struct amba_device *dev);
96 };
97
98 static unsigned int get_fifosize_arm(struct amba_device *dev)
99 {
100 return amba_rev(dev) < 3 ? 16 : 32;
101 }
102
103 static struct vendor_data vendor_arm = {
104 .reg_offset = pl011_std_offsets,
105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
106 .fr_busy = UART01x_FR_BUSY,
107 .fr_dsr = UART01x_FR_DSR,
108 .fr_cts = UART01x_FR_CTS,
109 .fr_ri = UART011_FR_RI,
110 .oversampling = false,
111 .dma_threshold = false,
112 .cts_event_workaround = false,
113 .always_enabled = false,
114 .fixed_options = false,
115 .get_fifosize = get_fifosize_arm,
116 };
117
118 static const struct vendor_data vendor_sbsa = {
119 .reg_offset = pl011_std_offsets,
120 .fr_busy = UART01x_FR_BUSY,
121 .fr_dsr = UART01x_FR_DSR,
122 .fr_cts = UART01x_FR_CTS,
123 .fr_ri = UART011_FR_RI,
124 .access_32b = true,
125 .oversampling = false,
126 .dma_threshold = false,
127 .cts_event_workaround = false,
128 .always_enabled = true,
129 .fixed_options = true,
130 };
131
132 #ifdef CONFIG_ACPI_SPCR_TABLE
133 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
134 .reg_offset = pl011_std_offsets,
135 .fr_busy = UART011_FR_TXFE,
136 .fr_dsr = UART01x_FR_DSR,
137 .fr_cts = UART01x_FR_CTS,
138 .fr_ri = UART011_FR_RI,
139 .inv_fr = UART011_FR_TXFE,
140 .access_32b = true,
141 .oversampling = false,
142 .dma_threshold = false,
143 .cts_event_workaround = false,
144 .always_enabled = true,
145 .fixed_options = true,
146 };
147 #endif
148
149 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
150 [REG_DR] = UART01x_DR,
151 [REG_ST_DMAWM] = ST_UART011_DMAWM,
152 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
153 [REG_FR] = UART01x_FR,
154 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
155 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
156 [REG_IBRD] = UART011_IBRD,
157 [REG_FBRD] = UART011_FBRD,
158 [REG_CR] = UART011_CR,
159 [REG_IFLS] = UART011_IFLS,
160 [REG_IMSC] = UART011_IMSC,
161 [REG_RIS] = UART011_RIS,
162 [REG_MIS] = UART011_MIS,
163 [REG_ICR] = UART011_ICR,
164 [REG_DMACR] = UART011_DMACR,
165 [REG_ST_XFCR] = ST_UART011_XFCR,
166 [REG_ST_XON1] = ST_UART011_XON1,
167 [REG_ST_XON2] = ST_UART011_XON2,
168 [REG_ST_XOFF1] = ST_UART011_XOFF1,
169 [REG_ST_XOFF2] = ST_UART011_XOFF2,
170 [REG_ST_ITCR] = ST_UART011_ITCR,
171 [REG_ST_ITIP] = ST_UART011_ITIP,
172 [REG_ST_ABCR] = ST_UART011_ABCR,
173 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
174 };
175
176 static unsigned int get_fifosize_st(struct amba_device *dev)
177 {
178 return 64;
179 }
180
181 static struct vendor_data vendor_st = {
182 .reg_offset = pl011_st_offsets,
183 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
184 .fr_busy = UART01x_FR_BUSY,
185 .fr_dsr = UART01x_FR_DSR,
186 .fr_cts = UART01x_FR_CTS,
187 .fr_ri = UART011_FR_RI,
188 .oversampling = true,
189 .dma_threshold = true,
190 .cts_event_workaround = true,
191 .always_enabled = false,
192 .fixed_options = false,
193 .get_fifosize = get_fifosize_st,
194 };
195
196 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
197 [REG_DR] = ZX_UART011_DR,
198 [REG_FR] = ZX_UART011_FR,
199 [REG_LCRH_RX] = ZX_UART011_LCRH,
200 [REG_LCRH_TX] = ZX_UART011_LCRH,
201 [REG_IBRD] = ZX_UART011_IBRD,
202 [REG_FBRD] = ZX_UART011_FBRD,
203 [REG_CR] = ZX_UART011_CR,
204 [REG_IFLS] = ZX_UART011_IFLS,
205 [REG_IMSC] = ZX_UART011_IMSC,
206 [REG_RIS] = ZX_UART011_RIS,
207 [REG_MIS] = ZX_UART011_MIS,
208 [REG_ICR] = ZX_UART011_ICR,
209 [REG_DMACR] = ZX_UART011_DMACR,
210 };
211
212 static unsigned int get_fifosize_zte(struct amba_device *dev)
213 {
214 return 16;
215 }
216
217 static struct vendor_data vendor_zte = {
218 .reg_offset = pl011_zte_offsets,
219 .access_32b = true,
220 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
221 .fr_busy = ZX_UART01x_FR_BUSY,
222 .fr_dsr = ZX_UART01x_FR_DSR,
223 .fr_cts = ZX_UART01x_FR_CTS,
224 .fr_ri = ZX_UART011_FR_RI,
225 .get_fifosize = get_fifosize_zte,
226 };
227
228
229
230 struct pl011_sgbuf {
231 struct scatterlist sg;
232 char *buf;
233 };
234
235 struct pl011_dmarx_data {
236 struct dma_chan *chan;
237 struct completion complete;
238 bool use_buf_b;
239 struct pl011_sgbuf sgbuf_a;
240 struct pl011_sgbuf sgbuf_b;
241 dma_cookie_t cookie;
242 bool running;
243 struct timer_list timer;
244 unsigned int last_residue;
245 unsigned long last_jiffies;
246 bool auto_poll_rate;
247 unsigned int poll_rate;
248 unsigned int poll_timeout;
249 };
250
251 struct pl011_dmatx_data {
252 struct dma_chan *chan;
253 struct scatterlist sg;
254 char *buf;
255 bool queued;
256 };
257
258
259
260
261 struct uart_amba_port {
262 struct uart_port port;
263 const u16 *reg_offset;
264 struct clk *clk;
265 const struct vendor_data *vendor;
266 unsigned int dmacr;
267 unsigned int im;
268 unsigned int old_status;
269 unsigned int fifosize;
270 unsigned int old_cr;
271 unsigned int fixed_baud;
272 char type[12];
273 #ifdef CONFIG_DMA_ENGINE
274
275 bool using_tx_dma;
276 bool using_rx_dma;
277 struct pl011_dmarx_data dmarx;
278 struct pl011_dmatx_data dmatx;
279 bool dma_probed;
280 #endif
281 };
282
283 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
284 unsigned int reg)
285 {
286 return uap->reg_offset[reg];
287 }
288
289 static unsigned int pl011_read(const struct uart_amba_port *uap,
290 unsigned int reg)
291 {
292 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
293
294 return (uap->port.iotype == UPIO_MEM32) ?
295 readl_relaxed(addr) : readw_relaxed(addr);
296 }
297
298 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
299 unsigned int reg)
300 {
301 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
302
303 if (uap->port.iotype == UPIO_MEM32)
304 writel_relaxed(val, addr);
305 else
306 writew_relaxed(val, addr);
307 }
308
309
310
311
312
313
314 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
315 {
316 u16 status;
317 unsigned int ch, flag, fifotaken;
318
319 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
320 status = pl011_read(uap, REG_FR);
321 if (status & UART01x_FR_RXFE)
322 break;
323
324
325 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
326 flag = TTY_NORMAL;
327 uap->port.icount.rx++;
328
329 if (unlikely(ch & UART_DR_ERROR)) {
330 if (ch & UART011_DR_BE) {
331 ch &= ~(UART011_DR_FE | UART011_DR_PE);
332 uap->port.icount.brk++;
333 if (uart_handle_break(&uap->port))
334 continue;
335 } else if (ch & UART011_DR_PE)
336 uap->port.icount.parity++;
337 else if (ch & UART011_DR_FE)
338 uap->port.icount.frame++;
339 if (ch & UART011_DR_OE)
340 uap->port.icount.overrun++;
341
342 ch &= uap->port.read_status_mask;
343
344 if (ch & UART011_DR_BE)
345 flag = TTY_BREAK;
346 else if (ch & UART011_DR_PE)
347 flag = TTY_PARITY;
348 else if (ch & UART011_DR_FE)
349 flag = TTY_FRAME;
350 }
351
352 if (uart_handle_sysrq_char(&uap->port, ch & 255))
353 continue;
354
355 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
356 }
357
358 return fifotaken;
359 }
360
361
362
363
364
365
366
367 #ifdef CONFIG_DMA_ENGINE
368
369 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
370
371 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
372 enum dma_data_direction dir)
373 {
374 dma_addr_t dma_addr;
375
376 sg->buf = dma_alloc_coherent(chan->device->dev,
377 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
378 if (!sg->buf)
379 return -ENOMEM;
380
381 sg_init_table(&sg->sg, 1);
382 sg_set_page(&sg->sg, phys_to_page(dma_addr),
383 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
384 sg_dma_address(&sg->sg) = dma_addr;
385 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
386
387 return 0;
388 }
389
390 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
391 enum dma_data_direction dir)
392 {
393 if (sg->buf) {
394 dma_free_coherent(chan->device->dev,
395 PL011_DMA_BUFFER_SIZE, sg->buf,
396 sg_dma_address(&sg->sg));
397 }
398 }
399
400 static void pl011_dma_probe(struct uart_amba_port *uap)
401 {
402
403 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
404 struct device *dev = uap->port.dev;
405 struct dma_slave_config tx_conf = {
406 .dst_addr = uap->port.mapbase +
407 pl011_reg_to_offset(uap, REG_DR),
408 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
409 .direction = DMA_MEM_TO_DEV,
410 .dst_maxburst = uap->fifosize >> 1,
411 .device_fc = false,
412 };
413 struct dma_chan *chan;
414 dma_cap_mask_t mask;
415
416 uap->dma_probed = true;
417 chan = dma_request_slave_channel_reason(dev, "tx");
418 if (IS_ERR(chan)) {
419 if (PTR_ERR(chan) == -EPROBE_DEFER) {
420 uap->dma_probed = false;
421 return;
422 }
423
424
425 if (!plat || !plat->dma_filter) {
426 dev_info(uap->port.dev, "no DMA platform data\n");
427 return;
428 }
429
430
431 dma_cap_zero(mask);
432 dma_cap_set(DMA_SLAVE, mask);
433
434 chan = dma_request_channel(mask, plat->dma_filter,
435 plat->dma_tx_param);
436 if (!chan) {
437 dev_err(uap->port.dev, "no TX DMA channel!\n");
438 return;
439 }
440 }
441
442 dmaengine_slave_config(chan, &tx_conf);
443 uap->dmatx.chan = chan;
444
445 dev_info(uap->port.dev, "DMA channel TX %s\n",
446 dma_chan_name(uap->dmatx.chan));
447
448
449 chan = dma_request_slave_channel(dev, "rx");
450
451 if (!chan && plat && plat->dma_rx_param) {
452 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
453
454 if (!chan) {
455 dev_err(uap->port.dev, "no RX DMA channel!\n");
456 return;
457 }
458 }
459
460 if (chan) {
461 struct dma_slave_config rx_conf = {
462 .src_addr = uap->port.mapbase +
463 pl011_reg_to_offset(uap, REG_DR),
464 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
465 .direction = DMA_DEV_TO_MEM,
466 .src_maxburst = uap->fifosize >> 2,
467 .device_fc = false,
468 };
469 struct dma_slave_caps caps;
470
471
472
473
474
475
476 if (0 == dma_get_slave_caps(chan, &caps)) {
477 if (caps.residue_granularity ==
478 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
479 dma_release_channel(chan);
480 dev_info(uap->port.dev,
481 "RX DMA disabled - no residue processing\n");
482 return;
483 }
484 }
485 dmaengine_slave_config(chan, &rx_conf);
486 uap->dmarx.chan = chan;
487
488 uap->dmarx.auto_poll_rate = false;
489 if (plat && plat->dma_rx_poll_enable) {
490
491 if (plat->dma_rx_poll_rate) {
492 uap->dmarx.auto_poll_rate = false;
493 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
494 } else {
495
496
497
498
499
500 uap->dmarx.auto_poll_rate = true;
501 uap->dmarx.poll_rate = 100;
502 }
503
504 if (plat->dma_rx_poll_timeout)
505 uap->dmarx.poll_timeout =
506 plat->dma_rx_poll_timeout;
507 else
508 uap->dmarx.poll_timeout = 3000;
509 } else if (!plat && dev->of_node) {
510 uap->dmarx.auto_poll_rate = of_property_read_bool(
511 dev->of_node, "auto-poll");
512 if (uap->dmarx.auto_poll_rate) {
513 u32 x;
514
515 if (0 == of_property_read_u32(dev->of_node,
516 "poll-rate-ms", &x))
517 uap->dmarx.poll_rate = x;
518 else
519 uap->dmarx.poll_rate = 100;
520 if (0 == of_property_read_u32(dev->of_node,
521 "poll-timeout-ms", &x))
522 uap->dmarx.poll_timeout = x;
523 else
524 uap->dmarx.poll_timeout = 3000;
525 }
526 }
527 dev_info(uap->port.dev, "DMA channel RX %s\n",
528 dma_chan_name(uap->dmarx.chan));
529 }
530 }
531
532 static void pl011_dma_remove(struct uart_amba_port *uap)
533 {
534 if (uap->dmatx.chan)
535 dma_release_channel(uap->dmatx.chan);
536 if (uap->dmarx.chan)
537 dma_release_channel(uap->dmarx.chan);
538 }
539
540
541 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
542 static void pl011_start_tx_pio(struct uart_amba_port *uap);
543
544
545
546
547
548 static void pl011_dma_tx_callback(void *data)
549 {
550 struct uart_amba_port *uap = data;
551 struct pl011_dmatx_data *dmatx = &uap->dmatx;
552 unsigned long flags;
553 u16 dmacr;
554
555 spin_lock_irqsave(&uap->port.lock, flags);
556 if (uap->dmatx.queued)
557 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
558 DMA_TO_DEVICE);
559
560 dmacr = uap->dmacr;
561 uap->dmacr = dmacr & ~UART011_TXDMAE;
562 pl011_write(uap->dmacr, uap, REG_DMACR);
563
564
565
566
567
568
569
570
571
572
573 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
574 uart_circ_empty(&uap->port.state->xmit)) {
575 uap->dmatx.queued = false;
576 spin_unlock_irqrestore(&uap->port.lock, flags);
577 return;
578 }
579
580 if (pl011_dma_tx_refill(uap) <= 0)
581
582
583
584
585 pl011_start_tx_pio(uap);
586
587 spin_unlock_irqrestore(&uap->port.lock, flags);
588 }
589
590
591
592
593
594
595
596
597
598 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
599 {
600 struct pl011_dmatx_data *dmatx = &uap->dmatx;
601 struct dma_chan *chan = dmatx->chan;
602 struct dma_device *dma_dev = chan->device;
603 struct dma_async_tx_descriptor *desc;
604 struct circ_buf *xmit = &uap->port.state->xmit;
605 unsigned int count;
606
607
608
609
610
611
612
613 count = uart_circ_chars_pending(xmit);
614 if (count < (uap->fifosize >> 1)) {
615 uap->dmatx.queued = false;
616 return 0;
617 }
618
619
620
621
622
623 count -= 1;
624
625
626 if (count > PL011_DMA_BUFFER_SIZE)
627 count = PL011_DMA_BUFFER_SIZE;
628
629 if (xmit->tail < xmit->head)
630 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
631 else {
632 size_t first = UART_XMIT_SIZE - xmit->tail;
633 size_t second;
634
635 if (first > count)
636 first = count;
637 second = count - first;
638
639 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
640 if (second)
641 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
642 }
643
644 dmatx->sg.length = count;
645
646 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
647 uap->dmatx.queued = false;
648 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
649 return -EBUSY;
650 }
651
652 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
653 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
654 if (!desc) {
655 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
656 uap->dmatx.queued = false;
657
658
659
660
661 dev_dbg(uap->port.dev, "TX DMA busy\n");
662 return -EBUSY;
663 }
664
665
666 desc->callback = pl011_dma_tx_callback;
667 desc->callback_param = uap;
668
669
670 dmaengine_submit(desc);
671
672
673 dma_dev->device_issue_pending(chan);
674
675 uap->dmacr |= UART011_TXDMAE;
676 pl011_write(uap->dmacr, uap, REG_DMACR);
677 uap->dmatx.queued = true;
678
679
680
681
682
683 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
684 uap->port.icount.tx += count;
685
686 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
687 uart_write_wakeup(&uap->port);
688
689 return 1;
690 }
691
692
693
694
695
696
697
698
699
700 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
701 {
702 if (!uap->using_tx_dma)
703 return false;
704
705
706
707
708
709
710 if (uap->dmatx.queued) {
711 uap->dmacr |= UART011_TXDMAE;
712 pl011_write(uap->dmacr, uap, REG_DMACR);
713 uap->im &= ~UART011_TXIM;
714 pl011_write(uap->im, uap, REG_IMSC);
715 return true;
716 }
717
718
719
720
721
722 if (pl011_dma_tx_refill(uap) > 0) {
723 uap->im &= ~UART011_TXIM;
724 pl011_write(uap->im, uap, REG_IMSC);
725 return true;
726 }
727 return false;
728 }
729
730
731
732
733
734 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
735 {
736 if (uap->dmatx.queued) {
737 uap->dmacr &= ~UART011_TXDMAE;
738 pl011_write(uap->dmacr, uap, REG_DMACR);
739 }
740 }
741
742
743
744
745
746
747
748
749
750 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
751 {
752 u16 dmacr;
753
754 if (!uap->using_tx_dma)
755 return false;
756
757 if (!uap->port.x_char) {
758
759 bool ret = true;
760
761 if (!uap->dmatx.queued) {
762 if (pl011_dma_tx_refill(uap) > 0) {
763 uap->im &= ~UART011_TXIM;
764 pl011_write(uap->im, uap, REG_IMSC);
765 } else
766 ret = false;
767 } else if (!(uap->dmacr & UART011_TXDMAE)) {
768 uap->dmacr |= UART011_TXDMAE;
769 pl011_write(uap->dmacr, uap, REG_DMACR);
770 }
771 return ret;
772 }
773
774
775
776
777
778 dmacr = uap->dmacr;
779 uap->dmacr &= ~UART011_TXDMAE;
780 pl011_write(uap->dmacr, uap, REG_DMACR);
781
782 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
783
784
785
786
787
788 return false;
789 }
790
791 pl011_write(uap->port.x_char, uap, REG_DR);
792 uap->port.icount.tx++;
793 uap->port.x_char = 0;
794
795
796 uap->dmacr = dmacr;
797 pl011_write(dmacr, uap, REG_DMACR);
798
799 return true;
800 }
801
802
803
804
805
806 static void pl011_dma_flush_buffer(struct uart_port *port)
807 __releases(&uap->port.lock)
808 __acquires(&uap->port.lock)
809 {
810 struct uart_amba_port *uap =
811 container_of(port, struct uart_amba_port, port);
812
813 if (!uap->using_tx_dma)
814 return;
815
816 dmaengine_terminate_async(uap->dmatx.chan);
817
818 if (uap->dmatx.queued) {
819 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
820 DMA_TO_DEVICE);
821 uap->dmatx.queued = false;
822 uap->dmacr &= ~UART011_TXDMAE;
823 pl011_write(uap->dmacr, uap, REG_DMACR);
824 }
825 }
826
827 static void pl011_dma_rx_callback(void *data);
828
829 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
830 {
831 struct dma_chan *rxchan = uap->dmarx.chan;
832 struct pl011_dmarx_data *dmarx = &uap->dmarx;
833 struct dma_async_tx_descriptor *desc;
834 struct pl011_sgbuf *sgbuf;
835
836 if (!rxchan)
837 return -EIO;
838
839
840 sgbuf = uap->dmarx.use_buf_b ?
841 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
842 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
843 DMA_DEV_TO_MEM,
844 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
845
846
847
848
849
850 if (!desc) {
851 uap->dmarx.running = false;
852 dmaengine_terminate_all(rxchan);
853 return -EBUSY;
854 }
855
856
857 desc->callback = pl011_dma_rx_callback;
858 desc->callback_param = uap;
859 dmarx->cookie = dmaengine_submit(desc);
860 dma_async_issue_pending(rxchan);
861
862 uap->dmacr |= UART011_RXDMAE;
863 pl011_write(uap->dmacr, uap, REG_DMACR);
864 uap->dmarx.running = true;
865
866 uap->im &= ~UART011_RXIM;
867 pl011_write(uap->im, uap, REG_IMSC);
868
869 return 0;
870 }
871
872
873
874
875
876
877 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
878 u32 pending, bool use_buf_b,
879 bool readfifo)
880 {
881 struct tty_port *port = &uap->port.state->port;
882 struct pl011_sgbuf *sgbuf = use_buf_b ?
883 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
884 int dma_count = 0;
885 u32 fifotaken = 0;
886
887 struct pl011_dmarx_data *dmarx = &uap->dmarx;
888 int dmataken = 0;
889
890 if (uap->dmarx.poll_rate) {
891
892 dmataken = sgbuf->sg.length - dmarx->last_residue;
893
894 if (pending >= dmataken)
895 pending -= dmataken;
896 }
897
898
899 if (pending) {
900
901
902
903
904
905
906 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
907 pending);
908
909 uap->port.icount.rx += dma_count;
910 if (dma_count < pending)
911 dev_warn(uap->port.dev,
912 "couldn't insert all characters (TTY is full?)\n");
913 }
914
915
916 if (uap->dmarx.poll_rate)
917 dmarx->last_residue = sgbuf->sg.length;
918
919
920
921
922
923 if (dma_count == pending && readfifo) {
924
925 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
926 UART011_FEIS, uap, REG_ICR);
927
928
929
930
931
932
933
934
935
936
937
938
939 fifotaken = pl011_fifo_to_tty(uap);
940 }
941
942 spin_unlock(&uap->port.lock);
943 dev_vdbg(uap->port.dev,
944 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
945 dma_count, fifotaken);
946 tty_flip_buffer_push(port);
947 spin_lock(&uap->port.lock);
948 }
949
950 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
951 {
952 struct pl011_dmarx_data *dmarx = &uap->dmarx;
953 struct dma_chan *rxchan = dmarx->chan;
954 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
955 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
956 size_t pending;
957 struct dma_tx_state state;
958 enum dma_status dmastat;
959
960
961
962
963
964
965 if (dmaengine_pause(rxchan))
966 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
967 dmastat = rxchan->device->device_tx_status(rxchan,
968 dmarx->cookie, &state);
969 if (dmastat != DMA_PAUSED)
970 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
971
972
973 uap->dmacr &= ~UART011_RXDMAE;
974 pl011_write(uap->dmacr, uap, REG_DMACR);
975 uap->dmarx.running = false;
976
977 pending = sgbuf->sg.length - state.residue;
978 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
979
980 dmaengine_terminate_all(rxchan);
981
982
983
984
985
986 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
987
988
989 dmarx->use_buf_b = !dmarx->use_buf_b;
990 if (pl011_dma_rx_trigger_dma(uap)) {
991 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
992 "fall back to interrupt mode\n");
993 uap->im |= UART011_RXIM;
994 pl011_write(uap->im, uap, REG_IMSC);
995 }
996 }
997
998 static void pl011_dma_rx_callback(void *data)
999 {
1000 struct uart_amba_port *uap = data;
1001 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1002 struct dma_chan *rxchan = dmarx->chan;
1003 bool lastbuf = dmarx->use_buf_b;
1004 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1005 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1006 size_t pending;
1007 struct dma_tx_state state;
1008 int ret;
1009
1010
1011
1012
1013
1014
1015
1016
1017 spin_lock_irq(&uap->port.lock);
1018
1019
1020
1021
1022 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1023 pending = sgbuf->sg.length - state.residue;
1024 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1025
1026 dmaengine_terminate_all(rxchan);
1027
1028 uap->dmarx.running = false;
1029 dmarx->use_buf_b = !lastbuf;
1030 ret = pl011_dma_rx_trigger_dma(uap);
1031
1032 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1033 spin_unlock_irq(&uap->port.lock);
1034
1035
1036
1037
1038 if (ret) {
1039 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1040 "fall back to interrupt mode\n");
1041 uap->im |= UART011_RXIM;
1042 pl011_write(uap->im, uap, REG_IMSC);
1043 }
1044 }
1045
1046
1047
1048
1049
1050
1051 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1052 {
1053
1054 uap->dmacr &= ~UART011_RXDMAE;
1055 pl011_write(uap->dmacr, uap, REG_DMACR);
1056 }
1057
1058
1059
1060
1061
1062
1063 static void pl011_dma_rx_poll(struct timer_list *t)
1064 {
1065 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1066 struct tty_port *port = &uap->port.state->port;
1067 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1068 struct dma_chan *rxchan = uap->dmarx.chan;
1069 unsigned long flags = 0;
1070 unsigned int dmataken = 0;
1071 unsigned int size = 0;
1072 struct pl011_sgbuf *sgbuf;
1073 int dma_count;
1074 struct dma_tx_state state;
1075
1076 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1077 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1078 if (likely(state.residue < dmarx->last_residue)) {
1079 dmataken = sgbuf->sg.length - dmarx->last_residue;
1080 size = dmarx->last_residue - state.residue;
1081 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1082 size);
1083 if (dma_count == size)
1084 dmarx->last_residue = state.residue;
1085 dmarx->last_jiffies = jiffies;
1086 }
1087 tty_flip_buffer_push(port);
1088
1089
1090
1091
1092
1093 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1094 > uap->dmarx.poll_timeout) {
1095
1096 spin_lock_irqsave(&uap->port.lock, flags);
1097 pl011_dma_rx_stop(uap);
1098 uap->im |= UART011_RXIM;
1099 pl011_write(uap->im, uap, REG_IMSC);
1100 spin_unlock_irqrestore(&uap->port.lock, flags);
1101
1102 uap->dmarx.running = false;
1103 dmaengine_terminate_all(rxchan);
1104 del_timer(&uap->dmarx.timer);
1105 } else {
1106 mod_timer(&uap->dmarx.timer,
1107 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1108 }
1109 }
1110
1111 static void pl011_dma_startup(struct uart_amba_port *uap)
1112 {
1113 int ret;
1114
1115 if (!uap->dma_probed)
1116 pl011_dma_probe(uap);
1117
1118 if (!uap->dmatx.chan)
1119 return;
1120
1121 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1122 if (!uap->dmatx.buf) {
1123 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1124 uap->port.fifosize = uap->fifosize;
1125 return;
1126 }
1127
1128 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1129
1130
1131 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1132 uap->using_tx_dma = true;
1133
1134 if (!uap->dmarx.chan)
1135 goto skip_rx;
1136
1137
1138 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1139 DMA_FROM_DEVICE);
1140 if (ret) {
1141 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1142 "RX buffer A", ret);
1143 goto skip_rx;
1144 }
1145
1146 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1147 DMA_FROM_DEVICE);
1148 if (ret) {
1149 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1150 "RX buffer B", ret);
1151 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1152 DMA_FROM_DEVICE);
1153 goto skip_rx;
1154 }
1155
1156 uap->using_rx_dma = true;
1157
1158 skip_rx:
1159
1160 uap->dmacr |= UART011_DMAONERR;
1161 pl011_write(uap->dmacr, uap, REG_DMACR);
1162
1163
1164
1165
1166
1167
1168 if (uap->vendor->dma_threshold)
1169 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1170 uap, REG_ST_DMAWM);
1171
1172 if (uap->using_rx_dma) {
1173 if (pl011_dma_rx_trigger_dma(uap))
1174 dev_dbg(uap->port.dev, "could not trigger initial "
1175 "RX DMA job, fall back to interrupt mode\n");
1176 if (uap->dmarx.poll_rate) {
1177 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1178 mod_timer(&uap->dmarx.timer,
1179 jiffies +
1180 msecs_to_jiffies(uap->dmarx.poll_rate));
1181 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1182 uap->dmarx.last_jiffies = jiffies;
1183 }
1184 }
1185 }
1186
1187 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1188 {
1189 if (!(uap->using_tx_dma || uap->using_rx_dma))
1190 return;
1191
1192
1193 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1194 cpu_relax();
1195
1196 spin_lock_irq(&uap->port.lock);
1197 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1198 pl011_write(uap->dmacr, uap, REG_DMACR);
1199 spin_unlock_irq(&uap->port.lock);
1200
1201 if (uap->using_tx_dma) {
1202
1203 dmaengine_terminate_all(uap->dmatx.chan);
1204 if (uap->dmatx.queued) {
1205 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1206 DMA_TO_DEVICE);
1207 uap->dmatx.queued = false;
1208 }
1209
1210 kfree(uap->dmatx.buf);
1211 uap->using_tx_dma = false;
1212 }
1213
1214 if (uap->using_rx_dma) {
1215 dmaengine_terminate_all(uap->dmarx.chan);
1216
1217 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1218 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1219 if (uap->dmarx.poll_rate)
1220 del_timer_sync(&uap->dmarx.timer);
1221 uap->using_rx_dma = false;
1222 }
1223 }
1224
1225 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1226 {
1227 return uap->using_rx_dma;
1228 }
1229
1230 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1231 {
1232 return uap->using_rx_dma && uap->dmarx.running;
1233 }
1234
1235 #else
1236
1237 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1238 {
1239 }
1240
1241 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1242 {
1243 }
1244
1245 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1246 {
1247 }
1248
1249 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1250 {
1251 }
1252
1253 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1254 {
1255 return false;
1256 }
1257
1258 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1259 {
1260 }
1261
1262 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1263 {
1264 return false;
1265 }
1266
1267 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1268 {
1269 }
1270
1271 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1272 {
1273 }
1274
1275 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1276 {
1277 return -EIO;
1278 }
1279
1280 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1281 {
1282 return false;
1283 }
1284
1285 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1286 {
1287 return false;
1288 }
1289
1290 #define pl011_dma_flush_buffer NULL
1291 #endif
1292
1293 static void pl011_stop_tx(struct uart_port *port)
1294 {
1295 struct uart_amba_port *uap =
1296 container_of(port, struct uart_amba_port, port);
1297
1298 uap->im &= ~UART011_TXIM;
1299 pl011_write(uap->im, uap, REG_IMSC);
1300 pl011_dma_tx_stop(uap);
1301 }
1302
1303 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1304
1305
1306 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1307 {
1308 if (pl011_tx_chars(uap, false)) {
1309 uap->im |= UART011_TXIM;
1310 pl011_write(uap->im, uap, REG_IMSC);
1311 }
1312 }
1313
1314 static void pl011_start_tx(struct uart_port *port)
1315 {
1316 struct uart_amba_port *uap =
1317 container_of(port, struct uart_amba_port, port);
1318
1319 if (!pl011_dma_tx_start(uap))
1320 pl011_start_tx_pio(uap);
1321 }
1322
1323 static void pl011_stop_rx(struct uart_port *port)
1324 {
1325 struct uart_amba_port *uap =
1326 container_of(port, struct uart_amba_port, port);
1327
1328 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1329 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1330 pl011_write(uap->im, uap, REG_IMSC);
1331
1332 pl011_dma_rx_stop(uap);
1333 }
1334
1335 static void pl011_enable_ms(struct uart_port *port)
1336 {
1337 struct uart_amba_port *uap =
1338 container_of(port, struct uart_amba_port, port);
1339
1340 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1341 pl011_write(uap->im, uap, REG_IMSC);
1342 }
1343
1344 static void pl011_rx_chars(struct uart_amba_port *uap)
1345 __releases(&uap->port.lock)
1346 __acquires(&uap->port.lock)
1347 {
1348 pl011_fifo_to_tty(uap);
1349
1350 spin_unlock(&uap->port.lock);
1351 tty_flip_buffer_push(&uap->port.state->port);
1352
1353
1354
1355
1356 if (pl011_dma_rx_available(uap)) {
1357 if (pl011_dma_rx_trigger_dma(uap)) {
1358 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1359 "fall back to interrupt mode again\n");
1360 uap->im |= UART011_RXIM;
1361 pl011_write(uap->im, uap, REG_IMSC);
1362 } else {
1363 #ifdef CONFIG_DMA_ENGINE
1364
1365 if (uap->dmarx.poll_rate) {
1366 uap->dmarx.last_jiffies = jiffies;
1367 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1368 mod_timer(&uap->dmarx.timer,
1369 jiffies +
1370 msecs_to_jiffies(uap->dmarx.poll_rate));
1371 }
1372 #endif
1373 }
1374 }
1375 spin_lock(&uap->port.lock);
1376 }
1377
1378 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1379 bool from_irq)
1380 {
1381 if (unlikely(!from_irq) &&
1382 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1383 return false;
1384
1385 pl011_write(c, uap, REG_DR);
1386 uap->port.icount.tx++;
1387
1388 return true;
1389 }
1390
1391
1392 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1393 {
1394 struct circ_buf *xmit = &uap->port.state->xmit;
1395 int count = uap->fifosize >> 1;
1396
1397 if (uap->port.x_char) {
1398 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1399 return true;
1400 uap->port.x_char = 0;
1401 --count;
1402 }
1403 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1404 pl011_stop_tx(&uap->port);
1405 return false;
1406 }
1407
1408
1409 if (pl011_dma_tx_irq(uap))
1410 return true;
1411
1412 do {
1413 if (likely(from_irq) && count-- == 0)
1414 break;
1415
1416 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1417 break;
1418
1419 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1420 } while (!uart_circ_empty(xmit));
1421
1422 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1423 uart_write_wakeup(&uap->port);
1424
1425 if (uart_circ_empty(xmit)) {
1426 pl011_stop_tx(&uap->port);
1427 return false;
1428 }
1429 return true;
1430 }
1431
1432 static void pl011_modem_status(struct uart_amba_port *uap)
1433 {
1434 unsigned int status, delta;
1435
1436 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1437
1438 delta = status ^ uap->old_status;
1439 uap->old_status = status;
1440
1441 if (!delta)
1442 return;
1443
1444 if (delta & UART01x_FR_DCD)
1445 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1446
1447 if (delta & uap->vendor->fr_dsr)
1448 uap->port.icount.dsr++;
1449
1450 if (delta & uap->vendor->fr_cts)
1451 uart_handle_cts_change(&uap->port,
1452 status & uap->vendor->fr_cts);
1453
1454 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1455 }
1456
1457 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1458 {
1459 unsigned int dummy_read;
1460
1461 if (!uap->vendor->cts_event_workaround)
1462 return;
1463
1464
1465 pl011_write(0x00, uap, REG_ICR);
1466
1467
1468
1469
1470
1471
1472 dummy_read = pl011_read(uap, REG_ICR);
1473 dummy_read = pl011_read(uap, REG_ICR);
1474 }
1475
1476 static irqreturn_t pl011_int(int irq, void *dev_id)
1477 {
1478 struct uart_amba_port *uap = dev_id;
1479 unsigned long flags;
1480 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1481 int handled = 0;
1482
1483 spin_lock_irqsave(&uap->port.lock, flags);
1484 status = pl011_read(uap, REG_RIS) & uap->im;
1485 if (status) {
1486 do {
1487 check_apply_cts_event_workaround(uap);
1488
1489 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1490 UART011_RXIS),
1491 uap, REG_ICR);
1492
1493 if (status & (UART011_RTIS|UART011_RXIS)) {
1494 if (pl011_dma_rx_running(uap))
1495 pl011_dma_rx_irq(uap);
1496 else
1497 pl011_rx_chars(uap);
1498 }
1499 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1500 UART011_CTSMIS|UART011_RIMIS))
1501 pl011_modem_status(uap);
1502 if (status & UART011_TXIS)
1503 pl011_tx_chars(uap, true);
1504
1505 if (pass_counter-- == 0)
1506 break;
1507
1508 status = pl011_read(uap, REG_RIS) & uap->im;
1509 } while (status != 0);
1510 handled = 1;
1511 }
1512
1513 spin_unlock_irqrestore(&uap->port.lock, flags);
1514
1515 return IRQ_RETVAL(handled);
1516 }
1517
1518 static unsigned int pl011_tx_empty(struct uart_port *port)
1519 {
1520 struct uart_amba_port *uap =
1521 container_of(port, struct uart_amba_port, port);
1522
1523
1524 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1525
1526 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1527 0 : TIOCSER_TEMT;
1528 }
1529
1530 static unsigned int pl011_get_mctrl(struct uart_port *port)
1531 {
1532 struct uart_amba_port *uap =
1533 container_of(port, struct uart_amba_port, port);
1534 unsigned int result = 0;
1535 unsigned int status = pl011_read(uap, REG_FR);
1536
1537 #define TIOCMBIT(uartbit, tiocmbit) \
1538 if (status & uartbit) \
1539 result |= tiocmbit
1540
1541 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1542 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1543 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1544 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1545 #undef TIOCMBIT
1546 return result;
1547 }
1548
1549 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1550 {
1551 struct uart_amba_port *uap =
1552 container_of(port, struct uart_amba_port, port);
1553 unsigned int cr;
1554
1555 cr = pl011_read(uap, REG_CR);
1556
1557 #define TIOCMBIT(tiocmbit, uartbit) \
1558 if (mctrl & tiocmbit) \
1559 cr |= uartbit; \
1560 else \
1561 cr &= ~uartbit
1562
1563 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1564 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1565 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1566 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1567 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1568
1569 if (port->status & UPSTAT_AUTORTS) {
1570
1571 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1572 }
1573 #undef TIOCMBIT
1574
1575 pl011_write(cr, uap, REG_CR);
1576 }
1577
1578 static void pl011_break_ctl(struct uart_port *port, int break_state)
1579 {
1580 struct uart_amba_port *uap =
1581 container_of(port, struct uart_amba_port, port);
1582 unsigned long flags;
1583 unsigned int lcr_h;
1584
1585 spin_lock_irqsave(&uap->port.lock, flags);
1586 lcr_h = pl011_read(uap, REG_LCRH_TX);
1587 if (break_state == -1)
1588 lcr_h |= UART01x_LCRH_BRK;
1589 else
1590 lcr_h &= ~UART01x_LCRH_BRK;
1591 pl011_write(lcr_h, uap, REG_LCRH_TX);
1592 spin_unlock_irqrestore(&uap->port.lock, flags);
1593 }
1594
1595 #ifdef CONFIG_CONSOLE_POLL
1596
1597 static void pl011_quiesce_irqs(struct uart_port *port)
1598 {
1599 struct uart_amba_port *uap =
1600 container_of(port, struct uart_amba_port, port);
1601
1602 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1617 REG_IMSC);
1618 }
1619
1620 static int pl011_get_poll_char(struct uart_port *port)
1621 {
1622 struct uart_amba_port *uap =
1623 container_of(port, struct uart_amba_port, port);
1624 unsigned int status;
1625
1626
1627
1628
1629
1630 pl011_quiesce_irqs(port);
1631
1632 status = pl011_read(uap, REG_FR);
1633 if (status & UART01x_FR_RXFE)
1634 return NO_POLL_CHAR;
1635
1636 return pl011_read(uap, REG_DR);
1637 }
1638
1639 static void pl011_put_poll_char(struct uart_port *port,
1640 unsigned char ch)
1641 {
1642 struct uart_amba_port *uap =
1643 container_of(port, struct uart_amba_port, port);
1644
1645 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1646 cpu_relax();
1647
1648 pl011_write(ch, uap, REG_DR);
1649 }
1650
1651 #endif
1652
1653 static int pl011_hwinit(struct uart_port *port)
1654 {
1655 struct uart_amba_port *uap =
1656 container_of(port, struct uart_amba_port, port);
1657 int retval;
1658
1659
1660 pinctrl_pm_select_default_state(port->dev);
1661
1662
1663
1664
1665 retval = clk_prepare_enable(uap->clk);
1666 if (retval)
1667 return retval;
1668
1669 uap->port.uartclk = clk_get_rate(uap->clk);
1670
1671
1672 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1673 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1674 uap, REG_ICR);
1675
1676
1677
1678
1679
1680 uap->im = pl011_read(uap, REG_IMSC);
1681 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1682
1683 if (dev_get_platdata(uap->port.dev)) {
1684 struct amba_pl011_data *plat;
1685
1686 plat = dev_get_platdata(uap->port.dev);
1687 if (plat->init)
1688 plat->init();
1689 }
1690 return 0;
1691 }
1692
1693 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1694 {
1695 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1696 pl011_reg_to_offset(uap, REG_LCRH_TX);
1697 }
1698
1699 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1700 {
1701 pl011_write(lcr_h, uap, REG_LCRH_RX);
1702 if (pl011_split_lcrh(uap)) {
1703 int i;
1704
1705
1706
1707
1708 for (i = 0; i < 10; ++i)
1709 pl011_write(0xff, uap, REG_MIS);
1710 pl011_write(lcr_h, uap, REG_LCRH_TX);
1711 }
1712 }
1713
1714 static int pl011_allocate_irq(struct uart_amba_port *uap)
1715 {
1716 pl011_write(uap->im, uap, REG_IMSC);
1717
1718 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1719 }
1720
1721
1722
1723
1724
1725
1726 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1727 {
1728 unsigned int i;
1729
1730 spin_lock_irq(&uap->port.lock);
1731
1732
1733 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1734
1735
1736
1737
1738
1739
1740
1741 for (i = 0; i < uap->fifosize * 2; ++i) {
1742 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1743 break;
1744
1745 pl011_read(uap, REG_DR);
1746 }
1747
1748 uap->im = UART011_RTIM;
1749 if (!pl011_dma_rx_running(uap))
1750 uap->im |= UART011_RXIM;
1751 pl011_write(uap->im, uap, REG_IMSC);
1752 spin_unlock_irq(&uap->port.lock);
1753 }
1754
1755 static int pl011_startup(struct uart_port *port)
1756 {
1757 struct uart_amba_port *uap =
1758 container_of(port, struct uart_amba_port, port);
1759 unsigned int cr;
1760 int retval;
1761
1762 retval = pl011_hwinit(port);
1763 if (retval)
1764 goto clk_dis;
1765
1766 retval = pl011_allocate_irq(uap);
1767 if (retval)
1768 goto clk_dis;
1769
1770 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1771
1772 spin_lock_irq(&uap->port.lock);
1773
1774
1775 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1776 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1777 pl011_write(cr, uap, REG_CR);
1778
1779 spin_unlock_irq(&uap->port.lock);
1780
1781
1782
1783
1784 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1785
1786
1787 pl011_dma_startup(uap);
1788
1789 pl011_enable_interrupts(uap);
1790
1791 return 0;
1792
1793 clk_dis:
1794 clk_disable_unprepare(uap->clk);
1795 return retval;
1796 }
1797
1798 static int sbsa_uart_startup(struct uart_port *port)
1799 {
1800 struct uart_amba_port *uap =
1801 container_of(port, struct uart_amba_port, port);
1802 int retval;
1803
1804 retval = pl011_hwinit(port);
1805 if (retval)
1806 return retval;
1807
1808 retval = pl011_allocate_irq(uap);
1809 if (retval)
1810 return retval;
1811
1812
1813 uap->old_status = 0;
1814
1815 pl011_enable_interrupts(uap);
1816
1817 return 0;
1818 }
1819
1820 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1821 unsigned int lcrh)
1822 {
1823 unsigned long val;
1824
1825 val = pl011_read(uap, lcrh);
1826 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1827 pl011_write(val, uap, lcrh);
1828 }
1829
1830
1831
1832
1833
1834
1835 static void pl011_disable_uart(struct uart_amba_port *uap)
1836 {
1837 unsigned int cr;
1838
1839 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1840 spin_lock_irq(&uap->port.lock);
1841 cr = pl011_read(uap, REG_CR);
1842 uap->old_cr = cr;
1843 cr &= UART011_CR_RTS | UART011_CR_DTR;
1844 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1845 pl011_write(cr, uap, REG_CR);
1846 spin_unlock_irq(&uap->port.lock);
1847
1848
1849
1850
1851 pl011_shutdown_channel(uap, REG_LCRH_RX);
1852 if (pl011_split_lcrh(uap))
1853 pl011_shutdown_channel(uap, REG_LCRH_TX);
1854 }
1855
1856 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1857 {
1858 spin_lock_irq(&uap->port.lock);
1859
1860
1861 uap->im = 0;
1862 pl011_write(uap->im, uap, REG_IMSC);
1863 pl011_write(0xffff, uap, REG_ICR);
1864
1865 spin_unlock_irq(&uap->port.lock);
1866 }
1867
1868 static void pl011_shutdown(struct uart_port *port)
1869 {
1870 struct uart_amba_port *uap =
1871 container_of(port, struct uart_amba_port, port);
1872
1873 pl011_disable_interrupts(uap);
1874
1875 pl011_dma_shutdown(uap);
1876
1877 free_irq(uap->port.irq, uap);
1878
1879 pl011_disable_uart(uap);
1880
1881
1882
1883
1884 clk_disable_unprepare(uap->clk);
1885
1886 pinctrl_pm_select_sleep_state(port->dev);
1887
1888 if (dev_get_platdata(uap->port.dev)) {
1889 struct amba_pl011_data *plat;
1890
1891 plat = dev_get_platdata(uap->port.dev);
1892 if (plat->exit)
1893 plat->exit();
1894 }
1895
1896 if (uap->port.ops->flush_buffer)
1897 uap->port.ops->flush_buffer(port);
1898 }
1899
1900 static void sbsa_uart_shutdown(struct uart_port *port)
1901 {
1902 struct uart_amba_port *uap =
1903 container_of(port, struct uart_amba_port, port);
1904
1905 pl011_disable_interrupts(uap);
1906
1907 free_irq(uap->port.irq, uap);
1908
1909 if (uap->port.ops->flush_buffer)
1910 uap->port.ops->flush_buffer(port);
1911 }
1912
1913 static void
1914 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1915 {
1916 port->read_status_mask = UART011_DR_OE | 255;
1917 if (termios->c_iflag & INPCK)
1918 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1919 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1920 port->read_status_mask |= UART011_DR_BE;
1921
1922
1923
1924
1925 port->ignore_status_mask = 0;
1926 if (termios->c_iflag & IGNPAR)
1927 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1928 if (termios->c_iflag & IGNBRK) {
1929 port->ignore_status_mask |= UART011_DR_BE;
1930
1931
1932
1933
1934 if (termios->c_iflag & IGNPAR)
1935 port->ignore_status_mask |= UART011_DR_OE;
1936 }
1937
1938
1939
1940
1941 if ((termios->c_cflag & CREAD) == 0)
1942 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1943 }
1944
1945 static void
1946 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1947 struct ktermios *old)
1948 {
1949 struct uart_amba_port *uap =
1950 container_of(port, struct uart_amba_port, port);
1951 unsigned int lcr_h, old_cr;
1952 unsigned long flags;
1953 unsigned int baud, quot, clkdiv;
1954
1955 if (uap->vendor->oversampling)
1956 clkdiv = 8;
1957 else
1958 clkdiv = 16;
1959
1960
1961
1962
1963 baud = uart_get_baud_rate(port, termios, old, 0,
1964 port->uartclk / clkdiv);
1965 #ifdef CONFIG_DMA_ENGINE
1966
1967
1968
1969 if (uap->dmarx.auto_poll_rate)
1970 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1971 #endif
1972
1973 if (baud > port->uartclk/16)
1974 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1975 else
1976 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1977
1978 switch (termios->c_cflag & CSIZE) {
1979 case CS5:
1980 lcr_h = UART01x_LCRH_WLEN_5;
1981 break;
1982 case CS6:
1983 lcr_h = UART01x_LCRH_WLEN_6;
1984 break;
1985 case CS7:
1986 lcr_h = UART01x_LCRH_WLEN_7;
1987 break;
1988 default:
1989 lcr_h = UART01x_LCRH_WLEN_8;
1990 break;
1991 }
1992 if (termios->c_cflag & CSTOPB)
1993 lcr_h |= UART01x_LCRH_STP2;
1994 if (termios->c_cflag & PARENB) {
1995 lcr_h |= UART01x_LCRH_PEN;
1996 if (!(termios->c_cflag & PARODD))
1997 lcr_h |= UART01x_LCRH_EPS;
1998 if (termios->c_cflag & CMSPAR)
1999 lcr_h |= UART011_LCRH_SPS;
2000 }
2001 if (uap->fifosize > 1)
2002 lcr_h |= UART01x_LCRH_FEN;
2003
2004 spin_lock_irqsave(&port->lock, flags);
2005
2006
2007
2008
2009 uart_update_timeout(port, termios->c_cflag, baud);
2010
2011 pl011_setup_status_masks(port, termios);
2012
2013 if (UART_ENABLE_MS(port, termios->c_cflag))
2014 pl011_enable_ms(port);
2015
2016
2017 old_cr = pl011_read(uap, REG_CR);
2018 pl011_write(0, uap, REG_CR);
2019
2020 if (termios->c_cflag & CRTSCTS) {
2021 if (old_cr & UART011_CR_RTS)
2022 old_cr |= UART011_CR_RTSEN;
2023
2024 old_cr |= UART011_CR_CTSEN;
2025 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2026 } else {
2027 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2028 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2029 }
2030
2031 if (uap->vendor->oversampling) {
2032 if (baud > port->uartclk / 16)
2033 old_cr |= ST_UART011_CR_OVSFACT;
2034 else
2035 old_cr &= ~ST_UART011_CR_OVSFACT;
2036 }
2037
2038
2039
2040
2041
2042
2043
2044 if (uap->vendor->oversampling) {
2045 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2046 quot -= 1;
2047 else if ((baud > 3250000) && (quot > 2))
2048 quot -= 2;
2049 }
2050
2051 pl011_write(quot & 0x3f, uap, REG_FBRD);
2052 pl011_write(quot >> 6, uap, REG_IBRD);
2053
2054
2055
2056
2057
2058
2059
2060 pl011_write_lcr_h(uap, lcr_h);
2061 pl011_write(old_cr, uap, REG_CR);
2062
2063 spin_unlock_irqrestore(&port->lock, flags);
2064 }
2065
2066 static void
2067 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2068 struct ktermios *old)
2069 {
2070 struct uart_amba_port *uap =
2071 container_of(port, struct uart_amba_port, port);
2072 unsigned long flags;
2073
2074 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2075
2076
2077 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2078 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2079 termios->c_cflag |= CS8 | CLOCAL;
2080
2081 spin_lock_irqsave(&port->lock, flags);
2082 uart_update_timeout(port, CS8, uap->fixed_baud);
2083 pl011_setup_status_masks(port, termios);
2084 spin_unlock_irqrestore(&port->lock, flags);
2085 }
2086
2087 static const char *pl011_type(struct uart_port *port)
2088 {
2089 struct uart_amba_port *uap =
2090 container_of(port, struct uart_amba_port, port);
2091 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2092 }
2093
2094
2095
2096
2097 static void pl011_release_port(struct uart_port *port)
2098 {
2099 release_mem_region(port->mapbase, SZ_4K);
2100 }
2101
2102
2103
2104
2105 static int pl011_request_port(struct uart_port *port)
2106 {
2107 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2108 != NULL ? 0 : -EBUSY;
2109 }
2110
2111
2112
2113
2114 static void pl011_config_port(struct uart_port *port, int flags)
2115 {
2116 if (flags & UART_CONFIG_TYPE) {
2117 port->type = PORT_AMBA;
2118 pl011_request_port(port);
2119 }
2120 }
2121
2122
2123
2124
2125 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2126 {
2127 int ret = 0;
2128 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2129 ret = -EINVAL;
2130 if (ser->irq < 0 || ser->irq >= nr_irqs)
2131 ret = -EINVAL;
2132 if (ser->baud_base < 9600)
2133 ret = -EINVAL;
2134 return ret;
2135 }
2136
2137 static const struct uart_ops amba_pl011_pops = {
2138 .tx_empty = pl011_tx_empty,
2139 .set_mctrl = pl011_set_mctrl,
2140 .get_mctrl = pl011_get_mctrl,
2141 .stop_tx = pl011_stop_tx,
2142 .start_tx = pl011_start_tx,
2143 .stop_rx = pl011_stop_rx,
2144 .enable_ms = pl011_enable_ms,
2145 .break_ctl = pl011_break_ctl,
2146 .startup = pl011_startup,
2147 .shutdown = pl011_shutdown,
2148 .flush_buffer = pl011_dma_flush_buffer,
2149 .set_termios = pl011_set_termios,
2150 .type = pl011_type,
2151 .release_port = pl011_release_port,
2152 .request_port = pl011_request_port,
2153 .config_port = pl011_config_port,
2154 .verify_port = pl011_verify_port,
2155 #ifdef CONFIG_CONSOLE_POLL
2156 .poll_init = pl011_hwinit,
2157 .poll_get_char = pl011_get_poll_char,
2158 .poll_put_char = pl011_put_poll_char,
2159 #endif
2160 };
2161
2162 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2163 {
2164 }
2165
2166 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2167 {
2168 return 0;
2169 }
2170
2171 static const struct uart_ops sbsa_uart_pops = {
2172 .tx_empty = pl011_tx_empty,
2173 .set_mctrl = sbsa_uart_set_mctrl,
2174 .get_mctrl = sbsa_uart_get_mctrl,
2175 .stop_tx = pl011_stop_tx,
2176 .start_tx = pl011_start_tx,
2177 .stop_rx = pl011_stop_rx,
2178 .startup = sbsa_uart_startup,
2179 .shutdown = sbsa_uart_shutdown,
2180 .set_termios = sbsa_uart_set_termios,
2181 .type = pl011_type,
2182 .release_port = pl011_release_port,
2183 .request_port = pl011_request_port,
2184 .config_port = pl011_config_port,
2185 .verify_port = pl011_verify_port,
2186 #ifdef CONFIG_CONSOLE_POLL
2187 .poll_init = pl011_hwinit,
2188 .poll_get_char = pl011_get_poll_char,
2189 .poll_put_char = pl011_put_poll_char,
2190 #endif
2191 };
2192
2193 static struct uart_amba_port *amba_ports[UART_NR];
2194
2195 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2196
2197 static void pl011_console_putchar(struct uart_port *port, int ch)
2198 {
2199 struct uart_amba_port *uap =
2200 container_of(port, struct uart_amba_port, port);
2201
2202 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2203 cpu_relax();
2204 pl011_write(ch, uap, REG_DR);
2205 }
2206
2207 static void
2208 pl011_console_write(struct console *co, const char *s, unsigned int count)
2209 {
2210 struct uart_amba_port *uap = amba_ports[co->index];
2211 unsigned int old_cr = 0, new_cr;
2212 unsigned long flags;
2213 int locked = 1;
2214
2215 clk_enable(uap->clk);
2216
2217 local_irq_save(flags);
2218 if (uap->port.sysrq)
2219 locked = 0;
2220 else if (oops_in_progress)
2221 locked = spin_trylock(&uap->port.lock);
2222 else
2223 spin_lock(&uap->port.lock);
2224
2225
2226
2227
2228 if (!uap->vendor->always_enabled) {
2229 old_cr = pl011_read(uap, REG_CR);
2230 new_cr = old_cr & ~UART011_CR_CTSEN;
2231 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2232 pl011_write(new_cr, uap, REG_CR);
2233 }
2234
2235 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2236
2237
2238
2239
2240
2241
2242 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2243 & uap->vendor->fr_busy)
2244 cpu_relax();
2245 if (!uap->vendor->always_enabled)
2246 pl011_write(old_cr, uap, REG_CR);
2247
2248 if (locked)
2249 spin_unlock(&uap->port.lock);
2250 local_irq_restore(flags);
2251
2252 clk_disable(uap->clk);
2253 }
2254
2255 static void __init
2256 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2257 int *parity, int *bits)
2258 {
2259 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2260 unsigned int lcr_h, ibrd, fbrd;
2261
2262 lcr_h = pl011_read(uap, REG_LCRH_TX);
2263
2264 *parity = 'n';
2265 if (lcr_h & UART01x_LCRH_PEN) {
2266 if (lcr_h & UART01x_LCRH_EPS)
2267 *parity = 'e';
2268 else
2269 *parity = 'o';
2270 }
2271
2272 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2273 *bits = 7;
2274 else
2275 *bits = 8;
2276
2277 ibrd = pl011_read(uap, REG_IBRD);
2278 fbrd = pl011_read(uap, REG_FBRD);
2279
2280 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2281
2282 if (uap->vendor->oversampling) {
2283 if (pl011_read(uap, REG_CR)
2284 & ST_UART011_CR_OVSFACT)
2285 *baud *= 2;
2286 }
2287 }
2288 }
2289
2290 static int __init pl011_console_setup(struct console *co, char *options)
2291 {
2292 struct uart_amba_port *uap;
2293 int baud = 38400;
2294 int bits = 8;
2295 int parity = 'n';
2296 int flow = 'n';
2297 int ret;
2298
2299
2300
2301
2302
2303
2304 if (co->index >= UART_NR)
2305 co->index = 0;
2306 uap = amba_ports[co->index];
2307 if (!uap)
2308 return -ENODEV;
2309
2310
2311 pinctrl_pm_select_default_state(uap->port.dev);
2312
2313 ret = clk_prepare(uap->clk);
2314 if (ret)
2315 return ret;
2316
2317 if (dev_get_platdata(uap->port.dev)) {
2318 struct amba_pl011_data *plat;
2319
2320 plat = dev_get_platdata(uap->port.dev);
2321 if (plat->init)
2322 plat->init();
2323 }
2324
2325 uap->port.uartclk = clk_get_rate(uap->clk);
2326
2327 if (uap->vendor->fixed_options) {
2328 baud = uap->fixed_baud;
2329 } else {
2330 if (options)
2331 uart_parse_options(options,
2332 &baud, &parity, &bits, &flow);
2333 else
2334 pl011_console_get_options(uap, &baud, &parity, &bits);
2335 }
2336
2337 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2338 }
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358 static int __init pl011_console_match(struct console *co, char *name, int idx,
2359 char *options)
2360 {
2361 unsigned char iotype;
2362 resource_size_t addr;
2363 int i;
2364
2365
2366
2367
2368
2369
2370
2371 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2372 return -ENODEV;
2373
2374 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2375 return -ENODEV;
2376
2377 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2378 return -ENODEV;
2379
2380
2381 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2382 struct uart_port *port;
2383
2384 if (!amba_ports[i])
2385 continue;
2386
2387 port = &amba_ports[i]->port;
2388
2389 if (port->mapbase != addr)
2390 continue;
2391
2392 co->index = i;
2393 port->cons = co;
2394 return pl011_console_setup(co, options);
2395 }
2396
2397 return -ENODEV;
2398 }
2399
2400 static struct uart_driver amba_reg;
2401 static struct console amba_console = {
2402 .name = "ttyAMA",
2403 .write = pl011_console_write,
2404 .device = uart_console_device,
2405 .setup = pl011_console_setup,
2406 .match = pl011_console_match,
2407 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2408 .index = -1,
2409 .data = &amba_reg,
2410 };
2411
2412 #define AMBA_CONSOLE (&amba_console)
2413
2414 static void qdf2400_e44_putc(struct uart_port *port, int c)
2415 {
2416 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2417 cpu_relax();
2418 writel(c, port->membase + UART01x_DR);
2419 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2420 cpu_relax();
2421 }
2422
2423 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2424 {
2425 struct earlycon_device *dev = con->data;
2426
2427 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2428 }
2429
2430 static void pl011_putc(struct uart_port *port, int c)
2431 {
2432 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2433 cpu_relax();
2434 if (port->iotype == UPIO_MEM32)
2435 writel(c, port->membase + UART01x_DR);
2436 else
2437 writeb(c, port->membase + UART01x_DR);
2438 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2439 cpu_relax();
2440 }
2441
2442 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2443 {
2444 struct earlycon_device *dev = con->data;
2445
2446 uart_console_write(&dev->port, s, n, pl011_putc);
2447 }
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461 static int __init pl011_early_console_setup(struct earlycon_device *device,
2462 const char *opt)
2463 {
2464 if (!device->port.membase)
2465 return -ENODEV;
2466
2467 device->con->write = pl011_early_write;
2468
2469 return 0;
2470 }
2471 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2472 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484 static int __init
2485 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2486 const char *opt)
2487 {
2488 if (!device->port.membase)
2489 return -ENODEV;
2490
2491 device->con->write = qdf2400_e44_early_write;
2492 return 0;
2493 }
2494 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2495
2496 #else
2497 #define AMBA_CONSOLE NULL
2498 #endif
2499
2500 static struct uart_driver amba_reg = {
2501 .owner = THIS_MODULE,
2502 .driver_name = "ttyAMA",
2503 .dev_name = "ttyAMA",
2504 .major = SERIAL_AMBA_MAJOR,
2505 .minor = SERIAL_AMBA_MINOR,
2506 .nr = UART_NR,
2507 .cons = AMBA_CONSOLE,
2508 };
2509
2510 static int pl011_probe_dt_alias(int index, struct device *dev)
2511 {
2512 struct device_node *np;
2513 static bool seen_dev_with_alias = false;
2514 static bool seen_dev_without_alias = false;
2515 int ret = index;
2516
2517 if (!IS_ENABLED(CONFIG_OF))
2518 return ret;
2519
2520 np = dev->of_node;
2521 if (!np)
2522 return ret;
2523
2524 ret = of_alias_get_id(np, "serial");
2525 if (ret < 0) {
2526 seen_dev_without_alias = true;
2527 ret = index;
2528 } else {
2529 seen_dev_with_alias = true;
2530 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2531 dev_warn(dev, "requested serial port %d not available.\n", ret);
2532 ret = index;
2533 }
2534 }
2535
2536 if (seen_dev_with_alias && seen_dev_without_alias)
2537 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2538
2539 return ret;
2540 }
2541
2542
2543 static void pl011_unregister_port(struct uart_amba_port *uap)
2544 {
2545 int i;
2546 bool busy = false;
2547
2548 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2549 if (amba_ports[i] == uap)
2550 amba_ports[i] = NULL;
2551 else if (amba_ports[i])
2552 busy = true;
2553 }
2554 pl011_dma_remove(uap);
2555 if (!busy)
2556 uart_unregister_driver(&amba_reg);
2557 }
2558
2559 static int pl011_find_free_port(void)
2560 {
2561 int i;
2562
2563 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2564 if (amba_ports[i] == NULL)
2565 return i;
2566
2567 return -EBUSY;
2568 }
2569
2570 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2571 struct resource *mmiobase, int index)
2572 {
2573 void __iomem *base;
2574
2575 base = devm_ioremap_resource(dev, mmiobase);
2576 if (IS_ERR(base))
2577 return PTR_ERR(base);
2578
2579 index = pl011_probe_dt_alias(index, dev);
2580
2581 uap->old_cr = 0;
2582 uap->port.dev = dev;
2583 uap->port.mapbase = mmiobase->start;
2584 uap->port.membase = base;
2585 uap->port.fifosize = uap->fifosize;
2586 uap->port.flags = UPF_BOOT_AUTOCONF;
2587 uap->port.line = index;
2588
2589 amba_ports[index] = uap;
2590
2591 return 0;
2592 }
2593
2594 static int pl011_register_port(struct uart_amba_port *uap)
2595 {
2596 int ret;
2597
2598
2599 pl011_write(0, uap, REG_IMSC);
2600 pl011_write(0xffff, uap, REG_ICR);
2601
2602 if (!amba_reg.state) {
2603 ret = uart_register_driver(&amba_reg);
2604 if (ret < 0) {
2605 dev_err(uap->port.dev,
2606 "Failed to register AMBA-PL011 driver\n");
2607 return ret;
2608 }
2609 }
2610
2611 ret = uart_add_one_port(&amba_reg, &uap->port);
2612 if (ret)
2613 pl011_unregister_port(uap);
2614
2615 return ret;
2616 }
2617
2618 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2619 {
2620 struct uart_amba_port *uap;
2621 struct vendor_data *vendor = id->data;
2622 int portnr, ret;
2623
2624 portnr = pl011_find_free_port();
2625 if (portnr < 0)
2626 return portnr;
2627
2628 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2629 GFP_KERNEL);
2630 if (!uap)
2631 return -ENOMEM;
2632
2633 uap->clk = devm_clk_get(&dev->dev, NULL);
2634 if (IS_ERR(uap->clk))
2635 return PTR_ERR(uap->clk);
2636
2637 uap->reg_offset = vendor->reg_offset;
2638 uap->vendor = vendor;
2639 uap->fifosize = vendor->get_fifosize(dev);
2640 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2641 uap->port.irq = dev->irq[0];
2642 uap->port.ops = &amba_pl011_pops;
2643
2644 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2645
2646 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2647 if (ret)
2648 return ret;
2649
2650 amba_set_drvdata(dev, uap);
2651
2652 return pl011_register_port(uap);
2653 }
2654
2655 static int pl011_remove(struct amba_device *dev)
2656 {
2657 struct uart_amba_port *uap = amba_get_drvdata(dev);
2658
2659 uart_remove_one_port(&amba_reg, &uap->port);
2660 pl011_unregister_port(uap);
2661 return 0;
2662 }
2663
2664 #ifdef CONFIG_PM_SLEEP
2665 static int pl011_suspend(struct device *dev)
2666 {
2667 struct uart_amba_port *uap = dev_get_drvdata(dev);
2668
2669 if (!uap)
2670 return -EINVAL;
2671
2672 return uart_suspend_port(&amba_reg, &uap->port);
2673 }
2674
2675 static int pl011_resume(struct device *dev)
2676 {
2677 struct uart_amba_port *uap = dev_get_drvdata(dev);
2678
2679 if (!uap)
2680 return -EINVAL;
2681
2682 return uart_resume_port(&amba_reg, &uap->port);
2683 }
2684 #endif
2685
2686 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2687
2688 static int sbsa_uart_probe(struct platform_device *pdev)
2689 {
2690 struct uart_amba_port *uap;
2691 struct resource *r;
2692 int portnr, ret;
2693 int baudrate;
2694
2695
2696
2697
2698
2699 if (pdev->dev.of_node) {
2700 struct device_node *np = pdev->dev.of_node;
2701
2702 ret = of_property_read_u32(np, "current-speed", &baudrate);
2703 if (ret)
2704 return ret;
2705 } else {
2706 baudrate = 115200;
2707 }
2708
2709 portnr = pl011_find_free_port();
2710 if (portnr < 0)
2711 return portnr;
2712
2713 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2714 GFP_KERNEL);
2715 if (!uap)
2716 return -ENOMEM;
2717
2718 ret = platform_get_irq(pdev, 0);
2719 if (ret < 0)
2720 return ret;
2721 uap->port.irq = ret;
2722
2723 #ifdef CONFIG_ACPI_SPCR_TABLE
2724 if (qdf2400_e44_present) {
2725 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2726 uap->vendor = &vendor_qdt_qdf2400_e44;
2727 } else
2728 #endif
2729 uap->vendor = &vendor_sbsa;
2730
2731 uap->reg_offset = uap->vendor->reg_offset;
2732 uap->fifosize = 32;
2733 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2734 uap->port.ops = &sbsa_uart_pops;
2735 uap->fixed_baud = baudrate;
2736
2737 snprintf(uap->type, sizeof(uap->type), "SBSA");
2738
2739 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2740
2741 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2742 if (ret)
2743 return ret;
2744
2745 platform_set_drvdata(pdev, uap);
2746
2747 return pl011_register_port(uap);
2748 }
2749
2750 static int sbsa_uart_remove(struct platform_device *pdev)
2751 {
2752 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2753
2754 uart_remove_one_port(&amba_reg, &uap->port);
2755 pl011_unregister_port(uap);
2756 return 0;
2757 }
2758
2759 static const struct of_device_id sbsa_uart_of_match[] = {
2760 { .compatible = "arm,sbsa-uart", },
2761 {},
2762 };
2763 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2764
2765 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2766 { "ARMH0011", 0 },
2767 {},
2768 };
2769 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2770
2771 static struct platform_driver arm_sbsa_uart_platform_driver = {
2772 .probe = sbsa_uart_probe,
2773 .remove = sbsa_uart_remove,
2774 .driver = {
2775 .name = "sbsa-uart",
2776 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2777 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2778 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2779 },
2780 };
2781
2782 static const struct amba_id pl011_ids[] = {
2783 {
2784 .id = 0x00041011,
2785 .mask = 0x000fffff,
2786 .data = &vendor_arm,
2787 },
2788 {
2789 .id = 0x00380802,
2790 .mask = 0x00ffffff,
2791 .data = &vendor_st,
2792 },
2793 {
2794 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2795 .mask = 0x00ffffff,
2796 .data = &vendor_zte,
2797 },
2798 { 0, 0 },
2799 };
2800
2801 MODULE_DEVICE_TABLE(amba, pl011_ids);
2802
2803 static struct amba_driver pl011_driver = {
2804 .drv = {
2805 .name = "uart-pl011",
2806 .pm = &pl011_dev_pm_ops,
2807 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2808 },
2809 .id_table = pl011_ids,
2810 .probe = pl011_probe,
2811 .remove = pl011_remove,
2812 };
2813
2814 static int __init pl011_init(void)
2815 {
2816 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2817
2818 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2819 pr_warn("could not register SBSA UART platform driver\n");
2820 return amba_driver_register(&pl011_driver);
2821 }
2822
2823 static void __exit pl011_exit(void)
2824 {
2825 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2826 amba_driver_unregister(&pl011_driver);
2827 }
2828
2829
2830
2831
2832
2833 arch_initcall(pl011_init);
2834 module_exit(pl011_exit);
2835
2836 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2837 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2838 MODULE_LICENSE("GPL");