root/drivers/tty/serial/lantiq.c

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DEFINITIONS

This source file includes following definitions.
  1. asc_update_bits
  2. to_ltq_uart_port
  3. lqasc_stop_tx
  4. lqasc_start_tx
  5. lqasc_stop_rx
  6. lqasc_rx_chars
  7. lqasc_tx_chars
  8. lqasc_tx_int
  9. lqasc_err_int
  10. lqasc_rx_int
  11. lqasc_irq
  12. lqasc_tx_empty
  13. lqasc_get_mctrl
  14. lqasc_set_mctrl
  15. lqasc_break_ctl
  16. lqasc_startup
  17. lqasc_shutdown
  18. lqasc_set_termios
  19. lqasc_type
  20. lqasc_release_port
  21. lqasc_request_port
  22. lqasc_config_port
  23. lqasc_verify_port
  24. lqasc_console_putchar
  25. lqasc_serial_port_write
  26. lqasc_console_write
  27. lqasc_console_setup
  28. lqasc_console_init
  29. lqasc_serial_early_console_write
  30. lqasc_serial_early_console_setup
  31. fetch_irq_lantiq
  32. request_irq_lantiq
  33. free_irq_lantiq
  34. fetch_irq_intel
  35. request_irq_intel
  36. free_irq_intel
  37. lqasc_probe
  38. init_lqasc

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   4  *
   5  * Copyright (C) 2004 Infineon IFAP DC COM CPE
   6  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
   7  * Copyright (C) 2007 John Crispin <john@phrozen.org>
   8  * Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
   9  */
  10 
  11 #include <linux/clk.h>
  12 #include <linux/console.h>
  13 #include <linux/device.h>
  14 #include <linux/gpio.h>
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/ioport.h>
  18 #include <linux/lantiq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/serial.h>
  23 #include <linux/serial_core.h>
  24 #include <linux/slab.h>
  25 #include <linux/sysrq.h>
  26 #include <linux/tty.h>
  27 #include <linux/tty_flip.h>
  28 
  29 #define PORT_LTQ_ASC            111
  30 #define MAXPORTS                2
  31 #define UART_DUMMY_UER_RX       1
  32 #define DRVNAME                 "lantiq,asc"
  33 #ifdef __BIG_ENDIAN
  34 #define LTQ_ASC_TBUF            (0x0020 + 3)
  35 #define LTQ_ASC_RBUF            (0x0024 + 3)
  36 #else
  37 #define LTQ_ASC_TBUF            0x0020
  38 #define LTQ_ASC_RBUF            0x0024
  39 #endif
  40 #define LTQ_ASC_FSTAT           0x0048
  41 #define LTQ_ASC_WHBSTATE        0x0018
  42 #define LTQ_ASC_STATE           0x0014
  43 #define LTQ_ASC_IRNCR           0x00F8
  44 #define LTQ_ASC_CLC             0x0000
  45 #define LTQ_ASC_ID              0x0008
  46 #define LTQ_ASC_PISEL           0x0004
  47 #define LTQ_ASC_TXFCON          0x0044
  48 #define LTQ_ASC_RXFCON          0x0040
  49 #define LTQ_ASC_CON             0x0010
  50 #define LTQ_ASC_BG              0x0050
  51 #define LTQ_ASC_IRNREN          0x00F4
  52 
  53 #define ASC_IRNREN_TX           0x1
  54 #define ASC_IRNREN_RX           0x2
  55 #define ASC_IRNREN_ERR          0x4
  56 #define ASC_IRNREN_TX_BUF       0x8
  57 #define ASC_IRNCR_TIR           0x1
  58 #define ASC_IRNCR_RIR           0x2
  59 #define ASC_IRNCR_EIR           0x4
  60 #define ASC_IRNCR_MASK          GENMASK(2, 0)
  61 
  62 #define ASCOPT_CSIZE            0x3
  63 #define TXFIFO_FL               1
  64 #define RXFIFO_FL               1
  65 #define ASCCLC_DISS             0x2
  66 #define ASCCLC_RMCMASK          0x0000FF00
  67 #define ASCCLC_RMCOFFSET        8
  68 #define ASCCON_M_8ASYNC         0x0
  69 #define ASCCON_M_7ASYNC         0x2
  70 #define ASCCON_ODD              0x00000020
  71 #define ASCCON_STP              0x00000080
  72 #define ASCCON_BRS              0x00000100
  73 #define ASCCON_FDE              0x00000200
  74 #define ASCCON_R                0x00008000
  75 #define ASCCON_FEN              0x00020000
  76 #define ASCCON_ROEN             0x00080000
  77 #define ASCCON_TOEN             0x00100000
  78 #define ASCSTATE_PE             0x00010000
  79 #define ASCSTATE_FE             0x00020000
  80 #define ASCSTATE_ROE            0x00080000
  81 #define ASCSTATE_ANY            (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
  82 #define ASCWHBSTATE_CLRREN      0x00000001
  83 #define ASCWHBSTATE_SETREN      0x00000002
  84 #define ASCWHBSTATE_CLRPE       0x00000004
  85 #define ASCWHBSTATE_CLRFE       0x00000008
  86 #define ASCWHBSTATE_CLRROE      0x00000020
  87 #define ASCTXFCON_TXFEN         0x0001
  88 #define ASCTXFCON_TXFFLU        0x0002
  89 #define ASCTXFCON_TXFITLMASK    0x3F00
  90 #define ASCTXFCON_TXFITLOFF     8
  91 #define ASCRXFCON_RXFEN         0x0001
  92 #define ASCRXFCON_RXFFLU        0x0002
  93 #define ASCRXFCON_RXFITLMASK    0x3F00
  94 #define ASCRXFCON_RXFITLOFF     8
  95 #define ASCFSTAT_RXFFLMASK      0x003F
  96 #define ASCFSTAT_TXFFLMASK      0x3F00
  97 #define ASCFSTAT_TXFREEMASK     0x3F000000
  98 #define ASCFSTAT_TXFREEOFF      24
  99 
 100 static void lqasc_tx_chars(struct uart_port *port);
 101 static struct ltq_uart_port *lqasc_port[MAXPORTS];
 102 static struct uart_driver lqasc_reg;
 103 
 104 struct ltq_soc_data {
 105         int     (*fetch_irq)(struct device *dev, struct ltq_uart_port *ltq_port);
 106         int     (*request_irq)(struct uart_port *port);
 107         void    (*free_irq)(struct uart_port *port);
 108 };
 109 
 110 struct ltq_uart_port {
 111         struct uart_port        port;
 112         /* clock used to derive divider */
 113         struct clk              *freqclk;
 114         /* clock gating of the ASC core */
 115         struct clk              *clk;
 116         unsigned int            tx_irq;
 117         unsigned int            rx_irq;
 118         unsigned int            err_irq;
 119         unsigned int            common_irq;
 120         spinlock_t              lock; /* exclusive access for multi core */
 121 
 122         const struct ltq_soc_data       *soc;
 123 };
 124 
 125 static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
 126 {
 127         u32 tmp = __raw_readl(reg);
 128 
 129         __raw_writel((tmp & ~clear) | set, reg);
 130 }
 131 
 132 static inline struct
 133 ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
 134 {
 135         return container_of(port, struct ltq_uart_port, port);
 136 }
 137 
 138 static void
 139 lqasc_stop_tx(struct uart_port *port)
 140 {
 141         return;
 142 }
 143 
 144 static void
 145 lqasc_start_tx(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 149 
 150         spin_lock_irqsave(&ltq_port->lock, flags);
 151         lqasc_tx_chars(port);
 152         spin_unlock_irqrestore(&ltq_port->lock, flags);
 153         return;
 154 }
 155 
 156 static void
 157 lqasc_stop_rx(struct uart_port *port)
 158 {
 159         __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
 160 }
 161 
 162 static int
 163 lqasc_rx_chars(struct uart_port *port)
 164 {
 165         struct tty_port *tport = &port->state->port;
 166         unsigned int ch = 0, rsr = 0, fifocnt;
 167 
 168         fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
 169                   ASCFSTAT_RXFFLMASK;
 170         while (fifocnt--) {
 171                 u8 flag = TTY_NORMAL;
 172                 ch = readb(port->membase + LTQ_ASC_RBUF);
 173                 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
 174                         & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
 175                 tty_flip_buffer_push(tport);
 176                 port->icount.rx++;
 177 
 178                 /*
 179                  * Note that the error handling code is
 180                  * out of the main execution path
 181                  */
 182                 if (rsr & ASCSTATE_ANY) {
 183                         if (rsr & ASCSTATE_PE) {
 184                                 port->icount.parity++;
 185                                 asc_update_bits(0, ASCWHBSTATE_CLRPE,
 186                                         port->membase + LTQ_ASC_WHBSTATE);
 187                         } else if (rsr & ASCSTATE_FE) {
 188                                 port->icount.frame++;
 189                                 asc_update_bits(0, ASCWHBSTATE_CLRFE,
 190                                         port->membase + LTQ_ASC_WHBSTATE);
 191                         }
 192                         if (rsr & ASCSTATE_ROE) {
 193                                 port->icount.overrun++;
 194                                 asc_update_bits(0, ASCWHBSTATE_CLRROE,
 195                                         port->membase + LTQ_ASC_WHBSTATE);
 196                         }
 197 
 198                         rsr &= port->read_status_mask;
 199 
 200                         if (rsr & ASCSTATE_PE)
 201                                 flag = TTY_PARITY;
 202                         else if (rsr & ASCSTATE_FE)
 203                                 flag = TTY_FRAME;
 204                 }
 205 
 206                 if ((rsr & port->ignore_status_mask) == 0)
 207                         tty_insert_flip_char(tport, ch, flag);
 208 
 209                 if (rsr & ASCSTATE_ROE)
 210                         /*
 211                          * Overrun is special, since it's reported
 212                          * immediately, and doesn't affect the current
 213                          * character
 214                          */
 215                         tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 216         }
 217 
 218         if (ch != 0)
 219                 tty_flip_buffer_push(tport);
 220 
 221         return 0;
 222 }
 223 
 224 static void
 225 lqasc_tx_chars(struct uart_port *port)
 226 {
 227         struct circ_buf *xmit = &port->state->xmit;
 228         if (uart_tx_stopped(port)) {
 229                 lqasc_stop_tx(port);
 230                 return;
 231         }
 232 
 233         while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) &
 234                 ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
 235                 if (port->x_char) {
 236                         writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
 237                         port->icount.tx++;
 238                         port->x_char = 0;
 239                         continue;
 240                 }
 241 
 242                 if (uart_circ_empty(xmit))
 243                         break;
 244 
 245                 writeb(port->state->xmit.buf[port->state->xmit.tail],
 246                         port->membase + LTQ_ASC_TBUF);
 247                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 248                 port->icount.tx++;
 249         }
 250 
 251         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 252                 uart_write_wakeup(port);
 253 }
 254 
 255 static irqreturn_t
 256 lqasc_tx_int(int irq, void *_port)
 257 {
 258         unsigned long flags;
 259         struct uart_port *port = (struct uart_port *)_port;
 260         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 261 
 262         spin_lock_irqsave(&ltq_port->lock, flags);
 263         __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
 264         spin_unlock_irqrestore(&ltq_port->lock, flags);
 265         lqasc_start_tx(port);
 266         return IRQ_HANDLED;
 267 }
 268 
 269 static irqreturn_t
 270 lqasc_err_int(int irq, void *_port)
 271 {
 272         unsigned long flags;
 273         struct uart_port *port = (struct uart_port *)_port;
 274         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 275 
 276         spin_lock_irqsave(&ltq_port->lock, flags);
 277         /* clear any pending interrupts */
 278         asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
 279                 ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
 280         spin_unlock_irqrestore(&ltq_port->lock, flags);
 281         return IRQ_HANDLED;
 282 }
 283 
 284 static irqreturn_t
 285 lqasc_rx_int(int irq, void *_port)
 286 {
 287         unsigned long flags;
 288         struct uart_port *port = (struct uart_port *)_port;
 289         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 290 
 291         spin_lock_irqsave(&ltq_port->lock, flags);
 292         __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
 293         lqasc_rx_chars(port);
 294         spin_unlock_irqrestore(&ltq_port->lock, flags);
 295         return IRQ_HANDLED;
 296 }
 297 
 298 static irqreturn_t lqasc_irq(int irq, void *p)
 299 {
 300         unsigned long flags;
 301         u32 stat;
 302         struct uart_port *port = p;
 303         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 304 
 305         spin_lock_irqsave(&ltq_port->lock, flags);
 306         stat = readl(port->membase + LTQ_ASC_IRNCR);
 307         spin_unlock_irqrestore(&ltq_port->lock, flags);
 308         if (!(stat & ASC_IRNCR_MASK))
 309                 return IRQ_NONE;
 310 
 311         if (stat & ASC_IRNCR_TIR)
 312                 lqasc_tx_int(irq, p);
 313 
 314         if (stat & ASC_IRNCR_RIR)
 315                 lqasc_rx_int(irq, p);
 316 
 317         if (stat & ASC_IRNCR_EIR)
 318                 lqasc_err_int(irq, p);
 319 
 320         return IRQ_HANDLED;
 321 }
 322 
 323 static unsigned int
 324 lqasc_tx_empty(struct uart_port *port)
 325 {
 326         int status;
 327         status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
 328                  ASCFSTAT_TXFFLMASK;
 329         return status ? 0 : TIOCSER_TEMT;
 330 }
 331 
 332 static unsigned int
 333 lqasc_get_mctrl(struct uart_port *port)
 334 {
 335         return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
 336 }
 337 
 338 static void
 339 lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
 340 {
 341 }
 342 
 343 static void
 344 lqasc_break_ctl(struct uart_port *port, int break_state)
 345 {
 346 }
 347 
 348 static int
 349 lqasc_startup(struct uart_port *port)
 350 {
 351         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 352         int retval;
 353         unsigned long flags;
 354 
 355         if (!IS_ERR(ltq_port->clk))
 356                 clk_prepare_enable(ltq_port->clk);
 357         port->uartclk = clk_get_rate(ltq_port->freqclk);
 358 
 359         spin_lock_irqsave(&ltq_port->lock, flags);
 360         asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
 361                 port->membase + LTQ_ASC_CLC);
 362 
 363         __raw_writel(0, port->membase + LTQ_ASC_PISEL);
 364         __raw_writel(
 365                 ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
 366                 ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
 367                 port->membase + LTQ_ASC_TXFCON);
 368         __raw_writel(
 369                 ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
 370                 | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
 371                 port->membase + LTQ_ASC_RXFCON);
 372         /* make sure other settings are written to hardware before
 373          * setting enable bits
 374          */
 375         wmb();
 376         asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
 377                 ASCCON_ROEN, port->membase + LTQ_ASC_CON);
 378 
 379         spin_unlock_irqrestore(&ltq_port->lock, flags);
 380 
 381         retval = ltq_port->soc->request_irq(port);
 382         if (retval)
 383                 return retval;
 384 
 385         __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
 386                 port->membase + LTQ_ASC_IRNREN);
 387         return retval;
 388 }
 389 
 390 static void
 391 lqasc_shutdown(struct uart_port *port)
 392 {
 393         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 394         unsigned long flags;
 395 
 396         ltq_port->soc->free_irq(port);
 397 
 398         spin_lock_irqsave(&ltq_port->lock, flags);
 399         __raw_writel(0, port->membase + LTQ_ASC_CON);
 400         asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
 401                 port->membase + LTQ_ASC_RXFCON);
 402         asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
 403                 port->membase + LTQ_ASC_TXFCON);
 404         spin_unlock_irqrestore(&ltq_port->lock, flags);
 405         if (!IS_ERR(ltq_port->clk))
 406                 clk_disable_unprepare(ltq_port->clk);
 407 }
 408 
 409 static void
 410 lqasc_set_termios(struct uart_port *port,
 411         struct ktermios *new, struct ktermios *old)
 412 {
 413         unsigned int cflag;
 414         unsigned int iflag;
 415         unsigned int divisor;
 416         unsigned int baud;
 417         unsigned int con = 0;
 418         unsigned long flags;
 419         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 420 
 421         cflag = new->c_cflag;
 422         iflag = new->c_iflag;
 423 
 424         switch (cflag & CSIZE) {
 425         case CS7:
 426                 con = ASCCON_M_7ASYNC;
 427                 break;
 428 
 429         case CS5:
 430         case CS6:
 431         default:
 432                 new->c_cflag &= ~ CSIZE;
 433                 new->c_cflag |= CS8;
 434                 con = ASCCON_M_8ASYNC;
 435                 break;
 436         }
 437 
 438         cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
 439 
 440         if (cflag & CSTOPB)
 441                 con |= ASCCON_STP;
 442 
 443         if (cflag & PARENB) {
 444                 if (!(cflag & PARODD))
 445                         con &= ~ASCCON_ODD;
 446                 else
 447                         con |= ASCCON_ODD;
 448         }
 449 
 450         port->read_status_mask = ASCSTATE_ROE;
 451         if (iflag & INPCK)
 452                 port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 453 
 454         port->ignore_status_mask = 0;
 455         if (iflag & IGNPAR)
 456                 port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
 457 
 458         if (iflag & IGNBRK) {
 459                 /*
 460                  * If we're ignoring parity and break indicators,
 461                  * ignore overruns too (for real raw support).
 462                  */
 463                 if (iflag & IGNPAR)
 464                         port->ignore_status_mask |= ASCSTATE_ROE;
 465         }
 466 
 467         if ((cflag & CREAD) == 0)
 468                 port->ignore_status_mask |= UART_DUMMY_UER_RX;
 469 
 470         /* set error signals  - framing, parity  and overrun, enable receiver */
 471         con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
 472 
 473         spin_lock_irqsave(&ltq_port->lock, flags);
 474 
 475         /* set up CON */
 476         asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
 477 
 478         /* Set baud rate - take a divider of 2 into account */
 479         baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
 480         divisor = uart_get_divisor(port, baud);
 481         divisor = divisor / 2 - 1;
 482 
 483         /* disable the baudrate generator */
 484         asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
 485 
 486         /* make sure the fractional divider is off */
 487         asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
 488 
 489         /* set up to use divisor of 2 */
 490         asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
 491 
 492         /* now we can write the new baudrate into the register */
 493         __raw_writel(divisor, port->membase + LTQ_ASC_BG);
 494 
 495         /* turn the baudrate generator back on */
 496         asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
 497 
 498         /* enable rx */
 499         __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
 500 
 501         spin_unlock_irqrestore(&ltq_port->lock, flags);
 502 
 503         /* Don't rewrite B0 */
 504         if (tty_termios_baud_rate(new))
 505                 tty_termios_encode_baud_rate(new, baud, baud);
 506 
 507         uart_update_timeout(port, cflag, baud);
 508 }
 509 
 510 static const char*
 511 lqasc_type(struct uart_port *port)
 512 {
 513         if (port->type == PORT_LTQ_ASC)
 514                 return DRVNAME;
 515         else
 516                 return NULL;
 517 }
 518 
 519 static void
 520 lqasc_release_port(struct uart_port *port)
 521 {
 522         struct platform_device *pdev = to_platform_device(port->dev);
 523 
 524         if (port->flags & UPF_IOREMAP) {
 525                 devm_iounmap(&pdev->dev, port->membase);
 526                 port->membase = NULL;
 527         }
 528 }
 529 
 530 static int
 531 lqasc_request_port(struct uart_port *port)
 532 {
 533         struct platform_device *pdev = to_platform_device(port->dev);
 534         struct resource *res;
 535         int size;
 536 
 537         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 538         if (!res) {
 539                 dev_err(&pdev->dev, "cannot obtain I/O memory region");
 540                 return -ENODEV;
 541         }
 542         size = resource_size(res);
 543 
 544         res = devm_request_mem_region(&pdev->dev, res->start,
 545                 size, dev_name(&pdev->dev));
 546         if (!res) {
 547                 dev_err(&pdev->dev, "cannot request I/O memory region");
 548                 return -EBUSY;
 549         }
 550 
 551         if (port->flags & UPF_IOREMAP) {
 552                 port->membase = devm_ioremap_nocache(&pdev->dev,
 553                         port->mapbase, size);
 554                 if (port->membase == NULL)
 555                         return -ENOMEM;
 556         }
 557         return 0;
 558 }
 559 
 560 static void
 561 lqasc_config_port(struct uart_port *port, int flags)
 562 {
 563         if (flags & UART_CONFIG_TYPE) {
 564                 port->type = PORT_LTQ_ASC;
 565                 lqasc_request_port(port);
 566         }
 567 }
 568 
 569 static int
 570 lqasc_verify_port(struct uart_port *port,
 571         struct serial_struct *ser)
 572 {
 573         int ret = 0;
 574         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
 575                 ret = -EINVAL;
 576         if (ser->irq < 0 || ser->irq >= NR_IRQS)
 577                 ret = -EINVAL;
 578         if (ser->baud_base < 9600)
 579                 ret = -EINVAL;
 580         return ret;
 581 }
 582 
 583 static const struct uart_ops lqasc_pops = {
 584         .tx_empty =     lqasc_tx_empty,
 585         .set_mctrl =    lqasc_set_mctrl,
 586         .get_mctrl =    lqasc_get_mctrl,
 587         .stop_tx =      lqasc_stop_tx,
 588         .start_tx =     lqasc_start_tx,
 589         .stop_rx =      lqasc_stop_rx,
 590         .break_ctl =    lqasc_break_ctl,
 591         .startup =      lqasc_startup,
 592         .shutdown =     lqasc_shutdown,
 593         .set_termios =  lqasc_set_termios,
 594         .type =         lqasc_type,
 595         .release_port = lqasc_release_port,
 596         .request_port = lqasc_request_port,
 597         .config_port =  lqasc_config_port,
 598         .verify_port =  lqasc_verify_port,
 599 };
 600 
 601 static void
 602 lqasc_console_putchar(struct uart_port *port, int ch)
 603 {
 604         int fifofree;
 605 
 606         if (!port->membase)
 607                 return;
 608 
 609         do {
 610                 fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT)
 611                         & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
 612         } while (fifofree == 0);
 613         writeb(ch, port->membase + LTQ_ASC_TBUF);
 614 }
 615 
 616 static void lqasc_serial_port_write(struct uart_port *port, const char *s,
 617                                     u_int count)
 618 {
 619         uart_console_write(port, s, count, lqasc_console_putchar);
 620 }
 621 
 622 static void
 623 lqasc_console_write(struct console *co, const char *s, u_int count)
 624 {
 625         struct ltq_uart_port *ltq_port;
 626         unsigned long flags;
 627 
 628         if (co->index >= MAXPORTS)
 629                 return;
 630 
 631         ltq_port = lqasc_port[co->index];
 632         if (!ltq_port)
 633                 return;
 634 
 635         spin_lock_irqsave(&ltq_port->lock, flags);
 636         lqasc_serial_port_write(&ltq_port->port, s, count);
 637         spin_unlock_irqrestore(&ltq_port->lock, flags);
 638 }
 639 
 640 static int __init
 641 lqasc_console_setup(struct console *co, char *options)
 642 {
 643         struct ltq_uart_port *ltq_port;
 644         struct uart_port *port;
 645         int baud = 115200;
 646         int bits = 8;
 647         int parity = 'n';
 648         int flow = 'n';
 649 
 650         if (co->index >= MAXPORTS)
 651                 return -ENODEV;
 652 
 653         ltq_port = lqasc_port[co->index];
 654         if (!ltq_port)
 655                 return -ENODEV;
 656 
 657         port = &ltq_port->port;
 658 
 659         if (!IS_ERR(ltq_port->clk))
 660                 clk_prepare_enable(ltq_port->clk);
 661 
 662         port->uartclk = clk_get_rate(ltq_port->freqclk);
 663 
 664         if (options)
 665                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 666         return uart_set_options(port, co, baud, parity, bits, flow);
 667 }
 668 
 669 static struct console lqasc_console = {
 670         .name =         "ttyLTQ",
 671         .write =        lqasc_console_write,
 672         .device =       uart_console_device,
 673         .setup =        lqasc_console_setup,
 674         .flags =        CON_PRINTBUFFER,
 675         .index =        -1,
 676         .data =         &lqasc_reg,
 677 };
 678 
 679 static int __init
 680 lqasc_console_init(void)
 681 {
 682         register_console(&lqasc_console);
 683         return 0;
 684 }
 685 console_initcall(lqasc_console_init);
 686 
 687 static void lqasc_serial_early_console_write(struct console *co,
 688                                              const char *s,
 689                                              u_int count)
 690 {
 691         struct earlycon_device *dev = co->data;
 692 
 693         lqasc_serial_port_write(&dev->port, s, count);
 694 }
 695 
 696 static int __init
 697 lqasc_serial_early_console_setup(struct earlycon_device *device,
 698                                  const char *opt)
 699 {
 700         if (!device->port.membase)
 701                 return -ENODEV;
 702 
 703         device->con->write = lqasc_serial_early_console_write;
 704         return 0;
 705 }
 706 OF_EARLYCON_DECLARE(lantiq, "lantiq,asc", lqasc_serial_early_console_setup);
 707 OF_EARLYCON_DECLARE(lantiq, "intel,lgm-asc", lqasc_serial_early_console_setup);
 708 
 709 static struct uart_driver lqasc_reg = {
 710         .owner =        THIS_MODULE,
 711         .driver_name =  DRVNAME,
 712         .dev_name =     "ttyLTQ",
 713         .major =        0,
 714         .minor =        0,
 715         .nr =           MAXPORTS,
 716         .cons =         &lqasc_console,
 717 };
 718 
 719 static int fetch_irq_lantiq(struct device *dev, struct ltq_uart_port *ltq_port)
 720 {
 721         struct uart_port *port = &ltq_port->port;
 722         struct resource irqres[3];
 723         int ret;
 724 
 725         ret = of_irq_to_resource_table(dev->of_node, irqres, 3);
 726         if (ret != 3) {
 727                 dev_err(dev,
 728                         "failed to get IRQs for serial port\n");
 729                 return -ENODEV;
 730         }
 731         ltq_port->tx_irq = irqres[0].start;
 732         ltq_port->rx_irq = irqres[1].start;
 733         ltq_port->err_irq = irqres[2].start;
 734         port->irq = irqres[0].start;
 735 
 736         return 0;
 737 }
 738 
 739 static int request_irq_lantiq(struct uart_port *port)
 740 {
 741         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 742         int retval;
 743 
 744         retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
 745                              0, "asc_tx", port);
 746         if (retval) {
 747                 dev_err(port->dev, "failed to request asc_tx\n");
 748                 return retval;
 749         }
 750 
 751         retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
 752                              0, "asc_rx", port);
 753         if (retval) {
 754                 dev_err(port->dev, "failed to request asc_rx\n");
 755                 goto err1;
 756         }
 757 
 758         retval = request_irq(ltq_port->err_irq, lqasc_err_int,
 759                              0, "asc_err", port);
 760         if (retval) {
 761                 dev_err(port->dev, "failed to request asc_err\n");
 762                 goto err2;
 763         }
 764         return 0;
 765 
 766 err2:
 767         free_irq(ltq_port->rx_irq, port);
 768 err1:
 769         free_irq(ltq_port->tx_irq, port);
 770         return retval;
 771 }
 772 
 773 static void free_irq_lantiq(struct uart_port *port)
 774 {
 775         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 776 
 777         free_irq(ltq_port->tx_irq, port);
 778         free_irq(ltq_port->rx_irq, port);
 779         free_irq(ltq_port->err_irq, port);
 780 }
 781 
 782 static int fetch_irq_intel(struct device *dev, struct ltq_uart_port *ltq_port)
 783 {
 784         struct uart_port *port = &ltq_port->port;
 785         int ret;
 786 
 787         ret = of_irq_get(dev->of_node, 0);
 788         if (ret < 0) {
 789                 dev_err(dev, "failed to fetch IRQ for serial port\n");
 790                 return ret;
 791         }
 792         ltq_port->common_irq = ret;
 793         port->irq = ret;
 794 
 795         return 0;
 796 }
 797 
 798 static int request_irq_intel(struct uart_port *port)
 799 {
 800         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 801         int retval;
 802 
 803         retval = request_irq(ltq_port->common_irq, lqasc_irq, 0,
 804                              "asc_irq", port);
 805         if (retval)
 806                 dev_err(port->dev, "failed to request asc_irq\n");
 807 
 808         return retval;
 809 }
 810 
 811 static void free_irq_intel(struct uart_port *port)
 812 {
 813         struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
 814 
 815         free_irq(ltq_port->common_irq, port);
 816 }
 817 
 818 static int __init
 819 lqasc_probe(struct platform_device *pdev)
 820 {
 821         struct device_node *node = pdev->dev.of_node;
 822         struct ltq_uart_port *ltq_port;
 823         struct uart_port *port;
 824         struct resource *mmres;
 825         int line;
 826         int ret;
 827 
 828         mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 829         if (!mmres) {
 830                 dev_err(&pdev->dev,
 831                         "failed to get memory for serial port\n");
 832                 return -ENODEV;
 833         }
 834 
 835         ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
 836                                 GFP_KERNEL);
 837         if (!ltq_port)
 838                 return -ENOMEM;
 839 
 840         port = &ltq_port->port;
 841 
 842         ltq_port->soc = of_device_get_match_data(&pdev->dev);
 843         ret = ltq_port->soc->fetch_irq(&pdev->dev, ltq_port);
 844         if (ret)
 845                 return ret;
 846 
 847         /* get serial id */
 848         line = of_alias_get_id(node, "serial");
 849         if (line < 0) {
 850                 if (IS_ENABLED(CONFIG_LANTIQ)) {
 851                         if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
 852                                 line = 0;
 853                         else
 854                                 line = 1;
 855                 } else {
 856                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
 857                                 line);
 858                         return line;
 859                 }
 860         }
 861 
 862         if (lqasc_port[line]) {
 863                 dev_err(&pdev->dev, "port %d already allocated\n", line);
 864                 return -EBUSY;
 865         }
 866 
 867         port->iotype    = SERIAL_IO_MEM;
 868         port->flags     = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
 869         port->ops       = &lqasc_pops;
 870         port->fifosize  = 16;
 871         port->type      = PORT_LTQ_ASC,
 872         port->line      = line;
 873         port->dev       = &pdev->dev;
 874         /* unused, just to be backward-compatible */
 875         port->mapbase   = mmres->start;
 876 
 877         if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
 878                 ltq_port->freqclk = clk_get_fpi();
 879         else
 880                 ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
 881 
 882 
 883         if (IS_ERR(ltq_port->freqclk)) {
 884                 pr_err("failed to get fpi clk\n");
 885                 return -ENOENT;
 886         }
 887 
 888         /* not all asc ports have clock gates, lets ignore the return code */
 889         if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
 890                 ltq_port->clk = clk_get(&pdev->dev, NULL);
 891         else
 892                 ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
 893 
 894         spin_lock_init(&ltq_port->lock);
 895         lqasc_port[line] = ltq_port;
 896         platform_set_drvdata(pdev, ltq_port);
 897 
 898         ret = uart_add_one_port(&lqasc_reg, port);
 899 
 900         return ret;
 901 }
 902 
 903 static const struct ltq_soc_data soc_data_lantiq = {
 904         .fetch_irq = fetch_irq_lantiq,
 905         .request_irq = request_irq_lantiq,
 906         .free_irq = free_irq_lantiq,
 907 };
 908 
 909 static const struct ltq_soc_data soc_data_intel = {
 910         .fetch_irq = fetch_irq_intel,
 911         .request_irq = request_irq_intel,
 912         .free_irq = free_irq_intel,
 913 };
 914 
 915 static const struct of_device_id ltq_asc_match[] = {
 916         { .compatible = "lantiq,asc", .data = &soc_data_lantiq },
 917         { .compatible = "intel,lgm-asc", .data = &soc_data_intel },
 918         {},
 919 };
 920 
 921 static struct platform_driver lqasc_driver = {
 922         .driver         = {
 923                 .name   = DRVNAME,
 924                 .of_match_table = ltq_asc_match,
 925         },
 926 };
 927 
 928 static int __init
 929 init_lqasc(void)
 930 {
 931         int ret;
 932 
 933         ret = uart_register_driver(&lqasc_reg);
 934         if (ret != 0)
 935                 return ret;
 936 
 937         ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
 938         if (ret != 0)
 939                 uart_unregister_driver(&lqasc_reg);
 940 
 941         return ret;
 942 }
 943 device_initcall(init_lqasc);

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