drivers/tty/serial/max310x.c

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This source file includes following definitions.
max310x_port_read
max310x_port_write
max310x_port_update
max3107_detect
max3108_detect
max3109_detect
max310x_power
max14830_detect
max14830_power
max310x_reg_writeable
max310x_reg_volatile
max310x_reg_precious
max310x_set_baud
max310x_update_best_err
max310x_set_ref_clk
max310x_batch_write
max310x_batch_read
max310x_handle_rx
max310x_handle_tx
max310x_start_tx
max310x_port_irq
max310x_ist
max310x_tx_proc
max310x_tx_empty
max310x_get_mctrl
max310x_md_proc
max310x_set_mctrl
max310x_break_ctl
max310x_set_termios
max310x_rs_proc
max310x_rs485_config
max310x_startup
max310x_shutdown
max310x_type
max310x_request_port
max310x_config_port
max310x_verify_port
max310x_null_void
max310x_suspend
max310x_resume
max310x_gpio_get
max310x_gpio_set
max310x_gpio_direction_input
max310x_gpio_direction_output
max310x_gpio_set_config
max310x_probe
max310x_remove
max310x_spi_probe
max310x_spi_remove
max310x_uart_init
max310x_uart_exit
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
   4  *
   5  *  Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
   6  *
   7  *  Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
   8  *  Based on max3110.c, by Feng Tang <feng.tang@intel.com>
   9  *  Based on max3107.c, by Aavamobile
  10  */
  11 
  12 #include <linux/bitops.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/device.h>
  16 #include <linux/gpio/driver.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/regmap.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/uaccess.h>
  27 
  28 #define MAX310X_NAME                    "max310x"
  29 #define MAX310X_MAJOR                   204
  30 #define MAX310X_MINOR                   209
  31 #define MAX310X_UART_NRMAX              16
  32 
  33 /* MAX310X register definitions */
  34 #define MAX310X_RHR_REG                 (0x00) /* RX FIFO */
  35 #define MAX310X_THR_REG                 (0x00) /* TX FIFO */
  36 #define MAX310X_IRQEN_REG               (0x01) /* IRQ enable */
  37 #define MAX310X_IRQSTS_REG              (0x02) /* IRQ status */
  38 #define MAX310X_LSR_IRQEN_REG           (0x03) /* LSR IRQ enable */
  39 #define MAX310X_LSR_IRQSTS_REG          (0x04) /* LSR IRQ status */
  40 #define MAX310X_REG_05                  (0x05)
  41 #define MAX310X_SPCHR_IRQEN_REG         MAX310X_REG_05 /* Special char IRQ en */
  42 #define MAX310X_SPCHR_IRQSTS_REG        (0x06) /* Special char IRQ status */
  43 #define MAX310X_STS_IRQEN_REG           (0x07) /* Status IRQ enable */
  44 #define MAX310X_STS_IRQSTS_REG          (0x08) /* Status IRQ status */
  45 #define MAX310X_MODE1_REG               (0x09) /* MODE1 */
  46 #define MAX310X_MODE2_REG               (0x0a) /* MODE2 */
  47 #define MAX310X_LCR_REG                 (0x0b) /* LCR */
  48 #define MAX310X_RXTO_REG                (0x0c) /* RX timeout */
  49 #define MAX310X_HDPIXDELAY_REG          (0x0d) /* Auto transceiver delays */
  50 #define MAX310X_IRDA_REG                (0x0e) /* IRDA settings */
  51 #define MAX310X_FLOWLVL_REG             (0x0f) /* Flow control levels */
  52 #define MAX310X_FIFOTRIGLVL_REG         (0x10) /* FIFO IRQ trigger levels */
  53 #define MAX310X_TXFIFOLVL_REG           (0x11) /* TX FIFO level */
  54 #define MAX310X_RXFIFOLVL_REG           (0x12) /* RX FIFO level */
  55 #define MAX310X_FLOWCTRL_REG            (0x13) /* Flow control */
  56 #define MAX310X_XON1_REG                (0x14) /* XON1 character */
  57 #define MAX310X_XON2_REG                (0x15) /* XON2 character */
  58 #define MAX310X_XOFF1_REG               (0x16) /* XOFF1 character */
  59 #define MAX310X_XOFF2_REG               (0x17) /* XOFF2 character */
  60 #define MAX310X_GPIOCFG_REG             (0x18) /* GPIO config */
  61 #define MAX310X_GPIODATA_REG            (0x19) /* GPIO data */
  62 #define MAX310X_PLLCFG_REG              (0x1a) /* PLL config */
  63 #define MAX310X_BRGCFG_REG              (0x1b) /* Baud rate generator conf */
  64 #define MAX310X_BRGDIVLSB_REG           (0x1c) /* Baud rate divisor LSB */
  65 #define MAX310X_BRGDIVMSB_REG           (0x1d) /* Baud rate divisor MSB */
  66 #define MAX310X_CLKSRC_REG              (0x1e) /* Clock source */
  67 #define MAX310X_REG_1F                  (0x1f)
  68 
  69 #define MAX310X_REVID_REG               MAX310X_REG_1F /* Revision ID */
  70 
  71 #define MAX310X_GLOBALIRQ_REG           MAX310X_REG_1F /* Global IRQ (RO) */
  72 #define MAX310X_GLOBALCMD_REG           MAX310X_REG_1F /* Global Command (WO) */
  73 
  74 /* Extended registers */
  75 #define MAX310X_REVID_EXTREG            MAX310X_REG_05 /* Revision ID */
  76 
  77 /* IRQ register bits */
  78 #define MAX310X_IRQ_LSR_BIT             (1 << 0) /* LSR interrupt */
  79 #define MAX310X_IRQ_SPCHR_BIT           (1 << 1) /* Special char interrupt */
  80 #define MAX310X_IRQ_STS_BIT             (1 << 2) /* Status interrupt */
  81 #define MAX310X_IRQ_RXFIFO_BIT          (1 << 3) /* RX FIFO interrupt */
  82 #define MAX310X_IRQ_TXFIFO_BIT          (1 << 4) /* TX FIFO interrupt */
  83 #define MAX310X_IRQ_TXEMPTY_BIT         (1 << 5) /* TX FIFO empty interrupt */
  84 #define MAX310X_IRQ_RXEMPTY_BIT         (1 << 6) /* RX FIFO empty interrupt */
  85 #define MAX310X_IRQ_CTS_BIT             (1 << 7) /* CTS interrupt */
  86 
  87 /* LSR register bits */
  88 #define MAX310X_LSR_RXTO_BIT            (1 << 0) /* RX timeout */
  89 #define MAX310X_LSR_RXOVR_BIT           (1 << 1) /* RX overrun */
  90 #define MAX310X_LSR_RXPAR_BIT           (1 << 2) /* RX parity error */
  91 #define MAX310X_LSR_FRERR_BIT           (1 << 3) /* Frame error */
  92 #define MAX310X_LSR_RXBRK_BIT           (1 << 4) /* RX break */
  93 #define MAX310X_LSR_RXNOISE_BIT         (1 << 5) /* RX noise */
  94 #define MAX310X_LSR_CTS_BIT             (1 << 7) /* CTS pin state */
  95 
  96 /* Special character register bits */
  97 #define MAX310X_SPCHR_XON1_BIT          (1 << 0) /* XON1 character */
  98 #define MAX310X_SPCHR_XON2_BIT          (1 << 1) /* XON2 character */
  99 #define MAX310X_SPCHR_XOFF1_BIT         (1 << 2) /* XOFF1 character */
 100 #define MAX310X_SPCHR_XOFF2_BIT         (1 << 3) /* XOFF2 character */
 101 #define MAX310X_SPCHR_BREAK_BIT         (1 << 4) /* RX break */
 102 #define MAX310X_SPCHR_MULTIDROP_BIT     (1 << 5) /* 9-bit multidrop addr char */
 103 
 104 /* Status register bits */
 105 #define MAX310X_STS_GPIO0_BIT           (1 << 0) /* GPIO 0 interrupt */
 106 #define MAX310X_STS_GPIO1_BIT           (1 << 1) /* GPIO 1 interrupt */
 107 #define MAX310X_STS_GPIO2_BIT           (1 << 2) /* GPIO 2 interrupt */
 108 #define MAX310X_STS_GPIO3_BIT           (1 << 3) /* GPIO 3 interrupt */
 109 #define MAX310X_STS_CLKREADY_BIT        (1 << 5) /* Clock ready */
 110 #define MAX310X_STS_SLEEP_BIT           (1 << 6) /* Sleep interrupt */
 111 
 112 /* MODE1 register bits */
 113 #define MAX310X_MODE1_RXDIS_BIT         (1 << 0) /* RX disable */
 114 #define MAX310X_MODE1_TXDIS_BIT         (1 << 1) /* TX disable */
 115 #define MAX310X_MODE1_TXHIZ_BIT         (1 << 2) /* TX pin three-state */
 116 #define MAX310X_MODE1_RTSHIZ_BIT        (1 << 3) /* RTS pin three-state */
 117 #define MAX310X_MODE1_TRNSCVCTRL_BIT    (1 << 4) /* Transceiver ctrl enable */
 118 #define MAX310X_MODE1_FORCESLEEP_BIT    (1 << 5) /* Force sleep mode */
 119 #define MAX310X_MODE1_AUTOSLEEP_BIT     (1 << 6) /* Auto sleep enable */
 120 #define MAX310X_MODE1_IRQSEL_BIT        (1 << 7) /* IRQ pin enable */
 121 
 122 /* MODE2 register bits */
 123 #define MAX310X_MODE2_RST_BIT           (1 << 0) /* Chip reset */
 124 #define MAX310X_MODE2_FIFORST_BIT       (1 << 1) /* FIFO reset */
 125 #define MAX310X_MODE2_RXTRIGINV_BIT     (1 << 2) /* RX FIFO INT invert */
 126 #define MAX310X_MODE2_RXEMPTINV_BIT     (1 << 3) /* RX FIFO empty INT invert */
 127 #define MAX310X_MODE2_SPCHR_BIT         (1 << 4) /* Special chr detect enable */
 128 #define MAX310X_MODE2_LOOPBACK_BIT      (1 << 5) /* Internal loopback enable */
 129 #define MAX310X_MODE2_MULTIDROP_BIT     (1 << 6) /* 9-bit multidrop enable */
 130 #define MAX310X_MODE2_ECHOSUPR_BIT      (1 << 7) /* ECHO suppression enable */
 131 
 132 /* LCR register bits */
 133 #define MAX310X_LCR_LENGTH0_BIT         (1 << 0) /* Word length bit 0 */
 134 #define MAX310X_LCR_LENGTH1_BIT         (1 << 1) /* Word length bit 1
 135                                                   *
 136                                                   * Word length bits table:
 137                                                   * 00 -> 5 bit words
 138                                                   * 01 -> 6 bit words
 139                                                   * 10 -> 7 bit words
 140                                                   * 11 -> 8 bit words
 141                                                   */
 142 #define MAX310X_LCR_STOPLEN_BIT         (1 << 2) /* STOP length bit
 143                                                   *
 144                                                   * STOP length bit table:
 145                                                   * 0 -> 1 stop bit
 146                                                   * 1 -> 1-1.5 stop bits if
 147                                                   *      word length is 5,
 148                                                   *      2 stop bits otherwise
 149                                                   */
 150 #define MAX310X_LCR_PARITY_BIT          (1 << 3) /* Parity bit enable */
 151 #define MAX310X_LCR_EVENPARITY_BIT      (1 << 4) /* Even parity bit enable */
 152 #define MAX310X_LCR_FORCEPARITY_BIT     (1 << 5) /* 9-bit multidrop parity */
 153 #define MAX310X_LCR_TXBREAK_BIT         (1 << 6) /* TX break enable */
 154 #define MAX310X_LCR_RTS_BIT             (1 << 7) /* RTS pin control */
 155 
 156 /* IRDA register bits */
 157 #define MAX310X_IRDA_IRDAEN_BIT         (1 << 0) /* IRDA mode enable */
 158 #define MAX310X_IRDA_SIR_BIT            (1 << 1) /* SIR mode enable */
 159 
 160 /* Flow control trigger level register masks */
 161 #define MAX310X_FLOWLVL_HALT_MASK       (0x000f) /* Flow control halt level */
 162 #define MAX310X_FLOWLVL_RES_MASK        (0x00f0) /* Flow control resume level */
 163 #define MAX310X_FLOWLVL_HALT(words)     ((words / 8) & 0x0f)
 164 #define MAX310X_FLOWLVL_RES(words)      (((words / 8) & 0x0f) << 4)
 165 
 166 /* FIFO interrupt trigger level register masks */
 167 #define MAX310X_FIFOTRIGLVL_TX_MASK     (0x0f) /* TX FIFO trigger level */
 168 #define MAX310X_FIFOTRIGLVL_RX_MASK     (0xf0) /* RX FIFO trigger level */
 169 #define MAX310X_FIFOTRIGLVL_TX(words)   ((words / 8) & 0x0f)
 170 #define MAX310X_FIFOTRIGLVL_RX(words)   (((words / 8) & 0x0f) << 4)
 171 
 172 /* Flow control register bits */
 173 #define MAX310X_FLOWCTRL_AUTORTS_BIT    (1 << 0) /* Auto RTS flow ctrl enable */
 174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT    (1 << 1) /* Auto CTS flow ctrl enable */
 175 #define MAX310X_FLOWCTRL_GPIADDR_BIT    (1 << 2) /* Enables that GPIO inputs
 176                                                   * are used in conjunction with
 177                                                   * XOFF2 for definition of
 178                                                   * special character */
 179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT   (1 << 3) /* Auto SW flow ctrl enable */
 180 #define MAX310X_FLOWCTRL_SWFLOW0_BIT    (1 << 4) /* SWFLOW bit 0 */
 181 #define MAX310X_FLOWCTRL_SWFLOW1_BIT    (1 << 5) /* SWFLOW bit 1
 182                                                   *
 183                                                   * SWFLOW bits 1 & 0 table:
 184                                                   * 00 -> no transmitter flow
 185                                                   *       control
 186                                                   * 01 -> receiver compares
 187                                                   *       XON2 and XOFF2
 188                                                   *       and controls
 189                                                   *       transmitter
 190                                                   * 10 -> receiver compares
 191                                                   *       XON1 and XOFF1
 192                                                   *       and controls
 193                                                   *       transmitter
 194                                                   * 11 -> receiver compares
 195                                                   *       XON1, XON2, XOFF1 and
 196                                                   *       XOFF2 and controls
 197                                                   *       transmitter
 198                                                   */
 199 #define MAX310X_FLOWCTRL_SWFLOW2_BIT    (1 << 6) /* SWFLOW bit 2 */
 200 #define MAX310X_FLOWCTRL_SWFLOW3_BIT    (1 << 7) /* SWFLOW bit 3
 201                                                   *
 202                                                   * SWFLOW bits 3 & 2 table:
 203                                                   * 00 -> no received flow
 204                                                   *       control
 205                                                   * 01 -> transmitter generates
 206                                                   *       XON2 and XOFF2
 207                                                   * 10 -> transmitter generates
 208                                                   *       XON1 and XOFF1
 209                                                   * 11 -> transmitter generates
 210                                                   *       XON1, XON2, XOFF1 and
 211                                                   *       XOFF2
 212                                                   */
 213 
 214 /* PLL configuration register masks */
 215 #define MAX310X_PLLCFG_PREDIV_MASK      (0x3f) /* PLL predivision value */
 216 #define MAX310X_PLLCFG_PLLFACTOR_MASK   (0xc0) /* PLL multiplication factor */
 217 
 218 /* Baud rate generator configuration register bits */
 219 #define MAX310X_BRGCFG_2XMODE_BIT       (1 << 4) /* Double baud rate */
 220 #define MAX310X_BRGCFG_4XMODE_BIT       (1 << 5) /* Quadruple baud rate */
 221 
 222 /* Clock source register bits */
 223 #define MAX310X_CLKSRC_CRYST_BIT        (1 << 1) /* Crystal osc enable */
 224 #define MAX310X_CLKSRC_PLL_BIT          (1 << 2) /* PLL enable */
 225 #define MAX310X_CLKSRC_PLLBYP_BIT       (1 << 3) /* PLL bypass */
 226 #define MAX310X_CLKSRC_EXTCLK_BIT       (1 << 4) /* External clock enable */
 227 #define MAX310X_CLKSRC_CLK2RTS_BIT      (1 << 7) /* Baud clk to RTS pin */
 228 
 229 /* Global commands */
 230 #define MAX310X_EXTREG_ENBL             (0xce)
 231 #define MAX310X_EXTREG_DSBL             (0xcd)
 232 
 233 /* Misc definitions */
 234 #define MAX310X_FIFO_SIZE               (128)
 235 #define MAX310x_REV_MASK                (0xf8)
 236 #define MAX310X_WRITE_BIT               0x80
 237 
 238 /* MAX3107 specific */
 239 #define MAX3107_REV_ID                  (0xa0)
 240 
 241 /* MAX3109 specific */
 242 #define MAX3109_REV_ID                  (0xc0)
 243 
 244 /* MAX14830 specific */
 245 #define MAX14830_BRGCFG_CLKDIS_BIT      (1 << 6) /* Clock Disable */
 246 #define MAX14830_REV_ID                 (0xb0)
 247 
 248 struct max310x_devtype {
 249         char    name[9];
 250         int     nr;
 251         u8      mode1;
 252         int     (*detect)(struct device *);
 253         void    (*power)(struct uart_port *, int);
 254 };
 255 
 256 struct max310x_one {
 257         struct uart_port        port;
 258         struct work_struct      tx_work;
 259         struct work_struct      md_work;
 260         struct work_struct      rs_work;
 261 
 262         u8 wr_header;
 263         u8 rd_header;
 264         u8 rx_buf[MAX310X_FIFO_SIZE];
 265 };
 266 #define to_max310x_port(_port) \
 267         container_of(_port, struct max310x_one, port)
 268 
 269 struct max310x_port {
 270         struct max310x_devtype  *devtype;
 271         struct regmap           *regmap;
 272         struct clk              *clk;
 273 #ifdef CONFIG_GPIOLIB
 274         struct gpio_chip        gpio;
 275 #endif
 276         struct max310x_one      p[0];
 277 };
 278 
 279 static struct uart_driver max310x_uart = {
 280         .owner          = THIS_MODULE,
 281         .driver_name    = MAX310X_NAME,
 282         .dev_name       = "ttyMAX",
 283         .major          = MAX310X_MAJOR,
 284         .minor          = MAX310X_MINOR,
 285         .nr             = MAX310X_UART_NRMAX,
 286 };
 287 
 288 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
 289 
 290 static u8 max310x_port_read(struct uart_port *port, u8 reg)
 291 {
 292         struct max310x_port *s = dev_get_drvdata(port->dev);
 293         unsigned int val = 0;
 294 
 295         regmap_read(s->regmap, port->iobase + reg, &val);
 296 
 297         return val;
 298 }
 299 
 300 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
 301 {
 302         struct max310x_port *s = dev_get_drvdata(port->dev);
 303 
 304         regmap_write(s->regmap, port->iobase + reg, val);
 305 }
 306 
 307 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
 308 {
 309         struct max310x_port *s = dev_get_drvdata(port->dev);
 310 
 311         regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
 312 }
 313 
 314 static int max3107_detect(struct device *dev)
 315 {
 316         struct max310x_port *s = dev_get_drvdata(dev);
 317         unsigned int val = 0;
 318         int ret;
 319 
 320         ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
 321         if (ret)
 322                 return ret;
 323 
 324         if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
 325                 dev_err(dev,
 326                         "%s ID 0x%02x does not match\n", s->devtype->name, val);
 327                 return -ENODEV;
 328         }
 329 
 330         return 0;
 331 }
 332 
 333 static int max3108_detect(struct device *dev)
 334 {
 335         struct max310x_port *s = dev_get_drvdata(dev);
 336         unsigned int val = 0;
 337         int ret;
 338 
 339         /* MAX3108 have not REV ID register, we just check default value
 340          * from clocksource register to make sure everything works.
 341          */
 342         ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
 343         if (ret)
 344                 return ret;
 345 
 346         if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
 347                 dev_err(dev, "%s not present\n", s->devtype->name);
 348                 return -ENODEV;
 349         }
 350 
 351         return 0;
 352 }
 353 
 354 static int max3109_detect(struct device *dev)
 355 {
 356         struct max310x_port *s = dev_get_drvdata(dev);
 357         unsigned int val = 0;
 358         int ret;
 359 
 360         ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
 361                            MAX310X_EXTREG_ENBL);
 362         if (ret)
 363                 return ret;
 364 
 365         regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
 366         regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
 367         if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
 368                 dev_err(dev,
 369                         "%s ID 0x%02x does not match\n", s->devtype->name, val);
 370                 return -ENODEV;
 371         }
 372 
 373         return 0;
 374 }
 375 
 376 static void max310x_power(struct uart_port *port, int on)
 377 {
 378         max310x_port_update(port, MAX310X_MODE1_REG,
 379                             MAX310X_MODE1_FORCESLEEP_BIT,
 380                             on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
 381         if (on)
 382                 msleep(50);
 383 }
 384 
 385 static int max14830_detect(struct device *dev)
 386 {
 387         struct max310x_port *s = dev_get_drvdata(dev);
 388         unsigned int val = 0;
 389         int ret;
 390 
 391         ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
 392                            MAX310X_EXTREG_ENBL);
 393         if (ret)
 394                 return ret;
 395         
 396         regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
 397         regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
 398         if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
 399                 dev_err(dev,
 400                         "%s ID 0x%02x does not match\n", s->devtype->name, val);
 401                 return -ENODEV;
 402         }
 403 
 404         return 0;
 405 }
 406 
 407 static void max14830_power(struct uart_port *port, int on)
 408 {
 409         max310x_port_update(port, MAX310X_BRGCFG_REG,
 410                             MAX14830_BRGCFG_CLKDIS_BIT,
 411                             on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
 412         if (on)
 413                 msleep(50);
 414 }
 415 
 416 static const struct max310x_devtype max3107_devtype = {
 417         .name   = "MAX3107",
 418         .nr     = 1,
 419         .mode1  = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT,
 420         .detect = max3107_detect,
 421         .power  = max310x_power,
 422 };
 423 
 424 static const struct max310x_devtype max3108_devtype = {
 425         .name   = "MAX3108",
 426         .nr     = 1,
 427         .mode1  = MAX310X_MODE1_AUTOSLEEP_BIT,
 428         .detect = max3108_detect,
 429         .power  = max310x_power,
 430 };
 431 
 432 static const struct max310x_devtype max3109_devtype = {
 433         .name   = "MAX3109",
 434         .nr     = 2,
 435         .mode1  = MAX310X_MODE1_AUTOSLEEP_BIT,
 436         .detect = max3109_detect,
 437         .power  = max310x_power,
 438 };
 439 
 440 static const struct max310x_devtype max14830_devtype = {
 441         .name   = "MAX14830",
 442         .nr     = 4,
 443         .mode1  = MAX310X_MODE1_IRQSEL_BIT,
 444         .detect = max14830_detect,
 445         .power  = max14830_power,
 446 };
 447 
 448 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
 449 {
 450         switch (reg & 0x1f) {
 451         case MAX310X_IRQSTS_REG:
 452         case MAX310X_LSR_IRQSTS_REG:
 453         case MAX310X_SPCHR_IRQSTS_REG:
 454         case MAX310X_STS_IRQSTS_REG:
 455         case MAX310X_TXFIFOLVL_REG:
 456         case MAX310X_RXFIFOLVL_REG:
 457                 return false;
 458         default:
 459                 break;
 460         }
 461 
 462         return true;
 463 }
 464 
 465 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
 466 {
 467         switch (reg & 0x1f) {
 468         case MAX310X_RHR_REG:
 469         case MAX310X_IRQSTS_REG:
 470         case MAX310X_LSR_IRQSTS_REG:
 471         case MAX310X_SPCHR_IRQSTS_REG:
 472         case MAX310X_STS_IRQSTS_REG:
 473         case MAX310X_TXFIFOLVL_REG:
 474         case MAX310X_RXFIFOLVL_REG:
 475         case MAX310X_GPIODATA_REG:
 476         case MAX310X_BRGDIVLSB_REG:
 477         case MAX310X_REG_05:
 478         case MAX310X_REG_1F:
 479                 return true;
 480         default:
 481                 break;
 482         }
 483 
 484         return false;
 485 }
 486 
 487 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
 488 {
 489         switch (reg & 0x1f) {
 490         case MAX310X_RHR_REG:
 491         case MAX310X_IRQSTS_REG:
 492         case MAX310X_SPCHR_IRQSTS_REG:
 493         case MAX310X_STS_IRQSTS_REG:
 494                 return true;
 495         default:
 496                 break;
 497         }
 498 
 499         return false;
 500 }
 501 
 502 static int max310x_set_baud(struct uart_port *port, int baud)
 503 {
 504         unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
 505 
 506         /*
 507          * Calculate the integer divisor first. Select a proper mode
 508          * in case if the requested baud is too high for the pre-defined
 509          * clocks frequency.
 510          */
 511         div = port->uartclk / baud;
 512         if (div < 8) {
 513                 /* Mode x4 */
 514                 c = 4;
 515                 mode = MAX310X_BRGCFG_4XMODE_BIT;
 516         } else if (div < 16) {
 517                 /* Mode x2 */
 518                 c = 8;
 519                 mode = MAX310X_BRGCFG_2XMODE_BIT;
 520         } else {
 521                 c = 16;
 522         }
 523 
 524         /* Calculate the divisor in accordance with the fraction coefficient */
 525         div /= c;
 526         F = c*baud;
 527 
 528         /* Calculate the baud rate fraction */
 529         if (div > 0)
 530                 frac = (16*(port->uartclk % F)) / F;
 531         else
 532                 div = 1;
 533 
 534         max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
 535         max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
 536         max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode);
 537 
 538         /* Return the actual baud rate we just programmed */
 539         return (16*port->uartclk) / (c*(16*div + frac));
 540 }
 541 
 542 static int max310x_update_best_err(unsigned long f, long *besterr)
 543 {
 544         /* Use baudrate 115200 for calculate error */
 545         long err = f % (460800 * 16);
 546 
 547         if ((*besterr < 0) || (*besterr > err)) {
 548                 *besterr = err;
 549                 return 0;
 550         }
 551 
 552         return 1;
 553 }
 554 
 555 static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
 556                                unsigned long freq, bool xtal)
 557 {
 558         unsigned int div, clksrc, pllcfg = 0;
 559         long besterr = -1;
 560         unsigned long fdiv, fmul, bestfreq = freq;
 561 
 562         /* First, update error without PLL */
 563         max310x_update_best_err(freq, &besterr);
 564 
 565         /* Try all possible PLL dividers */
 566         for (div = 1; (div <= 63) && besterr; div++) {
 567                 fdiv = DIV_ROUND_CLOSEST(freq, div);
 568 
 569                 /* Try multiplier 6 */
 570                 fmul = fdiv * 6;
 571                 if ((fdiv >= 500000) && (fdiv <= 800000))
 572                         if (!max310x_update_best_err(fmul, &besterr)) {
 573                                 pllcfg = (0 << 6) | div;
 574                                 bestfreq = fmul;
 575                         }
 576                 /* Try multiplier 48 */
 577                 fmul = fdiv * 48;
 578                 if ((fdiv >= 850000) && (fdiv <= 1200000))
 579                         if (!max310x_update_best_err(fmul, &besterr)) {
 580                                 pllcfg = (1 << 6) | div;
 581                                 bestfreq = fmul;
 582                         }
 583                 /* Try multiplier 96 */
 584                 fmul = fdiv * 96;
 585                 if ((fdiv >= 425000) && (fdiv <= 1000000))
 586                         if (!max310x_update_best_err(fmul, &besterr)) {
 587                                 pllcfg = (2 << 6) | div;
 588                                 bestfreq = fmul;
 589                         }
 590                 /* Try multiplier 144 */
 591                 fmul = fdiv * 144;
 592                 if ((fdiv >= 390000) && (fdiv <= 667000))
 593                         if (!max310x_update_best_err(fmul, &besterr)) {
 594                                 pllcfg = (3 << 6) | div;
 595                                 bestfreq = fmul;
 596                         }
 597         }
 598 
 599         /* Configure clock source */
 600         clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0);
 601 
 602         /* Configure PLL */
 603         if (pllcfg) {
 604                 clksrc |= MAX310X_CLKSRC_PLL_BIT;
 605                 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
 606         } else
 607                 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
 608 
 609         regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
 610 
 611         /* Wait for crystal */
 612         if (xtal) {
 613                 unsigned int val;
 614                 msleep(10);
 615                 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val);
 616                 if (!(val & MAX310X_STS_CLKREADY_BIT)) {
 617                         dev_warn(dev, "clock is not stable yet\n");
 618                 }
 619         }
 620 
 621         return (int)bestfreq;
 622 }
 623 
 624 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
 625 {
 626         struct max310x_one *one = to_max310x_port(port);
 627         struct spi_transfer xfer[] = {
 628                 {
 629                         .tx_buf = &one->wr_header,
 630                         .len = sizeof(one->wr_header),
 631                 }, {
 632                         .tx_buf = txbuf,
 633                         .len = len,
 634                 }
 635         };
 636         spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
 637 }
 638 
 639 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
 640 {
 641         struct max310x_one *one = to_max310x_port(port);
 642         struct spi_transfer xfer[] = {
 643                 {
 644                         .tx_buf = &one->rd_header,
 645                         .len = sizeof(one->rd_header),
 646                 }, {
 647                         .rx_buf = rxbuf,
 648                         .len = len,
 649                 }
 650         };
 651         spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
 652 }
 653 
 654 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
 655 {
 656         struct max310x_one *one = to_max310x_port(port);
 657         unsigned int sts, ch, flag, i;
 658 
 659         if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
 660                 /* We are just reading, happily ignoring any error conditions.
 661                  * Break condition, parity checking, framing errors -- they
 662                  * are all ignored. That means that we can do a batch-read.
 663                  *
 664                  * There is a small opportunity for race if the RX FIFO
 665                  * overruns while we're reading the buffer; the datasheets says
 666                  * that the LSR register applies to the "current" character.
 667                  * That's also the reason why we cannot do batched reads when
 668                  * asked to check the individual statuses.
 669                  * */
 670 
 671                 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
 672                 max310x_batch_read(port, one->rx_buf, rxlen);
 673 
 674                 port->icount.rx += rxlen;
 675                 flag = TTY_NORMAL;
 676                 sts &= port->read_status_mask;
 677 
 678                 if (sts & MAX310X_LSR_RXOVR_BIT) {
 679                         dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
 680                         port->icount.overrun++;
 681                 }
 682 
 683                 for (i = 0; i < (rxlen - 1); ++i)
 684                         uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
 685 
 686                 /*
 687                  * Handle the overrun case for the last character only, since
 688                  * the RxFIFO overflow happens after it is pushed to the FIFO
 689                  * tail.
 690                  */
 691                 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
 692                                  one->rx_buf[rxlen-1], flag);
 693 
 694         } else {
 695                 if (unlikely(rxlen >= port->fifosize)) {
 696                         dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
 697                         port->icount.buf_overrun++;
 698                         /* Ensure sanity of RX level */
 699                         rxlen = port->fifosize;
 700                 }
 701 
 702                 while (rxlen--) {
 703                         ch = max310x_port_read(port, MAX310X_RHR_REG);
 704                         sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
 705 
 706                         sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
 707                                MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
 708 
 709                         port->icount.rx++;
 710                         flag = TTY_NORMAL;
 711 
 712                         if (unlikely(sts)) {
 713                                 if (sts & MAX310X_LSR_RXBRK_BIT) {
 714                                         port->icount.brk++;
 715                                         if (uart_handle_break(port))
 716                                                 continue;
 717                                 } else if (sts & MAX310X_LSR_RXPAR_BIT)
 718                                         port->icount.parity++;
 719                                 else if (sts & MAX310X_LSR_FRERR_BIT)
 720                                         port->icount.frame++;
 721                                 else if (sts & MAX310X_LSR_RXOVR_BIT)
 722                                         port->icount.overrun++;
 723 
 724                                 sts &= port->read_status_mask;
 725                                 if (sts & MAX310X_LSR_RXBRK_BIT)
 726                                         flag = TTY_BREAK;
 727                                 else if (sts & MAX310X_LSR_RXPAR_BIT)
 728                                         flag = TTY_PARITY;
 729                                 else if (sts & MAX310X_LSR_FRERR_BIT)
 730                                         flag = TTY_FRAME;
 731                                 else if (sts & MAX310X_LSR_RXOVR_BIT)
 732                                         flag = TTY_OVERRUN;
 733                         }
 734 
 735                         if (uart_handle_sysrq_char(port, ch))
 736                                 continue;
 737 
 738                         if (sts & port->ignore_status_mask)
 739                                 continue;
 740 
 741                         uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
 742                 }
 743         }
 744 
 745         tty_flip_buffer_push(&port->state->port);
 746 }
 747 
 748 static void max310x_handle_tx(struct uart_port *port)
 749 {
 750         struct circ_buf *xmit = &port->state->xmit;
 751         unsigned int txlen, to_send, until_end;
 752 
 753         if (unlikely(port->x_char)) {
 754                 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
 755                 port->icount.tx++;
 756                 port->x_char = 0;
 757                 return;
 758         }
 759 
 760         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 761                 return;
 762 
 763         /* Get length of data pending in circular buffer */
 764         to_send = uart_circ_chars_pending(xmit);
 765         until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 766         if (likely(to_send)) {
 767                 /* Limit to size of TX FIFO */
 768                 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
 769                 txlen = port->fifosize - txlen;
 770                 to_send = (to_send > txlen) ? txlen : to_send;
 771 
 772                 if (until_end < to_send) {
 773                         /* It's a circ buffer -- wrap around.
 774                          * We could do that in one SPI transaction, but meh. */
 775                         max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
 776                         max310x_batch_write(port, xmit->buf, to_send - until_end);
 777                 } else {
 778                         max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
 779                 }
 780 
 781                 /* Add data to send */
 782                 port->icount.tx += to_send;
 783                 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
 784         }
 785 
 786         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 787                 uart_write_wakeup(port);
 788 }
 789 
 790 static void max310x_start_tx(struct uart_port *port)
 791 {
 792         struct max310x_one *one = to_max310x_port(port);
 793 
 794         schedule_work(&one->tx_work);
 795 }
 796 
 797 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
 798 {
 799         struct uart_port *port = &s->p[portno].port;
 800         irqreturn_t res = IRQ_NONE;
 801 
 802         do {
 803                 unsigned int ists, lsr, rxlen;
 804 
 805                 /* Read IRQ status & RX FIFO level */
 806                 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
 807                 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
 808                 if (!ists && !rxlen)
 809                         break;
 810 
 811                 res = IRQ_HANDLED;
 812 
 813                 if (ists & MAX310X_IRQ_CTS_BIT) {
 814                         lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
 815                         uart_handle_cts_change(port,
 816                                                !!(lsr & MAX310X_LSR_CTS_BIT));
 817                 }
 818                 if (rxlen)
 819                         max310x_handle_rx(port, rxlen);
 820                 if (ists & MAX310X_IRQ_TXEMPTY_BIT)
 821                         max310x_start_tx(port);
 822         } while (1);
 823         return res;
 824 }
 825 
 826 static irqreturn_t max310x_ist(int irq, void *dev_id)
 827 {
 828         struct max310x_port *s = (struct max310x_port *)dev_id;
 829         bool handled = false;
 830 
 831         if (s->devtype->nr > 1) {
 832                 do {
 833                         unsigned int val = ~0;
 834 
 835                         WARN_ON_ONCE(regmap_read(s->regmap,
 836                                                  MAX310X_GLOBALIRQ_REG, &val));
 837                         val = ((1 << s->devtype->nr) - 1) & ~val;
 838                         if (!val)
 839                                 break;
 840                         if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
 841                                 handled = true;
 842                 } while (1);
 843         } else {
 844                 if (max310x_port_irq(s, 0) == IRQ_HANDLED)
 845                         handled = true;
 846         }
 847 
 848         return IRQ_RETVAL(handled);
 849 }
 850 
 851 static void max310x_tx_proc(struct work_struct *ws)
 852 {
 853         struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
 854 
 855         max310x_handle_tx(&one->port);
 856 }
 857 
 858 static unsigned int max310x_tx_empty(struct uart_port *port)
 859 {
 860         u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
 861 
 862         return lvl ? 0 : TIOCSER_TEMT;
 863 }
 864 
 865 static unsigned int max310x_get_mctrl(struct uart_port *port)
 866 {
 867         /* DCD and DSR are not wired and CTS/RTS is handled automatically
 868          * so just indicate DSR and CAR asserted
 869          */
 870         return TIOCM_DSR | TIOCM_CAR;
 871 }
 872 
 873 static void max310x_md_proc(struct work_struct *ws)
 874 {
 875         struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
 876 
 877         max310x_port_update(&one->port, MAX310X_MODE2_REG,
 878                             MAX310X_MODE2_LOOPBACK_BIT,
 879                             (one->port.mctrl & TIOCM_LOOP) ?
 880                             MAX310X_MODE2_LOOPBACK_BIT : 0);
 881 }
 882 
 883 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
 884 {
 885         struct max310x_one *one = to_max310x_port(port);
 886 
 887         schedule_work(&one->md_work);
 888 }
 889 
 890 static void max310x_break_ctl(struct uart_port *port, int break_state)
 891 {
 892         max310x_port_update(port, MAX310X_LCR_REG,
 893                             MAX310X_LCR_TXBREAK_BIT,
 894                             break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
 895 }
 896 
 897 static void max310x_set_termios(struct uart_port *port,
 898                                 struct ktermios *termios,
 899                                 struct ktermios *old)
 900 {
 901         unsigned int lcr = 0, flow = 0;
 902         int baud;
 903 
 904         /* Mask termios capabilities we don't support */
 905         termios->c_cflag &= ~CMSPAR;
 906 
 907         /* Word size */
 908         switch (termios->c_cflag & CSIZE) {
 909         case CS5:
 910                 break;
 911         case CS6:
 912                 lcr = MAX310X_LCR_LENGTH0_BIT;
 913                 break;
 914         case CS7:
 915                 lcr = MAX310X_LCR_LENGTH1_BIT;
 916                 break;
 917         case CS8:
 918         default:
 919                 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
 920                 break;
 921         }
 922 
 923         /* Parity */
 924         if (termios->c_cflag & PARENB) {
 925                 lcr |= MAX310X_LCR_PARITY_BIT;
 926                 if (!(termios->c_cflag & PARODD))
 927                         lcr |= MAX310X_LCR_EVENPARITY_BIT;
 928         }
 929 
 930         /* Stop bits */
 931         if (termios->c_cflag & CSTOPB)
 932                 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
 933 
 934         /* Update LCR register */
 935         max310x_port_write(port, MAX310X_LCR_REG, lcr);
 936 
 937         /* Set read status mask */
 938         port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
 939         if (termios->c_iflag & INPCK)
 940                 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
 941                                           MAX310X_LSR_FRERR_BIT;
 942         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 943                 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
 944 
 945         /* Set status ignore mask */
 946         port->ignore_status_mask = 0;
 947         if (termios->c_iflag & IGNBRK)
 948                 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
 949         if (!(termios->c_cflag & CREAD))
 950                 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
 951                                             MAX310X_LSR_RXOVR_BIT |
 952                                             MAX310X_LSR_FRERR_BIT |
 953                                             MAX310X_LSR_RXBRK_BIT;
 954 
 955         /* Configure flow control */
 956         max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
 957         max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
 958 
 959         /* Disable transmitter before enabling AutoCTS or auto transmitter
 960          * flow control
 961          */
 962         if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) {
 963                 max310x_port_update(port, MAX310X_MODE1_REG,
 964                                     MAX310X_MODE1_TXDIS_BIT,
 965                                     MAX310X_MODE1_TXDIS_BIT);
 966         }
 967 
 968         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 969 
 970         if (termios->c_cflag & CRTSCTS) {
 971                 /* Enable AUTORTS and AUTOCTS */
 972                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 973                 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
 974                         MAX310X_FLOWCTRL_AUTORTS_BIT;
 975         }
 976         if (termios->c_iflag & IXON)
 977                 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
 978                         MAX310X_FLOWCTRL_SWFLOWEN_BIT;
 979         if (termios->c_iflag & IXOFF) {
 980                 port->status |= UPSTAT_AUTOXOFF;
 981                 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
 982                         MAX310X_FLOWCTRL_SWFLOWEN_BIT;
 983         }
 984         max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
 985 
 986         /* Enable transmitter after disabling AutoCTS and auto transmitter
 987          * flow control
 988          */
 989         if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) {
 990                 max310x_port_update(port, MAX310X_MODE1_REG,
 991                                     MAX310X_MODE1_TXDIS_BIT,
 992                                     0);
 993         }
 994 
 995         /* Get baud rate generator configuration */
 996         baud = uart_get_baud_rate(port, termios, old,
 997                                   port->uartclk / 16 / 0xffff,
 998                                   port->uartclk / 4);
 999 
1000         /* Setup baudrate generator */
1001         baud = max310x_set_baud(port, baud);
1002 
1003         /* Update timeout according to new baud rate */
1004         uart_update_timeout(port, termios->c_cflag, baud);
1005 }
1006 
1007 static void max310x_rs_proc(struct work_struct *ws)
1008 {
1009         struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
1010         unsigned int delay, mode1 = 0, mode2 = 0;
1011 
1012         delay = (one->port.rs485.delay_rts_before_send << 4) |
1013                 one->port.rs485.delay_rts_after_send;
1014         max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
1015 
1016         if (one->port.rs485.flags & SER_RS485_ENABLED) {
1017                 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
1018 
1019                 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
1020                         mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
1021         }
1022 
1023         max310x_port_update(&one->port, MAX310X_MODE1_REG,
1024                         MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
1025         max310x_port_update(&one->port, MAX310X_MODE2_REG,
1026                         MAX310X_MODE2_ECHOSUPR_BIT, mode2);
1027 }
1028 
1029 static int max310x_rs485_config(struct uart_port *port,
1030                                 struct serial_rs485 *rs485)
1031 {
1032         struct max310x_one *one = to_max310x_port(port);
1033 
1034         if ((rs485->delay_rts_before_send > 0x0f) ||
1035             (rs485->delay_rts_after_send > 0x0f))
1036                 return -ERANGE;
1037 
1038         rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX |
1039                         SER_RS485_ENABLED;
1040         memset(rs485->padding, 0, sizeof(rs485->padding));
1041         port->rs485 = *rs485;
1042 
1043         schedule_work(&one->rs_work);
1044 
1045         return 0;
1046 }
1047 
1048 static int max310x_startup(struct uart_port *port)
1049 {
1050         struct max310x_port *s = dev_get_drvdata(port->dev);
1051         unsigned int val;
1052 
1053         s->devtype->power(port, 1);
1054 
1055         /* Configure MODE1 register */
1056         max310x_port_update(port, MAX310X_MODE1_REG,
1057                             MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1058 
1059         /* Configure MODE2 register & Reset FIFOs*/
1060         val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1061         max310x_port_write(port, MAX310X_MODE2_REG, val);
1062         max310x_port_update(port, MAX310X_MODE2_REG,
1063                             MAX310X_MODE2_FIFORST_BIT, 0);
1064 
1065         /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
1066         val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) |
1067                 clamp(port->rs485.delay_rts_after_send, 0U, 15U);
1068         max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
1069 
1070         if (port->rs485.flags & SER_RS485_ENABLED) {
1071                 max310x_port_update(port, MAX310X_MODE1_REG,
1072                                     MAX310X_MODE1_TRNSCVCTRL_BIT,
1073                                     MAX310X_MODE1_TRNSCVCTRL_BIT);
1074 
1075                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1076                         max310x_port_update(port, MAX310X_MODE2_REG,
1077                                             MAX310X_MODE2_ECHOSUPR_BIT,
1078                                             MAX310X_MODE2_ECHOSUPR_BIT);
1079         }
1080 
1081         /* Configure flow control levels */
1082         /* Flow control halt level 96, resume level 48 */
1083         max310x_port_write(port, MAX310X_FLOWLVL_REG,
1084                            MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1085 
1086         /* Clear IRQ status register */
1087         max310x_port_read(port, MAX310X_IRQSTS_REG);
1088 
1089         /* Enable RX, TX, CTS change interrupts */
1090         val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1091         max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1092 
1093         return 0;
1094 }
1095 
1096 static void max310x_shutdown(struct uart_port *port)
1097 {
1098         struct max310x_port *s = dev_get_drvdata(port->dev);
1099 
1100         /* Disable all interrupts */
1101         max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1102 
1103         s->devtype->power(port, 0);
1104 }
1105 
1106 static const char *max310x_type(struct uart_port *port)
1107 {
1108         struct max310x_port *s = dev_get_drvdata(port->dev);
1109 
1110         return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1111 }
1112 
1113 static int max310x_request_port(struct uart_port *port)
1114 {
1115         /* Do nothing */
1116         return 0;
1117 }
1118 
1119 static void max310x_config_port(struct uart_port *port, int flags)
1120 {
1121         if (flags & UART_CONFIG_TYPE)
1122                 port->type = PORT_MAX310X;
1123 }
1124 
1125 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1126 {
1127         if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1128                 return -EINVAL;
1129         if (s->irq != port->irq)
1130                 return -EINVAL;
1131 
1132         return 0;
1133 }
1134 
1135 static void max310x_null_void(struct uart_port *port)
1136 {
1137         /* Do nothing */
1138 }
1139 
1140 static const struct uart_ops max310x_ops = {
1141         .tx_empty       = max310x_tx_empty,
1142         .set_mctrl      = max310x_set_mctrl,
1143         .get_mctrl      = max310x_get_mctrl,
1144         .stop_tx        = max310x_null_void,
1145         .start_tx       = max310x_start_tx,
1146         .stop_rx        = max310x_null_void,
1147         .break_ctl      = max310x_break_ctl,
1148         .startup        = max310x_startup,
1149         .shutdown       = max310x_shutdown,
1150         .set_termios    = max310x_set_termios,
1151         .type           = max310x_type,
1152         .request_port   = max310x_request_port,
1153         .release_port   = max310x_null_void,
1154         .config_port    = max310x_config_port,
1155         .verify_port    = max310x_verify_port,
1156 };
1157 
1158 static int __maybe_unused max310x_suspend(struct device *dev)
1159 {
1160         struct max310x_port *s = dev_get_drvdata(dev);
1161         int i;
1162 
1163         for (i = 0; i < s->devtype->nr; i++) {
1164                 uart_suspend_port(&max310x_uart, &s->p[i].port);
1165                 s->devtype->power(&s->p[i].port, 0);
1166         }
1167 
1168         return 0;
1169 }
1170 
1171 static int __maybe_unused max310x_resume(struct device *dev)
1172 {
1173         struct max310x_port *s = dev_get_drvdata(dev);
1174         int i;
1175 
1176         for (i = 0; i < s->devtype->nr; i++) {
1177                 s->devtype->power(&s->p[i].port, 1);
1178                 uart_resume_port(&max310x_uart, &s->p[i].port);
1179         }
1180 
1181         return 0;
1182 }
1183 
1184 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1185 
1186 #ifdef CONFIG_GPIOLIB
1187 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1188 {
1189         unsigned int val;
1190         struct max310x_port *s = gpiochip_get_data(chip);
1191         struct uart_port *port = &s->p[offset / 4].port;
1192 
1193         val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1194 
1195         return !!((val >> 4) & (1 << (offset % 4)));
1196 }
1197 
1198 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1199 {
1200         struct max310x_port *s = gpiochip_get_data(chip);
1201         struct uart_port *port = &s->p[offset / 4].port;
1202 
1203         max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1204                             value ? 1 << (offset % 4) : 0);
1205 }
1206 
1207 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1208 {
1209         struct max310x_port *s = gpiochip_get_data(chip);
1210         struct uart_port *port = &s->p[offset / 4].port;
1211 
1212         max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1213 
1214         return 0;
1215 }
1216 
1217 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1218                                          unsigned offset, int value)
1219 {
1220         struct max310x_port *s = gpiochip_get_data(chip);
1221         struct uart_port *port = &s->p[offset / 4].port;
1222 
1223         max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1224                             value ? 1 << (offset % 4) : 0);
1225         max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1226                             1 << (offset % 4));
1227 
1228         return 0;
1229 }
1230 
1231 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1232                                    unsigned long config)
1233 {
1234         struct max310x_port *s = gpiochip_get_data(chip);
1235         struct uart_port *port = &s->p[offset / 4].port;
1236 
1237         switch (pinconf_to_config_param(config)) {
1238         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1239                 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1240                                 1 << ((offset % 4) + 4),
1241                                 1 << ((offset % 4) + 4));
1242                 return 0;
1243         case PIN_CONFIG_DRIVE_PUSH_PULL:
1244                 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1245                                 1 << ((offset % 4) + 4), 0);
1246                 return 0;
1247         default:
1248                 return -ENOTSUPP;
1249         }
1250 }
1251 #endif
1252 
1253 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1254                          struct regmap *regmap, int irq)
1255 {
1256         int i, ret, fmin, fmax, freq, uartclk;
1257         struct clk *clk_osc, *clk_xtal;
1258         struct max310x_port *s;
1259         bool xtal = false;
1260 
1261         if (IS_ERR(regmap))
1262                 return PTR_ERR(regmap);
1263 
1264         /* Alloc port structure */
1265         s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL);
1266         if (!s) {
1267                 dev_err(dev, "Error allocating port structure\n");
1268                 return -ENOMEM;
1269         }
1270 
1271         clk_osc = devm_clk_get(dev, "osc");
1272         clk_xtal = devm_clk_get(dev, "xtal");
1273         if (!IS_ERR(clk_osc)) {
1274                 s->clk = clk_osc;
1275                 fmin = 500000;
1276                 fmax = 35000000;
1277         } else if (!IS_ERR(clk_xtal)) {
1278                 s->clk = clk_xtal;
1279                 fmin = 1000000;
1280                 fmax = 4000000;
1281                 xtal = true;
1282         } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1283                    PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1284                 return -EPROBE_DEFER;
1285         } else {
1286                 dev_err(dev, "Cannot get clock\n");
1287                 return -EINVAL;
1288         }
1289 
1290         ret = clk_prepare_enable(s->clk);
1291         if (ret)
1292                 return ret;
1293 
1294         freq = clk_get_rate(s->clk);
1295         /* Check frequency limits */
1296         if (freq < fmin || freq > fmax) {
1297                 ret = -ERANGE;
1298                 goto out_clk;
1299         }
1300 
1301         s->regmap = regmap;
1302         s->devtype = devtype;
1303         dev_set_drvdata(dev, s);
1304 
1305         /* Check device to ensure we are talking to what we expect */
1306         ret = devtype->detect(dev);
1307         if (ret)
1308                 goto out_clk;
1309 
1310         for (i = 0; i < devtype->nr; i++) {
1311                 unsigned int offs = i << 5;
1312 
1313                 /* Reset port */
1314                 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1315                              MAX310X_MODE2_RST_BIT);
1316                 /* Clear port reset */
1317                 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1318 
1319                 /* Wait for port startup */
1320                 do {
1321                         regmap_read(s->regmap,
1322                                     MAX310X_BRGDIVLSB_REG + offs, &ret);
1323                 } while (ret != 0x01);
1324 
1325                 regmap_write(s->regmap, MAX310X_MODE1_REG + offs,
1326                              devtype->mode1);
1327         }
1328 
1329         uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1330         dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1331 
1332         for (i = 0; i < devtype->nr; i++) {
1333                 unsigned int line;
1334 
1335                 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1336                 if (line == MAX310X_UART_NRMAX) {
1337                         ret = -ERANGE;
1338                         goto out_uart;
1339                 }
1340 
1341                 /* Initialize port data */
1342                 s->p[i].port.line       = line;
1343                 s->p[i].port.dev        = dev;
1344                 s->p[i].port.irq        = irq;
1345                 s->p[i].port.type       = PORT_MAX310X;
1346                 s->p[i].port.fifosize   = MAX310X_FIFO_SIZE;
1347                 s->p[i].port.flags      = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1348                 s->p[i].port.iotype     = UPIO_PORT;
1349                 s->p[i].port.iobase     = i * 0x20;
1350                 s->p[i].port.membase    = (void __iomem *)~0;
1351                 s->p[i].port.uartclk    = uartclk;
1352                 s->p[i].port.rs485_config = max310x_rs485_config;
1353                 s->p[i].port.ops        = &max310x_ops;
1354                 /* Disable all interrupts */
1355                 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1356                 /* Clear IRQ status register */
1357                 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1358                 /* Initialize queue for start TX */
1359                 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
1360                 /* Initialize queue for changing LOOPBACK mode */
1361                 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1362                 /* Initialize queue for changing RS485 mode */
1363                 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1364                 /* Initialize SPI-transfer buffers */
1365                 s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) |
1366                                     MAX310X_WRITE_BIT;
1367                 s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG);
1368 
1369                 /* Register port */
1370                 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1371                 if (ret) {
1372                         s->p[i].port.dev = NULL;
1373                         goto out_uart;
1374                 }
1375                 set_bit(line, max310x_lines);
1376 
1377                 /* Go to suspend mode */
1378                 devtype->power(&s->p[i].port, 0);
1379         }
1380 
1381 #ifdef CONFIG_GPIOLIB
1382         /* Setup GPIO cotroller */
1383         s->gpio.owner           = THIS_MODULE;
1384         s->gpio.parent          = dev;
1385         s->gpio.label           = devtype->name;
1386         s->gpio.direction_input = max310x_gpio_direction_input;
1387         s->gpio.get             = max310x_gpio_get;
1388         s->gpio.direction_output= max310x_gpio_direction_output;
1389         s->gpio.set             = max310x_gpio_set;
1390         s->gpio.set_config      = max310x_gpio_set_config;
1391         s->gpio.base            = -1;
1392         s->gpio.ngpio           = devtype->nr * 4;
1393         s->gpio.can_sleep       = 1;
1394         ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1395         if (ret)
1396                 goto out_uart;
1397 #endif
1398 
1399         /* Setup interrupt */
1400         ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1401                                         IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1402         if (!ret)
1403                 return 0;
1404 
1405         dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1406 
1407 out_uart:
1408         for (i = 0; i < devtype->nr; i++) {
1409                 if (s->p[i].port.dev) {
1410                         uart_remove_one_port(&max310x_uart, &s->p[i].port);
1411                         clear_bit(s->p[i].port.line, max310x_lines);
1412                 }
1413         }
1414 
1415 out_clk:
1416         clk_disable_unprepare(s->clk);
1417 
1418         return ret;
1419 }
1420 
1421 static int max310x_remove(struct device *dev)
1422 {
1423         struct max310x_port *s = dev_get_drvdata(dev);
1424         int i;
1425 
1426         for (i = 0; i < s->devtype->nr; i++) {
1427                 cancel_work_sync(&s->p[i].tx_work);
1428                 cancel_work_sync(&s->p[i].md_work);
1429                 cancel_work_sync(&s->p[i].rs_work);
1430                 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1431                 clear_bit(s->p[i].port.line, max310x_lines);
1432                 s->devtype->power(&s->p[i].port, 0);
1433         }
1434 
1435         clk_disable_unprepare(s->clk);
1436 
1437         return 0;
1438 }
1439 
1440 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1441         { .compatible = "maxim,max3107",        .data = &max3107_devtype, },
1442         { .compatible = "maxim,max3108",        .data = &max3108_devtype, },
1443         { .compatible = "maxim,max3109",        .data = &max3109_devtype, },
1444         { .compatible = "maxim,max14830",       .data = &max14830_devtype },
1445         { }
1446 };
1447 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1448 
1449 static struct regmap_config regcfg = {
1450         .reg_bits = 8,
1451         .val_bits = 8,
1452         .write_flag_mask = MAX310X_WRITE_BIT,
1453         .cache_type = REGCACHE_RBTREE,
1454         .writeable_reg = max310x_reg_writeable,
1455         .volatile_reg = max310x_reg_volatile,
1456         .precious_reg = max310x_reg_precious,
1457 };
1458 
1459 #ifdef CONFIG_SPI_MASTER
1460 static int max310x_spi_probe(struct spi_device *spi)
1461 {
1462         struct max310x_devtype *devtype;
1463         struct regmap *regmap;
1464         int ret;
1465 
1466         /* Setup SPI bus */
1467         spi->bits_per_word      = 8;
1468         spi->mode               = spi->mode ? : SPI_MODE_0;
1469         spi->max_speed_hz       = spi->max_speed_hz ? : 26000000;
1470         ret = spi_setup(spi);
1471         if (ret)
1472                 return ret;
1473 
1474         if (spi->dev.of_node) {
1475                 const struct of_device_id *of_id =
1476                         of_match_device(max310x_dt_ids, &spi->dev);
1477                 if (!of_id)
1478                         return -ENODEV;
1479 
1480                 devtype = (struct max310x_devtype *)of_id->data;
1481         } else {
1482                 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1483 
1484                 devtype = (struct max310x_devtype *)id_entry->driver_data;
1485         }
1486 
1487         regcfg.max_register = devtype->nr * 0x20 - 1;
1488         regmap = devm_regmap_init_spi(spi, &regcfg);
1489 
1490         return max310x_probe(&spi->dev, devtype, regmap, spi->irq);
1491 }
1492 
1493 static int max310x_spi_remove(struct spi_device *spi)
1494 {
1495         return max310x_remove(&spi->dev);
1496 }
1497 
1498 static const struct spi_device_id max310x_id_table[] = {
1499         { "max3107",    (kernel_ulong_t)&max3107_devtype, },
1500         { "max3108",    (kernel_ulong_t)&max3108_devtype, },
1501         { "max3109",    (kernel_ulong_t)&max3109_devtype, },
1502         { "max14830",   (kernel_ulong_t)&max14830_devtype, },
1503         { }
1504 };
1505 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1506 
1507 static struct spi_driver max310x_spi_driver = {
1508         .driver = {
1509                 .name           = MAX310X_NAME,
1510                 .of_match_table = of_match_ptr(max310x_dt_ids),
1511                 .pm             = &max310x_pm_ops,
1512         },
1513         .probe          = max310x_spi_probe,
1514         .remove         = max310x_spi_remove,
1515         .id_table       = max310x_id_table,
1516 };
1517 #endif
1518 
1519 static int __init max310x_uart_init(void)
1520 {
1521         int ret;
1522 
1523         bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1524 
1525         ret = uart_register_driver(&max310x_uart);
1526         if (ret)
1527                 return ret;
1528 
1529 #ifdef CONFIG_SPI_MASTER
1530         ret = spi_register_driver(&max310x_spi_driver);
1531 #endif
1532 
1533         return ret;
1534 }
1535 module_init(max310x_uart_init);
1536 
1537 static void __exit max310x_uart_exit(void)
1538 {
1539 #ifdef CONFIG_SPI_MASTER
1540         spi_unregister_driver(&max310x_spi_driver);
1541 #endif
1542 
1543         uart_unregister_driver(&max310x_uart);
1544 }
1545 module_exit(max310x_uart_exit);
1546 
1547 MODULE_LICENSE("GPL");
1548 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1549 MODULE_DESCRIPTION("MAX310X serial driver");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/max310x.c

DEFINITIONS
