drivers/tty/serial/8250/8250

/* [<][>][^][v][top][bottom][index][help] */
This source file includes following definitions.
default_serial_dl_read
default_serial_dl_write
au_serial_in
au_serial_out
au_serial_dl_read
au_serial_dl_write
hub6_serial_in
hub6_serial_out
mem_serial_in
mem_serial_out
mem16_serial_out
mem16_serial_in
mem32_serial_out
mem32_serial_in
mem32be_serial_out
mem32be_serial_in
io_serial_in
io_serial_out
set_io_from_upio
serial_port_out_sync
serial_icr_write
serial_icr_read
serial8250_clear_fifos
serial8250_em485_rts_after_send
serial8250_clear_and_reinit_fifos
serial8250_rpm_get
serial8250_rpm_put
serial8250_em485_init
serial8250_em485_destroy
serial8250_rpm_get_tx
serial8250_rpm_put_tx
serial8250_set_sleep
__enable_rsa
enable_rsa
disable_rsa
size_fifo
autoconfig_read_divisor_id
autoconfig_has_efr
autoconfig_8250
broken_efr
autoconfig_16550a
autoconfig
autoconfig_irq
serial8250_stop_rx
__do_stop_tx_rs485
serial8250_em485_handle_stop_tx
start_hrtimer_ms
__stop_tx_rs485
__do_stop_tx
__stop_tx
serial8250_stop_tx
__start_tx
start_tx_rs485
serial8250_em485_handle_start_tx
serial8250_start_tx
serial8250_throttle
serial8250_unthrottle
serial8250_disable_ms
serial8250_enable_ms
serial8250_read_char
serial8250_rx_chars
serial8250_tx_chars
serial8250_modem_status
handle_rx_dma
serial8250_handle_irq
serial8250_default_handle_irq
serial8250_tx_threshold_handle_irq
serial8250_tx_empty
serial8250_do_get_mctrl
serial8250_get_mctrl
serial8250_do_set_mctrl
serial8250_set_mctrl
serial8250_break_ctl
wait_for_xmitr
serial8250_get_poll_char
serial8250_put_poll_char
serial8250_do_startup
serial8250_startup
serial8250_do_shutdown
serial8250_shutdown
npcm_get_divisor
serial8250_do_get_divisor
serial8250_get_divisor
serial8250_compute_lcr
serial8250_do_set_divisor
serial8250_set_divisor
serial8250_get_baud_rate
serial8250_do_set_termios
serial8250_set_termios
serial8250_do_set_ldisc
serial8250_set_ldisc
serial8250_do_pm
serial8250_pm
serial8250_port_size
serial8250_request_std_resource
serial8250_release_std_resource
serial8250_release_port
serial8250_request_port
fcr_get_rxtrig_bytes
bytes_to_fcr_rxtrig
do_get_rxtrig
do_serial8250_get_rxtrig
serial8250_get_attr_rx_trig_bytes
do_set_rxtrig
do_serial8250_set_rxtrig
serial8250_set_attr_rx_trig_bytes
register_dev_spec_attr_grp
serial8250_config_port
serial8250_verify_port
serial8250_type
serial8250_init_port
serial8250_set_defaults
serial8250_console_putchar
serial8250_console_restore
serial8250_console_write
probe_baud
serial8250_console_setup
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Base port operations for 8250/16550-type serial ports
   4  *
   5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   6  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
   7  *
   8  * A note about mapbase / membase
   9  *
  10  *  mapbase is the physical address of the IO port.
  11  *  membase is an 'ioremapped' cookie.
  12  */
  13 
  14 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  15 #define SUPPORT_SYSRQ
  16 #endif
  17 
  18 #include <linux/module.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/ioport.h>
  21 #include <linux/init.h>
  22 #include <linux/console.h>
  23 #include <linux/sysrq.h>
  24 #include <linux/delay.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/tty.h>
  27 #include <linux/ratelimit.h>
  28 #include <linux/tty_flip.h>
  29 #include <linux/serial.h>
  30 #include <linux/serial_8250.h>
  31 #include <linux/nmi.h>
  32 #include <linux/mutex.h>
  33 #include <linux/slab.h>
  34 #include <linux/uaccess.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/ktime.h>
  37 
  38 #include <asm/io.h>
  39 #include <asm/irq.h>
  40 
  41 #include "8250.h"
  42 
  43 /* Nuvoton NPCM timeout register */
  44 #define UART_NPCM_TOR          7
  45 #define UART_NPCM_TOIE         BIT(7)  /* Timeout Interrupt Enable */
  46 
  47 /*
  48  * Debugging.
  49  */
  50 #if 0
  51 #define DEBUG_AUTOCONF(fmt...)  printk(fmt)
  52 #else
  53 #define DEBUG_AUTOCONF(fmt...)  do { } while (0)
  54 #endif
  55 
  56 #define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
  57 
  58 /*
  59  * Here we define the default xmit fifo size used for each type of UART.
  60  */
  61 static const struct serial8250_config uart_config[] = {
  62         [PORT_UNKNOWN] = {
  63                 .name           = "unknown",
  64                 .fifo_size      = 1,
  65                 .tx_loadsz      = 1,
  66         },
  67         [PORT_8250] = {
  68                 .name           = "8250",
  69                 .fifo_size      = 1,
  70                 .tx_loadsz      = 1,
  71         },
  72         [PORT_16450] = {
  73                 .name           = "16450",
  74                 .fifo_size      = 1,
  75                 .tx_loadsz      = 1,
  76         },
  77         [PORT_16550] = {
  78                 .name           = "16550",
  79                 .fifo_size      = 1,
  80                 .tx_loadsz      = 1,
  81         },
  82         [PORT_16550A] = {
  83                 .name           = "16550A",
  84                 .fifo_size      = 16,
  85                 .tx_loadsz      = 16,
  86                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
  87                 .rxtrig_bytes   = {1, 4, 8, 14},
  88                 .flags          = UART_CAP_FIFO,
  89         },
  90         [PORT_CIRRUS] = {
  91                 .name           = "Cirrus",
  92                 .fifo_size      = 1,
  93                 .tx_loadsz      = 1,
  94         },
  95         [PORT_16650] = {
  96                 .name           = "ST16650",
  97                 .fifo_size      = 1,
  98                 .tx_loadsz      = 1,
  99                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 100         },
 101         [PORT_16650V2] = {
 102                 .name           = "ST16650V2",
 103                 .fifo_size      = 32,
 104                 .tx_loadsz      = 16,
 105                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
 106                                   UART_FCR_T_TRIG_00,
 107                 .rxtrig_bytes   = {8, 16, 24, 28},
 108                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 109         },
 110         [PORT_16750] = {
 111                 .name           = "TI16750",
 112                 .fifo_size      = 64,
 113                 .tx_loadsz      = 64,
 114                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
 115                                   UART_FCR7_64BYTE,
 116                 .rxtrig_bytes   = {1, 16, 32, 56},
 117                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
 118         },
 119         [PORT_STARTECH] = {
 120                 .name           = "Startech",
 121                 .fifo_size      = 1,
 122                 .tx_loadsz      = 1,
 123         },
 124         [PORT_16C950] = {
 125                 .name           = "16C950/954",
 126                 .fifo_size      = 128,
 127                 .tx_loadsz      = 128,
 128                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 129                 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
 130                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
 131         },
 132         [PORT_16654] = {
 133                 .name           = "ST16654",
 134                 .fifo_size      = 64,
 135                 .tx_loadsz      = 32,
 136                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
 137                                   UART_FCR_T_TRIG_10,
 138                 .rxtrig_bytes   = {8, 16, 56, 60},
 139                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 140         },
 141         [PORT_16850] = {
 142                 .name           = "XR16850",
 143                 .fifo_size      = 128,
 144                 .tx_loadsz      = 128,
 145                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 146                 .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
 147         },
 148         [PORT_RSA] = {
 149                 .name           = "RSA",
 150                 .fifo_size      = 2048,
 151                 .tx_loadsz      = 2048,
 152                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
 153                 .flags          = UART_CAP_FIFO,
 154         },
 155         [PORT_NS16550A] = {
 156                 .name           = "NS16550A",
 157                 .fifo_size      = 16,
 158                 .tx_loadsz      = 16,
 159                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 160                 .flags          = UART_CAP_FIFO | UART_NATSEMI,
 161         },
 162         [PORT_XSCALE] = {
 163                 .name           = "XScale",
 164                 .fifo_size      = 32,
 165                 .tx_loadsz      = 32,
 166                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 167                 .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
 168         },
 169         [PORT_OCTEON] = {
 170                 .name           = "OCTEON",
 171                 .fifo_size      = 64,
 172                 .tx_loadsz      = 64,
 173                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 174                 .flags          = UART_CAP_FIFO,
 175         },
 176         [PORT_AR7] = {
 177                 .name           = "AR7",
 178                 .fifo_size      = 16,
 179                 .tx_loadsz      = 16,
 180                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
 181                 .flags          = UART_CAP_FIFO /* | UART_CAP_AFE */,
 182         },
 183         [PORT_U6_16550A] = {
 184                 .name           = "U6_16550A",
 185                 .fifo_size      = 64,
 186                 .tx_loadsz      = 64,
 187                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 188                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 189         },
 190         [PORT_TEGRA] = {
 191                 .name           = "Tegra",
 192                 .fifo_size      = 32,
 193                 .tx_loadsz      = 8,
 194                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
 195                                   UART_FCR_T_TRIG_01,
 196                 .rxtrig_bytes   = {1, 4, 8, 14},
 197                 .flags          = UART_CAP_FIFO | UART_CAP_RTOIE,
 198         },
 199         [PORT_XR17D15X] = {
 200                 .name           = "XR17D15X",
 201                 .fifo_size      = 64,
 202                 .tx_loadsz      = 64,
 203                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 204                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
 205                                   UART_CAP_SLEEP,
 206         },
 207         [PORT_XR17V35X] = {
 208                 .name           = "XR17V35X",
 209                 .fifo_size      = 256,
 210                 .tx_loadsz      = 256,
 211                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
 212                                   UART_FCR_T_TRIG_11,
 213                 .flags          = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
 214                                   UART_CAP_SLEEP,
 215         },
 216         [PORT_LPC3220] = {
 217                 .name           = "LPC3220",
 218                 .fifo_size      = 64,
 219                 .tx_loadsz      = 32,
 220                 .fcr            = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
 221                                   UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
 222                 .flags          = UART_CAP_FIFO,
 223         },
 224         [PORT_BRCM_TRUMANAGE] = {
 225                 .name           = "TruManage",
 226                 .fifo_size      = 1,
 227                 .tx_loadsz      = 1024,
 228                 .flags          = UART_CAP_HFIFO,
 229         },
 230         [PORT_8250_CIR] = {
 231                 .name           = "CIR port"
 232         },
 233         [PORT_ALTR_16550_F32] = {
 234                 .name           = "Altera 16550 FIFO32",
 235                 .fifo_size      = 32,
 236                 .tx_loadsz      = 32,
 237                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 238                 .rxtrig_bytes   = {1, 8, 16, 30},
 239                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 240         },
 241         [PORT_ALTR_16550_F64] = {
 242                 .name           = "Altera 16550 FIFO64",
 243                 .fifo_size      = 64,
 244                 .tx_loadsz      = 64,
 245                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 246                 .rxtrig_bytes   = {1, 16, 32, 62},
 247                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 248         },
 249         [PORT_ALTR_16550_F128] = {
 250                 .name           = "Altera 16550 FIFO128",
 251                 .fifo_size      = 128,
 252                 .tx_loadsz      = 128,
 253                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 254                 .rxtrig_bytes   = {1, 32, 64, 126},
 255                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 256         },
 257         /*
 258          * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
 259          * workaround of errata A-008006 which states that tx_loadsz should
 260          * be configured less than Maximum supported fifo bytes.
 261          */
 262         [PORT_16550A_FSL64] = {
 263                 .name           = "16550A_FSL64",
 264                 .fifo_size      = 64,
 265                 .tx_loadsz      = 63,
 266                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
 267                                   UART_FCR7_64BYTE,
 268                 .flags          = UART_CAP_FIFO,
 269         },
 270         [PORT_RT2880] = {
 271                 .name           = "Palmchip BK-3103",
 272                 .fifo_size      = 16,
 273                 .tx_loadsz      = 16,
 274                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 275                 .rxtrig_bytes   = {1, 4, 8, 14},
 276                 .flags          = UART_CAP_FIFO,
 277         },
 278         [PORT_DA830] = {
 279                 .name           = "TI DA8xx/66AK2x",
 280                 .fifo_size      = 16,
 281                 .tx_loadsz      = 16,
 282                 .fcr            = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
 283                                   UART_FCR_R_TRIG_10,
 284                 .rxtrig_bytes   = {1, 4, 8, 14},
 285                 .flags          = UART_CAP_FIFO | UART_CAP_AFE,
 286         },
 287         [PORT_MTK_BTIF] = {
 288                 .name           = "MediaTek BTIF",
 289                 .fifo_size      = 16,
 290                 .tx_loadsz      = 16,
 291                 .fcr            = UART_FCR_ENABLE_FIFO |
 292                                   UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
 293                 .flags          = UART_CAP_FIFO,
 294         },
 295         [PORT_NPCM] = {
 296                 .name           = "Nuvoton 16550",
 297                 .fifo_size      = 16,
 298                 .tx_loadsz      = 16,
 299                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
 300                                   UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
 301                 .rxtrig_bytes   = {1, 4, 8, 14},
 302                 .flags          = UART_CAP_FIFO,
 303         },
 304         [PORT_SUNIX] = {
 305                 .name           = "Sunix",
 306                 .fifo_size      = 128,
 307                 .tx_loadsz      = 128,
 308                 .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 309                 .rxtrig_bytes   = {1, 32, 64, 112},
 310                 .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
 311         },
 312 };
 313 
 314 /* Uart divisor latch read */
 315 static int default_serial_dl_read(struct uart_8250_port *up)
 316 {
 317         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
 318 }
 319 
 320 /* Uart divisor latch write */
 321 static void default_serial_dl_write(struct uart_8250_port *up, int value)
 322 {
 323         serial_out(up, UART_DLL, value & 0xff);
 324         serial_out(up, UART_DLM, value >> 8 & 0xff);
 325 }
 326 
 327 #ifdef CONFIG_SERIAL_8250_RT288X
 328 
 329 /* Au1x00/RT288x UART hardware has a weird register layout */
 330 static const s8 au_io_in_map[8] = {
 331          0,     /* UART_RX  */
 332          2,     /* UART_IER */
 333          3,     /* UART_IIR */
 334          5,     /* UART_LCR */
 335          6,     /* UART_MCR */
 336          7,     /* UART_LSR */
 337          8,     /* UART_MSR */
 338         -1,     /* UART_SCR (unmapped) */
 339 };
 340 
 341 static const s8 au_io_out_map[8] = {
 342          1,     /* UART_TX  */
 343          2,     /* UART_IER */
 344          4,     /* UART_FCR */
 345          5,     /* UART_LCR */
 346          6,     /* UART_MCR */
 347         -1,     /* UART_LSR (unmapped) */
 348         -1,     /* UART_MSR (unmapped) */
 349         -1,     /* UART_SCR (unmapped) */
 350 };
 351 
 352 unsigned int au_serial_in(struct uart_port *p, int offset)
 353 {
 354         if (offset >= ARRAY_SIZE(au_io_in_map))
 355                 return UINT_MAX;
 356         offset = au_io_in_map[offset];
 357         if (offset < 0)
 358                 return UINT_MAX;
 359         return __raw_readl(p->membase + (offset << p->regshift));
 360 }
 361 
 362 void au_serial_out(struct uart_port *p, int offset, int value)
 363 {
 364         if (offset >= ARRAY_SIZE(au_io_out_map))
 365                 return;
 366         offset = au_io_out_map[offset];
 367         if (offset < 0)
 368                 return;
 369         __raw_writel(value, p->membase + (offset << p->regshift));
 370 }
 371 
 372 /* Au1x00 haven't got a standard divisor latch */
 373 static int au_serial_dl_read(struct uart_8250_port *up)
 374 {
 375         return __raw_readl(up->port.membase + 0x28);
 376 }
 377 
 378 static void au_serial_dl_write(struct uart_8250_port *up, int value)
 379 {
 380         __raw_writel(value, up->port.membase + 0x28);
 381 }
 382 
 383 #endif
 384 
 385 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
 386 {
 387         offset = offset << p->regshift;
 388         outb(p->hub6 - 1 + offset, p->iobase);
 389         return inb(p->iobase + 1);
 390 }
 391 
 392 static void hub6_serial_out(struct uart_port *p, int offset, int value)
 393 {
 394         offset = offset << p->regshift;
 395         outb(p->hub6 - 1 + offset, p->iobase);
 396         outb(value, p->iobase + 1);
 397 }
 398 
 399 static unsigned int mem_serial_in(struct uart_port *p, int offset)
 400 {
 401         offset = offset << p->regshift;
 402         return readb(p->membase + offset);
 403 }
 404 
 405 static void mem_serial_out(struct uart_port *p, int offset, int value)
 406 {
 407         offset = offset << p->regshift;
 408         writeb(value, p->membase + offset);
 409 }
 410 
 411 static void mem16_serial_out(struct uart_port *p, int offset, int value)
 412 {
 413         offset = offset << p->regshift;
 414         writew(value, p->membase + offset);
 415 }
 416 
 417 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
 418 {
 419         offset = offset << p->regshift;
 420         return readw(p->membase + offset);
 421 }
 422 
 423 static void mem32_serial_out(struct uart_port *p, int offset, int value)
 424 {
 425         offset = offset << p->regshift;
 426         writel(value, p->membase + offset);
 427 }
 428 
 429 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
 430 {
 431         offset = offset << p->regshift;
 432         return readl(p->membase + offset);
 433 }
 434 
 435 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
 436 {
 437         offset = offset << p->regshift;
 438         iowrite32be(value, p->membase + offset);
 439 }
 440 
 441 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
 442 {
 443         offset = offset << p->regshift;
 444         return ioread32be(p->membase + offset);
 445 }
 446 
 447 static unsigned int io_serial_in(struct uart_port *p, int offset)
 448 {
 449         offset = offset << p->regshift;
 450         return inb(p->iobase + offset);
 451 }
 452 
 453 static void io_serial_out(struct uart_port *p, int offset, int value)
 454 {
 455         offset = offset << p->regshift;
 456         outb(value, p->iobase + offset);
 457 }
 458 
 459 static int serial8250_default_handle_irq(struct uart_port *port);
 460 
 461 static void set_io_from_upio(struct uart_port *p)
 462 {
 463         struct uart_8250_port *up = up_to_u8250p(p);
 464 
 465         up->dl_read = default_serial_dl_read;
 466         up->dl_write = default_serial_dl_write;
 467 
 468         switch (p->iotype) {
 469         case UPIO_HUB6:
 470                 p->serial_in = hub6_serial_in;
 471                 p->serial_out = hub6_serial_out;
 472                 break;
 473 
 474         case UPIO_MEM:
 475                 p->serial_in = mem_serial_in;
 476                 p->serial_out = mem_serial_out;
 477                 break;
 478 
 479         case UPIO_MEM16:
 480                 p->serial_in = mem16_serial_in;
 481                 p->serial_out = mem16_serial_out;
 482                 break;
 483 
 484         case UPIO_MEM32:
 485                 p->serial_in = mem32_serial_in;
 486                 p->serial_out = mem32_serial_out;
 487                 break;
 488 
 489         case UPIO_MEM32BE:
 490                 p->serial_in = mem32be_serial_in;
 491                 p->serial_out = mem32be_serial_out;
 492                 break;
 493 
 494 #ifdef CONFIG_SERIAL_8250_RT288X
 495         case UPIO_AU:
 496                 p->serial_in = au_serial_in;
 497                 p->serial_out = au_serial_out;
 498                 up->dl_read = au_serial_dl_read;
 499                 up->dl_write = au_serial_dl_write;
 500                 break;
 501 #endif
 502 
 503         default:
 504                 p->serial_in = io_serial_in;
 505                 p->serial_out = io_serial_out;
 506                 break;
 507         }
 508         /* Remember loaded iotype */
 509         up->cur_iotype = p->iotype;
 510         p->handle_irq = serial8250_default_handle_irq;
 511 }
 512 
 513 static void
 514 serial_port_out_sync(struct uart_port *p, int offset, int value)
 515 {
 516         switch (p->iotype) {
 517         case UPIO_MEM:
 518         case UPIO_MEM16:
 519         case UPIO_MEM32:
 520         case UPIO_MEM32BE:
 521         case UPIO_AU:
 522                 p->serial_out(p, offset, value);
 523                 p->serial_in(p, UART_LCR);      /* safe, no side-effects */
 524                 break;
 525         default:
 526                 p->serial_out(p, offset, value);
 527         }
 528 }
 529 
 530 /*
 531  * For the 16C950
 532  */
 533 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
 534 {
 535         serial_out(up, UART_SCR, offset);
 536         serial_out(up, UART_ICR, value);
 537 }
 538 
 539 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
 540 {
 541         unsigned int value;
 542 
 543         serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
 544         serial_out(up, UART_SCR, offset);
 545         value = serial_in(up, UART_ICR);
 546         serial_icr_write(up, UART_ACR, up->acr);
 547 
 548         return value;
 549 }
 550 
 551 /*
 552  * FIFO support.
 553  */
 554 static void serial8250_clear_fifos(struct uart_8250_port *p)
 555 {
 556         if (p->capabilities & UART_CAP_FIFO) {
 557                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
 558                 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
 559                                UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 560                 serial_out(p, UART_FCR, 0);
 561         }
 562 }
 563 
 564 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
 565 {
 566         unsigned char mcr = serial8250_in_MCR(p);
 567 
 568         if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
 569                 mcr |= UART_MCR_RTS;
 570         else
 571                 mcr &= ~UART_MCR_RTS;
 572         serial8250_out_MCR(p, mcr);
 573 }
 574 
 575 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
 576 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
 577 
 578 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
 579 {
 580         serial8250_clear_fifos(p);
 581         serial_out(p, UART_FCR, p->fcr);
 582 }
 583 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
 584 
 585 void serial8250_rpm_get(struct uart_8250_port *p)
 586 {
 587         if (!(p->capabilities & UART_CAP_RPM))
 588                 return;
 589         pm_runtime_get_sync(p->port.dev);
 590 }
 591 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
 592 
 593 void serial8250_rpm_put(struct uart_8250_port *p)
 594 {
 595         if (!(p->capabilities & UART_CAP_RPM))
 596                 return;
 597         pm_runtime_mark_last_busy(p->port.dev);
 598         pm_runtime_put_autosuspend(p->port.dev);
 599 }
 600 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
 601 
 602 /**
 603  *      serial8250_em485_init() - put uart_8250_port into rs485 emulating
 604  *      @p:     uart_8250_port port instance
 605  *
 606  *      The function is used to start rs485 software emulating on the
 607  *      &struct uart_8250_port* @p. Namely, RTS is switched before/after
 608  *      transmission. The function is idempotent, so it is safe to call it
 609  *      multiple times.
 610  *
 611  *      The caller MUST enable interrupt on empty shift register before
 612  *      calling serial8250_em485_init(). This interrupt is not a part of
 613  *      8250 standard, but implementation defined.
 614  *
 615  *      The function is supposed to be called from .rs485_config callback
 616  *      or from any other callback protected with p->port.lock spinlock.
 617  *
 618  *      See also serial8250_em485_destroy()
 619  *
 620  *      Return 0 - success, -errno - otherwise
 621  */
 622 int serial8250_em485_init(struct uart_8250_port *p)
 623 {
 624         if (p->em485)
 625                 return 0;
 626 
 627         p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
 628         if (!p->em485)
 629                 return -ENOMEM;
 630 
 631         hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
 632                      HRTIMER_MODE_REL);
 633         hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
 634                      HRTIMER_MODE_REL);
 635         p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
 636         p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
 637         p->em485->port = p;
 638         p->em485->active_timer = NULL;
 639         serial8250_em485_rts_after_send(p);
 640 
 641         return 0;
 642 }
 643 EXPORT_SYMBOL_GPL(serial8250_em485_init);
 644 
 645 /**
 646  *      serial8250_em485_destroy() - put uart_8250_port into normal state
 647  *      @p:     uart_8250_port port instance
 648  *
 649  *      The function is used to stop rs485 software emulating on the
 650  *      &struct uart_8250_port* @p. The function is idempotent, so it is safe to
 651  *      call it multiple times.
 652  *
 653  *      The function is supposed to be called from .rs485_config callback
 654  *      or from any other callback protected with p->port.lock spinlock.
 655  *
 656  *      See also serial8250_em485_init()
 657  */
 658 void serial8250_em485_destroy(struct uart_8250_port *p)
 659 {
 660         if (!p->em485)
 661                 return;
 662 
 663         hrtimer_cancel(&p->em485->start_tx_timer);
 664         hrtimer_cancel(&p->em485->stop_tx_timer);
 665 
 666         kfree(p->em485);
 667         p->em485 = NULL;
 668 }
 669 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
 670 
 671 /*
 672  * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
 673  * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
 674  * empty and the HW can idle again.
 675  */
 676 void serial8250_rpm_get_tx(struct uart_8250_port *p)
 677 {
 678         unsigned char rpm_active;
 679 
 680         if (!(p->capabilities & UART_CAP_RPM))
 681                 return;
 682 
 683         rpm_active = xchg(&p->rpm_tx_active, 1);
 684         if (rpm_active)
 685                 return;
 686         pm_runtime_get_sync(p->port.dev);
 687 }
 688 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
 689 
 690 void serial8250_rpm_put_tx(struct uart_8250_port *p)
 691 {
 692         unsigned char rpm_active;
 693 
 694         if (!(p->capabilities & UART_CAP_RPM))
 695                 return;
 696 
 697         rpm_active = xchg(&p->rpm_tx_active, 0);
 698         if (!rpm_active)
 699                 return;
 700         pm_runtime_mark_last_busy(p->port.dev);
 701         pm_runtime_put_autosuspend(p->port.dev);
 702 }
 703 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
 704 
 705 /*
 706  * IER sleep support.  UARTs which have EFRs need the "extended
 707  * capability" bit enabled.  Note that on XR16C850s, we need to
 708  * reset LCR to write to IER.
 709  */
 710 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
 711 {
 712         unsigned char lcr = 0, efr = 0;
 713 
 714         serial8250_rpm_get(p);
 715 
 716         if (p->capabilities & UART_CAP_SLEEP) {
 717                 if (p->capabilities & UART_CAP_EFR) {
 718                         lcr = serial_in(p, UART_LCR);
 719                         efr = serial_in(p, UART_EFR);
 720                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
 721                         serial_out(p, UART_EFR, UART_EFR_ECB);
 722                         serial_out(p, UART_LCR, 0);
 723                 }
 724                 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
 725                 if (p->capabilities & UART_CAP_EFR) {
 726                         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
 727                         serial_out(p, UART_EFR, efr);
 728                         serial_out(p, UART_LCR, lcr);
 729                 }
 730         }
 731 
 732         serial8250_rpm_put(p);
 733 }
 734 
 735 #ifdef CONFIG_SERIAL_8250_RSA
 736 /*
 737  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
 738  * We set the port uart clock rate if we succeed.
 739  */
 740 static int __enable_rsa(struct uart_8250_port *up)
 741 {
 742         unsigned char mode;
 743         int result;
 744 
 745         mode = serial_in(up, UART_RSA_MSR);
 746         result = mode & UART_RSA_MSR_FIFO;
 747 
 748         if (!result) {
 749                 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
 750                 mode = serial_in(up, UART_RSA_MSR);
 751                 result = mode & UART_RSA_MSR_FIFO;
 752         }
 753 
 754         if (result)
 755                 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
 756 
 757         return result;
 758 }
 759 
 760 static void enable_rsa(struct uart_8250_port *up)
 761 {
 762         if (up->port.type == PORT_RSA) {
 763                 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
 764                         spin_lock_irq(&up->port.lock);
 765                         __enable_rsa(up);
 766                         spin_unlock_irq(&up->port.lock);
 767                 }
 768                 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
 769                         serial_out(up, UART_RSA_FRR, 0);
 770         }
 771 }
 772 
 773 /*
 774  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
 775  * It is unknown why interrupts were disabled in here.  However,
 776  * the caller is expected to preserve this behaviour by grabbing
 777  * the spinlock before calling this function.
 778  */
 779 static void disable_rsa(struct uart_8250_port *up)
 780 {
 781         unsigned char mode;
 782         int result;
 783 
 784         if (up->port.type == PORT_RSA &&
 785             up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
 786                 spin_lock_irq(&up->port.lock);
 787 
 788                 mode = serial_in(up, UART_RSA_MSR);
 789                 result = !(mode & UART_RSA_MSR_FIFO);
 790 
 791                 if (!result) {
 792                         serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
 793                         mode = serial_in(up, UART_RSA_MSR);
 794                         result = !(mode & UART_RSA_MSR_FIFO);
 795                 }
 796 
 797                 if (result)
 798                         up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
 799                 spin_unlock_irq(&up->port.lock);
 800         }
 801 }
 802 #endif /* CONFIG_SERIAL_8250_RSA */
 803 
 804 /*
 805  * This is a quickie test to see how big the FIFO is.
 806  * It doesn't work at all the time, more's the pity.
 807  */
 808 static int size_fifo(struct uart_8250_port *up)
 809 {
 810         unsigned char old_fcr, old_mcr, old_lcr;
 811         unsigned short old_dl;
 812         int count;
 813 
 814         old_lcr = serial_in(up, UART_LCR);
 815         serial_out(up, UART_LCR, 0);
 816         old_fcr = serial_in(up, UART_FCR);
 817         old_mcr = serial8250_in_MCR(up);
 818         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 819                     UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 820         serial8250_out_MCR(up, UART_MCR_LOOP);
 821         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 822         old_dl = serial_dl_read(up);
 823         serial_dl_write(up, 0x0001);
 824         serial_out(up, UART_LCR, 0x03);
 825         for (count = 0; count < 256; count++)
 826                 serial_out(up, UART_TX, count);
 827         mdelay(20);/* FIXME - schedule_timeout */
 828         for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
 829              (count < 256); count++)
 830                 serial_in(up, UART_RX);
 831         serial_out(up, UART_FCR, old_fcr);
 832         serial8250_out_MCR(up, old_mcr);
 833         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 834         serial_dl_write(up, old_dl);
 835         serial_out(up, UART_LCR, old_lcr);
 836 
 837         return count;
 838 }
 839 
 840 /*
 841  * Read UART ID using the divisor method - set DLL and DLM to zero
 842  * and the revision will be in DLL and device type in DLM.  We
 843  * preserve the device state across this.
 844  */
 845 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
 846 {
 847         unsigned char old_lcr;
 848         unsigned int id, old_dl;
 849 
 850         old_lcr = serial_in(p, UART_LCR);
 851         serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
 852         old_dl = serial_dl_read(p);
 853         serial_dl_write(p, 0);
 854         id = serial_dl_read(p);
 855         serial_dl_write(p, old_dl);
 856 
 857         serial_out(p, UART_LCR, old_lcr);
 858 
 859         return id;
 860 }
 861 
 862 /*
 863  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
 864  * When this function is called we know it is at least a StarTech
 865  * 16650 V2, but it might be one of several StarTech UARTs, or one of
 866  * its clones.  (We treat the broken original StarTech 16650 V1 as a
 867  * 16550, and why not?  Startech doesn't seem to even acknowledge its
 868  * existence.)
 869  *
 870  * What evil have men's minds wrought...
 871  */
 872 static void autoconfig_has_efr(struct uart_8250_port *up)
 873 {
 874         unsigned int id1, id2, id3, rev;
 875 
 876         /*
 877          * Everything with an EFR has SLEEP
 878          */
 879         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
 880 
 881         /*
 882          * First we check to see if it's an Oxford Semiconductor UART.
 883          *
 884          * If we have to do this here because some non-National
 885          * Semiconductor clone chips lock up if you try writing to the
 886          * LSR register (which serial_icr_read does)
 887          */
 888 
 889         /*
 890          * Check for Oxford Semiconductor 16C950.
 891          *
 892          * EFR [4] must be set else this test fails.
 893          *
 894          * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
 895          * claims that it's needed for 952 dual UART's (which are not
 896          * recommended for new designs).
 897          */
 898         up->acr = 0;
 899         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 900         serial_out(up, UART_EFR, UART_EFR_ECB);
 901         serial_out(up, UART_LCR, 0x00);
 902         id1 = serial_icr_read(up, UART_ID1);
 903         id2 = serial_icr_read(up, UART_ID2);
 904         id3 = serial_icr_read(up, UART_ID3);
 905         rev = serial_icr_read(up, UART_REV);
 906 
 907         DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
 908 
 909         if (id1 == 0x16 && id2 == 0xC9 &&
 910             (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
 911                 up->port.type = PORT_16C950;
 912 
 913                 /*
 914                  * Enable work around for the Oxford Semiconductor 952 rev B
 915                  * chip which causes it to seriously miscalculate baud rates
 916                  * when DLL is 0.
 917                  */
 918                 if (id3 == 0x52 && rev == 0x01)
 919                         up->bugs |= UART_BUG_QUOT;
 920                 return;
 921         }
 922 
 923         /*
 924          * We check for a XR16C850 by setting DLL and DLM to 0, and then
 925          * reading back DLL and DLM.  The chip type depends on the DLM
 926          * value read back:
 927          *  0x10 - XR16C850 and the DLL contains the chip revision.
 928          *  0x12 - XR16C2850.
 929          *  0x14 - XR16C854.
 930          */
 931         id1 = autoconfig_read_divisor_id(up);
 932         DEBUG_AUTOCONF("850id=%04x ", id1);
 933 
 934         id2 = id1 >> 8;
 935         if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
 936                 up->port.type = PORT_16850;
 937                 return;
 938         }
 939 
 940         /*
 941          * It wasn't an XR16C850.
 942          *
 943          * We distinguish between the '654 and the '650 by counting
 944          * how many bytes are in the FIFO.  I'm using this for now,
 945          * since that's the technique that was sent to me in the
 946          * serial driver update, but I'm not convinced this works.
 947          * I've had problems doing this in the past.  -TYT
 948          */
 949         if (size_fifo(up) == 64)
 950                 up->port.type = PORT_16654;
 951         else
 952                 up->port.type = PORT_16650V2;
 953 }
 954 
 955 /*
 956  * We detected a chip without a FIFO.  Only two fall into
 957  * this category - the original 8250 and the 16450.  The
 958  * 16450 has a scratch register (accessible with LCR=0)
 959  */
 960 static void autoconfig_8250(struct uart_8250_port *up)
 961 {
 962         unsigned char scratch, status1, status2;
 963 
 964         up->port.type = PORT_8250;
 965 
 966         scratch = serial_in(up, UART_SCR);
 967         serial_out(up, UART_SCR, 0xa5);
 968         status1 = serial_in(up, UART_SCR);
 969         serial_out(up, UART_SCR, 0x5a);
 970         status2 = serial_in(up, UART_SCR);
 971         serial_out(up, UART_SCR, scratch);
 972 
 973         if (status1 == 0xa5 && status2 == 0x5a)
 974                 up->port.type = PORT_16450;
 975 }
 976 
 977 static int broken_efr(struct uart_8250_port *up)
 978 {
 979         /*
 980          * Exar ST16C2550 "A2" devices incorrectly detect as
 981          * having an EFR, and report an ID of 0x0201.  See
 982          * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
 983          */
 984         if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
 985                 return 1;
 986 
 987         return 0;
 988 }
 989 
 990 /*
 991  * We know that the chip has FIFOs.  Does it have an EFR?  The
 992  * EFR is located in the same register position as the IIR and
 993  * we know the top two bits of the IIR are currently set.  The
 994  * EFR should contain zero.  Try to read the EFR.
 995  */
 996 static void autoconfig_16550a(struct uart_8250_port *up)
 997 {
 998         unsigned char status1, status2;
 999         unsigned int iersave;
1000 
1001         up->port.type = PORT_16550A;
1002         up->capabilities |= UART_CAP_FIFO;
1003 
1004         /*
1005          * Check for presence of the EFR when DLAB is set.
1006          * Only ST16C650V1 UARTs pass this test.
1007          */
1008         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1009         if (serial_in(up, UART_EFR) == 0) {
1010                 serial_out(up, UART_EFR, 0xA8);
1011                 if (serial_in(up, UART_EFR) != 0) {
1012                         DEBUG_AUTOCONF("EFRv1 ");
1013                         up->port.type = PORT_16650;
1014                         up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1015                 } else {
1016                         serial_out(up, UART_LCR, 0);
1017                         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1018                                    UART_FCR7_64BYTE);
1019                         status1 = serial_in(up, UART_IIR) >> 5;
1020                         serial_out(up, UART_FCR, 0);
1021                         serial_out(up, UART_LCR, 0);
1022 
1023                         if (status1 == 7)
1024                                 up->port.type = PORT_16550A_FSL64;
1025                         else
1026                                 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1027                 }
1028                 serial_out(up, UART_EFR, 0);
1029                 return;
1030         }
1031 
1032         /*
1033          * Maybe it requires 0xbf to be written to the LCR.
1034          * (other ST16C650V2 UARTs, TI16C752A, etc)
1035          */
1036         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1037         if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1038                 DEBUG_AUTOCONF("EFRv2 ");
1039                 autoconfig_has_efr(up);
1040                 return;
1041         }
1042 
1043         /*
1044          * Check for a National Semiconductor SuperIO chip.
1045          * Attempt to switch to bank 2, read the value of the LOOP bit
1046          * from EXCR1. Switch back to bank 0, change it in MCR. Then
1047          * switch back to bank 2, read it from EXCR1 again and check
1048          * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1049          */
1050         serial_out(up, UART_LCR, 0);
1051         status1 = serial8250_in_MCR(up);
1052         serial_out(up, UART_LCR, 0xE0);
1053         status2 = serial_in(up, 0x02); /* EXCR1 */
1054 
1055         if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1056                 serial_out(up, UART_LCR, 0);
1057                 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1058                 serial_out(up, UART_LCR, 0xE0);
1059                 status2 = serial_in(up, 0x02); /* EXCR1 */
1060                 serial_out(up, UART_LCR, 0);
1061                 serial8250_out_MCR(up, status1);
1062 
1063                 if ((status2 ^ status1) & UART_MCR_LOOP) {
1064                         unsigned short quot;
1065 
1066                         serial_out(up, UART_LCR, 0xE0);
1067 
1068                         quot = serial_dl_read(up);
1069                         quot <<= 3;
1070 
1071                         if (ns16550a_goto_highspeed(up))
1072                                 serial_dl_write(up, quot);
1073 
1074                         serial_out(up, UART_LCR, 0);
1075 
1076                         up->port.uartclk = 921600*16;
1077                         up->port.type = PORT_NS16550A;
1078                         up->capabilities |= UART_NATSEMI;
1079                         return;
1080                 }
1081         }
1082 
1083         /*
1084          * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1085          * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1086          * Try setting it with and without DLAB set.  Cheap clones
1087          * set bit 5 without DLAB set.
1088          */
1089         serial_out(up, UART_LCR, 0);
1090         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1091         status1 = serial_in(up, UART_IIR) >> 5;
1092         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1093         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1094         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1095         status2 = serial_in(up, UART_IIR) >> 5;
1096         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1097         serial_out(up, UART_LCR, 0);
1098 
1099         DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1100 
1101         if (status1 == 6 && status2 == 7) {
1102                 up->port.type = PORT_16750;
1103                 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1104                 return;
1105         }
1106 
1107         /*
1108          * Try writing and reading the UART_IER_UUE bit (b6).
1109          * If it works, this is probably one of the Xscale platform's
1110          * internal UARTs.
1111          * We're going to explicitly set the UUE bit to 0 before
1112          * trying to write and read a 1 just to make sure it's not
1113          * already a 1 and maybe locked there before we even start start.
1114          */
1115         iersave = serial_in(up, UART_IER);
1116         serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1117         if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1118                 /*
1119                  * OK it's in a known zero state, try writing and reading
1120                  * without disturbing the current state of the other bits.
1121                  */
1122                 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1123                 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1124                         /*
1125                          * It's an Xscale.
1126                          * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1127                          */
1128                         DEBUG_AUTOCONF("Xscale ");
1129                         up->port.type = PORT_XSCALE;
1130                         up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1131                         return;
1132                 }
1133         } else {
1134                 /*
1135                  * If we got here we couldn't force the IER_UUE bit to 0.
1136                  * Log it and continue.
1137                  */
1138                 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1139         }
1140         serial_out(up, UART_IER, iersave);
1141 
1142         /*
1143          * We distinguish between 16550A and U6 16550A by counting
1144          * how many bytes are in the FIFO.
1145          */
1146         if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1147                 up->port.type = PORT_U6_16550A;
1148                 up->capabilities |= UART_CAP_AFE;
1149         }
1150 }
1151 
1152 /*
1153  * This routine is called by rs_init() to initialize a specific serial
1154  * port.  It determines what type of UART chip this serial port is
1155  * using: 8250, 16450, 16550, 16550A.  The important question is
1156  * whether or not this UART is a 16550A or not, since this will
1157  * determine whether or not we can use its FIFO features or not.
1158  */
1159 static void autoconfig(struct uart_8250_port *up)
1160 {
1161         unsigned char status1, scratch, scratch2, scratch3;
1162         unsigned char save_lcr, save_mcr;
1163         struct uart_port *port = &up->port;
1164         unsigned long flags;
1165         unsigned int old_capabilities;
1166 
1167         if (!port->iobase && !port->mapbase && !port->membase)
1168                 return;
1169 
1170         DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1171                        port->name, port->iobase, port->membase);
1172 
1173         /*
1174          * We really do need global IRQs disabled here - we're going to
1175          * be frobbing the chips IRQ enable register to see if it exists.
1176          */
1177         spin_lock_irqsave(&port->lock, flags);
1178 
1179         up->capabilities = 0;
1180         up->bugs = 0;
1181 
1182         if (!(port->flags & UPF_BUGGY_UART)) {
1183                 /*
1184                  * Do a simple existence test first; if we fail this,
1185                  * there's no point trying anything else.
1186                  *
1187                  * 0x80 is used as a nonsense port to prevent against
1188                  * false positives due to ISA bus float.  The
1189                  * assumption is that 0x80 is a non-existent port;
1190                  * which should be safe since include/asm/io.h also
1191                  * makes this assumption.
1192                  *
1193                  * Note: this is safe as long as MCR bit 4 is clear
1194                  * and the device is in "PC" mode.
1195                  */
1196                 scratch = serial_in(up, UART_IER);
1197                 serial_out(up, UART_IER, 0);
1198 #ifdef __i386__
1199                 outb(0xff, 0x080);
1200 #endif
1201                 /*
1202                  * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1203                  * 16C754B) allow only to modify them if an EFR bit is set.
1204                  */
1205                 scratch2 = serial_in(up, UART_IER) & 0x0f;
1206                 serial_out(up, UART_IER, 0x0F);
1207 #ifdef __i386__
1208                 outb(0, 0x080);
1209 #endif
1210                 scratch3 = serial_in(up, UART_IER) & 0x0f;
1211                 serial_out(up, UART_IER, scratch);
1212                 if (scratch2 != 0 || scratch3 != 0x0F) {
1213                         /*
1214                          * We failed; there's nothing here
1215                          */
1216                         spin_unlock_irqrestore(&port->lock, flags);
1217                         DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1218                                        scratch2, scratch3);
1219                         goto out;
1220                 }
1221         }
1222 
1223         save_mcr = serial8250_in_MCR(up);
1224         save_lcr = serial_in(up, UART_LCR);
1225 
1226         /*
1227          * Check to see if a UART is really there.  Certain broken
1228          * internal modems based on the Rockwell chipset fail this
1229          * test, because they apparently don't implement the loopback
1230          * test mode.  So this test is skipped on the COM 1 through
1231          * COM 4 ports.  This *should* be safe, since no board
1232          * manufacturer would be stupid enough to design a board
1233          * that conflicts with COM 1-4 --- we hope!
1234          */
1235         if (!(port->flags & UPF_SKIP_TEST)) {
1236                 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1237                 status1 = serial_in(up, UART_MSR) & 0xF0;
1238                 serial8250_out_MCR(up, save_mcr);
1239                 if (status1 != 0x90) {
1240                         spin_unlock_irqrestore(&port->lock, flags);
1241                         DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1242                                        status1);
1243                         goto out;
1244                 }
1245         }
1246 
1247         /*
1248          * We're pretty sure there's a port here.  Lets find out what
1249          * type of port it is.  The IIR top two bits allows us to find
1250          * out if it's 8250 or 16450, 16550, 16550A or later.  This
1251          * determines what we test for next.
1252          *
1253          * We also initialise the EFR (if any) to zero for later.  The
1254          * EFR occupies the same register location as the FCR and IIR.
1255          */
1256         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1257         serial_out(up, UART_EFR, 0);
1258         serial_out(up, UART_LCR, 0);
1259 
1260         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1261         scratch = serial_in(up, UART_IIR) >> 6;
1262 
1263         switch (scratch) {
1264         case 0:
1265                 autoconfig_8250(up);
1266                 break;
1267         case 1:
1268                 port->type = PORT_UNKNOWN;
1269                 break;
1270         case 2:
1271                 port->type = PORT_16550;
1272                 break;
1273         case 3:
1274                 autoconfig_16550a(up);
1275                 break;
1276         }
1277 
1278 #ifdef CONFIG_SERIAL_8250_RSA
1279         /*
1280          * Only probe for RSA ports if we got the region.
1281          */
1282         if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1283             __enable_rsa(up))
1284                 port->type = PORT_RSA;
1285 #endif
1286 
1287         serial_out(up, UART_LCR, save_lcr);
1288 
1289         port->fifosize = uart_config[up->port.type].fifo_size;
1290         old_capabilities = up->capabilities;
1291         up->capabilities = uart_config[port->type].flags;
1292         up->tx_loadsz = uart_config[port->type].tx_loadsz;
1293 
1294         if (port->type == PORT_UNKNOWN)
1295                 goto out_lock;
1296 
1297         /*
1298          * Reset the UART.
1299          */
1300 #ifdef CONFIG_SERIAL_8250_RSA
1301         if (port->type == PORT_RSA)
1302                 serial_out(up, UART_RSA_FRR, 0);
1303 #endif
1304         serial8250_out_MCR(up, save_mcr);
1305         serial8250_clear_fifos(up);
1306         serial_in(up, UART_RX);
1307         if (up->capabilities & UART_CAP_UUE)
1308                 serial_out(up, UART_IER, UART_IER_UUE);
1309         else
1310                 serial_out(up, UART_IER, 0);
1311 
1312 out_lock:
1313         spin_unlock_irqrestore(&port->lock, flags);
1314 
1315         /*
1316          * Check if the device is a Fintek F81216A
1317          */
1318         if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1319                 fintek_8250_probe(up);
1320 
1321         if (up->capabilities != old_capabilities) {
1322                 pr_warn("%s: detected caps %08x should be %08x\n",
1323                         port->name, old_capabilities, up->capabilities);
1324         }
1325 out:
1326         DEBUG_AUTOCONF("iir=%d ", scratch);
1327         DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1328 }
1329 
1330 static void autoconfig_irq(struct uart_8250_port *up)
1331 {
1332         struct uart_port *port = &up->port;
1333         unsigned char save_mcr, save_ier;
1334         unsigned char save_ICP = 0;
1335         unsigned int ICP = 0;
1336         unsigned long irqs;
1337         int irq;
1338 
1339         if (port->flags & UPF_FOURPORT) {
1340                 ICP = (port->iobase & 0xfe0) | 0x1f;
1341                 save_ICP = inb_p(ICP);
1342                 outb_p(0x80, ICP);
1343                 inb_p(ICP);
1344         }
1345 
1346         if (uart_console(port))
1347                 console_lock();
1348 
1349         /* forget possible initially masked and pending IRQ */
1350         probe_irq_off(probe_irq_on());
1351         save_mcr = serial8250_in_MCR(up);
1352         save_ier = serial_in(up, UART_IER);
1353         serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1354 
1355         irqs = probe_irq_on();
1356         serial8250_out_MCR(up, 0);
1357         udelay(10);
1358         if (port->flags & UPF_FOURPORT) {
1359                 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1360         } else {
1361                 serial8250_out_MCR(up,
1362                         UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1363         }
1364         serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1365         serial_in(up, UART_LSR);
1366         serial_in(up, UART_RX);
1367         serial_in(up, UART_IIR);
1368         serial_in(up, UART_MSR);
1369         serial_out(up, UART_TX, 0xFF);
1370         udelay(20);
1371         irq = probe_irq_off(irqs);
1372 
1373         serial8250_out_MCR(up, save_mcr);
1374         serial_out(up, UART_IER, save_ier);
1375 
1376         if (port->flags & UPF_FOURPORT)
1377                 outb_p(save_ICP, ICP);
1378 
1379         if (uart_console(port))
1380                 console_unlock();
1381 
1382         port->irq = (irq > 0) ? irq : 0;
1383 }
1384 
1385 static void serial8250_stop_rx(struct uart_port *port)
1386 {
1387         struct uart_8250_port *up = up_to_u8250p(port);
1388 
1389         serial8250_rpm_get(up);
1390 
1391         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1392         up->port.read_status_mask &= ~UART_LSR_DR;
1393         serial_port_out(port, UART_IER, up->ier);
1394 
1395         serial8250_rpm_put(up);
1396 }
1397 
1398 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1399 {
1400         serial8250_em485_rts_after_send(p);
1401 
1402         /*
1403          * Empty the RX FIFO, we are not interested in anything
1404          * received during the half-duplex transmission.
1405          * Enable previously disabled RX interrupts.
1406          */
1407         if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1408                 serial8250_clear_and_reinit_fifos(p);
1409 
1410                 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1411                 serial_port_out(&p->port, UART_IER, p->ier);
1412         }
1413 }
1414 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1415 {
1416         struct uart_8250_em485 *em485;
1417         struct uart_8250_port *p;
1418         unsigned long flags;
1419 
1420         em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1421         p = em485->port;
1422 
1423         serial8250_rpm_get(p);
1424         spin_lock_irqsave(&p->port.lock, flags);
1425         if (em485->active_timer == &em485->stop_tx_timer) {
1426                 __do_stop_tx_rs485(p);
1427                 em485->active_timer = NULL;
1428         }
1429         spin_unlock_irqrestore(&p->port.lock, flags);
1430         serial8250_rpm_put(p);
1431         return HRTIMER_NORESTART;
1432 }
1433 
1434 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1435 {
1436         long sec = msec / 1000;
1437         long nsec = (msec % 1000) * 1000000;
1438         ktime_t t = ktime_set(sec, nsec);
1439 
1440         hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1441 }
1442 
1443 static void __stop_tx_rs485(struct uart_8250_port *p)
1444 {
1445         struct uart_8250_em485 *em485 = p->em485;
1446 
1447         /*
1448          * __do_stop_tx_rs485 is going to set RTS according to config
1449          * AND flush RX FIFO if required.
1450          */
1451         if (p->port.rs485.delay_rts_after_send > 0) {
1452                 em485->active_timer = &em485->stop_tx_timer;
1453                 start_hrtimer_ms(&em485->stop_tx_timer,
1454                                    p->port.rs485.delay_rts_after_send);
1455         } else {
1456                 __do_stop_tx_rs485(p);
1457         }
1458 }
1459 
1460 static inline void __do_stop_tx(struct uart_8250_port *p)
1461 {
1462         if (serial8250_clear_THRI(p))
1463                 serial8250_rpm_put_tx(p);
1464 }
1465 
1466 static inline void __stop_tx(struct uart_8250_port *p)
1467 {
1468         struct uart_8250_em485 *em485 = p->em485;
1469 
1470         if (em485) {
1471                 unsigned char lsr = serial_in(p, UART_LSR);
1472                 /*
1473                  * To provide required timeing and allow FIFO transfer,
1474                  * __stop_tx_rs485() must be called only when both FIFO and
1475                  * shift register are empty. It is for device driver to enable
1476                  * interrupt on TEMT.
1477                  */
1478                 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1479                         return;
1480 
1481                 em485->active_timer = NULL;
1482 
1483                 __stop_tx_rs485(p);
1484         }
1485         __do_stop_tx(p);
1486 }
1487 
1488 static void serial8250_stop_tx(struct uart_port *port)
1489 {
1490         struct uart_8250_port *up = up_to_u8250p(port);
1491 
1492         serial8250_rpm_get(up);
1493         __stop_tx(up);
1494 
1495         /*
1496          * We really want to stop the transmitter from sending.
1497          */
1498         if (port->type == PORT_16C950) {
1499                 up->acr |= UART_ACR_TXDIS;
1500                 serial_icr_write(up, UART_ACR, up->acr);
1501         }
1502         serial8250_rpm_put(up);
1503 }
1504 
1505 static inline void __start_tx(struct uart_port *port)
1506 {
1507         struct uart_8250_port *up = up_to_u8250p(port);
1508 
1509         if (up->dma && !up->dma->tx_dma(up))
1510                 return;
1511 
1512         if (serial8250_set_THRI(up)) {
1513                 if (up->bugs & UART_BUG_TXEN) {
1514                         unsigned char lsr;
1515 
1516                         lsr = serial_in(up, UART_LSR);
1517                         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1518                         if (lsr & UART_LSR_THRE)
1519                                 serial8250_tx_chars(up);
1520                 }
1521         }
1522 
1523         /*
1524          * Re-enable the transmitter if we disabled it.
1525          */
1526         if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1527                 up->acr &= ~UART_ACR_TXDIS;
1528                 serial_icr_write(up, UART_ACR, up->acr);
1529         }
1530 }
1531 
1532 static inline void start_tx_rs485(struct uart_port *port)
1533 {
1534         struct uart_8250_port *up = up_to_u8250p(port);
1535         struct uart_8250_em485 *em485 = up->em485;
1536         unsigned char mcr;
1537 
1538         if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1539                 serial8250_stop_rx(&up->port);
1540 
1541         em485->active_timer = NULL;
1542 
1543         mcr = serial8250_in_MCR(up);
1544         if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1545             !!(mcr & UART_MCR_RTS)) {
1546                 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1547                         mcr |= UART_MCR_RTS;
1548                 else
1549                         mcr &= ~UART_MCR_RTS;
1550                 serial8250_out_MCR(up, mcr);
1551 
1552                 if (up->port.rs485.delay_rts_before_send > 0) {
1553                         em485->active_timer = &em485->start_tx_timer;
1554                         start_hrtimer_ms(&em485->start_tx_timer,
1555                                          up->port.rs485.delay_rts_before_send);
1556                         return;
1557                 }
1558         }
1559 
1560         __start_tx(port);
1561 }
1562 
1563 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1564 {
1565         struct uart_8250_em485 *em485;
1566         struct uart_8250_port *p;
1567         unsigned long flags;
1568 
1569         em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1570         p = em485->port;
1571 
1572         spin_lock_irqsave(&p->port.lock, flags);
1573         if (em485->active_timer == &em485->start_tx_timer) {
1574                 __start_tx(&p->port);
1575                 em485->active_timer = NULL;
1576         }
1577         spin_unlock_irqrestore(&p->port.lock, flags);
1578         return HRTIMER_NORESTART;
1579 }
1580 
1581 static void serial8250_start_tx(struct uart_port *port)
1582 {
1583         struct uart_8250_port *up = up_to_u8250p(port);
1584         struct uart_8250_em485 *em485 = up->em485;
1585 
1586         serial8250_rpm_get_tx(up);
1587 
1588         if (em485 &&
1589             em485->active_timer == &em485->start_tx_timer)
1590                 return;
1591 
1592         if (em485)
1593                 start_tx_rs485(port);
1594         else
1595                 __start_tx(port);
1596 }
1597 
1598 static void serial8250_throttle(struct uart_port *port)
1599 {
1600         port->throttle(port);
1601 }
1602 
1603 static void serial8250_unthrottle(struct uart_port *port)
1604 {
1605         port->unthrottle(port);
1606 }
1607 
1608 static void serial8250_disable_ms(struct uart_port *port)
1609 {
1610         struct uart_8250_port *up = up_to_u8250p(port);
1611 
1612         /* no MSR capabilities */
1613         if (up->bugs & UART_BUG_NOMSR)
1614                 return;
1615 
1616         mctrl_gpio_disable_ms(up->gpios);
1617 
1618         up->ier &= ~UART_IER_MSI;
1619         serial_port_out(port, UART_IER, up->ier);
1620 }
1621 
1622 static void serial8250_enable_ms(struct uart_port *port)
1623 {
1624         struct uart_8250_port *up = up_to_u8250p(port);
1625 
1626         /* no MSR capabilities */
1627         if (up->bugs & UART_BUG_NOMSR)
1628                 return;
1629 
1630         mctrl_gpio_enable_ms(up->gpios);
1631 
1632         up->ier |= UART_IER_MSI;
1633 
1634         serial8250_rpm_get(up);
1635         serial_port_out(port, UART_IER, up->ier);
1636         serial8250_rpm_put(up);
1637 }
1638 
1639 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1640 {
1641         struct uart_port *port = &up->port;
1642         unsigned char ch;
1643         char flag = TTY_NORMAL;
1644 
1645         if (likely(lsr & UART_LSR_DR))
1646                 ch = serial_in(up, UART_RX);
1647         else
1648                 /*
1649                  * Intel 82571 has a Serial Over Lan device that will
1650                  * set UART_LSR_BI without setting UART_LSR_DR when
1651                  * it receives a break. To avoid reading from the
1652                  * receive buffer without UART_LSR_DR bit set, we
1653                  * just force the read character to be 0
1654                  */
1655                 ch = 0;
1656 
1657         port->icount.rx++;
1658 
1659         lsr |= up->lsr_saved_flags;
1660         up->lsr_saved_flags = 0;
1661 
1662         if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1663                 if (lsr & UART_LSR_BI) {
1664                         lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1665                         port->icount.brk++;
1666                         /*
1667                          * We do the SysRQ and SAK checking
1668                          * here because otherwise the break
1669                          * may get masked by ignore_status_mask
1670                          * or read_status_mask.
1671                          */
1672                         if (uart_handle_break(port))
1673                                 return;
1674                 } else if (lsr & UART_LSR_PE)
1675                         port->icount.parity++;
1676                 else if (lsr & UART_LSR_FE)
1677                         port->icount.frame++;
1678                 if (lsr & UART_LSR_OE)
1679                         port->icount.overrun++;
1680 
1681                 /*
1682                  * Mask off conditions which should be ignored.
1683                  */
1684                 lsr &= port->read_status_mask;
1685 
1686                 if (lsr & UART_LSR_BI) {
1687                         pr_debug("%s: handling break\n", __func__);
1688                         flag = TTY_BREAK;
1689                 } else if (lsr & UART_LSR_PE)
1690                         flag = TTY_PARITY;
1691                 else if (lsr & UART_LSR_FE)
1692                         flag = TTY_FRAME;
1693         }
1694         if (uart_prepare_sysrq_char(port, ch))
1695                 return;
1696 
1697         uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1698 }
1699 EXPORT_SYMBOL_GPL(serial8250_read_char);
1700 
1701 /*
1702  * serial8250_rx_chars: processes according to the passed in LSR
1703  * value, and returns the remaining LSR bits not handled
1704  * by this Rx routine.
1705  */
1706 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1707 {
1708         struct uart_port *port = &up->port;
1709         int max_count = 256;
1710 
1711         do {
1712                 serial8250_read_char(up, lsr);
1713                 if (--max_count == 0)
1714                         break;
1715                 lsr = serial_in(up, UART_LSR);
1716         } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1717 
1718         tty_flip_buffer_push(&port->state->port);
1719         return lsr;
1720 }
1721 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1722 
1723 void serial8250_tx_chars(struct uart_8250_port *up)
1724 {
1725         struct uart_port *port = &up->port;
1726         struct circ_buf *xmit = &port->state->xmit;
1727         int count;
1728 
1729         if (port->x_char) {
1730                 serial_out(up, UART_TX, port->x_char);
1731                 port->icount.tx++;
1732                 port->x_char = 0;
1733                 return;
1734         }
1735         if (uart_tx_stopped(port)) {
1736                 serial8250_stop_tx(port);
1737                 return;
1738         }
1739         if (uart_circ_empty(xmit)) {
1740                 __stop_tx(up);
1741                 return;
1742         }
1743 
1744         count = up->tx_loadsz;
1745         do {
1746                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1747                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1748                 port->icount.tx++;
1749                 if (uart_circ_empty(xmit))
1750                         break;
1751                 if ((up->capabilities & UART_CAP_HFIFO) &&
1752                     (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1753                         break;
1754                 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1755                 if ((up->capabilities & UART_CAP_MINI) &&
1756                     !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1757                         break;
1758         } while (--count > 0);
1759 
1760         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1761                 uart_write_wakeup(port);
1762 
1763         /*
1764          * With RPM enabled, we have to wait until the FIFO is empty before the
1765          * HW can go idle. So we get here once again with empty FIFO and disable
1766          * the interrupt and RPM in __stop_tx()
1767          */
1768         if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1769                 __stop_tx(up);
1770 }
1771 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1772 
1773 /* Caller holds uart port lock */
1774 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1775 {
1776         struct uart_port *port = &up->port;
1777         unsigned int status = serial_in(up, UART_MSR);
1778 
1779         status |= up->msr_saved_flags;
1780         up->msr_saved_flags = 0;
1781         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1782             port->state != NULL) {
1783                 if (status & UART_MSR_TERI)
1784                         port->icount.rng++;
1785                 if (status & UART_MSR_DDSR)
1786                         port->icount.dsr++;
1787                 if (status & UART_MSR_DDCD)
1788                         uart_handle_dcd_change(port, status & UART_MSR_DCD);
1789                 if (status & UART_MSR_DCTS)
1790                         uart_handle_cts_change(port, status & UART_MSR_CTS);
1791 
1792                 wake_up_interruptible(&port->state->port.delta_msr_wait);
1793         }
1794 
1795         return status;
1796 }
1797 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1798 
1799 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1800 {
1801         switch (iir & 0x3f) {
1802         case UART_IIR_RX_TIMEOUT:
1803                 serial8250_rx_dma_flush(up);
1804                 /* fall-through */
1805         case UART_IIR_RLSI:
1806                 return true;
1807         }
1808         return up->dma->rx_dma(up);
1809 }
1810 
1811 /*
1812  * This handles the interrupt from one port.
1813  */
1814 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1815 {
1816         unsigned char status;
1817         unsigned long flags;
1818         struct uart_8250_port *up = up_to_u8250p(port);
1819 
1820         if (iir & UART_IIR_NO_INT)
1821                 return 0;
1822 
1823         spin_lock_irqsave(&port->lock, flags);
1824 
1825         status = serial_port_in(port, UART_LSR);
1826 
1827         if (status & (UART_LSR_DR | UART_LSR_BI)) {
1828                 if (!up->dma || handle_rx_dma(up, iir))
1829                         status = serial8250_rx_chars(up, status);
1830         }
1831         serial8250_modem_status(up);
1832         if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1833                 (up->ier & UART_IER_THRI))
1834                 serial8250_tx_chars(up);
1835 
1836         uart_unlock_and_check_sysrq(port, flags);
1837         return 1;
1838 }
1839 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1840 
1841 static int serial8250_default_handle_irq(struct uart_port *port)
1842 {
1843         struct uart_8250_port *up = up_to_u8250p(port);
1844         unsigned int iir;
1845         int ret;
1846 
1847         serial8250_rpm_get(up);
1848 
1849         iir = serial_port_in(port, UART_IIR);
1850         ret = serial8250_handle_irq(port, iir);
1851 
1852         serial8250_rpm_put(up);
1853         return ret;
1854 }
1855 
1856 /*
1857  * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1858  * have a programmable TX threshold that triggers the THRE interrupt in
1859  * the IIR register. In this case, the THRE interrupt indicates the FIFO
1860  * has space available. Load it up with tx_loadsz bytes.
1861  */
1862 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1863 {
1864         unsigned long flags;
1865         unsigned int iir = serial_port_in(port, UART_IIR);
1866 
1867         /* TX Threshold IRQ triggered so load up FIFO */
1868         if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1869                 struct uart_8250_port *up = up_to_u8250p(port);
1870 
1871                 spin_lock_irqsave(&port->lock, flags);
1872                 serial8250_tx_chars(up);
1873                 spin_unlock_irqrestore(&port->lock, flags);
1874         }
1875 
1876         iir = serial_port_in(port, UART_IIR);
1877         return serial8250_handle_irq(port, iir);
1878 }
1879 
1880 static unsigned int serial8250_tx_empty(struct uart_port *port)
1881 {
1882         struct uart_8250_port *up = up_to_u8250p(port);
1883         unsigned long flags;
1884         unsigned int lsr;
1885 
1886         serial8250_rpm_get(up);
1887 
1888         spin_lock_irqsave(&port->lock, flags);
1889         lsr = serial_port_in(port, UART_LSR);
1890         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1891         spin_unlock_irqrestore(&port->lock, flags);
1892 
1893         serial8250_rpm_put(up);
1894 
1895         return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1896 }
1897 
1898 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1899 {
1900         struct uart_8250_port *up = up_to_u8250p(port);
1901         unsigned int status;
1902         unsigned int val;
1903 
1904         serial8250_rpm_get(up);
1905         status = serial8250_modem_status(up);
1906         serial8250_rpm_put(up);
1907 
1908         val = serial8250_MSR_to_TIOCM(status);
1909         if (up->gpios)
1910                 return mctrl_gpio_get(up->gpios, &val);
1911 
1912         return val;
1913 }
1914 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1915 
1916 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1917 {
1918         if (port->get_mctrl)
1919                 return port->get_mctrl(port);
1920         return serial8250_do_get_mctrl(port);
1921 }
1922 
1923 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1924 {
1925         struct uart_8250_port *up = up_to_u8250p(port);
1926         unsigned char mcr;
1927 
1928         mcr = serial8250_TIOCM_to_MCR(mctrl);
1929 
1930         mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1931 
1932         serial8250_out_MCR(up, mcr);
1933 }
1934 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1935 
1936 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1937 {
1938         if (port->set_mctrl)
1939                 port->set_mctrl(port, mctrl);
1940         else
1941                 serial8250_do_set_mctrl(port, mctrl);
1942 }
1943 
1944 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1945 {
1946         struct uart_8250_port *up = up_to_u8250p(port);
1947         unsigned long flags;
1948 
1949         serial8250_rpm_get(up);
1950         spin_lock_irqsave(&port->lock, flags);
1951         if (break_state == -1)
1952                 up->lcr |= UART_LCR_SBC;
1953         else
1954                 up->lcr &= ~UART_LCR_SBC;
1955         serial_port_out(port, UART_LCR, up->lcr);
1956         spin_unlock_irqrestore(&port->lock, flags);
1957         serial8250_rpm_put(up);
1958 }
1959 
1960 /*
1961  *      Wait for transmitter & holding register to empty
1962  */
1963 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1964 {
1965         unsigned int status, tmout = 10000;
1966 
1967         /* Wait up to 10ms for the character(s) to be sent. */
1968         for (;;) {
1969                 status = serial_in(up, UART_LSR);
1970 
1971                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1972 
1973                 if ((status & bits) == bits)
1974                         break;
1975                 if (--tmout == 0)
1976                         break;
1977                 udelay(1);
1978                 touch_nmi_watchdog();
1979         }
1980 
1981         /* Wait up to 1s for flow control if necessary */
1982         if (up->port.flags & UPF_CONS_FLOW) {
1983                 for (tmout = 1000000; tmout; tmout--) {
1984                         unsigned int msr = serial_in(up, UART_MSR);
1985                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1986                         if (msr & UART_MSR_CTS)
1987                                 break;
1988                         udelay(1);
1989                         touch_nmi_watchdog();
1990                 }
1991         }
1992 }
1993 
1994 #ifdef CONFIG_CONSOLE_POLL
1995 /*
1996  * Console polling routines for writing and reading from the uart while
1997  * in an interrupt or debug context.
1998  */
1999 
2000 static int serial8250_get_poll_char(struct uart_port *port)
2001 {
2002         struct uart_8250_port *up = up_to_u8250p(port);
2003         unsigned char lsr;
2004         int status;
2005 
2006         serial8250_rpm_get(up);
2007 
2008         lsr = serial_port_in(port, UART_LSR);
2009 
2010         if (!(lsr & UART_LSR_DR)) {
2011                 status = NO_POLL_CHAR;
2012                 goto out;
2013         }
2014 
2015         status = serial_port_in(port, UART_RX);
2016 out:
2017         serial8250_rpm_put(up);
2018         return status;
2019 }
2020 
2021 
2022 static void serial8250_put_poll_char(struct uart_port *port,
2023                          unsigned char c)
2024 {
2025         unsigned int ier;
2026         struct uart_8250_port *up = up_to_u8250p(port);
2027 
2028         serial8250_rpm_get(up);
2029         /*
2030          *      First save the IER then disable the interrupts
2031          */
2032         ier = serial_port_in(port, UART_IER);
2033         if (up->capabilities & UART_CAP_UUE)
2034                 serial_port_out(port, UART_IER, UART_IER_UUE);
2035         else
2036                 serial_port_out(port, UART_IER, 0);
2037 
2038         wait_for_xmitr(up, BOTH_EMPTY);
2039         /*
2040          *      Send the character out.
2041          */
2042         serial_port_out(port, UART_TX, c);
2043 
2044         /*
2045          *      Finally, wait for transmitter to become empty
2046          *      and restore the IER
2047          */
2048         wait_for_xmitr(up, BOTH_EMPTY);
2049         serial_port_out(port, UART_IER, ier);
2050         serial8250_rpm_put(up);
2051 }
2052 
2053 #endif /* CONFIG_CONSOLE_POLL */
2054 
2055 int serial8250_do_startup(struct uart_port *port)
2056 {
2057         struct uart_8250_port *up = up_to_u8250p(port);
2058         unsigned long flags;
2059         unsigned char lsr, iir;
2060         int retval;
2061 
2062         if (!port->fifosize)
2063                 port->fifosize = uart_config[port->type].fifo_size;
2064         if (!up->tx_loadsz)
2065                 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2066         if (!up->capabilities)
2067                 up->capabilities = uart_config[port->type].flags;
2068         up->mcr = 0;
2069 
2070         if (port->iotype != up->cur_iotype)
2071                 set_io_from_upio(port);
2072 
2073         serial8250_rpm_get(up);
2074         if (port->type == PORT_16C950) {
2075                 /* Wake up and initialize UART */
2076                 up->acr = 0;
2077                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2078                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2079                 serial_port_out(port, UART_IER, 0);
2080                 serial_port_out(port, UART_LCR, 0);
2081                 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2082                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2083                 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2084                 serial_port_out(port, UART_LCR, 0);
2085         }
2086 
2087         if (port->type == PORT_DA830) {
2088                 /* Reset the port */
2089                 serial_port_out(port, UART_IER, 0);
2090                 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2091                 mdelay(10);
2092 
2093                 /* Enable Tx, Rx and free run mode */
2094                 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2095                                 UART_DA830_PWREMU_MGMT_UTRST |
2096                                 UART_DA830_PWREMU_MGMT_URRST |
2097                                 UART_DA830_PWREMU_MGMT_FREE);
2098         }
2099 
2100         if (port->type == PORT_NPCM) {
2101                 /*
2102                  * Nuvoton calls the scratch register 'UART_TOR' (timeout
2103                  * register). Enable it, and set TIOC (timeout interrupt
2104                  * comparator) to be 0x20 for correct operation.
2105                  */
2106                 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2107         }
2108 
2109 #ifdef CONFIG_SERIAL_8250_RSA
2110         /*
2111          * If this is an RSA port, see if we can kick it up to the
2112          * higher speed clock.
2113          */
2114         enable_rsa(up);
2115 #endif
2116 
2117         if (port->type == PORT_XR17V35X) {
2118                 /*
2119                  * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2120                  * MCR [7:5] and MSR [7:0]
2121                  */
2122                 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2123 
2124                 /*
2125                  * Make sure all interrups are masked until initialization is
2126                  * complete and the FIFOs are cleared
2127                  */
2128                 serial_port_out(port, UART_IER, 0);
2129         }
2130 
2131         /*
2132          * Clear the FIFO buffers and disable them.
2133          * (they will be reenabled in set_termios())
2134          */
2135         serial8250_clear_fifos(up);
2136 
2137         /*
2138          * Clear the interrupt registers.
2139          */
2140         serial_port_in(port, UART_LSR);
2141         serial_port_in(port, UART_RX);
2142         serial_port_in(port, UART_IIR);
2143         serial_port_in(port, UART_MSR);
2144 
2145         /*
2146          * At this point, there's no way the LSR could still be 0xff;
2147          * if it is, then bail out, because there's likely no UART
2148          * here.
2149          */
2150         if (!(port->flags & UPF_BUGGY_UART) &&
2151             (serial_port_in(port, UART_LSR) == 0xff)) {
2152                 pr_info_ratelimited("%s: LSR safety check engaged!\n", port->name);
2153                 retval = -ENODEV;
2154                 goto out;
2155         }
2156 
2157         /*
2158          * For a XR16C850, we need to set the trigger levels
2159          */
2160         if (port->type == PORT_16850) {
2161                 unsigned char fctr;
2162 
2163                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2164 
2165                 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2166                 serial_port_out(port, UART_FCTR,
2167                                 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2168                 serial_port_out(port, UART_TRG, UART_TRG_96);
2169                 serial_port_out(port, UART_FCTR,
2170                                 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2171                 serial_port_out(port, UART_TRG, UART_TRG_96);
2172 
2173                 serial_port_out(port, UART_LCR, 0);
2174         }
2175 
2176         /*
2177          * For the Altera 16550 variants, set TX threshold trigger level.
2178          */
2179         if (((port->type == PORT_ALTR_16550_F32) ||
2180              (port->type == PORT_ALTR_16550_F64) ||
2181              (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2182                 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2183                 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2184                         pr_err("%s TX FIFO Threshold errors, skipping\n",
2185                                port->name);
2186                 } else {
2187                         serial_port_out(port, UART_ALTR_AFR,
2188                                         UART_ALTR_EN_TXFIFO_LW);
2189                         serial_port_out(port, UART_ALTR_TX_LOW,
2190                                         port->fifosize - up->tx_loadsz);
2191                         port->handle_irq = serial8250_tx_threshold_handle_irq;
2192                 }
2193         }
2194 
2195         /* Check if we need to have shared IRQs */
2196         if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2197                 up->port.irqflags |= IRQF_SHARED;
2198 
2199         if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2200                 unsigned char iir1;
2201                 /*
2202                  * Test for UARTs that do not reassert THRE when the
2203                  * transmitter is idle and the interrupt has already
2204                  * been cleared.  Real 16550s should always reassert
2205                  * this interrupt whenever the transmitter is idle and
2206                  * the interrupt is enabled.  Delays are necessary to
2207                  * allow register changes to become visible.
2208                  */
2209                 spin_lock_irqsave(&port->lock, flags);
2210                 if (up->port.irqflags & IRQF_SHARED)
2211                         disable_irq_nosync(port->irq);
2212 
2213                 wait_for_xmitr(up, UART_LSR_THRE);
2214                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2215                 udelay(1); /* allow THRE to set */
2216                 iir1 = serial_port_in(port, UART_IIR);
2217                 serial_port_out(port, UART_IER, 0);
2218                 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2219                 udelay(1); /* allow a working UART time to re-assert THRE */
2220                 iir = serial_port_in(port, UART_IIR);
2221                 serial_port_out(port, UART_IER, 0);
2222 
2223                 if (port->irqflags & IRQF_SHARED)
2224                         enable_irq(port->irq);
2225                 spin_unlock_irqrestore(&port->lock, flags);
2226 
2227                 /*
2228                  * If the interrupt is not reasserted, or we otherwise
2229                  * don't trust the iir, setup a timer to kick the UART
2230                  * on a regular basis.
2231                  */
2232                 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2233                     up->port.flags & UPF_BUG_THRE) {
2234                         up->bugs |= UART_BUG_THRE;
2235                 }
2236         }
2237 
2238         retval = up->ops->setup_irq(up);
2239         if (retval)
2240                 goto out;
2241 
2242         /*
2243          * Now, initialize the UART
2244          */
2245         serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2246 
2247         spin_lock_irqsave(&port->lock, flags);
2248         if (up->port.flags & UPF_FOURPORT) {
2249                 if (!up->port.irq)
2250                         up->port.mctrl |= TIOCM_OUT1;
2251         } else
2252                 /*
2253                  * Most PC uarts need OUT2 raised to enable interrupts.
2254                  */
2255                 if (port->irq)
2256                         up->port.mctrl |= TIOCM_OUT2;
2257 
2258         serial8250_set_mctrl(port, port->mctrl);
2259 
2260         /*
2261          * Serial over Lan (SoL) hack:
2262          * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2263          * used for Serial Over Lan.  Those chips take a longer time than a
2264          * normal serial device to signalize that a transmission data was
2265          * queued. Due to that, the above test generally fails. One solution
2266          * would be to delay the reading of iir. However, this is not
2267          * reliable, since the timeout is variable. So, let's just don't
2268          * test if we receive TX irq.  This way, we'll never enable
2269          * UART_BUG_TXEN.
2270          */
2271         if (up->port.quirks & UPQ_NO_TXEN_TEST)
2272                 goto dont_test_tx_en;
2273 
2274         /*
2275          * Do a quick test to see if we receive an interrupt when we enable
2276          * the TX irq.
2277          */
2278         serial_port_out(port, UART_IER, UART_IER_THRI);
2279         lsr = serial_port_in(port, UART_LSR);
2280         iir = serial_port_in(port, UART_IIR);
2281         serial_port_out(port, UART_IER, 0);
2282 
2283         if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2284                 if (!(up->bugs & UART_BUG_TXEN)) {
2285                         up->bugs |= UART_BUG_TXEN;
2286                         pr_debug("%s - enabling bad tx status workarounds\n",
2287                                  port->name);
2288                 }
2289         } else {
2290                 up->bugs &= ~UART_BUG_TXEN;
2291         }
2292 
2293 dont_test_tx_en:
2294         spin_unlock_irqrestore(&port->lock, flags);
2295 
2296         /*
2297          * Clear the interrupt registers again for luck, and clear the
2298          * saved flags to avoid getting false values from polling
2299          * routines or the previous session.
2300          */
2301         serial_port_in(port, UART_LSR);
2302         serial_port_in(port, UART_RX);
2303         serial_port_in(port, UART_IIR);
2304         serial_port_in(port, UART_MSR);
2305         up->lsr_saved_flags = 0;
2306         up->msr_saved_flags = 0;
2307 
2308         /*
2309          * Request DMA channels for both RX and TX.
2310          */
2311         if (up->dma) {
2312                 retval = serial8250_request_dma(up);
2313                 if (retval) {
2314                         pr_warn_ratelimited("%s - failed to request DMA\n",
2315                                             port->name);
2316                         up->dma = NULL;
2317                 }
2318         }
2319 
2320         /*
2321          * Set the IER shadow for rx interrupts but defer actual interrupt
2322          * enable until after the FIFOs are enabled; otherwise, an already-
2323          * active sender can swamp the interrupt handler with "too much work".
2324          */
2325         up->ier = UART_IER_RLSI | UART_IER_RDI;
2326 
2327         if (port->flags & UPF_FOURPORT) {
2328                 unsigned int icp;
2329                 /*
2330                  * Enable interrupts on the AST Fourport board
2331                  */
2332                 icp = (port->iobase & 0xfe0) | 0x01f;
2333                 outb_p(0x80, icp);
2334                 inb_p(icp);
2335         }
2336         retval = 0;
2337 out:
2338         serial8250_rpm_put(up);
2339         return retval;
2340 }
2341 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2342 
2343 static int serial8250_startup(struct uart_port *port)
2344 {
2345         if (port->startup)
2346                 return port->startup(port);
2347         return serial8250_do_startup(port);
2348 }
2349 
2350 void serial8250_do_shutdown(struct uart_port *port)
2351 {
2352         struct uart_8250_port *up = up_to_u8250p(port);
2353         unsigned long flags;
2354 
2355         serial8250_rpm_get(up);
2356         /*
2357          * Disable interrupts from this port
2358          */
2359         spin_lock_irqsave(&port->lock, flags);
2360         up->ier = 0;
2361         serial_port_out(port, UART_IER, 0);
2362         spin_unlock_irqrestore(&port->lock, flags);
2363 
2364         synchronize_irq(port->irq);
2365 
2366         if (up->dma)
2367                 serial8250_release_dma(up);
2368 
2369         spin_lock_irqsave(&port->lock, flags);
2370         if (port->flags & UPF_FOURPORT) {
2371                 /* reset interrupts on the AST Fourport board */
2372                 inb((port->iobase & 0xfe0) | 0x1f);
2373                 port->mctrl |= TIOCM_OUT1;
2374         } else
2375                 port->mctrl &= ~TIOCM_OUT2;
2376 
2377         serial8250_set_mctrl(port, port->mctrl);
2378         spin_unlock_irqrestore(&port->lock, flags);
2379 
2380         /*
2381          * Disable break condition and FIFOs
2382          */
2383         serial_port_out(port, UART_LCR,
2384                         serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2385         serial8250_clear_fifos(up);
2386 
2387 #ifdef CONFIG_SERIAL_8250_RSA
2388         /*
2389          * Reset the RSA board back to 115kbps compat mode.
2390          */
2391         disable_rsa(up);
2392 #endif
2393 
2394         /*
2395          * Read data port to reset things, and then unlink from
2396          * the IRQ chain.
2397          */
2398         serial_port_in(port, UART_RX);
2399         serial8250_rpm_put(up);
2400 
2401         up->ops->release_irq(up);
2402 }
2403 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2404 
2405 static void serial8250_shutdown(struct uart_port *port)
2406 {
2407         if (port->shutdown)
2408                 port->shutdown(port);
2409         else
2410                 serial8250_do_shutdown(port);
2411 }
2412 
2413 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2414 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2415                 unsigned int baud)
2416 {
2417         struct uart_port *port = &up->port;
2418 
2419         return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2420 }
2421 
2422 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2423                                               unsigned int baud,
2424                                               unsigned int *frac)
2425 {
2426         struct uart_8250_port *up = up_to_u8250p(port);
2427         unsigned int quot;
2428 
2429         /*
2430          * Handle magic divisors for baud rates above baud_base on
2431          * SMSC SuperIO chips.
2432          *
2433          */
2434         if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2435             baud == (port->uartclk/4))
2436                 quot = 0x8001;
2437         else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2438                  baud == (port->uartclk/8))
2439                 quot = 0x8002;
2440         else if (up->port.type == PORT_NPCM)
2441                 quot = npcm_get_divisor(up, baud);
2442         else
2443                 quot = uart_get_divisor(port, baud);
2444 
2445         /*
2446          * Oxford Semi 952 rev B workaround
2447          */
2448         if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2449                 quot++;
2450 
2451         return quot;
2452 }
2453 
2454 static unsigned int serial8250_get_divisor(struct uart_port *port,
2455                                            unsigned int baud,
2456                                            unsigned int *frac)
2457 {
2458         if (port->get_divisor)
2459                 return port->get_divisor(port, baud, frac);
2460 
2461         return serial8250_do_get_divisor(port, baud, frac);
2462 }
2463 
2464 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2465                                             tcflag_t c_cflag)
2466 {
2467         unsigned char cval;
2468 
2469         switch (c_cflag & CSIZE) {
2470         case CS5:
2471                 cval = UART_LCR_WLEN5;
2472                 break;
2473         case CS6:
2474                 cval = UART_LCR_WLEN6;
2475                 break;
2476         case CS7:
2477                 cval = UART_LCR_WLEN7;
2478                 break;
2479         default:
2480         case CS8:
2481                 cval = UART_LCR_WLEN8;
2482                 break;
2483         }
2484 
2485         if (c_cflag & CSTOPB)
2486                 cval |= UART_LCR_STOP;
2487         if (c_cflag & PARENB) {
2488                 cval |= UART_LCR_PARITY;
2489                 if (up->bugs & UART_BUG_PARITY)
2490                         up->fifo_bug = true;
2491         }
2492         if (!(c_cflag & PARODD))
2493                 cval |= UART_LCR_EPAR;
2494 #ifdef CMSPAR
2495         if (c_cflag & CMSPAR)
2496                 cval |= UART_LCR_SPAR;
2497 #endif
2498 
2499         return cval;
2500 }
2501 
2502 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2503                                unsigned int quot, unsigned int quot_frac)
2504 {
2505         struct uart_8250_port *up = up_to_u8250p(port);
2506 
2507         /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2508         if (is_omap1510_8250(up)) {
2509                 if (baud == 115200) {
2510                         quot = 1;
2511                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2512                 } else
2513                         serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2514         }
2515 
2516         /*
2517          * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2518          * otherwise just set DLAB
2519          */
2520         if (up->capabilities & UART_NATSEMI)
2521                 serial_port_out(port, UART_LCR, 0xe0);
2522         else
2523                 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2524 
2525         serial_dl_write(up, quot);
2526 }
2527 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2528 
2529 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2530                                    unsigned int quot, unsigned int quot_frac)
2531 {
2532         if (port->set_divisor)
2533                 port->set_divisor(port, baud, quot, quot_frac);
2534         else
2535                 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2536 }
2537 
2538 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2539                                              struct ktermios *termios,
2540                                              struct ktermios *old)
2541 {
2542         /*
2543          * Ask the core to calculate the divisor for us.
2544          * Allow 1% tolerance at the upper limit so uart clks marginally
2545          * slower than nominal still match standard baud rates without
2546          * causing transmission errors.
2547          */
2548         return uart_get_baud_rate(port, termios, old,
2549                                   port->uartclk / 16 / UART_DIV_MAX,
2550                                   port->uartclk);
2551 }
2552 
2553 void
2554 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2555                           struct ktermios *old)
2556 {
2557         struct uart_8250_port *up = up_to_u8250p(port);
2558         unsigned char cval;
2559         unsigned long flags;
2560         unsigned int baud, quot, frac = 0;
2561 
2562         if (up->capabilities & UART_CAP_MINI) {
2563                 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2564                 if ((termios->c_cflag & CSIZE) == CS5 ||
2565                     (termios->c_cflag & CSIZE) == CS6)
2566                         termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2567         }
2568         cval = serial8250_compute_lcr(up, termios->c_cflag);
2569 
2570         baud = serial8250_get_baud_rate(port, termios, old);
2571         quot = serial8250_get_divisor(port, baud, &frac);
2572 
2573         /*
2574          * Ok, we're now changing the port state.  Do it with
2575          * interrupts disabled.
2576          */
2577         serial8250_rpm_get(up);
2578         spin_lock_irqsave(&port->lock, flags);
2579 
2580         up->lcr = cval;                                 /* Save computed LCR */
2581 
2582         if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2583                 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2584                 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2585                         up->fcr &= ~UART_FCR_TRIGGER_MASK;
2586                         up->fcr |= UART_FCR_TRIGGER_1;
2587                 }
2588         }
2589 
2590         /*
2591          * MCR-based auto flow control.  When AFE is enabled, RTS will be
2592          * deasserted when the receive FIFO contains more characters than
2593          * the trigger, or the MCR RTS bit is cleared.
2594          */
2595         if (up->capabilities & UART_CAP_AFE) {
2596                 up->mcr &= ~UART_MCR_AFE;
2597                 if (termios->c_cflag & CRTSCTS)
2598                         up->mcr |= UART_MCR_AFE;
2599         }
2600 
2601         /*
2602          * Update the per-port timeout.
2603          */
2604         uart_update_timeout(port, termios->c_cflag, baud);
2605 
2606         port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2607         if (termios->c_iflag & INPCK)
2608                 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2609         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2610                 port->read_status_mask |= UART_LSR_BI;
2611 
2612         /*
2613          * Characteres to ignore
2614          */
2615         port->ignore_status_mask = 0;
2616         if (termios->c_iflag & IGNPAR)
2617                 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2618         if (termios->c_iflag & IGNBRK) {
2619                 port->ignore_status_mask |= UART_LSR_BI;
2620                 /*
2621                  * If we're ignoring parity and break indicators,
2622                  * ignore overruns too (for real raw support).
2623                  */
2624                 if (termios->c_iflag & IGNPAR)
2625                         port->ignore_status_mask |= UART_LSR_OE;
2626         }
2627 
2628         /*
2629          * ignore all characters if CREAD is not set
2630          */
2631         if ((termios->c_cflag & CREAD) == 0)
2632                 port->ignore_status_mask |= UART_LSR_DR;
2633 
2634         /*
2635          * CTS flow control flag and modem status interrupts
2636          */
2637         up->ier &= ~UART_IER_MSI;
2638         if (!(up->bugs & UART_BUG_NOMSR) &&
2639                         UART_ENABLE_MS(&up->port, termios->c_cflag))
2640                 up->ier |= UART_IER_MSI;
2641         if (up->capabilities & UART_CAP_UUE)
2642                 up->ier |= UART_IER_UUE;
2643         if (up->capabilities & UART_CAP_RTOIE)
2644                 up->ier |= UART_IER_RTOIE;
2645 
2646         serial_port_out(port, UART_IER, up->ier);
2647 
2648         if (up->capabilities & UART_CAP_EFR) {
2649                 unsigned char efr = 0;
2650                 /*
2651                  * TI16C752/Startech hardware flow control.  FIXME:
2652                  * - TI16C752 requires control thresholds to be set.
2653                  * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2654                  */
2655                 if (termios->c_cflag & CRTSCTS)
2656                         efr |= UART_EFR_CTS;
2657 
2658                 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2659                 if (port->flags & UPF_EXAR_EFR)
2660                         serial_port_out(port, UART_XR_EFR, efr);
2661                 else
2662                         serial_port_out(port, UART_EFR, efr);
2663         }
2664 
2665         serial8250_set_divisor(port, baud, quot, frac);
2666 
2667         /*
2668          * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2669          * is written without DLAB set, this mode will be disabled.
2670          */
2671         if (port->type == PORT_16750)
2672                 serial_port_out(port, UART_FCR, up->fcr);
2673 
2674         serial_port_out(port, UART_LCR, up->lcr);       /* reset DLAB */
2675         if (port->type != PORT_16750) {
2676                 /* emulated UARTs (Lucent Venus 167x) need two steps */
2677                 if (up->fcr & UART_FCR_ENABLE_FIFO)
2678                         serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2679                 serial_port_out(port, UART_FCR, up->fcr);       /* set fcr */
2680         }
2681         serial8250_set_mctrl(port, port->mctrl);
2682         spin_unlock_irqrestore(&port->lock, flags);
2683         serial8250_rpm_put(up);
2684 
2685         /* Don't rewrite B0 */
2686         if (tty_termios_baud_rate(termios))
2687                 tty_termios_encode_baud_rate(termios, baud, baud);
2688 }
2689 EXPORT_SYMBOL(serial8250_do_set_termios);
2690 
2691 static void
2692 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2693                        struct ktermios *old)
2694 {
2695         if (port->set_termios)
2696                 port->set_termios(port, termios, old);
2697         else
2698                 serial8250_do_set_termios(port, termios, old);
2699 }
2700 
2701 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2702 {
2703         if (termios->c_line == N_PPS) {
2704                 port->flags |= UPF_HARDPPS_CD;
2705                 spin_lock_irq(&port->lock);
2706                 serial8250_enable_ms(port);
2707                 spin_unlock_irq(&port->lock);
2708         } else {
2709                 port->flags &= ~UPF_HARDPPS_CD;
2710                 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2711                         spin_lock_irq(&port->lock);
2712                         serial8250_disable_ms(port);
2713                         spin_unlock_irq(&port->lock);
2714                 }
2715         }
2716 }
2717 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2718 
2719 static void
2720 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2721 {
2722         if (port->set_ldisc)
2723                 port->set_ldisc(port, termios);
2724         else
2725                 serial8250_do_set_ldisc(port, termios);
2726 }
2727 
2728 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2729                       unsigned int oldstate)
2730 {
2731         struct uart_8250_port *p = up_to_u8250p(port);
2732 
2733         serial8250_set_sleep(p, state != 0);
2734 }
2735 EXPORT_SYMBOL(serial8250_do_pm);
2736 
2737 static void
2738 serial8250_pm(struct uart_port *port, unsigned int state,
2739               unsigned int oldstate)
2740 {
2741         if (port->pm)
2742                 port->pm(port, state, oldstate);
2743         else
2744                 serial8250_do_pm(port, state, oldstate);
2745 }
2746 
2747 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2748 {
2749         if (pt->port.mapsize)
2750                 return pt->port.mapsize;
2751         if (pt->port.iotype == UPIO_AU) {
2752                 if (pt->port.type == PORT_RT2880)
2753                         return 0x100;
2754                 return 0x1000;
2755         }
2756         if (is_omap1_8250(pt))
2757                 return 0x16 << pt->port.regshift;
2758 
2759         return 8 << pt->port.regshift;
2760 }
2761 
2762 /*
2763  * Resource handling.
2764  */
2765 static int serial8250_request_std_resource(struct uart_8250_port *up)
2766 {
2767         unsigned int size = serial8250_port_size(up);
2768         struct uart_port *port = &up->port;
2769         int ret = 0;
2770 
2771         switch (port->iotype) {
2772         case UPIO_AU:
2773         case UPIO_TSI:
2774         case UPIO_MEM32:
2775         case UPIO_MEM32BE:
2776         case UPIO_MEM16:
2777         case UPIO_MEM:
2778                 if (!port->mapbase)
2779                         break;
2780 
2781                 if (!request_mem_region(port->mapbase, size, "serial")) {
2782                         ret = -EBUSY;
2783                         break;
2784                 }
2785 
2786                 if (port->flags & UPF_IOREMAP) {
2787                         port->membase = ioremap_nocache(port->mapbase, size);
2788                         if (!port->membase) {
2789                                 release_mem_region(port->mapbase, size);
2790                                 ret = -ENOMEM;
2791                         }
2792                 }
2793                 break;
2794 
2795         case UPIO_HUB6:
2796         case UPIO_PORT:
2797                 if (!request_region(port->iobase, size, "serial"))
2798                         ret = -EBUSY;
2799                 break;
2800         }
2801         return ret;
2802 }
2803 
2804 static void serial8250_release_std_resource(struct uart_8250_port *up)
2805 {
2806         unsigned int size = serial8250_port_size(up);
2807         struct uart_port *port = &up->port;
2808 
2809         switch (port->iotype) {
2810         case UPIO_AU:
2811         case UPIO_TSI:
2812         case UPIO_MEM32:
2813         case UPIO_MEM32BE:
2814         case UPIO_MEM16:
2815         case UPIO_MEM:
2816                 if (!port->mapbase)
2817                         break;
2818 
2819                 if (port->flags & UPF_IOREMAP) {
2820                         iounmap(port->membase);
2821                         port->membase = NULL;
2822                 }
2823 
2824                 release_mem_region(port->mapbase, size);
2825                 break;
2826 
2827         case UPIO_HUB6:
2828         case UPIO_PORT:
2829                 release_region(port->iobase, size);
2830                 break;
2831         }
2832 }
2833 
2834 static void serial8250_release_port(struct uart_port *port)
2835 {
2836         struct uart_8250_port *up = up_to_u8250p(port);
2837 
2838         serial8250_release_std_resource(up);
2839 }
2840 
2841 static int serial8250_request_port(struct uart_port *port)
2842 {
2843         struct uart_8250_port *up = up_to_u8250p(port);
2844 
2845         return serial8250_request_std_resource(up);
2846 }
2847 
2848 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2849 {
2850         const struct serial8250_config *conf_type = &uart_config[up->port.type];
2851         unsigned char bytes;
2852 
2853         bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2854 
2855         return bytes ? bytes : -EOPNOTSUPP;
2856 }
2857 
2858 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2859 {
2860         const struct serial8250_config *conf_type = &uart_config[up->port.type];
2861         int i;
2862 
2863         if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2864                 return -EOPNOTSUPP;
2865 
2866         for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2867                 if (bytes < conf_type->rxtrig_bytes[i])
2868                         /* Use the nearest lower value */
2869                         return (--i) << UART_FCR_R_TRIG_SHIFT;
2870         }
2871 
2872         return UART_FCR_R_TRIG_11;
2873 }
2874 
2875 static int do_get_rxtrig(struct tty_port *port)
2876 {
2877         struct uart_state *state = container_of(port, struct uart_state, port);
2878         struct uart_port *uport = state->uart_port;
2879         struct uart_8250_port *up = up_to_u8250p(uport);
2880 
2881         if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2882                 return -EINVAL;
2883 
2884         return fcr_get_rxtrig_bytes(up);
2885 }
2886 
2887 static int do_serial8250_get_rxtrig(struct tty_port *port)
2888 {
2889         int rxtrig_bytes;
2890 
2891         mutex_lock(&port->mutex);
2892         rxtrig_bytes = do_get_rxtrig(port);
2893         mutex_unlock(&port->mutex);
2894 
2895         return rxtrig_bytes;
2896 }
2897 
2898 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2899         struct device_attribute *attr, char *buf)
2900 {
2901         struct tty_port *port = dev_get_drvdata(dev);
2902         int rxtrig_bytes;
2903 
2904         rxtrig_bytes = do_serial8250_get_rxtrig(port);
2905         if (rxtrig_bytes < 0)
2906                 return rxtrig_bytes;
2907 
2908         return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2909 }
2910 
2911 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2912 {
2913         struct uart_state *state = container_of(port, struct uart_state, port);
2914         struct uart_port *uport = state->uart_port;
2915         struct uart_8250_port *up = up_to_u8250p(uport);
2916         int rxtrig;
2917 
2918         if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2919             up->fifo_bug)
2920                 return -EINVAL;
2921 
2922         rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2923         if (rxtrig < 0)
2924                 return rxtrig;
2925 
2926         serial8250_clear_fifos(up);
2927         up->fcr &= ~UART_FCR_TRIGGER_MASK;
2928         up->fcr |= (unsigned char)rxtrig;
2929         serial_out(up, UART_FCR, up->fcr);
2930         return 0;
2931 }
2932 
2933 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2934 {
2935         int ret;
2936 
2937         mutex_lock(&port->mutex);
2938         ret = do_set_rxtrig(port, bytes);
2939         mutex_unlock(&port->mutex);
2940 
2941         return ret;
2942 }
2943 
2944 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2945         struct device_attribute *attr, const char *buf, size_t count)
2946 {
2947         struct tty_port *port = dev_get_drvdata(dev);
2948         unsigned char bytes;
2949         int ret;
2950 
2951         if (!count)
2952                 return -EINVAL;
2953 
2954         ret = kstrtou8(buf, 10, &bytes);
2955         if (ret < 0)
2956                 return ret;
2957 
2958         ret = do_serial8250_set_rxtrig(port, bytes);
2959         if (ret < 0)
2960                 return ret;
2961 
2962         return count;
2963 }
2964 
2965 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2966                    serial8250_get_attr_rx_trig_bytes,
2967                    serial8250_set_attr_rx_trig_bytes);
2968 
2969 static struct attribute *serial8250_dev_attrs[] = {
2970         &dev_attr_rx_trig_bytes.attr,
2971         NULL,
2972         };
2973 
2974 static struct attribute_group serial8250_dev_attr_group = {
2975         .attrs = serial8250_dev_attrs,
2976         };
2977 
2978 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2979 {
2980         const struct serial8250_config *conf_type = &uart_config[up->port.type];
2981 
2982         if (conf_type->rxtrig_bytes[0])
2983                 up->port.attr_group = &serial8250_dev_attr_group;
2984 }
2985 
2986 static void serial8250_config_port(struct uart_port *port, int flags)
2987 {
2988         struct uart_8250_port *up = up_to_u8250p(port);
2989         int ret;
2990 
2991         /*
2992          * Find the region that we can probe for.  This in turn
2993          * tells us whether we can probe for the type of port.
2994          */
2995         ret = serial8250_request_std_resource(up);
2996         if (ret < 0)
2997                 return;
2998 
2999         if (port->iotype != up->cur_iotype)
3000                 set_io_from_upio(port);
3001 
3002         if (flags & UART_CONFIG_TYPE)
3003                 autoconfig(up);
3004 
3005         /* if access method is AU, it is a 16550 with a quirk */
3006         if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3007                 up->bugs |= UART_BUG_NOMSR;
3008 
3009         /* HW bugs may trigger IRQ while IIR == NO_INT */
3010         if (port->type == PORT_TEGRA)
3011                 up->bugs |= UART_BUG_NOMSR;
3012 
3013         if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3014                 autoconfig_irq(up);
3015 
3016         if (port->type == PORT_UNKNOWN)
3017                 serial8250_release_std_resource(up);
3018 
3019         register_dev_spec_attr_grp(up);
3020         up->fcr = uart_config[up->port.type].fcr;
3021 }
3022 
3023 static int
3024 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3025 {
3026         if (ser->irq >= nr_irqs || ser->irq < 0 ||
3027             ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3028             ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3029             ser->type == PORT_STARTECH)
3030                 return -EINVAL;
3031         return 0;
3032 }
3033 
3034 static const char *serial8250_type(struct uart_port *port)
3035 {
3036         int type = port->type;
3037 
3038         if (type >= ARRAY_SIZE(uart_config))
3039                 type = 0;
3040         return uart_config[type].name;
3041 }
3042 
3043 static const struct uart_ops serial8250_pops = {
3044         .tx_empty       = serial8250_tx_empty,
3045         .set_mctrl      = serial8250_set_mctrl,
3046         .get_mctrl      = serial8250_get_mctrl,
3047         .stop_tx        = serial8250_stop_tx,
3048         .start_tx       = serial8250_start_tx,
3049         .throttle       = serial8250_throttle,
3050         .unthrottle     = serial8250_unthrottle,
3051         .stop_rx        = serial8250_stop_rx,
3052         .enable_ms      = serial8250_enable_ms,
3053         .break_ctl      = serial8250_break_ctl,
3054         .startup        = serial8250_startup,
3055         .shutdown       = serial8250_shutdown,
3056         .set_termios    = serial8250_set_termios,
3057         .set_ldisc      = serial8250_set_ldisc,
3058         .pm             = serial8250_pm,
3059         .type           = serial8250_type,
3060         .release_port   = serial8250_release_port,
3061         .request_port   = serial8250_request_port,
3062         .config_port    = serial8250_config_port,
3063         .verify_port    = serial8250_verify_port,
3064 #ifdef CONFIG_CONSOLE_POLL
3065         .poll_get_char = serial8250_get_poll_char,
3066         .poll_put_char = serial8250_put_poll_char,
3067 #endif
3068 };
3069 
3070 void serial8250_init_port(struct uart_8250_port *up)
3071 {
3072         struct uart_port *port = &up->port;
3073 
3074         spin_lock_init(&port->lock);
3075         port->ops = &serial8250_pops;
3076 
3077         up->cur_iotype = 0xFF;
3078 }
3079 EXPORT_SYMBOL_GPL(serial8250_init_port);
3080 
3081 void serial8250_set_defaults(struct uart_8250_port *up)
3082 {
3083         struct uart_port *port = &up->port;
3084 
3085         if (up->port.flags & UPF_FIXED_TYPE) {
3086                 unsigned int type = up->port.type;
3087 
3088                 if (!up->port.fifosize)
3089                         up->port.fifosize = uart_config[type].fifo_size;
3090                 if (!up->tx_loadsz)
3091                         up->tx_loadsz = uart_config[type].tx_loadsz;
3092                 if (!up->capabilities)
3093                         up->capabilities = uart_config[type].flags;
3094         }
3095 
3096         set_io_from_upio(port);
3097 
3098         /* default dma handlers */
3099         if (up->dma) {
3100                 if (!up->dma->tx_dma)
3101                         up->dma->tx_dma = serial8250_tx_dma;
3102                 if (!up->dma->rx_dma)
3103                         up->dma->rx_dma = serial8250_rx_dma;
3104         }
3105 }
3106 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3107 
3108 #ifdef CONFIG_SERIAL_8250_CONSOLE
3109 
3110 static void serial8250_console_putchar(struct uart_port *port, int ch)
3111 {
3112         struct uart_8250_port *up = up_to_u8250p(port);
3113 
3114         wait_for_xmitr(up, UART_LSR_THRE);
3115         serial_port_out(port, UART_TX, ch);
3116 }
3117 
3118 /*
3119  *      Restore serial console when h/w power-off detected
3120  */
3121 static void serial8250_console_restore(struct uart_8250_port *up)
3122 {
3123         struct uart_port *port = &up->port;
3124         struct ktermios termios;
3125         unsigned int baud, quot, frac = 0;
3126 
3127         termios.c_cflag = port->cons->cflag;
3128         if (port->state->port.tty && termios.c_cflag == 0)
3129                 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3130 
3131         baud = serial8250_get_baud_rate(port, &termios, NULL);
3132         quot = serial8250_get_divisor(port, baud, &frac);
3133 
3134         serial8250_set_divisor(port, baud, quot, frac);
3135         serial_port_out(port, UART_LCR, up->lcr);
3136         serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3137 }
3138 
3139 /*
3140  *      Print a string to the serial port trying not to disturb
3141  *      any possible real use of the port...
3142  *
3143  *      The console_lock must be held when we get here.
3144  */
3145 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3146                               unsigned int count)
3147 {
3148         struct uart_port *port = &up->port;
3149         unsigned long flags;
3150         unsigned int ier;
3151         int locked = 1;
3152 
3153         touch_nmi_watchdog();
3154 
3155         serial8250_rpm_get(up);
3156 
3157         if (oops_in_progress)
3158                 locked = spin_trylock_irqsave(&port->lock, flags);
3159         else
3160                 spin_lock_irqsave(&port->lock, flags);
3161 
3162         /*
3163          *      First save the IER then disable the interrupts
3164          */
3165         ier = serial_port_in(port, UART_IER);
3166 
3167         if (up->capabilities & UART_CAP_UUE)
3168                 serial_port_out(port, UART_IER, UART_IER_UUE);
3169         else
3170                 serial_port_out(port, UART_IER, 0);
3171 
3172         /* check scratch reg to see if port powered off during system sleep */
3173         if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3174                 serial8250_console_restore(up);
3175                 up->canary = 0;
3176         }
3177 
3178         uart_console_write(port, s, count, serial8250_console_putchar);
3179 
3180         /*
3181          *      Finally, wait for transmitter to become empty
3182          *      and restore the IER
3183          */
3184         wait_for_xmitr(up, BOTH_EMPTY);
3185         serial_port_out(port, UART_IER, ier);
3186 
3187         /*
3188          *      The receive handling will happen properly because the
3189          *      receive ready bit will still be set; it is not cleared
3190          *      on read.  However, modem control will not, we must
3191          *      call it if we have saved something in the saved flags
3192          *      while processing with interrupts off.
3193          */
3194         if (up->msr_saved_flags)
3195                 serial8250_modem_status(up);
3196 
3197         if (locked)
3198                 spin_unlock_irqrestore(&port->lock, flags);
3199         serial8250_rpm_put(up);
3200 }
3201 
3202 static unsigned int probe_baud(struct uart_port *port)
3203 {
3204         unsigned char lcr, dll, dlm;
3205         unsigned int quot;
3206 
3207         lcr = serial_port_in(port, UART_LCR);
3208         serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3209         dll = serial_port_in(port, UART_DLL);
3210         dlm = serial_port_in(port, UART_DLM);
3211         serial_port_out(port, UART_LCR, lcr);
3212 
3213         quot = (dlm << 8) | dll;
3214         return (port->uartclk / 16) / quot;
3215 }
3216 
3217 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3218 {
3219         int baud = 9600;
3220         int bits = 8;
3221         int parity = 'n';
3222         int flow = 'n';
3223 
3224         if (!port->iobase && !port->membase)
3225                 return -ENODEV;
3226 
3227         if (options)
3228                 uart_parse_options(options, &baud, &parity, &bits, &flow);
3229         else if (probe)
3230                 baud = probe_baud(port);
3231 
3232         return uart_set_options(port, port->cons, baud, parity, bits, flow);
3233 }
3234 
3235 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3236 
3237 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/8250/8250_port.c

DEFINITIONS
