This source file includes following definitions.
- tegra_serial_handle_break
- tegra_serial_handle_break
- of_platform_serial_setup
- of_platform_serial_probe
- of_platform_serial_remove
- of_serial_suspend
- of_serial_resume
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7 #include <linux/console.h>
8 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/delay.h>
11 #include <linux/serial_core.h>
12 #include <linux/serial_reg.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/clk.h>
18 #include <linux/reset.h>
19
20 #include "8250.h"
21
22 struct of_serial_info {
23 struct clk *clk;
24 struct reset_control *rst;
25 int type;
26 int line;
27 };
28
29 #ifdef CONFIG_ARCH_TEGRA
30 static void tegra_serial_handle_break(struct uart_port *p)
31 {
32 unsigned int status, tmout = 10000;
33
34 do {
35 status = p->serial_in(p, UART_LSR);
36 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
37 status = p->serial_in(p, UART_RX);
38 else
39 break;
40 if (--tmout == 0)
41 break;
42 udelay(1);
43 } while (1);
44 }
45 #else
46 static inline void tegra_serial_handle_break(struct uart_port *port)
47 {
48 }
49 #endif
50
51
52
53
54 static int of_platform_serial_setup(struct platform_device *ofdev,
55 int type, struct uart_port *port,
56 struct of_serial_info *info)
57 {
58 struct resource resource;
59 struct device_node *np = ofdev->dev.of_node;
60 u32 clk, spd, prop;
61 int ret, irq;
62
63 memset(port, 0, sizeof *port);
64
65 pm_runtime_enable(&ofdev->dev);
66 pm_runtime_get_sync(&ofdev->dev);
67
68 if (of_property_read_u32(np, "clock-frequency", &clk)) {
69
70
71 info->clk = devm_clk_get(&ofdev->dev, NULL);
72 if (IS_ERR(info->clk)) {
73 ret = PTR_ERR(info->clk);
74 if (ret != -EPROBE_DEFER)
75 dev_warn(&ofdev->dev,
76 "failed to get clock: %d\n", ret);
77 goto err_pmruntime;
78 }
79
80 ret = clk_prepare_enable(info->clk);
81 if (ret < 0)
82 goto err_pmruntime;
83
84 clk = clk_get_rate(info->clk);
85 }
86
87 if (of_property_read_u32(np, "current-speed", &spd) == 0)
88 port->custom_divisor = clk / (16 * spd);
89
90 ret = of_address_to_resource(np, 0, &resource);
91 if (ret) {
92 dev_warn(&ofdev->dev, "invalid address\n");
93 goto err_unprepare;
94 }
95
96 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
97 UPF_FIXED_TYPE;
98 spin_lock_init(&port->lock);
99
100 if (resource_type(&resource) == IORESOURCE_IO) {
101 port->iotype = UPIO_PORT;
102 port->iobase = resource.start;
103 } else {
104 port->mapbase = resource.start;
105 port->mapsize = resource_size(&resource);
106
107
108 if (of_property_read_u32(np, "reg-offset", &prop) == 0)
109 port->mapbase += prop;
110
111 port->iotype = UPIO_MEM;
112 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
113 switch (prop) {
114 case 1:
115 port->iotype = UPIO_MEM;
116 break;
117 case 2:
118 port->iotype = UPIO_MEM16;
119 break;
120 case 4:
121 port->iotype = of_device_is_big_endian(np) ?
122 UPIO_MEM32BE : UPIO_MEM32;
123 break;
124 default:
125 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
126 prop);
127 ret = -EINVAL;
128 goto err_unprepare;
129 }
130 }
131 port->flags |= UPF_IOREMAP;
132 }
133
134
135 if (of_device_is_compatible(np, "mrvl,mmp-uart"))
136 port->regshift = 2;
137
138
139 if (of_property_read_u32(np, "reg-shift", &prop) == 0)
140 port->regshift = prop;
141
142
143 if (of_property_read_u32(np, "fifo-size", &prop) == 0)
144 port->fifosize = prop;
145
146
147 ret = of_alias_get_id(np, "serial");
148 if (ret >= 0)
149 port->line = ret;
150
151 irq = of_irq_get(np, 0);
152 if (irq < 0) {
153 if (irq == -EPROBE_DEFER) {
154 ret = -EPROBE_DEFER;
155 goto err_unprepare;
156 }
157
158 irq = 0;
159 }
160
161 port->irq = irq;
162
163 info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL);
164 if (IS_ERR(info->rst)) {
165 ret = PTR_ERR(info->rst);
166 goto err_unprepare;
167 }
168
169 ret = reset_control_deassert(info->rst);
170 if (ret)
171 goto err_unprepare;
172
173 port->type = type;
174 port->uartclk = clk;
175
176 if (of_property_read_bool(np, "no-loopback-test"))
177 port->flags |= UPF_SKIP_TEST;
178
179 port->dev = &ofdev->dev;
180
181 switch (type) {
182 case PORT_TEGRA:
183 port->handle_break = tegra_serial_handle_break;
184 break;
185
186 case PORT_RT2880:
187 port->iotype = UPIO_AU;
188 break;
189 }
190
191 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
192 (of_device_is_compatible(np, "fsl,ns16550") ||
193 of_device_is_compatible(np, "fsl,16550-FIFO64")))
194 port->handle_irq = fsl8250_handle_irq;
195
196 return 0;
197 err_unprepare:
198 clk_disable_unprepare(info->clk);
199 err_pmruntime:
200 pm_runtime_put_sync(&ofdev->dev);
201 pm_runtime_disable(&ofdev->dev);
202 return ret;
203 }
204
205
206
207
208 static int of_platform_serial_probe(struct platform_device *ofdev)
209 {
210 struct of_serial_info *info;
211 struct uart_8250_port port8250;
212 unsigned int port_type;
213 u32 tx_threshold;
214 int ret;
215
216 port_type = (unsigned long)of_device_get_match_data(&ofdev->dev);
217 if (port_type == PORT_UNKNOWN)
218 return -EINVAL;
219
220 if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
221 return -EBUSY;
222
223 info = kzalloc(sizeof(*info), GFP_KERNEL);
224 if (info == NULL)
225 return -ENOMEM;
226
227 memset(&port8250, 0, sizeof(port8250));
228 ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info);
229 if (ret)
230 goto err_free;
231
232 if (port8250.port.fifosize)
233 port8250.capabilities = UART_CAP_FIFO;
234
235
236 if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
237 &tx_threshold) == 0) &&
238 (tx_threshold < port8250.port.fifosize))
239 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold;
240
241 if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control"))
242 port8250.capabilities |= UART_CAP_AFE;
243
244 if (of_property_read_u32(ofdev->dev.of_node,
245 "overrun-throttle-ms",
246 &port8250.overrun_backoff_time_ms) != 0)
247 port8250.overrun_backoff_time_ms = 0;
248
249 ret = serial8250_register_8250_port(&port8250);
250 if (ret < 0)
251 goto err_dispose;
252
253 info->type = port_type;
254 info->line = ret;
255 platform_set_drvdata(ofdev, info);
256 return 0;
257 err_dispose:
258 irq_dispose_mapping(port8250.port.irq);
259 pm_runtime_put_sync(&ofdev->dev);
260 pm_runtime_disable(&ofdev->dev);
261 clk_disable_unprepare(info->clk);
262 err_free:
263 kfree(info);
264 return ret;
265 }
266
267
268
269
270 static int of_platform_serial_remove(struct platform_device *ofdev)
271 {
272 struct of_serial_info *info = platform_get_drvdata(ofdev);
273
274 serial8250_unregister_port(info->line);
275
276 reset_control_assert(info->rst);
277 pm_runtime_put_sync(&ofdev->dev);
278 pm_runtime_disable(&ofdev->dev);
279 clk_disable_unprepare(info->clk);
280 kfree(info);
281 return 0;
282 }
283
284 #ifdef CONFIG_PM_SLEEP
285 static int of_serial_suspend(struct device *dev)
286 {
287 struct of_serial_info *info = dev_get_drvdata(dev);
288 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
289 struct uart_port *port = &port8250->port;
290
291 serial8250_suspend_port(info->line);
292
293 if (!uart_console(port) || console_suspend_enabled) {
294 pm_runtime_put_sync(dev);
295 clk_disable_unprepare(info->clk);
296 }
297 return 0;
298 }
299
300 static int of_serial_resume(struct device *dev)
301 {
302 struct of_serial_info *info = dev_get_drvdata(dev);
303 struct uart_8250_port *port8250 = serial8250_get_port(info->line);
304 struct uart_port *port = &port8250->port;
305
306 if (!uart_console(port) || console_suspend_enabled) {
307 pm_runtime_get_sync(dev);
308 clk_prepare_enable(info->clk);
309 }
310
311 serial8250_resume_port(info->line);
312
313 return 0;
314 }
315 #endif
316 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
317
318
319
320
321 static const struct of_device_id of_platform_serial_table[] = {
322 { .compatible = "ns8250", .data = (void *)PORT_8250, },
323 { .compatible = "ns16450", .data = (void *)PORT_16450, },
324 { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
325 { .compatible = "ns16550", .data = (void *)PORT_16550, },
326 { .compatible = "ns16750", .data = (void *)PORT_16750, },
327 { .compatible = "ns16850", .data = (void *)PORT_16850, },
328 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
329 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
330 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
331 { .compatible = "intel,xscale-uart", .data = (void *)PORT_XSCALE, },
332 { .compatible = "altr,16550-FIFO32",
333 .data = (void *)PORT_ALTR_16550_F32, },
334 { .compatible = "altr,16550-FIFO64",
335 .data = (void *)PORT_ALTR_16550_F64, },
336 { .compatible = "altr,16550-FIFO128",
337 .data = (void *)PORT_ALTR_16550_F128, },
338 { .compatible = "mediatek,mtk-btif",
339 .data = (void *)PORT_MTK_BTIF, },
340 { .compatible = "mrvl,mmp-uart",
341 .data = (void *)PORT_XSCALE, },
342 { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
343 { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
344 { },
345 };
346 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
347
348 static struct platform_driver of_platform_serial_driver = {
349 .driver = {
350 .name = "of_serial",
351 .of_match_table = of_platform_serial_table,
352 .pm = &of_serial_pm_ops,
353 },
354 .probe = of_platform_serial_probe,
355 .remove = of_platform_serial_remove,
356 };
357
358 module_platform_driver(of_platform_serial_driver);
359
360 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
361 MODULE_LICENSE("GPL");
362 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");