drivers/tty/serial/8250/8250

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This source file includes following definitions.
moan_device
setup_port
addidata_apci7800_setup
afavlab_setup
pci_hp_diva_init
pci_hp_diva_setup
pci_inteli960ni_init
pci_plx9050_init
pci_plx9050_exit
pci_ni8420_exit
pci_ni8430_exit
sbs_setup
sbs_init
sbs_exit
pci_siig10x_init
pci_siig20x_init
pci_siig_init
pci_siig_setup
pci_timedia_probe
pci_timedia_init
pci_timedia_setup
titan_400l_800l_setup
pci_xircom_init
pci_ni8420_init
pci_ni8430_init
pci_ni8430_setup
pci_netmos_9900_setup
pci_netmos_9900_numports
pci_netmos_init
pci_ite887x_init
pci_ite887x_exit
pci_endrun_init
pci_oxsemi_tornado_init
pci_asix_setup
pci_quatech_amcc
pci_quatech_rqopr
pci_quatech_wqopr
pci_quatech_rqmcr
pci_quatech_wqmcr
pci_quatech_has_qmcr
pci_quatech_test
pci_quatech_clock
pci_quatech_rs422
pci_quatech_init
pci_quatech_setup
pci_quatech_exit
pci_default_setup
pericom_do_set_divisor
pci_pericom_setup
pci_pericom_setup_four_at_eight
ce4100_serial_setup
pci_omegapci_setup
pci_brcm_trumanage_setup
pci_fintek_rs485_config
pci_fintek_setup
pci_fintek_init
f815xxa_mem_serial_out
pci_fintek_f815xxa_setup
pci_fintek_f815xxa_init
skip_tx_en_setup
kt_handle_break
kt_serial_in
kt_serial_setup
pci_eg20t_init
pci_wch_ch353_setup
pci_wch_ch355_setup
pci_wch_ch38x_setup
pci_sunix_setup
pci_moxa_setup
quirk_id_matches
find_quirk
get_pci_irq
serial_pci_is_class_communication
serial_pci_guess_board
serial_pci_matches
pciserial_init_ports
pciserial_detach_ports
pciserial_remove_ports
pciserial_suspend_ports
pciserial_resume_ports
pciserial_init_one
pciserial_remove_one
pciserial_suspend_one
pciserial_resume_one
serial8250_io_error_detected
serial8250_io_slot_reset
serial8250_io_resume
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Probe module for 8250/16550-type PCI serial ports.
   4  *
   5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   6  *
   7  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   8  */
   9 #undef DEBUG
  10 #include <linux/module.h>
  11 #include <linux/pci.h>
  12 #include <linux/string.h>
  13 #include <linux/kernel.h>
  14 #include <linux/slab.h>
  15 #include <linux/delay.h>
  16 #include <linux/tty.h>
  17 #include <linux/serial_reg.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/8250_pci.h>
  20 #include <linux/bitops.h>
  21 
  22 #include <asm/byteorder.h>
  23 #include <asm/io.h>
  24 
  25 #include "8250.h"
  26 
  27 /*
  28  * init function returns:
  29  *  > 0 - number of ports
  30  *  = 0 - use board->num_ports
  31  *  < 0 - error
  32  */
  33 struct pci_serial_quirk {
  34         u32     vendor;
  35         u32     device;
  36         u32     subvendor;
  37         u32     subdevice;
  38         int     (*probe)(struct pci_dev *dev);
  39         int     (*init)(struct pci_dev *dev);
  40         int     (*setup)(struct serial_private *,
  41                          const struct pciserial_board *,
  42                          struct uart_8250_port *, int);
  43         void    (*exit)(struct pci_dev *dev);
  44 };
  45 
  46 struct f815xxa_data {
  47         spinlock_t lock;
  48         int idx;
  49 };
  50 
  51 #define PCI_NUM_BAR_RESOURCES   6
  52 
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         struct pci_serial_quirk *quirk;
  57         const struct pciserial_board *board;
  58         int                     line[0];
  59 };
  60 
  61 static const struct pci_device_id pci_use_msi[] = {
  62         { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  63                          0xA000, 0x1000) },
  64         { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
  65                          0xA000, 0x1000) },
  66         { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
  67                          0xA000, 0x1000) },
  68         { }
  69 };
  70 
  71 static int pci_default_setup(struct serial_private*,
  72           const struct pciserial_board*, struct uart_8250_port *, int);
  73 
  74 static void moan_device(const char *str, struct pci_dev *dev)
  75 {
  76         dev_err(&dev->dev,
  77                "%s: %s\n"
  78                "Please send the output of lspci -vv, this\n"
  79                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  80                "manufacturer and name of serial board or\n"
  81                "modem board to <linux-serial@vger.kernel.org>.\n",
  82                pci_name(dev), str, dev->vendor, dev->device,
  83                dev->subsystem_vendor, dev->subsystem_device);
  84 }
  85 
  86 static int
  87 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  88            int bar, int offset, int regshift)
  89 {
  90         struct pci_dev *dev = priv->dev;
  91 
  92         if (bar >= PCI_NUM_BAR_RESOURCES)
  93                 return -EINVAL;
  94 
  95         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  96                 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
  97                         return -ENOMEM;
  98 
  99                 port->port.iotype = UPIO_MEM;
 100                 port->port.iobase = 0;
 101                 port->port.mapbase = pci_resource_start(dev, bar) + offset;
 102                 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
 103                 port->port.regshift = regshift;
 104         } else {
 105                 port->port.iotype = UPIO_PORT;
 106                 port->port.iobase = pci_resource_start(dev, bar) + offset;
 107                 port->port.mapbase = 0;
 108                 port->port.membase = NULL;
 109                 port->port.regshift = 0;
 110         }
 111         return 0;
 112 }
 113 
 114 /*
 115  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 116  */
 117 static int addidata_apci7800_setup(struct serial_private *priv,
 118                                 const struct pciserial_board *board,
 119                                 struct uart_8250_port *port, int idx)
 120 {
 121         unsigned int bar = 0, offset = board->first_offset;
 122         bar = FL_GET_BASE(board->flags);
 123 
 124         if (idx < 2) {
 125                 offset += idx * board->uart_offset;
 126         } else if ((idx >= 2) && (idx < 4)) {
 127                 bar += 1;
 128                 offset += ((idx - 2) * board->uart_offset);
 129         } else if ((idx >= 4) && (idx < 6)) {
 130                 bar += 2;
 131                 offset += ((idx - 4) * board->uart_offset);
 132         } else if (idx >= 6) {
 133                 bar += 3;
 134                 offset += ((idx - 6) * board->uart_offset);
 135         }
 136 
 137         return setup_port(priv, port, bar, offset, board->reg_shift);
 138 }
 139 
 140 /*
 141  * AFAVLAB uses a different mixture of BARs and offsets
 142  * Not that ugly ;) -- HW
 143  */
 144 static int
 145 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 146               struct uart_8250_port *port, int idx)
 147 {
 148         unsigned int bar, offset = board->first_offset;
 149 
 150         bar = FL_GET_BASE(board->flags);
 151         if (idx < 4)
 152                 bar += idx;
 153         else {
 154                 bar = 4;
 155                 offset += (idx - 4) * board->uart_offset;
 156         }
 157 
 158         return setup_port(priv, port, bar, offset, board->reg_shift);
 159 }
 160 
 161 /*
 162  * HP's Remote Management Console.  The Diva chip came in several
 163  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 164  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 165  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 166  * one Diva chip, but it has been expanded to 5 UARTs.
 167  */
 168 static int pci_hp_diva_init(struct pci_dev *dev)
 169 {
 170         int rc = 0;
 171 
 172         switch (dev->subsystem_device) {
 173         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 174         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 175         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 176         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 177                 rc = 3;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 180                 rc = 2;
 181                 break;
 182         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 183                 rc = 4;
 184                 break;
 185         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 186         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 187                 rc = 1;
 188                 break;
 189         }
 190 
 191         return rc;
 192 }
 193 
 194 /*
 195  * HP's Diva chip puts the 4th/5th serial port further out, and
 196  * some serial ports are supposed to be hidden on certain models.
 197  */
 198 static int
 199 pci_hp_diva_setup(struct serial_private *priv,
 200                 const struct pciserial_board *board,
 201                 struct uart_8250_port *port, int idx)
 202 {
 203         unsigned int offset = board->first_offset;
 204         unsigned int bar = FL_GET_BASE(board->flags);
 205 
 206         switch (priv->dev->subsystem_device) {
 207         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 208                 if (idx == 3)
 209                         idx++;
 210                 break;
 211         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 212                 if (idx > 0)
 213                         idx++;
 214                 if (idx > 2)
 215                         idx++;
 216                 break;
 217         }
 218         if (idx > 2)
 219                 offset = 0x18;
 220 
 221         offset += idx * board->uart_offset;
 222 
 223         return setup_port(priv, port, bar, offset, board->reg_shift);
 224 }
 225 
 226 /*
 227  * Added for EKF Intel i960 serial boards
 228  */
 229 static int pci_inteli960ni_init(struct pci_dev *dev)
 230 {
 231         u32 oldval;
 232 
 233         if (!(dev->subsystem_device & 0x1000))
 234                 return -ENODEV;
 235 
 236         /* is firmware started? */
 237         pci_read_config_dword(dev, 0x44, &oldval);
 238         if (oldval == 0x00001000L) { /* RESET value */
 239                 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 240                 return -ENODEV;
 241         }
 242         return 0;
 243 }
 244 
 245 /*
 246  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 247  * that the card interrupt be explicitly enabled or disabled.  This
 248  * seems to be mainly needed on card using the PLX which also use I/O
 249  * mapped memory.
 250  */
 251 static int pci_plx9050_init(struct pci_dev *dev)
 252 {
 253         u8 irq_config;
 254         void __iomem *p;
 255 
 256         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 257                 moan_device("no memory in bar 0", dev);
 258                 return 0;
 259         }
 260 
 261         irq_config = 0x41;
 262         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 263             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 264                 irq_config = 0x43;
 265 
 266         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 267             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 268                 /*
 269                  * As the megawolf cards have the int pins active
 270                  * high, and have 2 UART chips, both ints must be
 271                  * enabled on the 9050. Also, the UARTS are set in
 272                  * 16450 mode by default, so we have to enable the
 273                  * 16C950 'enhanced' mode so that we can use the
 274                  * deep FIFOs
 275                  */
 276                 irq_config = 0x5b;
 277         /*
 278          * enable/disable interrupts
 279          */
 280         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 281         if (p == NULL)
 282                 return -ENOMEM;
 283         writel(irq_config, p + 0x4c);
 284 
 285         /*
 286          * Read the register back to ensure that it took effect.
 287          */
 288         readl(p + 0x4c);
 289         iounmap(p);
 290 
 291         return 0;
 292 }
 293 
 294 static void pci_plx9050_exit(struct pci_dev *dev)
 295 {
 296         u8 __iomem *p;
 297 
 298         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 299                 return;
 300 
 301         /*
 302          * disable interrupts
 303          */
 304         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 305         if (p != NULL) {
 306                 writel(0, p + 0x4c);
 307 
 308                 /*
 309                  * Read the register back to ensure that it took effect.
 310                  */
 311                 readl(p + 0x4c);
 312                 iounmap(p);
 313         }
 314 }
 315 
 316 #define NI8420_INT_ENABLE_REG   0x38
 317 #define NI8420_INT_ENABLE_BIT   0x2000
 318 
 319 static void pci_ni8420_exit(struct pci_dev *dev)
 320 {
 321         void __iomem *p;
 322         unsigned int bar = 0;
 323 
 324         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 325                 moan_device("no memory in bar", dev);
 326                 return;
 327         }
 328 
 329         p = pci_ioremap_bar(dev, bar);
 330         if (p == NULL)
 331                 return;
 332 
 333         /* Disable the CPU Interrupt */
 334         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 335                p + NI8420_INT_ENABLE_REG);
 336         iounmap(p);
 337 }
 338 
 339 
 340 /* MITE registers */
 341 #define MITE_IOWBSR1    0xc4
 342 #define MITE_IOWCR1     0xf4
 343 #define MITE_LCIMR1     0x08
 344 #define MITE_LCIMR2     0x10
 345 
 346 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 347 
 348 static void pci_ni8430_exit(struct pci_dev *dev)
 349 {
 350         void __iomem *p;
 351         unsigned int bar = 0;
 352 
 353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 354                 moan_device("no memory in bar", dev);
 355                 return;
 356         }
 357 
 358         p = pci_ioremap_bar(dev, bar);
 359         if (p == NULL)
 360                 return;
 361 
 362         /* Disable the CPU Interrupt */
 363         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 364         iounmap(p);
 365 }
 366 
 367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 368 static int
 369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 370                 struct uart_8250_port *port, int idx)
 371 {
 372         unsigned int bar, offset = board->first_offset;
 373 
 374         bar = 0;
 375 
 376         if (idx < 4) {
 377                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 378                 offset += idx * board->uart_offset;
 379         } else if (idx < 8) {
 380                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 381                 offset += idx * board->uart_offset + 0xC00;
 382         } else /* we have only 8 ports on PMC-OCTALPRO */
 383                 return 1;
 384 
 385         return setup_port(priv, port, bar, offset, board->reg_shift);
 386 }
 387 
 388 /*
 389 * This does initialization for PMC OCTALPRO cards:
 390 * maps the device memory, resets the UARTs (needed, bc
 391 * if the module is removed and inserted again, the card
 392 * is in the sleep mode) and enables global interrupt.
 393 */
 394 
 395 /* global control register offset for SBS PMC-OctalPro */
 396 #define OCT_REG_CR_OFF          0x500
 397 
 398 static int sbs_init(struct pci_dev *dev)
 399 {
 400         u8 __iomem *p;
 401 
 402         p = pci_ioremap_bar(dev, 0);
 403 
 404         if (p == NULL)
 405                 return -ENOMEM;
 406         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 407         writeb(0x10, p + OCT_REG_CR_OFF);
 408         udelay(50);
 409         writeb(0x0, p + OCT_REG_CR_OFF);
 410 
 411         /* Set bit-2 (INTENABLE) of Control Register */
 412         writeb(0x4, p + OCT_REG_CR_OFF);
 413         iounmap(p);
 414 
 415         return 0;
 416 }
 417 
 418 /*
 419  * Disables the global interrupt of PMC-OctalPro
 420  */
 421 
 422 static void sbs_exit(struct pci_dev *dev)
 423 {
 424         u8 __iomem *p;
 425 
 426         p = pci_ioremap_bar(dev, 0);
 427         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 428         if (p != NULL)
 429                 writeb(0, p + OCT_REG_CR_OFF);
 430         iounmap(p);
 431 }
 432 
 433 /*
 434  * SIIG serial cards have an PCI interface chip which also controls
 435  * the UART clocking frequency. Each UART can be clocked independently
 436  * (except cards equipped with 4 UARTs) and initial clocking settings
 437  * are stored in the EEPROM chip. It can cause problems because this
 438  * version of serial driver doesn't support differently clocked UART's
 439  * on single PCI card. To prevent this, initialization functions set
 440  * high frequency clocking for all UART's on given card. It is safe (I
 441  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 442  * with other OSes (like M$ DOS).
 443  *
 444  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 445  *
 446  * There is two family of SIIG serial cards with different PCI
 447  * interface chip and different configuration methods:
 448  *     - 10x cards have control registers in IO and/or memory space;
 449  *     - 20x cards have control registers in standard PCI configuration space.
 450  *
 451  * Note: all 10x cards have PCI device ids 0x10..
 452  *       all 20x cards have PCI device ids 0x20..
 453  *
 454  * There are also Quartet Serial cards which use Oxford Semiconductor
 455  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 456  *
 457  * Note: some SIIG cards are probed by the parport_serial object.
 458  */
 459 
 460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 462 
 463 static int pci_siig10x_init(struct pci_dev *dev)
 464 {
 465         u16 data;
 466         void __iomem *p;
 467 
 468         switch (dev->device & 0xfff8) {
 469         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 470                 data = 0xffdf;
 471                 break;
 472         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 473                 data = 0xf7ff;
 474                 break;
 475         default:                        /* 1S1P, 4S */
 476                 data = 0xfffb;
 477                 break;
 478         }
 479 
 480         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 481         if (p == NULL)
 482                 return -ENOMEM;
 483 
 484         writew(readw(p + 0x28) & data, p + 0x28);
 485         readw(p + 0x28);
 486         iounmap(p);
 487         return 0;
 488 }
 489 
 490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 492 
 493 static int pci_siig20x_init(struct pci_dev *dev)
 494 {
 495         u8 data;
 496 
 497         /* Change clock frequency for the first UART. */
 498         pci_read_config_byte(dev, 0x6f, &data);
 499         pci_write_config_byte(dev, 0x6f, data & 0xef);
 500 
 501         /* If this card has 2 UART, we have to do the same with second UART. */
 502         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 503             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 504                 pci_read_config_byte(dev, 0x73, &data);
 505                 pci_write_config_byte(dev, 0x73, data & 0xef);
 506         }
 507         return 0;
 508 }
 509 
 510 static int pci_siig_init(struct pci_dev *dev)
 511 {
 512         unsigned int type = dev->device & 0xff00;
 513 
 514         if (type == 0x1000)
 515                 return pci_siig10x_init(dev);
 516         else if (type == 0x2000)
 517                 return pci_siig20x_init(dev);
 518 
 519         moan_device("Unknown SIIG card", dev);
 520         return -ENODEV;
 521 }
 522 
 523 static int pci_siig_setup(struct serial_private *priv,
 524                           const struct pciserial_board *board,
 525                           struct uart_8250_port *port, int idx)
 526 {
 527         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 528 
 529         if (idx > 3) {
 530                 bar = 4;
 531                 offset = (idx - 4) * 8;
 532         }
 533 
 534         return setup_port(priv, port, bar, offset, 0);
 535 }
 536 
 537 /*
 538  * Timedia has an explosion of boards, and to avoid the PCI table from
 539  * growing *huge*, we use this function to collapse some 70 entries
 540  * in the PCI table into one, for sanity's and compactness's sake.
 541  */
 542 static const unsigned short timedia_single_port[] = {
 543         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 544 };
 545 
 546 static const unsigned short timedia_dual_port[] = {
 547         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 548         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 549         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 550         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 551         0xD079, 0
 552 };
 553 
 554 static const unsigned short timedia_quad_port[] = {
 555         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 556         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 557         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 558         0xB157, 0
 559 };
 560 
 561 static const unsigned short timedia_eight_port[] = {
 562         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 563         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 564 };
 565 
 566 static const struct timedia_struct {
 567         int num;
 568         const unsigned short *ids;
 569 } timedia_data[] = {
 570         { 1, timedia_single_port },
 571         { 2, timedia_dual_port },
 572         { 4, timedia_quad_port },
 573         { 8, timedia_eight_port }
 574 };
 575 
 576 /*
 577  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 578  * listing them individually, this driver merely grabs them all with
 579  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 580  * and should be left free to be claimed by parport_serial instead.
 581  */
 582 static int pci_timedia_probe(struct pci_dev *dev)
 583 {
 584         /*
 585          * Check the third digit of the subdevice ID
 586          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 587          */
 588         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 589                 dev_info(&dev->dev,
 590                         "ignoring Timedia subdevice %04x for parport_serial\n",
 591                         dev->subsystem_device);
 592                 return -ENODEV;
 593         }
 594 
 595         return 0;
 596 }
 597 
 598 static int pci_timedia_init(struct pci_dev *dev)
 599 {
 600         const unsigned short *ids;
 601         int i, j;
 602 
 603         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 604                 ids = timedia_data[i].ids;
 605                 for (j = 0; ids[j]; j++)
 606                         if (dev->subsystem_device == ids[j])
 607                                 return timedia_data[i].num;
 608         }
 609         return 0;
 610 }
 611 
 612 /*
 613  * Timedia/SUNIX uses a mixture of BARs and offsets
 614  * Ugh, this is ugly as all hell --- TYT
 615  */
 616 static int
 617 pci_timedia_setup(struct serial_private *priv,
 618                   const struct pciserial_board *board,
 619                   struct uart_8250_port *port, int idx)
 620 {
 621         unsigned int bar = 0, offset = board->first_offset;
 622 
 623         switch (idx) {
 624         case 0:
 625                 bar = 0;
 626                 break;
 627         case 1:
 628                 offset = board->uart_offset;
 629                 bar = 0;
 630                 break;
 631         case 2:
 632                 bar = 1;
 633                 break;
 634         case 3:
 635                 offset = board->uart_offset;
 636                 /* FALLTHROUGH */
 637         case 4: /* BAR 2 */
 638         case 5: /* BAR 3 */
 639         case 6: /* BAR 4 */
 640         case 7: /* BAR 5 */
 641                 bar = idx - 2;
 642         }
 643 
 644         return setup_port(priv, port, bar, offset, board->reg_shift);
 645 }
 646 
 647 /*
 648  * Some Titan cards are also a little weird
 649  */
 650 static int
 651 titan_400l_800l_setup(struct serial_private *priv,
 652                       const struct pciserial_board *board,
 653                       struct uart_8250_port *port, int idx)
 654 {
 655         unsigned int bar, offset = board->first_offset;
 656 
 657         switch (idx) {
 658         case 0:
 659                 bar = 1;
 660                 break;
 661         case 1:
 662                 bar = 2;
 663                 break;
 664         default:
 665                 bar = 4;
 666                 offset = (idx - 2) * board->uart_offset;
 667         }
 668 
 669         return setup_port(priv, port, bar, offset, board->reg_shift);
 670 }
 671 
 672 static int pci_xircom_init(struct pci_dev *dev)
 673 {
 674         msleep(100);
 675         return 0;
 676 }
 677 
 678 static int pci_ni8420_init(struct pci_dev *dev)
 679 {
 680         void __iomem *p;
 681         unsigned int bar = 0;
 682 
 683         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 684                 moan_device("no memory in bar", dev);
 685                 return 0;
 686         }
 687 
 688         p = pci_ioremap_bar(dev, bar);
 689         if (p == NULL)
 690                 return -ENOMEM;
 691 
 692         /* Enable CPU Interrupt */
 693         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 694                p + NI8420_INT_ENABLE_REG);
 695 
 696         iounmap(p);
 697         return 0;
 698 }
 699 
 700 #define MITE_IOWBSR1_WSIZE      0xa
 701 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 702 #define MITE_IOWBSR1_WENAB      (1 << 7)
 703 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 704 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 706 
 707 static int pci_ni8430_init(struct pci_dev *dev)
 708 {
 709         void __iomem *p;
 710         struct pci_bus_region region;
 711         u32 device_window;
 712         unsigned int bar = 0;
 713 
 714         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 715                 moan_device("no memory in bar", dev);
 716                 return 0;
 717         }
 718 
 719         p = pci_ioremap_bar(dev, bar);
 720         if (p == NULL)
 721                 return -ENOMEM;
 722 
 723         /*
 724          * Set device window address and size in BAR0, while acknowledging that
 725          * the resource structure may contain a translated address that differs
 726          * from the address the device responds to.
 727          */
 728         pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 729         device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 730                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 731         writel(device_window, p + MITE_IOWBSR1);
 732 
 733         /* Set window access to go to RAMSEL IO address space */
 734         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 735                p + MITE_IOWCR1);
 736 
 737         /* Enable IO Bus Interrupt 0 */
 738         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 739 
 740         /* Enable CPU Interrupt */
 741         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 742 
 743         iounmap(p);
 744         return 0;
 745 }
 746 
 747 /* UART Port Control Register */
 748 #define NI8430_PORTCON  0x0f
 749 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 750 
 751 static int
 752 pci_ni8430_setup(struct serial_private *priv,
 753                  const struct pciserial_board *board,
 754                  struct uart_8250_port *port, int idx)
 755 {
 756         struct pci_dev *dev = priv->dev;
 757         void __iomem *p;
 758         unsigned int bar, offset = board->first_offset;
 759 
 760         if (idx >= board->num_ports)
 761                 return 1;
 762 
 763         bar = FL_GET_BASE(board->flags);
 764         offset += idx * board->uart_offset;
 765 
 766         p = pci_ioremap_bar(dev, bar);
 767         if (!p)
 768                 return -ENOMEM;
 769 
 770         /* enable the transceiver */
 771         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 772                p + offset + NI8430_PORTCON);
 773 
 774         iounmap(p);
 775 
 776         return setup_port(priv, port, bar, offset, board->reg_shift);
 777 }
 778 
 779 static int pci_netmos_9900_setup(struct serial_private *priv,
 780                                 const struct pciserial_board *board,
 781                                 struct uart_8250_port *port, int idx)
 782 {
 783         unsigned int bar;
 784 
 785         if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 786             (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 787                 /* netmos apparently orders BARs by datasheet layout, so serial
 788                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 789                  */
 790                 bar = 3 * idx;
 791 
 792                 return setup_port(priv, port, bar, 0, board->reg_shift);
 793         } else {
 794                 return pci_default_setup(priv, board, port, idx);
 795         }
 796 }
 797 
 798 /* the 99xx series comes with a range of device IDs and a variety
 799  * of capabilities:
 800  *
 801  * 9900 has varying capabilities and can cascade to sub-controllers
 802  *   (cascading should be purely internal)
 803  * 9904 is hardwired with 4 serial ports
 804  * 9912 and 9922 are hardwired with 2 serial ports
 805  */
 806 static int pci_netmos_9900_numports(struct pci_dev *dev)
 807 {
 808         unsigned int c = dev->class;
 809         unsigned int pi;
 810         unsigned short sub_serports;
 811 
 812         pi = c & 0xff;
 813 
 814         if (pi == 2)
 815                 return 1;
 816 
 817         if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 818                 /* two possibilities: 0x30ps encodes number of parallel and
 819                  * serial ports, or 0x1000 indicates *something*. This is not
 820                  * immediately obvious, since the 2s1p+4s configuration seems
 821                  * to offer all functionality on functions 0..2, while still
 822                  * advertising the same function 3 as the 4s+2s1p config.
 823                  */
 824                 sub_serports = dev->subsystem_device & 0xf;
 825                 if (sub_serports > 0)
 826                         return sub_serports;
 827 
 828                 dev_err(&dev->dev,
 829                         "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 830                 return 0;
 831         }
 832 
 833         moan_device("unknown NetMos/Mostech program interface", dev);
 834         return 0;
 835 }
 836 
 837 static int pci_netmos_init(struct pci_dev *dev)
 838 {
 839         /* subdevice 0x00PS means <P> parallel, <S> serial */
 840         unsigned int num_serial = dev->subsystem_device & 0xf;
 841 
 842         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 843                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 844                 return 0;
 845 
 846         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 847                         dev->subsystem_device == 0x0299)
 848                 return 0;
 849 
 850         switch (dev->device) { /* FALLTHROUGH on all */
 851         case PCI_DEVICE_ID_NETMOS_9904:
 852         case PCI_DEVICE_ID_NETMOS_9912:
 853         case PCI_DEVICE_ID_NETMOS_9922:
 854         case PCI_DEVICE_ID_NETMOS_9900:
 855                 num_serial = pci_netmos_9900_numports(dev);
 856                 break;
 857 
 858         default:
 859                 break;
 860         }
 861 
 862         if (num_serial == 0) {
 863                 moan_device("unknown NetMos/Mostech device", dev);
 864                 return -ENODEV;
 865         }
 866 
 867         return num_serial;
 868 }
 869 
 870 /*
 871  * These chips are available with optionally one parallel port and up to
 872  * two serial ports. Unfortunately they all have the same product id.
 873  *
 874  * Basic configuration is done over a region of 32 I/O ports. The base
 875  * ioport is called INTA or INTC, depending on docs/other drivers.
 876  *
 877  * The region of the 32 I/O ports is configured in POSIO0R...
 878  */
 879 
 880 /* registers */
 881 #define ITE_887x_MISCR          0x9c
 882 #define ITE_887x_INTCBAR        0x78
 883 #define ITE_887x_UARTBAR        0x7c
 884 #define ITE_887x_PS0BAR         0x10
 885 #define ITE_887x_POSIO0         0x60
 886 
 887 /* I/O space size */
 888 #define ITE_887x_IOSIZE         32
 889 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 890 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 891 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 892 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 893 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 894 #define ITE_887x_POSIO_SPEED            (3 << 29)
 895 /* enable IO_Space bit */
 896 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 897 
 898 static int pci_ite887x_init(struct pci_dev *dev)
 899 {
 900         /* inta_addr are the configuration addresses of the ITE */
 901         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 902                                                         0x200, 0x280, 0 };
 903         int ret, i, type;
 904         struct resource *iobase = NULL;
 905         u32 miscr, uartbar, ioport;
 906 
 907         /* search for the base-ioport */
 908         i = 0;
 909         while (inta_addr[i] && iobase == NULL) {
 910                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 911                                                                 "ite887x");
 912                 if (iobase != NULL) {
 913                         /* write POSIO0R - speed | size | ioport */
 914                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 915                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 916                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 917                         /* write INTCBAR - ioport */
 918                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 919                                                                 inta_addr[i]);
 920                         ret = inb(inta_addr[i]);
 921                         if (ret != 0xff) {
 922                                 /* ioport connected */
 923                                 break;
 924                         }
 925                         release_region(iobase->start, ITE_887x_IOSIZE);
 926                         iobase = NULL;
 927                 }
 928                 i++;
 929         }
 930 
 931         if (!inta_addr[i]) {
 932                 dev_err(&dev->dev, "ite887x: could not find iobase\n");
 933                 return -ENODEV;
 934         }
 935 
 936         /* start of undocumented type checking (see parport_pc.c) */
 937         type = inb(iobase->start + 0x18) & 0x0f;
 938 
 939         switch (type) {
 940         case 0x2:       /* ITE8871 (1P) */
 941         case 0xa:       /* ITE8875 (1P) */
 942                 ret = 0;
 943                 break;
 944         case 0xe:       /* ITE8872 (2S1P) */
 945                 ret = 2;
 946                 break;
 947         case 0x6:       /* ITE8873 (1S) */
 948                 ret = 1;
 949                 break;
 950         case 0x8:       /* ITE8874 (2S) */
 951                 ret = 2;
 952                 break;
 953         default:
 954                 moan_device("Unknown ITE887x", dev);
 955                 ret = -ENODEV;
 956         }
 957 
 958         /* configure all serial ports */
 959         for (i = 0; i < ret; i++) {
 960                 /* read the I/O port from the device */
 961                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 962                                                                 &ioport);
 963                 ioport &= 0x0000FF00;   /* the actual base address */
 964                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 965                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 966                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 967 
 968                 /* write the ioport to the UARTBAR */
 969                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 970                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 971                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 972                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 973 
 974                 /* get current config */
 975                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 976                 /* disable interrupts (UARTx_Routing[3:0]) */
 977                 miscr &= ~(0xf << (12 - 4 * i));
 978                 /* activate the UART (UARTx_En) */
 979                 miscr |= 1 << (23 - i);
 980                 /* write new config with activated UART */
 981                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 982         }
 983 
 984         if (ret <= 0) {
 985                 /* the device has no UARTs if we get here */
 986                 release_region(iobase->start, ITE_887x_IOSIZE);
 987         }
 988 
 989         return ret;
 990 }
 991 
 992 static void pci_ite887x_exit(struct pci_dev *dev)
 993 {
 994         u32 ioport;
 995         /* the ioport is bit 0-15 in POSIO0R */
 996         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 997         ioport &= 0xffff;
 998         release_region(ioport, ITE_887x_IOSIZE);
 999 }
1000 
1001 /*
1002  * EndRun Technologies.
1003  * Determine the number of ports available on the device.
1004  */
1005 #define PCI_VENDOR_ID_ENDRUN                    0x7401
1006 #define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1007 
1008 static int pci_endrun_init(struct pci_dev *dev)
1009 {
1010         u8 __iomem *p;
1011         unsigned long deviceID;
1012         unsigned int  number_uarts = 0;
1013 
1014         /* EndRun device is all 0xexxx */
1015         if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1016                 (dev->device & 0xf000) != 0xe000)
1017                 return 0;
1018 
1019         p = pci_iomap(dev, 0, 5);
1020         if (p == NULL)
1021                 return -ENOMEM;
1022 
1023         deviceID = ioread32(p);
1024         /* EndRun device */
1025         if (deviceID == 0x07000200) {
1026                 number_uarts = ioread8(p + 4);
1027                 dev_dbg(&dev->dev,
1028                         "%d ports detected on EndRun PCI Express device\n",
1029                         number_uarts);
1030         }
1031         pci_iounmap(dev, p);
1032         return number_uarts;
1033 }
1034 
1035 /*
1036  * Oxford Semiconductor Inc.
1037  * Check that device is part of the Tornado range of devices, then determine
1038  * the number of ports available on the device.
1039  */
1040 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1041 {
1042         u8 __iomem *p;
1043         unsigned long deviceID;
1044         unsigned int  number_uarts = 0;
1045 
1046         /* OxSemi Tornado devices are all 0xCxxx */
1047         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1048             (dev->device & 0xF000) != 0xC000)
1049                 return 0;
1050 
1051         p = pci_iomap(dev, 0, 5);
1052         if (p == NULL)
1053                 return -ENOMEM;
1054 
1055         deviceID = ioread32(p);
1056         /* Tornado device */
1057         if (deviceID == 0x07000200) {
1058                 number_uarts = ioread8(p + 4);
1059                 dev_dbg(&dev->dev,
1060                         "%d ports detected on Oxford PCI Express device\n",
1061                         number_uarts);
1062         }
1063         pci_iounmap(dev, p);
1064         return number_uarts;
1065 }
1066 
1067 static int pci_asix_setup(struct serial_private *priv,
1068                   const struct pciserial_board *board,
1069                   struct uart_8250_port *port, int idx)
1070 {
1071         port->bugs |= UART_BUG_PARITY;
1072         return pci_default_setup(priv, board, port, idx);
1073 }
1074 
1075 /* Quatech devices have their own extra interface features */
1076 
1077 struct quatech_feature {
1078         u16 devid;
1079         bool amcc;
1080 };
1081 
1082 #define QPCR_TEST_FOR1          0x3F
1083 #define QPCR_TEST_GET1          0x00
1084 #define QPCR_TEST_FOR2          0x40
1085 #define QPCR_TEST_GET2          0x40
1086 #define QPCR_TEST_FOR3          0x80
1087 #define QPCR_TEST_GET3          0x40
1088 #define QPCR_TEST_FOR4          0xC0
1089 #define QPCR_TEST_GET4          0x80
1090 
1091 #define QOPR_CLOCK_X1           0x0000
1092 #define QOPR_CLOCK_X2           0x0001
1093 #define QOPR_CLOCK_X4           0x0002
1094 #define QOPR_CLOCK_X8           0x0003
1095 #define QOPR_CLOCK_RATE_MASK    0x0003
1096 
1097 
1098 static struct quatech_feature quatech_cards[] = {
1099         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1100         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1101         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1102         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1103         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1104         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1105         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1106         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1107         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1108         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1109         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1110         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1111         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1112         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1113         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1114         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1115         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1116         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1117         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1118         { 0, }
1119 };
1120 
1121 static int pci_quatech_amcc(u16 devid)
1122 {
1123         struct quatech_feature *qf = &quatech_cards[0];
1124         while (qf->devid) {
1125                 if (qf->devid == devid)
1126                         return qf->amcc;
1127                 qf++;
1128         }
1129         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1130         return 0;
1131 };
1132 
1133 static int pci_quatech_rqopr(struct uart_8250_port *port)
1134 {
1135         unsigned long base = port->port.iobase;
1136         u8 LCR, val;
1137 
1138         LCR = inb(base + UART_LCR);
1139         outb(0xBF, base + UART_LCR);
1140         val = inb(base + UART_SCR);
1141         outb(LCR, base + UART_LCR);
1142         return val;
1143 }
1144 
1145 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1146 {
1147         unsigned long base = port->port.iobase;
1148         u8 LCR;
1149 
1150         LCR = inb(base + UART_LCR);
1151         outb(0xBF, base + UART_LCR);
1152         inb(base + UART_SCR);
1153         outb(qopr, base + UART_SCR);
1154         outb(LCR, base + UART_LCR);
1155 }
1156 
1157 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1158 {
1159         unsigned long base = port->port.iobase;
1160         u8 LCR, val, qmcr;
1161 
1162         LCR = inb(base + UART_LCR);
1163         outb(0xBF, base + UART_LCR);
1164         val = inb(base + UART_SCR);
1165         outb(val | 0x10, base + UART_SCR);
1166         qmcr = inb(base + UART_MCR);
1167         outb(val, base + UART_SCR);
1168         outb(LCR, base + UART_LCR);
1169 
1170         return qmcr;
1171 }
1172 
1173 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1174 {
1175         unsigned long base = port->port.iobase;
1176         u8 LCR, val;
1177 
1178         LCR = inb(base + UART_LCR);
1179         outb(0xBF, base + UART_LCR);
1180         val = inb(base + UART_SCR);
1181         outb(val | 0x10, base + UART_SCR);
1182         outb(qmcr, base + UART_MCR);
1183         outb(val, base + UART_SCR);
1184         outb(LCR, base + UART_LCR);
1185 }
1186 
1187 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1188 {
1189         unsigned long base = port->port.iobase;
1190         u8 LCR, val;
1191 
1192         LCR = inb(base + UART_LCR);
1193         outb(0xBF, base + UART_LCR);
1194         val = inb(base + UART_SCR);
1195         if (val & 0x20) {
1196                 outb(0x80, UART_LCR);
1197                 if (!(inb(UART_SCR) & 0x20)) {
1198                         outb(LCR, base + UART_LCR);
1199                         return 1;
1200                 }
1201         }
1202         return 0;
1203 }
1204 
1205 static int pci_quatech_test(struct uart_8250_port *port)
1206 {
1207         u8 reg, qopr;
1208 
1209         qopr = pci_quatech_rqopr(port);
1210         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1211         reg = pci_quatech_rqopr(port) & 0xC0;
1212         if (reg != QPCR_TEST_GET1)
1213                 return -EINVAL;
1214         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1215         reg = pci_quatech_rqopr(port) & 0xC0;
1216         if (reg != QPCR_TEST_GET2)
1217                 return -EINVAL;
1218         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1219         reg = pci_quatech_rqopr(port) & 0xC0;
1220         if (reg != QPCR_TEST_GET3)
1221                 return -EINVAL;
1222         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1223         reg = pci_quatech_rqopr(port) & 0xC0;
1224         if (reg != QPCR_TEST_GET4)
1225                 return -EINVAL;
1226 
1227         pci_quatech_wqopr(port, qopr);
1228         return 0;
1229 }
1230 
1231 static int pci_quatech_clock(struct uart_8250_port *port)
1232 {
1233         u8 qopr, reg, set;
1234         unsigned long clock;
1235 
1236         if (pci_quatech_test(port) < 0)
1237                 return 1843200;
1238 
1239         qopr = pci_quatech_rqopr(port);
1240 
1241         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1242         reg = pci_quatech_rqopr(port);
1243         if (reg & QOPR_CLOCK_X8) {
1244                 clock = 1843200;
1245                 goto out;
1246         }
1247         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1248         reg = pci_quatech_rqopr(port);
1249         if (!(reg & QOPR_CLOCK_X8)) {
1250                 clock = 1843200;
1251                 goto out;
1252         }
1253         reg &= QOPR_CLOCK_X8;
1254         if (reg == QOPR_CLOCK_X2) {
1255                 clock =  3685400;
1256                 set = QOPR_CLOCK_X2;
1257         } else if (reg == QOPR_CLOCK_X4) {
1258                 clock = 7372800;
1259                 set = QOPR_CLOCK_X4;
1260         } else if (reg == QOPR_CLOCK_X8) {
1261                 clock = 14745600;
1262                 set = QOPR_CLOCK_X8;
1263         } else {
1264                 clock = 1843200;
1265                 set = QOPR_CLOCK_X1;
1266         }
1267         qopr &= ~QOPR_CLOCK_RATE_MASK;
1268         qopr |= set;
1269 
1270 out:
1271         pci_quatech_wqopr(port, qopr);
1272         return clock;
1273 }
1274 
1275 static int pci_quatech_rs422(struct uart_8250_port *port)
1276 {
1277         u8 qmcr;
1278         int rs422 = 0;
1279 
1280         if (!pci_quatech_has_qmcr(port))
1281                 return 0;
1282         qmcr = pci_quatech_rqmcr(port);
1283         pci_quatech_wqmcr(port, 0xFF);
1284         if (pci_quatech_rqmcr(port))
1285                 rs422 = 1;
1286         pci_quatech_wqmcr(port, qmcr);
1287         return rs422;
1288 }
1289 
1290 static int pci_quatech_init(struct pci_dev *dev)
1291 {
1292         if (pci_quatech_amcc(dev->device)) {
1293                 unsigned long base = pci_resource_start(dev, 0);
1294                 if (base) {
1295                         u32 tmp;
1296 
1297                         outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1298                         tmp = inl(base + 0x3c);
1299                         outl(tmp | 0x01000000, base + 0x3c);
1300                         outl(tmp &= ~0x01000000, base + 0x3c);
1301                 }
1302         }
1303         return 0;
1304 }
1305 
1306 static int pci_quatech_setup(struct serial_private *priv,
1307                   const struct pciserial_board *board,
1308                   struct uart_8250_port *port, int idx)
1309 {
1310         /* Needed by pci_quatech calls below */
1311         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1312         /* Set up the clocking */
1313         port->port.uartclk = pci_quatech_clock(port);
1314         /* For now just warn about RS422 */
1315         if (pci_quatech_rs422(port))
1316                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1317         return pci_default_setup(priv, board, port, idx);
1318 }
1319 
1320 static void pci_quatech_exit(struct pci_dev *dev)
1321 {
1322 }
1323 
1324 static int pci_default_setup(struct serial_private *priv,
1325                   const struct pciserial_board *board,
1326                   struct uart_8250_port *port, int idx)
1327 {
1328         unsigned int bar, offset = board->first_offset, maxnr;
1329 
1330         bar = FL_GET_BASE(board->flags);
1331         if (board->flags & FL_BASE_BARS)
1332                 bar += idx;
1333         else
1334                 offset += idx * board->uart_offset;
1335 
1336         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1337                 (board->reg_shift + 3);
1338 
1339         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1340                 return 1;
1341 
1342         return setup_port(priv, port, bar, offset, board->reg_shift);
1343 }
1344 static void
1345 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1346                                unsigned int quot, unsigned int quot_frac)
1347 {
1348         int scr;
1349         int lcr;
1350         int actual_baud;
1351         int tolerance;
1352 
1353         for (scr = 5 ; scr <= 15 ; scr++) {
1354                 actual_baud = 921600 * 16 / scr;
1355                 tolerance = actual_baud / 50;
1356 
1357                 if ((baud < actual_baud + tolerance) &&
1358                         (baud > actual_baud - tolerance)) {
1359 
1360                         lcr = serial_port_in(port, UART_LCR);
1361                         serial_port_out(port, UART_LCR, lcr | 0x80);
1362 
1363                         serial_port_out(port, UART_DLL, 1);
1364                         serial_port_out(port, UART_DLM, 0);
1365                         serial_port_out(port, 2, 16 - scr);
1366                         serial_port_out(port, UART_LCR, lcr);
1367                         return;
1368                 } else if (baud > actual_baud) {
1369                         break;
1370                 }
1371         }
1372         serial8250_do_set_divisor(port, baud, quot, quot_frac);
1373 }
1374 static int pci_pericom_setup(struct serial_private *priv,
1375                   const struct pciserial_board *board,
1376                   struct uart_8250_port *port, int idx)
1377 {
1378         unsigned int bar, offset = board->first_offset, maxnr;
1379 
1380         bar = FL_GET_BASE(board->flags);
1381         if (board->flags & FL_BASE_BARS)
1382                 bar += idx;
1383         else
1384                 offset += idx * board->uart_offset;
1385 
1386 
1387         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1388                 (board->reg_shift + 3);
1389 
1390         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1391                 return 1;
1392 
1393         port->port.set_divisor = pericom_do_set_divisor;
1394 
1395         return setup_port(priv, port, bar, offset, board->reg_shift);
1396 }
1397 
1398 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1399                   const struct pciserial_board *board,
1400                   struct uart_8250_port *port, int idx)
1401 {
1402         unsigned int bar, offset = board->first_offset, maxnr;
1403 
1404         bar = FL_GET_BASE(board->flags);
1405         if (board->flags & FL_BASE_BARS)
1406                 bar += idx;
1407         else
1408                 offset += idx * board->uart_offset;
1409 
1410         if (idx==3)
1411                 offset = 0x38;
1412 
1413         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1414                 (board->reg_shift + 3);
1415 
1416         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1417                 return 1;
1418 
1419         port->port.set_divisor = pericom_do_set_divisor;
1420 
1421         return setup_port(priv, port, bar, offset, board->reg_shift);
1422 }
1423 
1424 static int
1425 ce4100_serial_setup(struct serial_private *priv,
1426                   const struct pciserial_board *board,
1427                   struct uart_8250_port *port, int idx)
1428 {
1429         int ret;
1430 
1431         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1432         port->port.iotype = UPIO_MEM32;
1433         port->port.type = PORT_XSCALE;
1434         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1435         port->port.regshift = 2;
1436 
1437         return ret;
1438 }
1439 
1440 static int
1441 pci_omegapci_setup(struct serial_private *priv,
1442                       const struct pciserial_board *board,
1443                       struct uart_8250_port *port, int idx)
1444 {
1445         return setup_port(priv, port, 2, idx * 8, 0);
1446 }
1447 
1448 static int
1449 pci_brcm_trumanage_setup(struct serial_private *priv,
1450                          const struct pciserial_board *board,
1451                          struct uart_8250_port *port, int idx)
1452 {
1453         int ret = pci_default_setup(priv, board, port, idx);
1454 
1455         port->port.type = PORT_BRCM_TRUMANAGE;
1456         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1457         return ret;
1458 }
1459 
1460 /* RTS will control by MCR if this bit is 0 */
1461 #define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1462 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1463 #define FINTEK_RTS_INVERT               BIT(5)
1464 
1465 /* We should do proper H/W transceiver setting before change to RS485 mode */
1466 static int pci_fintek_rs485_config(struct uart_port *port,
1467                                struct serial_rs485 *rs485)
1468 {
1469         struct pci_dev *pci_dev = to_pci_dev(port->dev);
1470         u8 setting;
1471         u8 *index = (u8 *) port->private_data;
1472 
1473         pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1474 
1475         if (!rs485)
1476                 rs485 = &port->rs485;
1477         else if (rs485->flags & SER_RS485_ENABLED)
1478                 memset(rs485->padding, 0, sizeof(rs485->padding));
1479         else
1480                 memset(rs485, 0, sizeof(*rs485));
1481 
1482         /* F81504/508/512 not support RTS delay before or after send */
1483         rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1484 
1485         if (rs485->flags & SER_RS485_ENABLED) {
1486                 /* Enable RTS H/W control mode */
1487                 setting |= FINTEK_RTS_CONTROL_BY_HW;
1488 
1489                 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1490                         /* RTS driving high on TX */
1491                         setting &= ~FINTEK_RTS_INVERT;
1492                 } else {
1493                         /* RTS driving low on TX */
1494                         setting |= FINTEK_RTS_INVERT;
1495                 }
1496 
1497                 rs485->delay_rts_after_send = 0;
1498                 rs485->delay_rts_before_send = 0;
1499         } else {
1500                 /* Disable RTS H/W control mode */
1501                 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1502         }
1503 
1504         pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1505 
1506         if (rs485 != &port->rs485)
1507                 port->rs485 = *rs485;
1508 
1509         return 0;
1510 }
1511 
1512 static int pci_fintek_setup(struct serial_private *priv,
1513                             const struct pciserial_board *board,
1514                             struct uart_8250_port *port, int idx)
1515 {
1516         struct pci_dev *pdev = priv->dev;
1517         u8 *data;
1518         u8 config_base;
1519         u16 iobase;
1520 
1521         config_base = 0x40 + 0x08 * idx;
1522 
1523         /* Get the io address from configuration space */
1524         pci_read_config_word(pdev, config_base + 4, &iobase);
1525 
1526         dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1527 
1528         port->port.iotype = UPIO_PORT;
1529         port->port.iobase = iobase;
1530         port->port.rs485_config = pci_fintek_rs485_config;
1531 
1532         data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1533         if (!data)
1534                 return -ENOMEM;
1535 
1536         /* preserve index in PCI configuration space */
1537         *data = idx;
1538         port->port.private_data = data;
1539 
1540         return 0;
1541 }
1542 
1543 static int pci_fintek_init(struct pci_dev *dev)
1544 {
1545         unsigned long iobase;
1546         u32 max_port, i;
1547         resource_size_t bar_data[3];
1548         u8 config_base;
1549         struct serial_private *priv = pci_get_drvdata(dev);
1550         struct uart_8250_port *port;
1551 
1552         if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1553                         !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1554                         !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1555                 return -ENODEV;
1556 
1557         switch (dev->device) {
1558         case 0x1104: /* 4 ports */
1559         case 0x1108: /* 8 ports */
1560                 max_port = dev->device & 0xff;
1561                 break;
1562         case 0x1112: /* 12 ports */
1563                 max_port = 12;
1564                 break;
1565         default:
1566                 return -EINVAL;
1567         }
1568 
1569         /* Get the io address dispatch from the BIOS */
1570         bar_data[0] = pci_resource_start(dev, 5);
1571         bar_data[1] = pci_resource_start(dev, 4);
1572         bar_data[2] = pci_resource_start(dev, 3);
1573 
1574         for (i = 0; i < max_port; ++i) {
1575                 /* UART0 configuration offset start from 0x40 */
1576                 config_base = 0x40 + 0x08 * i;
1577 
1578                 /* Calculate Real IO Port */
1579                 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1580 
1581                 /* Enable UART I/O port */
1582                 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1583 
1584                 /* Select 128-byte FIFO and 8x FIFO threshold */
1585                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1586 
1587                 /* LSB UART */
1588                 pci_write_config_byte(dev, config_base + 0x04,
1589                                 (u8)(iobase & 0xff));
1590 
1591                 /* MSB UART */
1592                 pci_write_config_byte(dev, config_base + 0x05,
1593                                 (u8)((iobase & 0xff00) >> 8));
1594 
1595                 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1596 
1597                 if (priv) {
1598                         /* re-apply RS232/485 mode when
1599                          * pciserial_resume_ports()
1600                          */
1601                         port = serial8250_get_port(priv->line[i]);
1602                         pci_fintek_rs485_config(&port->port, NULL);
1603                 } else {
1604                         /* First init without port data
1605                          * force init to RS232 Mode
1606                          */
1607                         pci_write_config_byte(dev, config_base + 0x07, 0x01);
1608                 }
1609         }
1610 
1611         return max_port;
1612 }
1613 
1614 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1615 {
1616         struct f815xxa_data *data = p->private_data;
1617         unsigned long flags;
1618 
1619         spin_lock_irqsave(&data->lock, flags);
1620         writeb(value, p->membase + offset);
1621         readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1622         spin_unlock_irqrestore(&data->lock, flags);
1623 }
1624 
1625 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1626                             const struct pciserial_board *board,
1627                             struct uart_8250_port *port, int idx)
1628 {
1629         struct pci_dev *pdev = priv->dev;
1630         struct f815xxa_data *data;
1631 
1632         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1633         if (!data)
1634                 return -ENOMEM;
1635 
1636         data->idx = idx;
1637         spin_lock_init(&data->lock);
1638 
1639         port->port.private_data = data;
1640         port->port.iotype = UPIO_MEM;
1641         port->port.flags |= UPF_IOREMAP;
1642         port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1643         port->port.serial_out = f815xxa_mem_serial_out;
1644 
1645         return 0;
1646 }
1647 
1648 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1649 {
1650         u32 max_port, i;
1651         int config_base;
1652 
1653         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1654                 return -ENODEV;
1655 
1656         switch (dev->device) {
1657         case 0x1204: /* 4 ports */
1658         case 0x1208: /* 8 ports */
1659                 max_port = dev->device & 0xff;
1660                 break;
1661         case 0x1212: /* 12 ports */
1662                 max_port = 12;
1663                 break;
1664         default:
1665                 return -EINVAL;
1666         }
1667 
1668         /* Set to mmio decode */
1669         pci_write_config_byte(dev, 0x209, 0x40);
1670 
1671         for (i = 0; i < max_port; ++i) {
1672                 /* UART0 configuration offset start from 0x2A0 */
1673                 config_base = 0x2A0 + 0x08 * i;
1674 
1675                 /* Select 128-byte FIFO and 8x FIFO threshold */
1676                 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1677 
1678                 /* Enable UART I/O port */
1679                 pci_write_config_byte(dev, config_base + 0, 0x01);
1680         }
1681 
1682         return max_port;
1683 }
1684 
1685 static int skip_tx_en_setup(struct serial_private *priv,
1686                         const struct pciserial_board *board,
1687                         struct uart_8250_port *port, int idx)
1688 {
1689         port->port.quirks |= UPQ_NO_TXEN_TEST;
1690         dev_dbg(&priv->dev->dev,
1691                 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1692                 priv->dev->vendor, priv->dev->device,
1693                 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1694 
1695         return pci_default_setup(priv, board, port, idx);
1696 }
1697 
1698 static void kt_handle_break(struct uart_port *p)
1699 {
1700         struct uart_8250_port *up = up_to_u8250p(p);
1701         /*
1702          * On receipt of a BI, serial device in Intel ME (Intel
1703          * management engine) needs to have its fifos cleared for sane
1704          * SOL (Serial Over Lan) output.
1705          */
1706         serial8250_clear_and_reinit_fifos(up);
1707 }
1708 
1709 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1710 {
1711         struct uart_8250_port *up = up_to_u8250p(p);
1712         unsigned int val;
1713 
1714         /*
1715          * When the Intel ME (management engine) gets reset its serial
1716          * port registers could return 0 momentarily.  Functions like
1717          * serial8250_console_write, read and save the IER, perform
1718          * some operation and then restore it.  In order to avoid
1719          * setting IER register inadvertently to 0, if the value read
1720          * is 0, double check with ier value in uart_8250_port and use
1721          * that instead.  up->ier should be the same value as what is
1722          * currently configured.
1723          */
1724         val = inb(p->iobase + offset);
1725         if (offset == UART_IER) {
1726                 if (val == 0)
1727                         val = up->ier;
1728         }
1729         return val;
1730 }
1731 
1732 static int kt_serial_setup(struct serial_private *priv,
1733                            const struct pciserial_board *board,
1734                            struct uart_8250_port *port, int idx)
1735 {
1736         port->port.flags |= UPF_BUG_THRE;
1737         port->port.serial_in = kt_serial_in;
1738         port->port.handle_break = kt_handle_break;
1739         return skip_tx_en_setup(priv, board, port, idx);
1740 }
1741 
1742 static int pci_eg20t_init(struct pci_dev *dev)
1743 {
1744 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1745         return -ENODEV;
1746 #else
1747         return 0;
1748 #endif
1749 }
1750 
1751 static int
1752 pci_wch_ch353_setup(struct serial_private *priv,
1753                     const struct pciserial_board *board,
1754                     struct uart_8250_port *port, int idx)
1755 {
1756         port->port.flags |= UPF_FIXED_TYPE;
1757         port->port.type = PORT_16550A;
1758         return pci_default_setup(priv, board, port, idx);
1759 }
1760 
1761 static int
1762 pci_wch_ch355_setup(struct serial_private *priv,
1763                 const struct pciserial_board *board,
1764                 struct uart_8250_port *port, int idx)
1765 {
1766         port->port.flags |= UPF_FIXED_TYPE;
1767         port->port.type = PORT_16550A;
1768         return pci_default_setup(priv, board, port, idx);
1769 }
1770 
1771 static int
1772 pci_wch_ch38x_setup(struct serial_private *priv,
1773                     const struct pciserial_board *board,
1774                     struct uart_8250_port *port, int idx)
1775 {
1776         port->port.flags |= UPF_FIXED_TYPE;
1777         port->port.type = PORT_16850;
1778         return pci_default_setup(priv, board, port, idx);
1779 }
1780 
1781 static int
1782 pci_sunix_setup(struct serial_private *priv,
1783                 const struct pciserial_board *board,
1784                 struct uart_8250_port *port, int idx)
1785 {
1786         int bar;
1787         int offset;
1788 
1789         port->port.flags |= UPF_FIXED_TYPE;
1790         port->port.type = PORT_SUNIX;
1791 
1792         if (idx < 4) {
1793                 bar = 0;
1794                 offset = idx * board->uart_offset;
1795         } else {
1796                 bar = 1;
1797                 idx -= 4;
1798                 idx = div_s64_rem(idx, 4, &offset);
1799                 offset = idx * 64 + offset * board->uart_offset;
1800         }
1801 
1802         return setup_port(priv, port, bar, offset, 0);
1803 }
1804 
1805 static int
1806 pci_moxa_setup(struct serial_private *priv,
1807                 const struct pciserial_board *board,
1808                 struct uart_8250_port *port, int idx)
1809 {
1810         unsigned int bar = FL_GET_BASE(board->flags);
1811         int offset;
1812 
1813         if (board->num_ports == 4 && idx == 3)
1814                 offset = 7 * board->uart_offset;
1815         else
1816                 offset = idx * board->uart_offset;
1817 
1818         return setup_port(priv, port, bar, offset, 0);
1819 }
1820 
1821 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1822 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1823 #define PCI_DEVICE_ID_OCTPRO            0x0001
1824 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1825 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1826 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1827 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1828 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1829 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1830 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1831 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1832 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1833 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1834 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1835 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1836 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1837 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1838 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1839 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1840 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1841 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1842 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1843 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1844 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1845 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1846 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1847 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1848 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1849 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1850 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1851 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1852 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1853 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1854 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1855 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1856 #define PCI_VENDOR_ID_WCH               0x4348
1857 #define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1858 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1859 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1860 #define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1861 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1862 #define PCI_DEVICE_ID_WCH_CH355_4S      0x7173
1863 #define PCI_VENDOR_ID_AGESTAR           0x5372
1864 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1865 #define PCI_VENDOR_ID_ASIX              0x9710
1866 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1867 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1868 
1869 #define PCIE_VENDOR_ID_WCH              0x1c00
1870 #define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1871 #define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1872 #define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1873 
1874 #define PCI_VENDOR_ID_PERICOM                   0x12D8
1875 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951        0x7951
1876 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952        0x7952
1877 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954        0x7954
1878 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958        0x7958
1879 
1880 #define PCI_VENDOR_ID_ACCESIO                   0x494f
1881 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB     0x1051
1882 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S      0x1053
1883 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB     0x105C
1884 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S      0x105E
1885 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB   0x1091
1886 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2    0x1093
1887 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB   0x1099
1888 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4    0x109B
1889 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB    0x10D1
1890 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM     0x10D3
1891 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB    0x10DA
1892 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM     0x10DC
1893 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1    0x1108
1894 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2    0x1110
1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2    0x1111
1896 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4    0x1118
1897 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4    0x1119
1898 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S       0x1152
1899 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S       0x115A
1900 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2     0x1190
1901 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2    0x1191
1902 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4     0x1198
1903 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4    0x1199
1904 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM      0x11D0
1905 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4     0x105A
1906 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4     0x105B
1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8     0x106A
1908 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8     0x106B
1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4     0x1098
1910 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8     0x10A9
1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM      0x10D9
1912 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM      0x10E9
1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM      0x11D8
1914 
1915 
1916 #define PCI_DEVICE_ID_MOXA_CP102E       0x1024
1917 #define PCI_DEVICE_ID_MOXA_CP102EL      0x1025
1918 #define PCI_DEVICE_ID_MOXA_CP104EL_A    0x1045
1919 #define PCI_DEVICE_ID_MOXA_CP114EL      0x1144
1920 #define PCI_DEVICE_ID_MOXA_CP116E_A_A   0x1160
1921 #define PCI_DEVICE_ID_MOXA_CP116E_A_B   0x1161
1922 #define PCI_DEVICE_ID_MOXA_CP118EL_A    0x1182
1923 #define PCI_DEVICE_ID_MOXA_CP118E_A_I   0x1183
1924 #define PCI_DEVICE_ID_MOXA_CP132EL      0x1322
1925 #define PCI_DEVICE_ID_MOXA_CP134EL_A    0x1342
1926 #define PCI_DEVICE_ID_MOXA_CP138E_A     0x1381
1927 #define PCI_DEVICE_ID_MOXA_CP168EL_A    0x1683
1928 
1929 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1930 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1931 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1932 
1933 /*
1934  * Master list of serial port init/setup/exit quirks.
1935  * This does not describe the general nature of the port.
1936  * (ie, baud base, number and location of ports, etc)
1937  *
1938  * This list is ordered alphabetically by vendor then device.
1939  * Specific entries must come before more generic entries.
1940  */
1941 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1942         /*
1943         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1944         */
1945         {
1946                 .vendor         = PCI_VENDOR_ID_AMCC,
1947                 .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1948                 .subvendor      = PCI_ANY_ID,
1949                 .subdevice      = PCI_ANY_ID,
1950                 .setup          = addidata_apci7800_setup,
1951         },
1952         /*
1953          * AFAVLAB cards - these may be called via parport_serial
1954          *  It is not clear whether this applies to all products.
1955          */
1956         {
1957                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1958                 .device         = PCI_ANY_ID,
1959                 .subvendor      = PCI_ANY_ID,
1960                 .subdevice      = PCI_ANY_ID,
1961                 .setup          = afavlab_setup,
1962         },
1963         /*
1964          * HP Diva
1965          */
1966         {
1967                 .vendor         = PCI_VENDOR_ID_HP,
1968                 .device         = PCI_DEVICE_ID_HP_DIVA,
1969                 .subvendor      = PCI_ANY_ID,
1970                 .subdevice      = PCI_ANY_ID,
1971                 .init           = pci_hp_diva_init,
1972                 .setup          = pci_hp_diva_setup,
1973         },
1974         /*
1975          * Intel
1976          */
1977         {
1978                 .vendor         = PCI_VENDOR_ID_INTEL,
1979                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1980                 .subvendor      = 0xe4bf,
1981                 .subdevice      = PCI_ANY_ID,
1982                 .init           = pci_inteli960ni_init,
1983                 .setup          = pci_default_setup,
1984         },
1985         {
1986                 .vendor         = PCI_VENDOR_ID_INTEL,
1987                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1988                 .subvendor      = PCI_ANY_ID,
1989                 .subdevice      = PCI_ANY_ID,
1990                 .setup          = skip_tx_en_setup,
1991         },
1992         {
1993                 .vendor         = PCI_VENDOR_ID_INTEL,
1994                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1995                 .subvendor      = PCI_ANY_ID,
1996                 .subdevice      = PCI_ANY_ID,
1997                 .setup          = skip_tx_en_setup,
1998         },
1999         {
2000                 .vendor         = PCI_VENDOR_ID_INTEL,
2001                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2002                 .subvendor      = PCI_ANY_ID,
2003                 .subdevice      = PCI_ANY_ID,
2004                 .setup          = skip_tx_en_setup,
2005         },
2006         {
2007                 .vendor         = PCI_VENDOR_ID_INTEL,
2008                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2009                 .subvendor      = PCI_ANY_ID,
2010                 .subdevice      = PCI_ANY_ID,
2011                 .setup          = ce4100_serial_setup,
2012         },
2013         {
2014                 .vendor         = PCI_VENDOR_ID_INTEL,
2015                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2016                 .subvendor      = PCI_ANY_ID,
2017                 .subdevice      = PCI_ANY_ID,
2018                 .setup          = kt_serial_setup,
2019         },
2020         /*
2021          * ITE
2022          */
2023         {
2024                 .vendor         = PCI_VENDOR_ID_ITE,
2025                 .device         = PCI_DEVICE_ID_ITE_8872,
2026                 .subvendor      = PCI_ANY_ID,
2027                 .subdevice      = PCI_ANY_ID,
2028                 .init           = pci_ite887x_init,
2029                 .setup          = pci_default_setup,
2030                 .exit           = pci_ite887x_exit,
2031         },
2032         /*
2033          * National Instruments
2034          */
2035         {
2036                 .vendor         = PCI_VENDOR_ID_NI,
2037                 .device         = PCI_DEVICE_ID_NI_PCI23216,
2038                 .subvendor      = PCI_ANY_ID,
2039                 .subdevice      = PCI_ANY_ID,
2040                 .init           = pci_ni8420_init,
2041                 .setup          = pci_default_setup,
2042                 .exit           = pci_ni8420_exit,
2043         },
2044         {
2045                 .vendor         = PCI_VENDOR_ID_NI,
2046                 .device         = PCI_DEVICE_ID_NI_PCI2328,
2047                 .subvendor      = PCI_ANY_ID,
2048                 .subdevice      = PCI_ANY_ID,
2049                 .init           = pci_ni8420_init,
2050                 .setup          = pci_default_setup,
2051                 .exit           = pci_ni8420_exit,
2052         },
2053         {
2054                 .vendor         = PCI_VENDOR_ID_NI,
2055                 .device         = PCI_DEVICE_ID_NI_PCI2324,
2056                 .subvendor      = PCI_ANY_ID,
2057                 .subdevice      = PCI_ANY_ID,
2058                 .init           = pci_ni8420_init,
2059                 .setup          = pci_default_setup,
2060                 .exit           = pci_ni8420_exit,
2061         },
2062         {
2063                 .vendor         = PCI_VENDOR_ID_NI,
2064                 .device         = PCI_DEVICE_ID_NI_PCI2322,
2065                 .subvendor      = PCI_ANY_ID,
2066                 .subdevice      = PCI_ANY_ID,
2067                 .init           = pci_ni8420_init,
2068                 .setup          = pci_default_setup,
2069                 .exit           = pci_ni8420_exit,
2070         },
2071         {
2072                 .vendor         = PCI_VENDOR_ID_NI,
2073                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
2074                 .subvendor      = PCI_ANY_ID,
2075                 .subdevice      = PCI_ANY_ID,
2076                 .init           = pci_ni8420_init,
2077                 .setup          = pci_default_setup,
2078                 .exit           = pci_ni8420_exit,
2079         },
2080         {
2081                 .vendor         = PCI_VENDOR_ID_NI,
2082                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
2083                 .subvendor      = PCI_ANY_ID,
2084                 .subdevice      = PCI_ANY_ID,
2085                 .init           = pci_ni8420_init,
2086                 .setup          = pci_default_setup,
2087                 .exit           = pci_ni8420_exit,
2088         },
2089         {
2090                 .vendor         = PCI_VENDOR_ID_NI,
2091                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2092                 .subvendor      = PCI_ANY_ID,
2093                 .subdevice      = PCI_ANY_ID,
2094                 .init           = pci_ni8420_init,
2095                 .setup          = pci_default_setup,
2096                 .exit           = pci_ni8420_exit,
2097         },
2098         {
2099                 .vendor         = PCI_VENDOR_ID_NI,
2100                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2101                 .subvendor      = PCI_ANY_ID,
2102                 .subdevice      = PCI_ANY_ID,
2103                 .init           = pci_ni8420_init,
2104                 .setup          = pci_default_setup,
2105                 .exit           = pci_ni8420_exit,
2106         },
2107         {
2108                 .vendor         = PCI_VENDOR_ID_NI,
2109                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2110                 .subvendor      = PCI_ANY_ID,
2111                 .subdevice      = PCI_ANY_ID,
2112                 .init           = pci_ni8420_init,
2113                 .setup          = pci_default_setup,
2114                 .exit           = pci_ni8420_exit,
2115         },
2116         {
2117                 .vendor         = PCI_VENDOR_ID_NI,
2118                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2119                 .subvendor      = PCI_ANY_ID,
2120                 .subdevice      = PCI_ANY_ID,
2121                 .init           = pci_ni8420_init,
2122                 .setup          = pci_default_setup,
2123                 .exit           = pci_ni8420_exit,
2124         },
2125         {
2126                 .vendor         = PCI_VENDOR_ID_NI,
2127                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2128                 .subvendor      = PCI_ANY_ID,
2129                 .subdevice      = PCI_ANY_ID,
2130                 .init           = pci_ni8420_init,
2131                 .setup          = pci_default_setup,
2132                 .exit           = pci_ni8420_exit,
2133         },
2134         {
2135                 .vendor         = PCI_VENDOR_ID_NI,
2136                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2137                 .subvendor      = PCI_ANY_ID,
2138                 .subdevice      = PCI_ANY_ID,
2139                 .init           = pci_ni8420_init,
2140                 .setup          = pci_default_setup,
2141                 .exit           = pci_ni8420_exit,
2142         },
2143         {
2144                 .vendor         = PCI_VENDOR_ID_NI,
2145                 .device         = PCI_ANY_ID,
2146                 .subvendor      = PCI_ANY_ID,
2147                 .subdevice      = PCI_ANY_ID,
2148                 .init           = pci_ni8430_init,
2149                 .setup          = pci_ni8430_setup,
2150                 .exit           = pci_ni8430_exit,
2151         },
2152         /* Quatech */
2153         {
2154                 .vendor         = PCI_VENDOR_ID_QUATECH,
2155                 .device         = PCI_ANY_ID,
2156                 .subvendor      = PCI_ANY_ID,
2157                 .subdevice      = PCI_ANY_ID,
2158                 .init           = pci_quatech_init,
2159                 .setup          = pci_quatech_setup,
2160                 .exit           = pci_quatech_exit,
2161         },
2162         /*
2163          * Panacom
2164          */
2165         {
2166                 .vendor         = PCI_VENDOR_ID_PANACOM,
2167                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2168                 .subvendor      = PCI_ANY_ID,
2169                 .subdevice      = PCI_ANY_ID,
2170                 .init           = pci_plx9050_init,
2171                 .setup          = pci_default_setup,
2172                 .exit           = pci_plx9050_exit,
2173         },
2174         {
2175                 .vendor         = PCI_VENDOR_ID_PANACOM,
2176                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2177                 .subvendor      = PCI_ANY_ID,
2178                 .subdevice      = PCI_ANY_ID,
2179                 .init           = pci_plx9050_init,
2180                 .setup          = pci_default_setup,
2181                 .exit           = pci_plx9050_exit,
2182         },
2183         /*
2184          * Pericom (Only 7954 - It have a offset jump for port 4)
2185          */
2186         {
2187                 .vendor         = PCI_VENDOR_ID_PERICOM,
2188                 .device         = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2189                 .subvendor      = PCI_ANY_ID,
2190                 .subdevice      = PCI_ANY_ID,
2191                 .setup          = pci_pericom_setup_four_at_eight,
2192         },
2193         /*
2194          * PLX
2195          */
2196         {
2197                 .vendor         = PCI_VENDOR_ID_PLX,
2198                 .device         = PCI_DEVICE_ID_PLX_9050,
2199                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2200                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2201                 .init           = pci_plx9050_init,
2202                 .setup          = pci_default_setup,
2203                 .exit           = pci_plx9050_exit,
2204         },
2205         {
2206                 .vendor         = PCI_VENDOR_ID_PLX,
2207                 .device         = PCI_DEVICE_ID_PLX_9050,
2208                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2209                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2210                 .init           = pci_plx9050_init,
2211                 .setup          = pci_default_setup,
2212                 .exit           = pci_plx9050_exit,
2213         },
2214         {
2215                 .vendor         = PCI_VENDOR_ID_PLX,
2216                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2217                 .subvendor      = PCI_VENDOR_ID_PLX,
2218                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2219                 .init           = pci_plx9050_init,
2220                 .setup          = pci_default_setup,
2221                 .exit           = pci_plx9050_exit,
2222         },
2223         {
2224                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2225                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2226                 .subvendor  = PCI_ANY_ID,
2227                 .subdevice  = PCI_ANY_ID,
2228                 .setup      = pci_pericom_setup_four_at_eight,
2229         },
2230         {
2231                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2232                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2233                 .subvendor  = PCI_ANY_ID,
2234                 .subdevice  = PCI_ANY_ID,
2235                 .setup      = pci_pericom_setup_four_at_eight,
2236         },
2237         {
2238                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2239                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2240                 .subvendor  = PCI_ANY_ID,
2241                 .subdevice  = PCI_ANY_ID,
2242                 .setup      = pci_pericom_setup_four_at_eight,
2243         },
2244         {
2245                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2246                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2247                 .subvendor  = PCI_ANY_ID,
2248                 .subdevice  = PCI_ANY_ID,
2249                 .setup      = pci_pericom_setup_four_at_eight,
2250         },
2251         {
2252                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2253                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2254                 .subvendor  = PCI_ANY_ID,
2255                 .subdevice  = PCI_ANY_ID,
2256                 .setup      = pci_pericom_setup_four_at_eight,
2257         },
2258         {
2259                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2260                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2261                 .subvendor  = PCI_ANY_ID,
2262                 .subdevice  = PCI_ANY_ID,
2263                 .setup      = pci_pericom_setup_four_at_eight,
2264         },
2265         {
2266                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2267                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2268                 .subvendor  = PCI_ANY_ID,
2269                 .subdevice  = PCI_ANY_ID,
2270                 .setup      = pci_pericom_setup_four_at_eight,
2271         },
2272         {
2273                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2274                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2275                 .subvendor  = PCI_ANY_ID,
2276                 .subdevice  = PCI_ANY_ID,
2277                 .setup      = pci_pericom_setup_four_at_eight,
2278         },
2279         {
2280                 .vendor     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2281                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2282                 .subvendor  = PCI_ANY_ID,
2283                 .subdevice  = PCI_ANY_ID,
2284                 .setup      = pci_pericom_setup_four_at_eight,
2285         },
2286         {
2287                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2288                 .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2289                 .subvendor  = PCI_ANY_ID,
2290                 .subdevice  = PCI_ANY_ID,
2291                 .setup      = pci_pericom_setup_four_at_eight,
2292         },
2293         {
2294                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2295                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2296                 .subvendor  = PCI_ANY_ID,
2297                 .subdevice  = PCI_ANY_ID,
2298                 .setup      = pci_pericom_setup_four_at_eight,
2299         },
2300         {
2301                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2302                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2303                 .subvendor  = PCI_ANY_ID,
2304                 .subdevice  = PCI_ANY_ID,
2305                 .setup      = pci_pericom_setup_four_at_eight,
2306         },
2307         {
2308                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2309                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2310                 .subvendor  = PCI_ANY_ID,
2311                 .subdevice  = PCI_ANY_ID,
2312                 .setup      = pci_pericom_setup_four_at_eight,
2313         },
2314         {
2315                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2316                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2317                 .subvendor  = PCI_ANY_ID,
2318                 .subdevice  = PCI_ANY_ID,
2319                 .setup      = pci_pericom_setup_four_at_eight,
2320         },
2321         {
2322                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2323                 .device     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2324                 .subvendor  = PCI_ANY_ID,
2325                 .subdevice  = PCI_ANY_ID,
2326                 .setup      = pci_pericom_setup_four_at_eight,
2327         },
2328         {
2329                 .vendor     = PCI_VENDOR_ID_ACCESIO,
2330                 .device     = PCI_ANY_ID,
2331                 .subvendor  = PCI_ANY_ID,
2332                 .subdevice  = PCI_ANY_ID,
2333                 .setup      = pci_pericom_setup,
2334         },      /*
2335          * SBS Technologies, Inc., PMC-OCTALPRO 232
2336          */
2337         {
2338                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2339                 .device         = PCI_DEVICE_ID_OCTPRO,
2340                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2341                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2342                 .init           = sbs_init,
2343                 .setup          = sbs_setup,
2344                 .exit           = sbs_exit,
2345         },
2346         /*
2347          * SBS Technologies, Inc., PMC-OCTALPRO 422
2348          */
2349         {
2350                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2351                 .device         = PCI_DEVICE_ID_OCTPRO,
2352                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2353                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2354                 .init           = sbs_init,
2355                 .setup          = sbs_setup,
2356                 .exit           = sbs_exit,
2357         },
2358         /*
2359          * SBS Technologies, Inc., P-Octal 232
2360          */
2361         {
2362                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2363                 .device         = PCI_DEVICE_ID_OCTPRO,
2364                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2365                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2366                 .init           = sbs_init,
2367                 .setup          = sbs_setup,
2368                 .exit           = sbs_exit,
2369         },
2370         /*
2371          * SBS Technologies, Inc., P-Octal 422
2372          */
2373         {
2374                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2375                 .device         = PCI_DEVICE_ID_OCTPRO,
2376                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2377                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2378                 .init           = sbs_init,
2379                 .setup          = sbs_setup,
2380                 .exit           = sbs_exit,
2381         },
2382         /*
2383          * SIIG cards - these may be called via parport_serial
2384          */
2385         {
2386                 .vendor         = PCI_VENDOR_ID_SIIG,
2387                 .device         = PCI_ANY_ID,
2388                 .subvendor      = PCI_ANY_ID,
2389                 .subdevice      = PCI_ANY_ID,
2390                 .init           = pci_siig_init,
2391                 .setup          = pci_siig_setup,
2392         },
2393         /*
2394          * Titan cards
2395          */
2396         {
2397                 .vendor         = PCI_VENDOR_ID_TITAN,
2398                 .device         = PCI_DEVICE_ID_TITAN_400L,
2399                 .subvendor      = PCI_ANY_ID,
2400                 .subdevice      = PCI_ANY_ID,
2401                 .setup          = titan_400l_800l_setup,
2402         },
2403         {
2404                 .vendor         = PCI_VENDOR_ID_TITAN,
2405                 .device         = PCI_DEVICE_ID_TITAN_800L,
2406                 .subvendor      = PCI_ANY_ID,
2407                 .subdevice      = PCI_ANY_ID,
2408                 .setup          = titan_400l_800l_setup,
2409         },
2410         /*
2411          * Timedia cards
2412          */
2413         {
2414                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2415                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2416                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2417                 .subdevice      = PCI_ANY_ID,
2418                 .probe          = pci_timedia_probe,
2419                 .init           = pci_timedia_init,
2420                 .setup          = pci_timedia_setup,
2421         },
2422         {
2423                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
2424                 .device         = PCI_ANY_ID,
2425                 .subvendor      = PCI_ANY_ID,
2426                 .subdevice      = PCI_ANY_ID,
2427                 .setup          = pci_timedia_setup,
2428         },
2429         /*
2430          * Sunix PCI serial boards
2431          */
2432         {
2433                 .vendor         = PCI_VENDOR_ID_SUNIX,
2434                 .device         = PCI_DEVICE_ID_SUNIX_1999,
2435                 .subvendor      = PCI_VENDOR_ID_SUNIX,
2436                 .subdevice      = PCI_ANY_ID,
2437                 .setup          = pci_sunix_setup,
2438         },
2439         /*
2440          * Xircom cards
2441          */
2442         {
2443                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2444                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2445                 .subvendor      = PCI_ANY_ID,
2446                 .subdevice      = PCI_ANY_ID,
2447                 .init           = pci_xircom_init,
2448                 .setup          = pci_default_setup,
2449         },
2450         /*
2451          * Netmos cards - these may be called via parport_serial
2452          */
2453         {
2454                 .vendor         = PCI_VENDOR_ID_NETMOS,
2455                 .device         = PCI_ANY_ID,
2456                 .subvendor      = PCI_ANY_ID,
2457                 .subdevice      = PCI_ANY_ID,
2458                 .init           = pci_netmos_init,
2459                 .setup          = pci_netmos_9900_setup,
2460         },
2461         /*
2462          * EndRun Technologies
2463         */
2464         {
2465                 .vendor         = PCI_VENDOR_ID_ENDRUN,
2466                 .device         = PCI_ANY_ID,
2467                 .subvendor      = PCI_ANY_ID,
2468                 .subdevice      = PCI_ANY_ID,
2469                 .init           = pci_endrun_init,
2470                 .setup          = pci_default_setup,
2471         },
2472         /*
2473          * For Oxford Semiconductor Tornado based devices
2474          */
2475         {
2476                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2477                 .device         = PCI_ANY_ID,
2478                 .subvendor      = PCI_ANY_ID,
2479                 .subdevice      = PCI_ANY_ID,
2480                 .init           = pci_oxsemi_tornado_init,
2481                 .setup          = pci_default_setup,
2482         },
2483         {
2484                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2485                 .device         = PCI_ANY_ID,
2486                 .subvendor      = PCI_ANY_ID,
2487                 .subdevice      = PCI_ANY_ID,
2488                 .init           = pci_oxsemi_tornado_init,
2489                 .setup          = pci_default_setup,
2490         },
2491         {
2492                 .vendor         = PCI_VENDOR_ID_DIGI,
2493                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2494                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2495                 .subdevice              = PCI_ANY_ID,
2496                 .init                   = pci_oxsemi_tornado_init,
2497                 .setup          = pci_default_setup,
2498         },
2499         {
2500                 .vendor         = PCI_VENDOR_ID_INTEL,
2501                 .device         = 0x8811,
2502                 .subvendor      = PCI_ANY_ID,
2503                 .subdevice      = PCI_ANY_ID,
2504                 .init           = pci_eg20t_init,
2505                 .setup          = pci_default_setup,
2506         },
2507         {
2508                 .vendor         = PCI_VENDOR_ID_INTEL,
2509                 .device         = 0x8812,
2510                 .subvendor      = PCI_ANY_ID,
2511                 .subdevice      = PCI_ANY_ID,
2512                 .init           = pci_eg20t_init,
2513                 .setup          = pci_default_setup,
2514         },
2515         {
2516                 .vendor         = PCI_VENDOR_ID_INTEL,
2517                 .device         = 0x8813,
2518                 .subvendor      = PCI_ANY_ID,
2519                 .subdevice      = PCI_ANY_ID,
2520                 .init           = pci_eg20t_init,
2521                 .setup          = pci_default_setup,
2522         },
2523         {
2524                 .vendor         = PCI_VENDOR_ID_INTEL,
2525                 .device         = 0x8814,
2526                 .subvendor      = PCI_ANY_ID,
2527                 .subdevice      = PCI_ANY_ID,
2528                 .init           = pci_eg20t_init,
2529                 .setup          = pci_default_setup,
2530         },
2531         {
2532                 .vendor         = 0x10DB,
2533                 .device         = 0x8027,
2534                 .subvendor      = PCI_ANY_ID,
2535                 .subdevice      = PCI_ANY_ID,
2536                 .init           = pci_eg20t_init,
2537                 .setup          = pci_default_setup,
2538         },
2539         {
2540                 .vendor         = 0x10DB,
2541                 .device         = 0x8028,
2542                 .subvendor      = PCI_ANY_ID,
2543                 .subdevice      = PCI_ANY_ID,
2544                 .init           = pci_eg20t_init,
2545                 .setup          = pci_default_setup,
2546         },
2547         {
2548                 .vendor         = 0x10DB,
2549                 .device         = 0x8029,
2550                 .subvendor      = PCI_ANY_ID,
2551                 .subdevice      = PCI_ANY_ID,
2552                 .init           = pci_eg20t_init,
2553                 .setup          = pci_default_setup,
2554         },
2555         {
2556                 .vendor         = 0x10DB,
2557                 .device         = 0x800C,
2558                 .subvendor      = PCI_ANY_ID,
2559                 .subdevice      = PCI_ANY_ID,
2560                 .init           = pci_eg20t_init,
2561                 .setup          = pci_default_setup,
2562         },
2563         {
2564                 .vendor         = 0x10DB,
2565                 .device         = 0x800D,
2566                 .subvendor      = PCI_ANY_ID,
2567                 .subdevice      = PCI_ANY_ID,
2568                 .init           = pci_eg20t_init,
2569                 .setup          = pci_default_setup,
2570         },
2571         /*
2572          * Cronyx Omega PCI (PLX-chip based)
2573          */
2574         {
2575                 .vendor         = PCI_VENDOR_ID_PLX,
2576                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2577                 .subvendor      = PCI_ANY_ID,
2578                 .subdevice      = PCI_ANY_ID,
2579                 .setup          = pci_omegapci_setup,
2580         },
2581         /* WCH CH353 1S1P card (16550 clone) */
2582         {
2583                 .vendor         = PCI_VENDOR_ID_WCH,
2584                 .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2585                 .subvendor      = PCI_ANY_ID,
2586                 .subdevice      = PCI_ANY_ID,
2587                 .setup          = pci_wch_ch353_setup,
2588         },
2589         /* WCH CH353 2S1P card (16550 clone) */
2590         {
2591                 .vendor         = PCI_VENDOR_ID_WCH,
2592                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2593                 .subvendor      = PCI_ANY_ID,
2594                 .subdevice      = PCI_ANY_ID,
2595                 .setup          = pci_wch_ch353_setup,
2596         },
2597         /* WCH CH353 4S card (16550 clone) */
2598         {
2599                 .vendor         = PCI_VENDOR_ID_WCH,
2600                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2601                 .subvendor      = PCI_ANY_ID,
2602                 .subdevice      = PCI_ANY_ID,
2603                 .setup          = pci_wch_ch353_setup,
2604         },
2605         /* WCH CH353 2S1PF card (16550 clone) */
2606         {
2607                 .vendor         = PCI_VENDOR_ID_WCH,
2608                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2609                 .subvendor      = PCI_ANY_ID,
2610                 .subdevice      = PCI_ANY_ID,
2611                 .setup          = pci_wch_ch353_setup,
2612         },
2613         /* WCH CH352 2S card (16550 clone) */
2614         {
2615                 .vendor         = PCI_VENDOR_ID_WCH,
2616                 .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2617                 .subvendor      = PCI_ANY_ID,
2618                 .subdevice      = PCI_ANY_ID,
2619                 .setup          = pci_wch_ch353_setup,
2620         },
2621         /* WCH CH355 4S card (16550 clone) */
2622         {
2623                 .vendor         = PCI_VENDOR_ID_WCH,
2624                 .device         = PCI_DEVICE_ID_WCH_CH355_4S,
2625                 .subvendor      = PCI_ANY_ID,
2626                 .subdevice      = PCI_ANY_ID,
2627                 .setup          = pci_wch_ch355_setup,
2628         },
2629         /* WCH CH382 2S card (16850 clone) */
2630         {
2631                 .vendor         = PCIE_VENDOR_ID_WCH,
2632                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2633                 .subvendor      = PCI_ANY_ID,
2634                 .subdevice      = PCI_ANY_ID,
2635                 .setup          = pci_wch_ch38x_setup,
2636         },
2637         /* WCH CH382 2S1P card (16850 clone) */
2638         {
2639                 .vendor         = PCIE_VENDOR_ID_WCH,
2640                 .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2641                 .subvendor      = PCI_ANY_ID,
2642                 .subdevice      = PCI_ANY_ID,
2643                 .setup          = pci_wch_ch38x_setup,
2644         },
2645         /* WCH CH384 4S card (16850 clone) */
2646         {
2647                 .vendor         = PCIE_VENDOR_ID_WCH,
2648                 .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2649                 .subvendor      = PCI_ANY_ID,
2650                 .subdevice      = PCI_ANY_ID,
2651                 .setup          = pci_wch_ch38x_setup,
2652         },
2653         /*
2654          * ASIX devices with FIFO bug
2655          */
2656         {
2657                 .vendor         = PCI_VENDOR_ID_ASIX,
2658                 .device         = PCI_ANY_ID,
2659                 .subvendor      = PCI_ANY_ID,
2660                 .subdevice      = PCI_ANY_ID,
2661                 .setup          = pci_asix_setup,
2662         },
2663         /*
2664          * Broadcom TruManage (NetXtreme)
2665          */
2666         {
2667                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2668                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2669                 .subvendor      = PCI_ANY_ID,
2670                 .subdevice      = PCI_ANY_ID,
2671                 .setup          = pci_brcm_trumanage_setup,
2672         },
2673         {
2674                 .vendor         = 0x1c29,
2675                 .device         = 0x1104,
2676                 .subvendor      = PCI_ANY_ID,
2677                 .subdevice      = PCI_ANY_ID,
2678                 .setup          = pci_fintek_setup,
2679                 .init           = pci_fintek_init,
2680         },
2681         {
2682                 .vendor         = 0x1c29,
2683                 .device         = 0x1108,
2684                 .subvendor      = PCI_ANY_ID,
2685                 .subdevice      = PCI_ANY_ID,
2686                 .setup          = pci_fintek_setup,
2687                 .init           = pci_fintek_init,
2688         },
2689         {
2690                 .vendor         = 0x1c29,
2691                 .device         = 0x1112,
2692                 .subvendor      = PCI_ANY_ID,
2693                 .subdevice      = PCI_ANY_ID,
2694                 .setup          = pci_fintek_setup,
2695                 .init           = pci_fintek_init,
2696         },
2697         /*
2698          * MOXA
2699          */
2700         {
2701                 .vendor         = PCI_VENDOR_ID_MOXA,
2702                 .device         = PCI_ANY_ID,
2703                 .subvendor      = PCI_ANY_ID,
2704                 .subdevice      = PCI_ANY_ID,
2705                 .setup          = pci_moxa_setup,
2706         },
2707         {
2708                 .vendor         = 0x1c29,
2709                 .device         = 0x1204,
2710                 .subvendor      = PCI_ANY_ID,
2711                 .subdevice      = PCI_ANY_ID,
2712                 .setup          = pci_fintek_f815xxa_setup,
2713                 .init           = pci_fintek_f815xxa_init,
2714         },
2715         {
2716                 .vendor         = 0x1c29,
2717                 .device         = 0x1208,
2718                 .subvendor      = PCI_ANY_ID,
2719                 .subdevice      = PCI_ANY_ID,
2720                 .setup          = pci_fintek_f815xxa_setup,
2721                 .init           = pci_fintek_f815xxa_init,
2722         },
2723         {
2724                 .vendor         = 0x1c29,
2725                 .device         = 0x1212,
2726                 .subvendor      = PCI_ANY_ID,
2727                 .subdevice      = PCI_ANY_ID,
2728                 .setup          = pci_fintek_f815xxa_setup,
2729                 .init           = pci_fintek_f815xxa_init,
2730         },
2731 
2732         /*
2733          * Default "match everything" terminator entry
2734          */
2735         {
2736                 .vendor         = PCI_ANY_ID,
2737                 .device         = PCI_ANY_ID,
2738                 .subvendor      = PCI_ANY_ID,
2739                 .subdevice      = PCI_ANY_ID,
2740                 .setup          = pci_default_setup,
2741         }
2742 };
2743 
2744 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2745 {
2746         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2747 }
2748 
2749 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2750 {
2751         struct pci_serial_quirk *quirk;
2752 
2753         for (quirk = pci_serial_quirks; ; quirk++)
2754                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2755                     quirk_id_matches(quirk->device, dev->device) &&
2756                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2757                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2758                         break;
2759         return quirk;
2760 }
2761 
2762 static inline int get_pci_irq(struct pci_dev *dev,
2763                                 const struct pciserial_board *board)
2764 {
2765         if (board->flags & FL_NOIRQ)
2766                 return 0;
2767         else
2768                 return dev->irq;
2769 }
2770 
2771 /*
2772  * This is the configuration table for all of the PCI serial boards
2773  * which we support.  It is directly indexed by the pci_board_num_t enum
2774  * value, which is encoded in the pci_device_id PCI probe table's
2775  * driver_data member.
2776  *
2777  * The makeup of these names are:
2778  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2779  *
2780  *  bn          = PCI BAR number
2781  *  bt          = Index using PCI BARs
2782  *  n           = number of serial ports
2783  *  baud        = baud rate
2784  *  offsetinhex = offset for each sequential port (in hex)
2785  *
2786  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2787  *
2788  * Please note: in theory if n = 1, _bt infix should make no difference.
2789  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2790  */
2791 enum pci_board_num_t {
2792         pbn_default = 0,
2793 
2794         pbn_b0_1_115200,
2795         pbn_b0_2_115200,
2796         pbn_b0_4_115200,
2797         pbn_b0_5_115200,
2798         pbn_b0_8_115200,
2799 
2800         pbn_b0_1_921600,
2801         pbn_b0_2_921600,
2802         pbn_b0_4_921600,
2803 
2804         pbn_b0_2_1130000,
2805 
2806         pbn_b0_4_1152000,
2807 
2808         pbn_b0_4_1250000,
2809 
2810         pbn_b0_2_1843200,
2811         pbn_b0_4_1843200,
2812 
2813         pbn_b0_1_4000000,
2814 
2815         pbn_b0_bt_1_115200,
2816         pbn_b0_bt_2_115200,
2817         pbn_b0_bt_4_115200,
2818         pbn_b0_bt_8_115200,
2819 
2820         pbn_b0_bt_1_460800,
2821         pbn_b0_bt_2_460800,
2822         pbn_b0_bt_4_460800,
2823 
2824         pbn_b0_bt_1_921600,
2825         pbn_b0_bt_2_921600,
2826         pbn_b0_bt_4_921600,
2827         pbn_b0_bt_8_921600,
2828 
2829         pbn_b1_1_115200,
2830         pbn_b1_2_115200,
2831         pbn_b1_4_115200,
2832         pbn_b1_8_115200,
2833         pbn_b1_16_115200,
2834 
2835         pbn_b1_1_921600,
2836         pbn_b1_2_921600,
2837         pbn_b1_4_921600,
2838         pbn_b1_8_921600,
2839 
2840         pbn_b1_2_1250000,
2841 
2842         pbn_b1_bt_1_115200,
2843         pbn_b1_bt_2_115200,
2844         pbn_b1_bt_4_115200,
2845 
2846         pbn_b1_bt_2_921600,
2847 
2848         pbn_b1_1_1382400,
2849         pbn_b1_2_1382400,
2850         pbn_b1_4_1382400,
2851         pbn_b1_8_1382400,
2852 
2853         pbn_b2_1_115200,
2854         pbn_b2_2_115200,
2855         pbn_b2_4_115200,
2856         pbn_b2_8_115200,
2857 
2858         pbn_b2_1_460800,
2859         pbn_b2_4_460800,
2860         pbn_b2_8_460800,
2861         pbn_b2_16_460800,
2862 
2863         pbn_b2_1_921600,
2864         pbn_b2_4_921600,
2865         pbn_b2_8_921600,
2866 
2867         pbn_b2_8_1152000,
2868 
2869         pbn_b2_bt_1_115200,
2870         pbn_b2_bt_2_115200,
2871         pbn_b2_bt_4_115200,
2872 
2873         pbn_b2_bt_2_921600,
2874         pbn_b2_bt_4_921600,
2875 
2876         pbn_b3_2_115200,
2877         pbn_b3_4_115200,
2878         pbn_b3_8_115200,
2879 
2880         pbn_b4_bt_2_921600,
2881         pbn_b4_bt_4_921600,
2882         pbn_b4_bt_8_921600,
2883 
2884         /*
2885          * Board-specific versions.
2886          */
2887         pbn_panacom,
2888         pbn_panacom2,
2889         pbn_panacom4,
2890         pbn_plx_romulus,
2891         pbn_endrun_2_4000000,
2892         pbn_oxsemi,
2893         pbn_oxsemi_1_4000000,
2894         pbn_oxsemi_2_4000000,
2895         pbn_oxsemi_4_4000000,
2896         pbn_oxsemi_8_4000000,
2897         pbn_intel_i960,
2898         pbn_sgi_ioc3,
2899         pbn_computone_4,
2900         pbn_computone_6,
2901         pbn_computone_8,
2902         pbn_sbsxrsio,
2903         pbn_pasemi_1682M,
2904         pbn_ni8430_2,
2905         pbn_ni8430_4,
2906         pbn_ni8430_8,
2907         pbn_ni8430_16,
2908         pbn_ADDIDATA_PCIe_1_3906250,
2909         pbn_ADDIDATA_PCIe_2_3906250,
2910         pbn_ADDIDATA_PCIe_4_3906250,
2911         pbn_ADDIDATA_PCIe_8_3906250,
2912         pbn_ce4100_1_115200,
2913         pbn_omegapci,
2914         pbn_NETMOS9900_2s_115200,
2915         pbn_brcm_trumanage,
2916         pbn_fintek_4,
2917         pbn_fintek_8,
2918         pbn_fintek_12,
2919         pbn_fintek_F81504A,
2920         pbn_fintek_F81508A,
2921         pbn_fintek_F81512A,
2922         pbn_wch382_2,
2923         pbn_wch384_4,
2924         pbn_pericom_PI7C9X7951,
2925         pbn_pericom_PI7C9X7952,
2926         pbn_pericom_PI7C9X7954,
2927         pbn_pericom_PI7C9X7958,
2928         pbn_sunix_pci_1s,
2929         pbn_sunix_pci_2s,
2930         pbn_sunix_pci_4s,
2931         pbn_sunix_pci_8s,
2932         pbn_sunix_pci_16s,
2933         pbn_moxa8250_2p,
2934         pbn_moxa8250_4p,
2935         pbn_moxa8250_8p,
2936 };
2937 
2938 /*
2939  * uart_offset - the space between channels
2940  * reg_shift   - describes how the UART registers are mapped
2941  *               to PCI memory by the card.
2942  * For example IER register on SBS, Inc. PMC-OctPro is located at
2943  * offset 0x10 from the UART base, while UART_IER is defined as 1
2944  * in include/linux/serial_reg.h,
2945  * see first lines of serial_in() and serial_out() in 8250.c
2946 */
2947 
2948 static struct pciserial_board pci_boards[] = {
2949         [pbn_default] = {
2950                 .flags          = FL_BASE0,
2951                 .num_ports      = 1,
2952                 .base_baud      = 115200,
2953                 .uart_offset    = 8,
2954         },
2955         [pbn_b0_1_115200] = {
2956                 .flags          = FL_BASE0,
2957                 .num_ports      = 1,
2958                 .base_baud      = 115200,
2959                 .uart_offset    = 8,
2960         },
2961         [pbn_b0_2_115200] = {
2962                 .flags          = FL_BASE0,
2963                 .num_ports      = 2,
2964                 .base_baud      = 115200,
2965                 .uart_offset    = 8,
2966         },
2967         [pbn_b0_4_115200] = {
2968                 .flags          = FL_BASE0,
2969                 .num_ports      = 4,
2970                 .base_baud      = 115200,
2971                 .uart_offset    = 8,
2972         },
2973         [pbn_b0_5_115200] = {
2974                 .flags          = FL_BASE0,
2975                 .num_ports      = 5,
2976                 .base_baud      = 115200,
2977                 .uart_offset    = 8,
2978         },
2979         [pbn_b0_8_115200] = {
2980                 .flags          = FL_BASE0,
2981                 .num_ports      = 8,
2982                 .base_baud      = 115200,
2983                 .uart_offset    = 8,
2984         },
2985         [pbn_b0_1_921600] = {
2986                 .flags          = FL_BASE0,
2987                 .num_ports      = 1,
2988                 .base_baud      = 921600,
2989                 .uart_offset    = 8,
2990         },
2991         [pbn_b0_2_921600] = {
2992                 .flags          = FL_BASE0,
2993                 .num_ports      = 2,
2994                 .base_baud      = 921600,
2995                 .uart_offset    = 8,
2996         },
2997         [pbn_b0_4_921600] = {
2998                 .flags          = FL_BASE0,
2999                 .num_ports      = 4,
3000                 .base_baud      = 921600,
3001                 .uart_offset    = 8,
3002         },
3003 
3004         [pbn_b0_2_1130000] = {
3005                 .flags          = FL_BASE0,
3006                 .num_ports      = 2,
3007                 .base_baud      = 1130000,
3008                 .uart_offset    = 8,
3009         },
3010 
3011         [pbn_b0_4_1152000] = {
3012                 .flags          = FL_BASE0,
3013                 .num_ports      = 4,
3014                 .base_baud      = 1152000,
3015                 .uart_offset    = 8,
3016         },
3017 
3018         [pbn_b0_4_1250000] = {
3019                 .flags          = FL_BASE0,
3020                 .num_ports      = 4,
3021                 .base_baud      = 1250000,
3022                 .uart_offset    = 8,
3023         },
3024 
3025         [pbn_b0_2_1843200] = {
3026                 .flags          = FL_BASE0,
3027                 .num_ports      = 2,
3028                 .base_baud      = 1843200,
3029                 .uart_offset    = 8,
3030         },
3031         [pbn_b0_4_1843200] = {
3032                 .flags          = FL_BASE0,
3033                 .num_ports      = 4,
3034                 .base_baud      = 1843200,
3035                 .uart_offset    = 8,
3036         },
3037 
3038         [pbn_b0_1_4000000] = {
3039                 .flags          = FL_BASE0,
3040                 .num_ports      = 1,
3041                 .base_baud      = 4000000,
3042                 .uart_offset    = 8,
3043         },
3044 
3045         [pbn_b0_bt_1_115200] = {
3046                 .flags          = FL_BASE0|FL_BASE_BARS,
3047                 .num_ports      = 1,
3048                 .base_baud      = 115200,
3049                 .uart_offset    = 8,
3050         },
3051         [pbn_b0_bt_2_115200] = {
3052                 .flags          = FL_BASE0|FL_BASE_BARS,
3053                 .num_ports      = 2,
3054                 .base_baud      = 115200,
3055                 .uart_offset    = 8,
3056         },
3057         [pbn_b0_bt_4_115200] = {
3058                 .flags          = FL_BASE0|FL_BASE_BARS,
3059                 .num_ports      = 4,
3060                 .base_baud      = 115200,
3061                 .uart_offset    = 8,
3062         },
3063         [pbn_b0_bt_8_115200] = {
3064                 .flags          = FL_BASE0|FL_BASE_BARS,
3065                 .num_ports      = 8,
3066                 .base_baud      = 115200,
3067                 .uart_offset    = 8,
3068         },
3069 
3070         [pbn_b0_bt_1_460800] = {
3071                 .flags          = FL_BASE0|FL_BASE_BARS,
3072                 .num_ports      = 1,
3073                 .base_baud      = 460800,
3074                 .uart_offset    = 8,
3075         },
3076         [pbn_b0_bt_2_460800] = {
3077                 .flags          = FL_BASE0|FL_BASE_BARS,
3078                 .num_ports      = 2,
3079                 .base_baud      = 460800,
3080                 .uart_offset    = 8,
3081         },
3082         [pbn_b0_bt_4_460800] = {
3083                 .flags          = FL_BASE0|FL_BASE_BARS,
3084                 .num_ports      = 4,
3085                 .base_baud      = 460800,
3086                 .uart_offset    = 8,
3087         },
3088 
3089         [pbn_b0_bt_1_921600] = {
3090                 .flags          = FL_BASE0|FL_BASE_BARS,
3091                 .num_ports      = 1,
3092                 .base_baud      = 921600,
3093                 .uart_offset    = 8,
3094         },
3095         [pbn_b0_bt_2_921600] = {
3096                 .flags          = FL_BASE0|FL_BASE_BARS,
3097                 .num_ports      = 2,
3098                 .base_baud      = 921600,
3099                 .uart_offset    = 8,
3100         },
3101         [pbn_b0_bt_4_921600] = {
3102                 .flags          = FL_BASE0|FL_BASE_BARS,
3103                 .num_ports      = 4,
3104                 .base_baud      = 921600,
3105                 .uart_offset    = 8,
3106         },
3107         [pbn_b0_bt_8_921600] = {
3108                 .flags          = FL_BASE0|FL_BASE_BARS,
3109                 .num_ports      = 8,
3110                 .base_baud      = 921600,
3111                 .uart_offset    = 8,
3112         },
3113 
3114         [pbn_b1_1_115200] = {
3115                 .flags          = FL_BASE1,
3116                 .num_ports      = 1,
3117                 .base_baud      = 115200,
3118                 .uart_offset    = 8,
3119         },
3120         [pbn_b1_2_115200] = {
3121                 .flags          = FL_BASE1,
3122                 .num_ports      = 2,
3123                 .base_baud      = 115200,
3124                 .uart_offset    = 8,
3125         },
3126         [pbn_b1_4_115200] = {
3127                 .flags          = FL_BASE1,
3128                 .num_ports      = 4,
3129                 .base_baud      = 115200,
3130                 .uart_offset    = 8,
3131         },
3132         [pbn_b1_8_115200] = {
3133                 .flags          = FL_BASE1,
3134                 .num_ports      = 8,
3135                 .base_baud      = 115200,
3136                 .uart_offset    = 8,
3137         },
3138         [pbn_b1_16_115200] = {
3139                 .flags          = FL_BASE1,
3140                 .num_ports      = 16,
3141                 .base_baud      = 115200,
3142                 .uart_offset    = 8,
3143         },
3144 
3145         [pbn_b1_1_921600] = {
3146                 .flags          = FL_BASE1,
3147                 .num_ports      = 1,
3148                 .base_baud      = 921600,
3149                 .uart_offset    = 8,
3150         },
3151         [pbn_b1_2_921600] = {
3152                 .flags          = FL_BASE1,
3153                 .num_ports      = 2,
3154                 .base_baud      = 921600,
3155                 .uart_offset    = 8,
3156         },
3157         [pbn_b1_4_921600] = {
3158                 .flags          = FL_BASE1,
3159                 .num_ports      = 4,
3160                 .base_baud      = 921600,
3161                 .uart_offset    = 8,
3162         },
3163         [pbn_b1_8_921600] = {
3164                 .flags          = FL_BASE1,
3165                 .num_ports      = 8,
3166                 .base_baud      = 921600,
3167                 .uart_offset    = 8,
3168         },
3169         [pbn_b1_2_1250000] = {
3170                 .flags          = FL_BASE1,
3171                 .num_ports      = 2,
3172                 .base_baud      = 1250000,
3173                 .uart_offset    = 8,
3174         },
3175 
3176         [pbn_b1_bt_1_115200] = {
3177                 .flags          = FL_BASE1|FL_BASE_BARS,
3178                 .num_ports      = 1,
3179                 .base_baud      = 115200,
3180                 .uart_offset    = 8,
3181         },
3182         [pbn_b1_bt_2_115200] = {
3183                 .flags          = FL_BASE1|FL_BASE_BARS,
3184                 .num_ports      = 2,
3185                 .base_baud      = 115200,
3186                 .uart_offset    = 8,
3187         },
3188         [pbn_b1_bt_4_115200] = {
3189                 .flags          = FL_BASE1|FL_BASE_BARS,
3190                 .num_ports      = 4,
3191                 .base_baud      = 115200,
3192                 .uart_offset    = 8,
3193         },
3194 
3195         [pbn_b1_bt_2_921600] = {
3196                 .flags          = FL_BASE1|FL_BASE_BARS,
3197                 .num_ports      = 2,
3198                 .base_baud      = 921600,
3199                 .uart_offset    = 8,
3200         },
3201 
3202         [pbn_b1_1_1382400] = {
3203                 .flags          = FL_BASE1,
3204                 .num_ports      = 1,
3205                 .base_baud      = 1382400,
3206                 .uart_offset    = 8,
3207         },
3208         [pbn_b1_2_1382400] = {
3209                 .flags          = FL_BASE1,
3210                 .num_ports      = 2,
3211                 .base_baud      = 1382400,
3212                 .uart_offset    = 8,
3213         },
3214         [pbn_b1_4_1382400] = {
3215                 .flags          = FL_BASE1,
3216                 .num_ports      = 4,
3217                 .base_baud      = 1382400,
3218                 .uart_offset    = 8,
3219         },
3220         [pbn_b1_8_1382400] = {
3221                 .flags          = FL_BASE1,
3222                 .num_ports      = 8,
3223                 .base_baud      = 1382400,
3224                 .uart_offset    = 8,
3225         },
3226 
3227         [pbn_b2_1_115200] = {
3228                 .flags          = FL_BASE2,
3229                 .num_ports      = 1,
3230                 .base_baud      = 115200,
3231                 .uart_offset    = 8,
3232         },
3233         [pbn_b2_2_115200] = {
3234                 .flags          = FL_BASE2,
3235                 .num_ports      = 2,
3236                 .base_baud      = 115200,
3237                 .uart_offset    = 8,
3238         },
3239         [pbn_b2_4_115200] = {
3240                 .flags          = FL_BASE2,
3241                 .num_ports      = 4,
3242                 .base_baud      = 115200,
3243                 .uart_offset    = 8,
3244         },
3245         [pbn_b2_8_115200] = {
3246                 .flags          = FL_BASE2,
3247                 .num_ports      = 8,
3248                 .base_baud      = 115200,
3249                 .uart_offset    = 8,
3250         },
3251 
3252         [pbn_b2_1_460800] = {
3253                 .flags          = FL_BASE2,
3254                 .num_ports      = 1,
3255                 .base_baud      = 460800,
3256                 .uart_offset    = 8,
3257         },
3258         [pbn_b2_4_460800] = {
3259                 .flags          = FL_BASE2,
3260                 .num_ports      = 4,
3261                 .base_baud      = 460800,
3262                 .uart_offset    = 8,
3263         },
3264         [pbn_b2_8_460800] = {
3265                 .flags          = FL_BASE2,
3266                 .num_ports      = 8,
3267                 .base_baud      = 460800,
3268                 .uart_offset    = 8,
3269         },
3270         [pbn_b2_16_460800] = {
3271                 .flags          = FL_BASE2,
3272                 .num_ports      = 16,
3273                 .base_baud      = 460800,
3274                 .uart_offset    = 8,
3275          },
3276 
3277         [pbn_b2_1_921600] = {
3278                 .flags          = FL_BASE2,
3279                 .num_ports      = 1,
3280                 .base_baud      = 921600,
3281                 .uart_offset    = 8,
3282         },
3283         [pbn_b2_4_921600] = {
3284                 .flags          = FL_BASE2,
3285                 .num_ports      = 4,
3286                 .base_baud      = 921600,
3287                 .uart_offset    = 8,
3288         },
3289         [pbn_b2_8_921600] = {
3290                 .flags          = FL_BASE2,
3291                 .num_ports      = 8,
3292                 .base_baud      = 921600,
3293                 .uart_offset    = 8,
3294         },
3295 
3296         [pbn_b2_8_1152000] = {
3297                 .flags          = FL_BASE2,
3298                 .num_ports      = 8,
3299                 .base_baud      = 1152000,
3300                 .uart_offset    = 8,
3301         },
3302 
3303         [pbn_b2_bt_1_115200] = {
3304                 .flags          = FL_BASE2|FL_BASE_BARS,
3305                 .num_ports      = 1,
3306                 .base_baud      = 115200,
3307                 .uart_offset    = 8,
3308         },
3309         [pbn_b2_bt_2_115200] = {
3310                 .flags          = FL_BASE2|FL_BASE_BARS,
3311                 .num_ports      = 2,
3312                 .base_baud      = 115200,
3313                 .uart_offset    = 8,
3314         },
3315         [pbn_b2_bt_4_115200] = {
3316                 .flags          = FL_BASE2|FL_BASE_BARS,
3317                 .num_ports      = 4,
3318                 .base_baud      = 115200,
3319                 .uart_offset    = 8,
3320         },
3321 
3322         [pbn_b2_bt_2_921600] = {
3323                 .flags          = FL_BASE2|FL_BASE_BARS,
3324                 .num_ports      = 2,
3325                 .base_baud      = 921600,
3326                 .uart_offset    = 8,
3327         },
3328         [pbn_b2_bt_4_921600] = {
3329                 .flags          = FL_BASE2|FL_BASE_BARS,
3330                 .num_ports      = 4,
3331                 .base_baud      = 921600,
3332                 .uart_offset    = 8,
3333         },
3334 
3335         [pbn_b3_2_115200] = {
3336                 .flags          = FL_BASE3,
3337                 .num_ports      = 2,
3338                 .base_baud      = 115200,
3339                 .uart_offset    = 8,
3340         },
3341         [pbn_b3_4_115200] = {
3342                 .flags          = FL_BASE3,
3343                 .num_ports      = 4,
3344                 .base_baud      = 115200,
3345                 .uart_offset    = 8,
3346         },
3347         [pbn_b3_8_115200] = {
3348                 .flags          = FL_BASE3,
3349                 .num_ports      = 8,
3350                 .base_baud      = 115200,
3351                 .uart_offset    = 8,
3352         },
3353 
3354         [pbn_b4_bt_2_921600] = {
3355                 .flags          = FL_BASE4,
3356                 .num_ports      = 2,
3357                 .base_baud      = 921600,
3358                 .uart_offset    = 8,
3359         },
3360         [pbn_b4_bt_4_921600] = {
3361                 .flags          = FL_BASE4,
3362                 .num_ports      = 4,
3363                 .base_baud      = 921600,
3364                 .uart_offset    = 8,
3365         },
3366         [pbn_b4_bt_8_921600] = {
3367                 .flags          = FL_BASE4,
3368                 .num_ports      = 8,
3369                 .base_baud      = 921600,
3370                 .uart_offset    = 8,
3371         },
3372 
3373         /*
3374          * Entries following this are board-specific.
3375          */
3376 
3377         /*
3378          * Panacom - IOMEM
3379          */
3380         [pbn_panacom] = {
3381                 .flags          = FL_BASE2,
3382                 .num_ports      = 2,
3383                 .base_baud      = 921600,
3384                 .uart_offset    = 0x400,
3385                 .reg_shift      = 7,
3386         },
3387         [pbn_panacom2] = {
3388                 .flags          = FL_BASE2|FL_BASE_BARS,
3389                 .num_ports      = 2,
3390                 .base_baud      = 921600,
3391                 .uart_offset    = 0x400,
3392                 .reg_shift      = 7,
3393         },
3394         [pbn_panacom4] = {
3395                 .flags          = FL_BASE2|FL_BASE_BARS,
3396                 .num_ports      = 4,
3397                 .base_baud      = 921600,
3398                 .uart_offset    = 0x400,
3399                 .reg_shift      = 7,
3400         },
3401 
3402         /* I think this entry is broken - the first_offset looks wrong --rmk */
3403         [pbn_plx_romulus] = {
3404                 .flags          = FL_BASE2,
3405                 .num_ports      = 4,
3406                 .base_baud      = 921600,
3407                 .uart_offset    = 8 << 2,
3408                 .reg_shift      = 2,
3409                 .first_offset   = 0x03,
3410         },
3411 
3412         /*
3413          * EndRun Technologies
3414         * Uses the size of PCI Base region 0 to
3415         * signal now many ports are available
3416         * 2 port 952 Uart support
3417         */
3418         [pbn_endrun_2_4000000] = {
3419                 .flags          = FL_BASE0,
3420                 .num_ports      = 2,
3421                 .base_baud      = 4000000,
3422                 .uart_offset    = 0x200,
3423                 .first_offset   = 0x1000,
3424         },
3425 
3426         /*
3427          * This board uses the size of PCI Base region 0 to
3428          * signal now many ports are available
3429          */
3430         [pbn_oxsemi] = {
3431                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3432                 .num_ports      = 32,
3433                 .base_baud      = 115200,
3434                 .uart_offset    = 8,
3435         },
3436         [pbn_oxsemi_1_4000000] = {
3437                 .flags          = FL_BASE0,
3438                 .num_ports      = 1,
3439                 .base_baud      = 4000000,
3440                 .uart_offset    = 0x200,
3441                 .first_offset   = 0x1000,
3442         },
3443         [pbn_oxsemi_2_4000000] = {
3444                 .flags          = FL_BASE0,
3445                 .num_ports      = 2,
3446                 .base_baud      = 4000000,
3447                 .uart_offset    = 0x200,
3448                 .first_offset   = 0x1000,
3449         },
3450         [pbn_oxsemi_4_4000000] = {
3451                 .flags          = FL_BASE0,
3452                 .num_ports      = 4,
3453                 .base_baud      = 4000000,
3454                 .uart_offset    = 0x200,
3455                 .first_offset   = 0x1000,
3456         },
3457         [pbn_oxsemi_8_4000000] = {
3458                 .flags          = FL_BASE0,
3459                 .num_ports      = 8,
3460                 .base_baud      = 4000000,
3461                 .uart_offset    = 0x200,
3462                 .first_offset   = 0x1000,
3463         },
3464 
3465 
3466         /*
3467          * EKF addition for i960 Boards form EKF with serial port.
3468          * Max 256 ports.
3469          */
3470         [pbn_intel_i960] = {
3471                 .flags          = FL_BASE0,
3472                 .num_ports      = 32,
3473                 .base_baud      = 921600,
3474                 .uart_offset    = 8 << 2,
3475                 .reg_shift      = 2,
3476                 .first_offset   = 0x10000,
3477         },
3478         [pbn_sgi_ioc3] = {
3479                 .flags          = FL_BASE0|FL_NOIRQ,
3480                 .num_ports      = 1,
3481                 .base_baud      = 458333,
3482                 .uart_offset    = 8,
3483                 .reg_shift      = 0,
3484                 .first_offset   = 0x20178,
3485         },
3486 
3487         /*
3488          * Computone - uses IOMEM.
3489          */
3490         [pbn_computone_4] = {
3491                 .flags          = FL_BASE0,
3492                 .num_ports      = 4,
3493                 .base_baud      = 921600,
3494                 .uart_offset    = 0x40,
3495                 .reg_shift      = 2,
3496                 .first_offset   = 0x200,
3497         },
3498         [pbn_computone_6] = {
3499                 .flags          = FL_BASE0,
3500                 .num_ports      = 6,
3501                 .base_baud      = 921600,
3502                 .uart_offset    = 0x40,
3503                 .reg_shift      = 2,
3504                 .first_offset   = 0x200,
3505         },
3506         [pbn_computone_8] = {
3507                 .flags          = FL_BASE0,
3508                 .num_ports      = 8,
3509                 .base_baud      = 921600,
3510                 .uart_offset    = 0x40,
3511                 .reg_shift      = 2,
3512                 .first_offset   = 0x200,
3513         },
3514         [pbn_sbsxrsio] = {
3515                 .flags          = FL_BASE0,
3516                 .num_ports      = 8,
3517                 .base_baud      = 460800,
3518                 .uart_offset    = 256,
3519                 .reg_shift      = 4,
3520         },
3521         /*
3522          * PA Semi PWRficient PA6T-1682M on-chip UART
3523          */
3524         [pbn_pasemi_1682M] = {
3525                 .flags          = FL_BASE0,
3526                 .num_ports      = 1,
3527                 .base_baud      = 8333333,
3528         },
3529         /*
3530          * National Instruments 843x
3531          */
3532         [pbn_ni8430_16] = {
3533                 .flags          = FL_BASE0,
3534                 .num_ports      = 16,
3535                 .base_baud      = 3686400,
3536                 .uart_offset    = 0x10,
3537                 .first_offset   = 0x800,
3538         },
3539         [pbn_ni8430_8] = {
3540                 .flags          = FL_BASE0,
3541                 .num_ports      = 8,
3542                 .base_baud      = 3686400,
3543                 .uart_offset    = 0x10,
3544                 .first_offset   = 0x800,
3545         },
3546         [pbn_ni8430_4] = {
3547                 .flags          = FL_BASE0,
3548                 .num_ports      = 4,
3549                 .base_baud      = 3686400,
3550                 .uart_offset    = 0x10,
3551                 .first_offset   = 0x800,
3552         },
3553         [pbn_ni8430_2] = {
3554                 .flags          = FL_BASE0,
3555                 .num_ports      = 2,
3556                 .base_baud      = 3686400,
3557                 .uart_offset    = 0x10,
3558                 .first_offset   = 0x800,
3559         },
3560         /*
3561          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3562          */
3563         [pbn_ADDIDATA_PCIe_1_3906250] = {
3564                 .flags          = FL_BASE0,
3565                 .num_ports      = 1,
3566                 .base_baud      = 3906250,
3567                 .uart_offset    = 0x200,
3568                 .first_offset   = 0x1000,
3569         },
3570         [pbn_ADDIDATA_PCIe_2_3906250] = {
3571                 .flags          = FL_BASE0,
3572                 .num_ports      = 2,
3573                 .base_baud      = 3906250,
3574                 .uart_offset    = 0x200,
3575                 .first_offset   = 0x1000,
3576         },
3577         [pbn_ADDIDATA_PCIe_4_3906250] = {
3578                 .flags          = FL_BASE0,
3579                 .num_ports      = 4,
3580                 .base_baud      = 3906250,
3581                 .uart_offset    = 0x200,
3582                 .first_offset   = 0x1000,
3583         },
3584         [pbn_ADDIDATA_PCIe_8_3906250] = {
3585                 .flags          = FL_BASE0,
3586                 .num_ports      = 8,
3587                 .base_baud      = 3906250,
3588                 .uart_offset    = 0x200,
3589                 .first_offset   = 0x1000,
3590         },
3591         [pbn_ce4100_1_115200] = {
3592                 .flags          = FL_BASE_BARS,
3593                 .num_ports      = 2,
3594                 .base_baud      = 921600,
3595                 .reg_shift      = 2,
3596         },
3597         [pbn_omegapci] = {
3598                 .flags          = FL_BASE0,
3599                 .num_ports      = 8,
3600                 .base_baud      = 115200,
3601                 .uart_offset    = 0x200,
3602         },
3603         [pbn_NETMOS9900_2s_115200] = {
3604                 .flags          = FL_BASE0,
3605                 .num_ports      = 2,
3606                 .base_baud      = 115200,
3607         },
3608         [pbn_brcm_trumanage] = {
3609                 .flags          = FL_BASE0,
3610                 .num_ports      = 1,
3611                 .reg_shift      = 2,
3612                 .base_baud      = 115200,
3613         },
3614         [pbn_fintek_4] = {
3615                 .num_ports      = 4,
3616                 .uart_offset    = 8,
3617                 .base_baud      = 115200,
3618                 .first_offset   = 0x40,
3619         },
3620         [pbn_fintek_8] = {
3621                 .num_ports      = 8,
3622                 .uart_offset    = 8,
3623                 .base_baud      = 115200,
3624                 .first_offset   = 0x40,
3625         },
3626         [pbn_fintek_12] = {
3627                 .num_ports      = 12,
3628                 .uart_offset    = 8,
3629                 .base_baud      = 115200,
3630                 .first_offset   = 0x40,
3631         },
3632         [pbn_fintek_F81504A] = {
3633                 .num_ports      = 4,
3634                 .uart_offset    = 8,
3635                 .base_baud      = 115200,
3636         },
3637         [pbn_fintek_F81508A] = {
3638                 .num_ports      = 8,
3639                 .uart_offset    = 8,
3640                 .base_baud      = 115200,
3641         },
3642         [pbn_fintek_F81512A] = {
3643                 .num_ports      = 12,
3644                 .uart_offset    = 8,
3645                 .base_baud      = 115200,
3646         },
3647         [pbn_wch382_2] = {
3648                 .flags          = FL_BASE0,
3649                 .num_ports      = 2,
3650                 .base_baud      = 115200,
3651                 .uart_offset    = 8,
3652                 .first_offset   = 0xC0,
3653         },
3654         [pbn_wch384_4] = {
3655                 .flags          = FL_BASE0,
3656                 .num_ports      = 4,
3657                 .base_baud      = 115200,
3658                 .uart_offset    = 8,
3659                 .first_offset   = 0xC0,
3660         },
3661         /*
3662          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3663          */
3664         [pbn_pericom_PI7C9X7951] = {
3665                 .flags          = FL_BASE0,
3666                 .num_ports      = 1,
3667                 .base_baud      = 921600,
3668                 .uart_offset    = 0x8,
3669         },
3670         [pbn_pericom_PI7C9X7952] = {
3671                 .flags          = FL_BASE0,
3672                 .num_ports      = 2,
3673                 .base_baud      = 921600,
3674                 .uart_offset    = 0x8,
3675         },
3676         [pbn_pericom_PI7C9X7954] = {
3677                 .flags          = FL_BASE0,
3678                 .num_ports      = 4,
3679                 .base_baud      = 921600,
3680                 .uart_offset    = 0x8,
3681         },
3682         [pbn_pericom_PI7C9X7958] = {
3683                 .flags          = FL_BASE0,
3684                 .num_ports      = 8,
3685                 .base_baud      = 921600,
3686                 .uart_offset    = 0x8,
3687         },
3688         [pbn_sunix_pci_1s] = {
3689                 .num_ports      = 1,
3690                 .base_baud      = 921600,
3691                 .uart_offset    = 0x8,
3692         },
3693         [pbn_sunix_pci_2s] = {
3694                 .num_ports      = 2,
3695                 .base_baud      = 921600,
3696                 .uart_offset    = 0x8,
3697         },
3698         [pbn_sunix_pci_4s] = {
3699                 .num_ports      = 4,
3700                 .base_baud      = 921600,
3701                 .uart_offset    = 0x8,
3702         },
3703         [pbn_sunix_pci_8s] = {
3704                 .num_ports      = 8,
3705                 .base_baud      = 921600,
3706                 .uart_offset    = 0x8,
3707         },
3708         [pbn_sunix_pci_16s] = {
3709                 .num_ports      = 16,
3710                 .base_baud      = 921600,
3711                 .uart_offset    = 0x8,
3712         },
3713         [pbn_moxa8250_2p] = {
3714                 .flags          = FL_BASE1,
3715                 .num_ports      = 2,
3716                 .base_baud      = 921600,
3717                 .uart_offset    = 0x200,
3718         },
3719         [pbn_moxa8250_4p] = {
3720                 .flags          = FL_BASE1,
3721                 .num_ports      = 4,
3722                 .base_baud      = 921600,
3723                 .uart_offset    = 0x200,
3724         },
3725         [pbn_moxa8250_8p] = {
3726                 .flags          = FL_BASE1,
3727                 .num_ports      = 8,
3728                 .base_baud      = 921600,
3729                 .uart_offset    = 0x200,
3730         },
3731 };
3732 
3733 static const struct pci_device_id blacklist[] = {
3734         /* softmodems */
3735         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3736         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3737         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3738 
3739         /* multi-io cards handled by parport_serial */
3740         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3741         { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3742         { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3743 
3744         /* Intel platforms with MID UART */
3745         { PCI_VDEVICE(INTEL, 0x081b), },
3746         { PCI_VDEVICE(INTEL, 0x081c), },
3747         { PCI_VDEVICE(INTEL, 0x081d), },
3748         { PCI_VDEVICE(INTEL, 0x1191), },
3749         { PCI_VDEVICE(INTEL, 0x18d8), },
3750         { PCI_VDEVICE(INTEL, 0x19d8), },
3751 
3752         /* Intel platforms with DesignWare UART */
3753         { PCI_VDEVICE(INTEL, 0x0936), },
3754         { PCI_VDEVICE(INTEL, 0x0f0a), },
3755         { PCI_VDEVICE(INTEL, 0x0f0c), },
3756         { PCI_VDEVICE(INTEL, 0x228a), },
3757         { PCI_VDEVICE(INTEL, 0x228c), },
3758         { PCI_VDEVICE(INTEL, 0x9ce3), },
3759         { PCI_VDEVICE(INTEL, 0x9ce4), },
3760 
3761         /* Exar devices */
3762         { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3763         { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3764 
3765         /* End of the black list */
3766         { }
3767 };
3768 
3769 static int serial_pci_is_class_communication(struct pci_dev *dev)
3770 {
3771         /*
3772          * If it is not a communications device or the programming
3773          * interface is greater than 6, give up.
3774          */
3775         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3776              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3777              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3778             (dev->class & 0xff) > 6)
3779                 return -ENODEV;
3780 
3781         return 0;
3782 }
3783 
3784 /*
3785  * Given a complete unknown PCI device, try to use some heuristics to
3786  * guess what the configuration might be, based on the pitiful PCI
3787  * serial specs.  Returns 0 on success, -ENODEV on failure.
3788  */
3789 static int
3790 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3791 {
3792         int num_iomem, num_port, first_port = -1, i;
3793         int rc;
3794 
3795         rc = serial_pci_is_class_communication(dev);
3796         if (rc)
3797                 return rc;
3798 
3799         /*
3800          * Should we try to make guesses for multiport serial devices later?
3801          */
3802         if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3803                 return -ENODEV;
3804 
3805         num_iomem = num_port = 0;
3806         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3807                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3808                         num_port++;
3809                         if (first_port == -1)
3810                                 first_port = i;
3811                 }
3812                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3813                         num_iomem++;
3814         }
3815 
3816         /*
3817          * If there is 1 or 0 iomem regions, and exactly one port,
3818          * use it.  We guess the number of ports based on the IO
3819          * region size.
3820          */
3821         if (num_iomem <= 1 && num_port == 1) {
3822                 board->flags = first_port;
3823                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3824                 return 0;
3825         }
3826 
3827         /*
3828          * Now guess if we've got a board which indexes by BARs.
3829          * Each IO BAR should be 8 bytes, and they should follow
3830          * consecutively.
3831          */
3832         first_port = -1;
3833         num_port = 0;
3834         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3835                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3836                     pci_resource_len(dev, i) == 8 &&
3837                     (first_port == -1 || (first_port + num_port) == i)) {
3838                         num_port++;
3839                         if (first_port == -1)
3840                                 first_port = i;
3841                 }
3842         }
3843 
3844         if (num_port > 1) {
3845                 board->flags = first_port | FL_BASE_BARS;
3846                 board->num_ports = num_port;
3847                 return 0;
3848         }
3849 
3850         return -ENODEV;
3851 }
3852 
3853 static inline int
3854 serial_pci_matches(const struct pciserial_board *board,
3855                    const struct pciserial_board *guessed)
3856 {
3857         return
3858             board->num_ports == guessed->num_ports &&
3859             board->base_baud == guessed->base_baud &&
3860             board->uart_offset == guessed->uart_offset &&
3861             board->reg_shift == guessed->reg_shift &&
3862             board->first_offset == guessed->first_offset;
3863 }
3864 
3865 struct serial_private *
3866 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3867 {
3868         struct uart_8250_port uart;
3869         struct serial_private *priv;
3870         struct pci_serial_quirk *quirk;
3871         int rc, nr_ports, i;
3872 
3873         nr_ports = board->num_ports;
3874 
3875         /*
3876          * Find an init and setup quirks.
3877          */
3878         quirk = find_quirk(dev);
3879 
3880         /*
3881          * Run the new-style initialization function.
3882          * The initialization function returns:
3883          *  <0  - error
3884          *   0  - use board->num_ports
3885          *  >0  - number of ports
3886          */
3887         if (quirk->init) {
3888                 rc = quirk->init(dev);
3889                 if (rc < 0) {
3890                         priv = ERR_PTR(rc);
3891                         goto err_out;
3892                 }
3893                 if (rc)
3894                         nr_ports = rc;
3895         }
3896 
3897         priv = kzalloc(sizeof(struct serial_private) +
3898                        sizeof(unsigned int) * nr_ports,
3899                        GFP_KERNEL);
3900         if (!priv) {
3901                 priv = ERR_PTR(-ENOMEM);
3902                 goto err_deinit;
3903         }
3904 
3905         priv->dev = dev;
3906         priv->quirk = quirk;
3907 
3908         memset(&uart, 0, sizeof(uart));
3909         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3910         uart.port.uartclk = board->base_baud * 16;
3911 
3912         if (pci_match_id(pci_use_msi, dev)) {
3913                 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n");
3914                 pci_set_master(dev);
3915                 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
3916         } else {
3917                 dev_dbg(&dev->dev, "Using legacy interrupts\n");
3918                 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
3919         }
3920         if (rc < 0) {
3921                 kfree(priv);
3922                 priv = ERR_PTR(rc);
3923                 goto err_deinit;
3924         }
3925 
3926         uart.port.irq = pci_irq_vector(dev, 0);
3927         uart.port.dev = &dev->dev;
3928 
3929         for (i = 0; i < nr_ports; i++) {
3930                 if (quirk->setup(priv, board, &uart, i))
3931                         break;
3932 
3933                 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3934                         uart.port.iobase, uart.port.irq, uart.port.iotype);
3935 
3936                 priv->line[i] = serial8250_register_8250_port(&uart);
3937                 if (priv->line[i] < 0) {
3938                         dev_err(&dev->dev,
3939                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3940                                 uart.port.iobase, uart.port.irq,
3941                                 uart.port.iotype, priv->line[i]);
3942                         break;
3943                 }
3944         }
3945         priv->nr = i;
3946         priv->board = board;
3947         return priv;
3948 
3949 err_deinit:
3950         if (quirk->exit)
3951                 quirk->exit(dev);
3952 err_out:
3953         return priv;
3954 }
3955 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3956 
3957 static void pciserial_detach_ports(struct serial_private *priv)
3958 {
3959         struct pci_serial_quirk *quirk;
3960         int i;
3961 
3962         for (i = 0; i < priv->nr; i++)
3963                 serial8250_unregister_port(priv->line[i]);
3964 
3965         /*
3966          * Find the exit quirks.
3967          */
3968         quirk = find_quirk(priv->dev);
3969         if (quirk->exit)
3970                 quirk->exit(priv->dev);
3971 }
3972 
3973 void pciserial_remove_ports(struct serial_private *priv)
3974 {
3975         pciserial_detach_ports(priv);
3976         kfree(priv);
3977 }
3978 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3979 
3980 void pciserial_suspend_ports(struct serial_private *priv)
3981 {
3982         int i;
3983 
3984         for (i = 0; i < priv->nr; i++)
3985                 if (priv->line[i] >= 0)
3986                         serial8250_suspend_port(priv->line[i]);
3987 
3988         /*
3989          * Ensure that every init quirk is properly torn down
3990          */
3991         if (priv->quirk->exit)
3992                 priv->quirk->exit(priv->dev);
3993 }
3994 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3995 
3996 void pciserial_resume_ports(struct serial_private *priv)
3997 {
3998         int i;
3999 
4000         /*
4001          * Ensure that the board is correctly configured.
4002          */
4003         if (priv->quirk->init)
4004                 priv->quirk->init(priv->dev);
4005 
4006         for (i = 0; i < priv->nr; i++)
4007                 if (priv->line[i] >= 0)
4008                         serial8250_resume_port(priv->line[i]);
4009 }
4010 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4011 
4012 /*
4013  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4014  * to the arrangement of serial ports on a PCI card.
4015  */
4016 static int
4017 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4018 {
4019         struct pci_serial_quirk *quirk;
4020         struct serial_private *priv;
4021         const struct pciserial_board *board;
4022         const struct pci_device_id *exclude;
4023         struct pciserial_board tmp;
4024         int rc;
4025 
4026         quirk = find_quirk(dev);
4027         if (quirk->probe) {
4028                 rc = quirk->probe(dev);
4029                 if (rc)
4030                         return rc;
4031         }
4032 
4033         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4034                 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4035                         ent->driver_data);
4036                 return -EINVAL;
4037         }
4038 
4039         board = &pci_boards[ent->driver_data];
4040 
4041         exclude = pci_match_id(blacklist, dev);
4042         if (exclude)
4043                 return -ENODEV;
4044 
4045         rc = pcim_enable_device(dev);
4046         pci_save_state(dev);
4047         if (rc)
4048                 return rc;
4049 
4050         if (ent->driver_data == pbn_default) {
4051                 /*
4052                  * Use a copy of the pci_board entry for this;
4053                  * avoid changing entries in the table.
4054                  */
4055                 memcpy(&tmp, board, sizeof(struct pciserial_board));
4056                 board = &tmp;
4057 
4058                 /*
4059                  * We matched one of our class entries.  Try to
4060                  * determine the parameters of this board.
4061                  */
4062                 rc = serial_pci_guess_board(dev, &tmp);
4063                 if (rc)
4064                         return rc;
4065         } else {
4066                 /*
4067                  * We matched an explicit entry.  If we are able to
4068                  * detect this boards settings with our heuristic,
4069                  * then we no longer need this entry.
4070                  */
4071                 memcpy(&tmp, &pci_boards[pbn_default],
4072                        sizeof(struct pciserial_board));
4073                 rc = serial_pci_guess_board(dev, &tmp);
4074                 if (rc == 0 && serial_pci_matches(board, &tmp))
4075                         moan_device("Redundant entry in serial pci_table.",
4076                                     dev);
4077         }
4078 
4079         priv = pciserial_init_ports(dev, board);
4080         if (IS_ERR(priv))
4081                 return PTR_ERR(priv);
4082 
4083         pci_set_drvdata(dev, priv);
4084         return 0;
4085 }
4086 
4087 static void pciserial_remove_one(struct pci_dev *dev)
4088 {
4089         struct serial_private *priv = pci_get_drvdata(dev);
4090 
4091         pciserial_remove_ports(priv);
4092 }
4093 
4094 #ifdef CONFIG_PM_SLEEP
4095 static int pciserial_suspend_one(struct device *dev)
4096 {
4097         struct serial_private *priv = dev_get_drvdata(dev);
4098 
4099         if (priv)
4100                 pciserial_suspend_ports(priv);
4101 
4102         return 0;
4103 }
4104 
4105 static int pciserial_resume_one(struct device *dev)
4106 {
4107         struct pci_dev *pdev = to_pci_dev(dev);
4108         struct serial_private *priv = pci_get_drvdata(pdev);
4109         int err;
4110 
4111         if (priv) {
4112                 /*
4113                  * The device may have been disabled.  Re-enable it.
4114                  */
4115                 err = pci_enable_device(pdev);
4116                 /* FIXME: We cannot simply error out here */
4117                 if (err)
4118                         dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4119                 pciserial_resume_ports(priv);
4120         }
4121         return 0;
4122 }
4123 #endif
4124 
4125 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4126                          pciserial_resume_one);
4127 
4128 static const struct pci_device_id serial_pci_tbl[] = {
4129         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4130         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4131                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4132                 pbn_b2_8_921600 },
4133         /* Advantech also use 0x3618 and 0xf618 */
4134         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4135                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4136                 pbn_b0_4_921600 },
4137         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4138                 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4139                 pbn_b0_4_921600 },
4140         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4141                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4142                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4143                 pbn_b1_8_1382400 },
4144         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4145                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4146                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4147                 pbn_b1_4_1382400 },
4148         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4149                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4150                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4151                 pbn_b1_2_1382400 },
4152         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4153                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4154                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4155                 pbn_b1_8_1382400 },
4156         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4157                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4158                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4159                 pbn_b1_4_1382400 },
4160         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4161                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4162                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4163                 pbn_b1_2_1382400 },
4164         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4165                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4166                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4167                 pbn_b1_8_921600 },
4168         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4169                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4170                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4171                 pbn_b1_8_921600 },
4172         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4173                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4174                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4175                 pbn_b1_4_921600 },
4176         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4177                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4178                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4179                 pbn_b1_4_921600 },
4180         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4181                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4182                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4183                 pbn_b1_2_921600 },
4184         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4185                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4186                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4187                 pbn_b1_8_921600 },
4188         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4189                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4190                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4191                 pbn_b1_8_921600 },
4192         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4193                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4194                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4195                 pbn_b1_4_921600 },
4196         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4197                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4198                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4199                 pbn_b1_2_1250000 },
4200         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4201                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4202                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4203                 pbn_b0_2_1843200 },
4204         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4205                 PCI_SUBVENDOR_ID_CONNECT_TECH,
4206                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4207                 pbn_b0_4_1843200 },
4208         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4209                 PCI_VENDOR_ID_AFAVLAB,
4210                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4211                 pbn_b0_4_1152000 },
4212         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4213                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4214                 pbn_b2_bt_1_115200 },
4215         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4216                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4217                 pbn_b2_bt_2_115200 },
4218         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4219                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4220                 pbn_b2_bt_4_115200 },
4221         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4222                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4223                 pbn_b2_bt_2_115200 },
4224         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4225                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226                 pbn_b2_bt_4_115200 },
4227         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4228                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229                 pbn_b2_8_115200 },
4230         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232                 pbn_b2_8_460800 },
4233         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235                 pbn_b2_8_115200 },
4236 
4237         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4238                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239                 pbn_b2_bt_2_115200 },
4240         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4241                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4242                 pbn_b2_bt_2_921600 },
4243         /*
4244          * VScom SPCOM800, from sl@s.pl
4245          */
4246         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248                 pbn_b2_8_921600 },
4249         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251                 pbn_b2_4_921600 },
4252         /* Unknown card - subdevice 0x1584 */
4253         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4254                 PCI_VENDOR_ID_PLX,
4255                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4256                 pbn_b2_4_115200 },
4257         /* Unknown card - subdevice 0x1588 */
4258         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4259                 PCI_VENDOR_ID_PLX,
4260                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4261                 pbn_b2_8_115200 },
4262         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4263                 PCI_SUBVENDOR_ID_KEYSPAN,
4264                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4265                 pbn_panacom },
4266         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268                 pbn_panacom4 },
4269         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4270                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4271                 pbn_panacom2 },
4272         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4273                 PCI_VENDOR_ID_ESDGMBH,
4274                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4275                 pbn_b2_4_115200 },
4276         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4277                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4278                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4279                 pbn_b2_4_460800 },
4280         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4281                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4282                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4283                 pbn_b2_8_460800 },
4284         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4285                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4286                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4287                 pbn_b2_16_460800 },
4288         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4289                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4290                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4291                 pbn_b2_16_460800 },
4292         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4293                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4294                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4295                 pbn_b2_4_460800 },
4296         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4297                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4298                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4299                 pbn_b2_8_460800 },
4300         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4301                 PCI_SUBVENDOR_ID_EXSYS,
4302                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4303                 pbn_b2_4_115200 },
4304         /*
4305          * Megawolf Romulus PCI Serial Card, from Mike Hudson
4306          * (Exoray@isys.ca)
4307          */
4308         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4309                 0x10b5, 0x106a, 0, 0,
4310                 pbn_plx_romulus },
4311         /*
4312         * EndRun Technologies. PCI express device range.
4313         *    EndRun PTP/1588 has 2 Native UARTs.
4314         */
4315         {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4316                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4317                 pbn_endrun_2_4000000 },
4318         /*
4319          * Quatech cards. These actually have configurable clocks but for
4320          * now we just use the default.
4321          *
4322          * 100 series are RS232, 200 series RS422,
4323          */
4324         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4325                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4326                 pbn_b1_4_115200 },
4327         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4328                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4329                 pbn_b1_2_115200 },
4330         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4331                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332                 pbn_b2_2_115200 },
4333         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4334                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335                 pbn_b1_2_115200 },
4336         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4337                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338                 pbn_b2_2_115200 },
4339         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4340                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341                 pbn_b1_4_115200 },
4342         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4343                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344                 pbn_b1_8_115200 },
4345         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4346                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347                 pbn_b1_8_115200 },
4348         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4349                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4350                 pbn_b1_4_115200 },
4351         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4352                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353                 pbn_b1_2_115200 },
4354         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356                 pbn_b1_4_115200 },
4357         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4358                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359                 pbn_b1_2_115200 },
4360         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4361                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362                 pbn_b2_4_115200 },
4363         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4364                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365                 pbn_b2_2_115200 },
4366         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4367                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4368                 pbn_b2_1_115200 },
4369         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4370                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4371                 pbn_b2_4_115200 },
4372         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4373                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4374                 pbn_b2_2_115200 },
4375         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4376                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4377                 pbn_b2_1_115200 },
4378         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4379                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380                 pbn_b0_8_115200 },
4381 
4382         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4383                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4384                 0, 0,
4385                 pbn_b0_4_921600 },
4386         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4387                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4388                 0, 0,
4389                 pbn_b0_4_1152000 },
4390         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
4391                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4392                 pbn_b0_bt_2_921600 },
4393 
4394                 /*
4395                  * The below card is a little controversial since it is the
4396                  * subject of a PCI vendor/device ID clash.  (See
4397                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4398                  * For now just used the hex ID 0x950a.
4399                  */
4400         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4401                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4402                 0, 0, pbn_b0_2_115200 },
4403         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4404                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4405                 0, 0, pbn_b0_2_115200 },
4406         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
4407                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408                 pbn_b0_2_1130000 },
4409         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4410                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4411                 pbn_b0_1_921600 },
4412         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4413                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4414                 pbn_b0_4_115200 },
4415         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4416                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417                 pbn_b0_bt_2_921600 },
4418         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4419                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420                 pbn_b2_8_1152000 },
4421 
4422         /*
4423          * Oxford Semiconductor Inc. Tornado PCI express device range.
4424          */
4425         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427                 pbn_b0_1_4000000 },
4428         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430                 pbn_b0_1_4000000 },
4431         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433                 pbn_oxsemi_1_4000000 },
4434         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436                 pbn_oxsemi_1_4000000 },
4437         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439                 pbn_b0_1_4000000 },
4440         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442                 pbn_b0_1_4000000 },
4443         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445                 pbn_oxsemi_1_4000000 },
4446         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448                 pbn_oxsemi_1_4000000 },
4449         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451                 pbn_b0_1_4000000 },
4452         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4453                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454                 pbn_b0_1_4000000 },
4455         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4456                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457                 pbn_b0_1_4000000 },
4458         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4459                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460                 pbn_b0_1_4000000 },
4461         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4462                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463                 pbn_oxsemi_2_4000000 },
4464         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4465                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466                 pbn_oxsemi_2_4000000 },
4467         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4468                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469                 pbn_oxsemi_4_4000000 },
4470         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4471                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472                 pbn_oxsemi_4_4000000 },
4473         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4474                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475                 pbn_oxsemi_8_4000000 },
4476         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4477                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478                 pbn_oxsemi_8_4000000 },
4479         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4480                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481                 pbn_oxsemi_1_4000000 },
4482         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4483                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484                 pbn_oxsemi_1_4000000 },
4485         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487                 pbn_oxsemi_1_4000000 },
4488         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4489                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490                 pbn_oxsemi_1_4000000 },
4491         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4492                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493                 pbn_oxsemi_1_4000000 },
4494         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4495                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496                 pbn_oxsemi_1_4000000 },
4497         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4498                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499                 pbn_oxsemi_1_4000000 },
4500         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4501                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502                 pbn_oxsemi_1_4000000 },
4503         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4504                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505                 pbn_oxsemi_1_4000000 },
4506         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4507                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508                 pbn_oxsemi_1_4000000 },
4509         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4510                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511                 pbn_oxsemi_1_4000000 },
4512         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4513                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514                 pbn_oxsemi_1_4000000 },
4515         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4516                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517                 pbn_oxsemi_1_4000000 },
4518         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4519                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520                 pbn_oxsemi_1_4000000 },
4521         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4522                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523                 pbn_oxsemi_1_4000000 },
4524         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4525                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4526                 pbn_oxsemi_1_4000000 },
4527         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4528                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529                 pbn_oxsemi_1_4000000 },
4530         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4531                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532                 pbn_oxsemi_1_4000000 },
4533         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4534                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535                 pbn_oxsemi_1_4000000 },
4536         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4537                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538                 pbn_oxsemi_1_4000000 },
4539         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4540                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541                 pbn_oxsemi_1_4000000 },
4542         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544                 pbn_oxsemi_1_4000000 },
4545         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4546                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547                 pbn_oxsemi_1_4000000 },
4548         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4549                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550                 pbn_oxsemi_1_4000000 },
4551         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4552                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553                 pbn_oxsemi_1_4000000 },
4554         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4555                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556                 pbn_oxsemi_1_4000000 },
4557         /*
4558          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4559          */
4560         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4561                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4562                 pbn_oxsemi_1_4000000 },
4563         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4564                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4565                 pbn_oxsemi_2_4000000 },
4566         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4567                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4568                 pbn_oxsemi_4_4000000 },
4569         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4570                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4571                 pbn_oxsemi_8_4000000 },
4572 
4573         /*
4574          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4575          */
4576         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4577                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4578                 pbn_oxsemi_2_4000000 },
4579 
4580         /*
4581          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4582          * from skokodyn@yahoo.com
4583          */
4584         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4585                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4586                 pbn_sbsxrsio },
4587         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4588                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4589                 pbn_sbsxrsio },
4590         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4591                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4592                 pbn_sbsxrsio },
4593         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4594                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4595                 pbn_sbsxrsio },
4596 
4597         /*
4598          * Digitan DS560-558, from jimd@esoft.com
4599          */
4600         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4601                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602                 pbn_b1_1_115200 },
4603 
4604         /*
4605          * Titan Electronic cards
4606          *  The 400L and 800L have a custom setup quirk.
4607          */
4608         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610                 pbn_b0_1_921600 },
4611         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4612                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613                 pbn_b0_2_921600 },
4614         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616                 pbn_b0_4_921600 },
4617         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619                 pbn_b0_4_921600 },
4620         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4621                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622                 pbn_b1_1_921600 },
4623         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625                 pbn_b1_bt_2_921600 },
4626         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4627                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628                 pbn_b0_bt_4_921600 },
4629         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4630                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631                 pbn_b0_bt_8_921600 },
4632         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4633                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634                 pbn_b4_bt_2_921600 },
4635         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4636                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637                 pbn_b4_bt_4_921600 },
4638         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4639                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640                 pbn_b4_bt_8_921600 },
4641         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4642                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643                 pbn_b0_4_921600 },
4644         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4645                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646                 pbn_b0_4_921600 },
4647         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4648                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649                 pbn_b0_4_921600 },
4650         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4651                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652                 pbn_oxsemi_1_4000000 },
4653         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655                 pbn_oxsemi_2_4000000 },
4656         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658                 pbn_oxsemi_4_4000000 },
4659         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4660                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661                 pbn_oxsemi_8_4000000 },
4662         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4663                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664                 pbn_oxsemi_2_4000000 },
4665         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4666                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667                 pbn_oxsemi_2_4000000 },
4668         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4669                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670                 pbn_b0_bt_2_921600 },
4671         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4672                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673                 pbn_b0_4_921600 },
4674         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4675                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676                 pbn_b0_4_921600 },
4677         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4678                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4679                 pbn_b0_4_921600 },
4680         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4681                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682                 pbn_b0_4_921600 },
4683 
4684         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4685                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686                 pbn_b2_1_460800 },
4687         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689                 pbn_b2_1_460800 },
4690         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4691                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692                 pbn_b2_1_460800 },
4693         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695                 pbn_b2_bt_2_921600 },
4696         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698                 pbn_b2_bt_2_921600 },
4699         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701                 pbn_b2_bt_2_921600 },
4702         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4703                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704                 pbn_b2_bt_4_921600 },
4705         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4706                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707                 pbn_b2_bt_4_921600 },
4708         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4709                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710                 pbn_b2_bt_4_921600 },
4711         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4712                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713                 pbn_b0_1_921600 },
4714         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4715                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716                 pbn_b0_1_921600 },
4717         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4718                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719                 pbn_b0_1_921600 },
4720         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4721                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722                 pbn_b0_bt_2_921600 },
4723         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4724                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725                 pbn_b0_bt_2_921600 },
4726         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4727                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728                 pbn_b0_bt_2_921600 },
4729         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4730                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731                 pbn_b0_bt_4_921600 },
4732         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4733                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734                 pbn_b0_bt_4_921600 },
4735         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4736                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737                 pbn_b0_bt_4_921600 },
4738         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4739                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740                 pbn_b0_bt_8_921600 },
4741         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4742                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743                 pbn_b0_bt_8_921600 },
4744         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4745                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746                 pbn_b0_bt_8_921600 },
4747 
4748         /*
4749          * Computone devices submitted by Doug McNash dmcnash@computone.com
4750          */
4751         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4752                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4753                 0, 0, pbn_computone_4 },
4754         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4755                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4756                 0, 0, pbn_computone_8 },
4757         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4758                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4759                 0, 0, pbn_computone_6 },
4760 
4761         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4762                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763                 pbn_oxsemi },
4764         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4765                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4766                 pbn_b0_bt_1_921600 },
4767 
4768         /*
4769          * Sunix PCI serial boards
4770          */
4771         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4772                 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
4773                 pbn_sunix_pci_1s },
4774         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4775                 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
4776                 pbn_sunix_pci_2s },
4777         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4778                 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
4779                 pbn_sunix_pci_4s },
4780         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4781                 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
4782                 pbn_sunix_pci_4s },
4783         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4784                 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
4785                 pbn_sunix_pci_8s },
4786         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4787                 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
4788                 pbn_sunix_pci_8s },
4789         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4790                 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
4791                 pbn_sunix_pci_16s },
4792 
4793         /*
4794          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4795          */
4796         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4797                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798                 pbn_b0_bt_8_115200 },
4799         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801                 pbn_b0_bt_8_115200 },
4802 
4803         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4804                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805                 pbn_b0_bt_2_115200 },
4806         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4807                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808                 pbn_b0_bt_2_115200 },
4809         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4810                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811                 pbn_b0_bt_2_115200 },
4812         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4813                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814                 pbn_b0_bt_2_115200 },
4815         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4816                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817                 pbn_b0_bt_2_115200 },
4818         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4819                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820                 pbn_b0_bt_4_460800 },
4821         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4822                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4823                 pbn_b0_bt_4_460800 },
4824         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4825                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4826                 pbn_b0_bt_2_460800 },
4827         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4828                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4829                 pbn_b0_bt_2_460800 },
4830         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4831                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4832                 pbn_b0_bt_2_460800 },
4833         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4834                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4835                 pbn_b0_bt_1_115200 },
4836         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4837                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4838                 pbn_b0_bt_1_460800 },
4839 
4840         /*
4841          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4842          * Cards are identified by their subsystem vendor IDs, which
4843          * (in hex) match the model number.
4844          *
4845          * Note that JC140x are RS422/485 cards which require ox950
4846          * ACR = 0x10, and as such are not currently fully supported.
4847          */
4848         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4849                 0x1204, 0x0004, 0, 0,
4850                 pbn_b0_4_921600 },
4851         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4852                 0x1208, 0x0004, 0, 0,
4853                 pbn_b0_4_921600 },
4854 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4855                 0x1402, 0x0002, 0, 0,
4856                 pbn_b0_2_921600 }, */
4857 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4858                 0x1404, 0x0004, 0, 0,
4859                 pbn_b0_4_921600 }, */
4860         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4861                 0x1208, 0x0004, 0, 0,
4862                 pbn_b0_4_921600 },
4863 
4864         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4865                 0x1204, 0x0004, 0, 0,
4866                 pbn_b0_4_921600 },
4867         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4868                 0x1208, 0x0004, 0, 0,
4869                 pbn_b0_4_921600 },
4870         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4871                 0x1208, 0x0004, 0, 0,
4872                 pbn_b0_4_921600 },
4873         /*
4874          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4875          */
4876         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4877                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4878                 pbn_b1_1_1382400 },
4879 
4880         /*
4881          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4882          */
4883         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4884                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885                 pbn_b1_1_1382400 },
4886 
4887         /*
4888          * RAStel 2 port modem, gerg@moreton.com.au
4889          */
4890         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4891                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892                 pbn_b2_bt_2_115200 },
4893 
4894         /*
4895          * EKF addition for i960 Boards form EKF with serial port
4896          */
4897         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4898                 0xE4BF, PCI_ANY_ID, 0, 0,
4899                 pbn_intel_i960 },
4900 
4901         /*
4902          * Xircom Cardbus/Ethernet combos
4903          */
4904         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4905                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906                 pbn_b0_1_115200 },
4907         /*
4908          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4909          */
4910         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4911                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912                 pbn_b0_1_115200 },
4913 
4914         /*
4915          * Untested PCI modems, sent in from various folks...
4916          */
4917 
4918         /*
4919          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4920          */
4921         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4922                 0x1048, 0x1500, 0, 0,
4923                 pbn_b1_1_115200 },
4924 
4925         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4926                 0xFF00, 0, 0, 0,
4927                 pbn_sgi_ioc3 },
4928 
4929         /*
4930          * HP Diva card
4931          */
4932         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4933                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4934                 pbn_b1_1_115200 },
4935         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4936                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937                 pbn_b0_5_115200 },
4938         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4939                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940                 pbn_b2_1_115200 },
4941 
4942         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4943                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944                 pbn_b3_2_115200 },
4945         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4946                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947                 pbn_b3_4_115200 },
4948         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4949                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950                 pbn_b3_8_115200 },
4951         /*
4952          * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4953          */
4954         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4955                 PCI_ANY_ID, PCI_ANY_ID,
4956                 0,
4957                 0, pbn_pericom_PI7C9X7951 },
4958         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4959                 PCI_ANY_ID, PCI_ANY_ID,
4960                 0,
4961                 0, pbn_pericom_PI7C9X7952 },
4962         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4963                 PCI_ANY_ID, PCI_ANY_ID,
4964                 0,
4965                 0, pbn_pericom_PI7C9X7954 },
4966         {   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4967                 PCI_ANY_ID, PCI_ANY_ID,
4968                 0,
4969                 0, pbn_pericom_PI7C9X7958 },
4970         /*
4971          * ACCES I/O Products quad
4972          */
4973         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4974                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975                 pbn_pericom_PI7C9X7952 },
4976         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978                 pbn_pericom_PI7C9X7952 },
4979         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4980                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981                 pbn_pericom_PI7C9X7954 },
4982         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4983                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984                 pbn_pericom_PI7C9X7954 },
4985         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4986                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987                 pbn_pericom_PI7C9X7952 },
4988         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4989                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990                 pbn_pericom_PI7C9X7952 },
4991         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4992                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993                 pbn_pericom_PI7C9X7954 },
4994         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4995                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996                 pbn_pericom_PI7C9X7954 },
4997         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4998                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999                 pbn_pericom_PI7C9X7952 },
5000         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5001                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002                 pbn_pericom_PI7C9X7952 },
5003         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5004                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005                 pbn_pericom_PI7C9X7954 },
5006         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5007                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008                 pbn_pericom_PI7C9X7954 },
5009         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5010                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011                 pbn_pericom_PI7C9X7951 },
5012         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5013                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014                 pbn_pericom_PI7C9X7952 },
5015         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5016                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5017                 pbn_pericom_PI7C9X7952 },
5018         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5019                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020                 pbn_pericom_PI7C9X7954 },
5021         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5022                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5023                 pbn_pericom_PI7C9X7954 },
5024         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5025                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5026                 pbn_pericom_PI7C9X7952 },
5027         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5028                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5029                 pbn_pericom_PI7C9X7954 },
5030         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5031                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5032                 pbn_pericom_PI7C9X7952 },
5033         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5034                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035                 pbn_pericom_PI7C9X7952 },
5036         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5037                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5038                 pbn_pericom_PI7C9X7954 },
5039         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5040                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5041                 pbn_pericom_PI7C9X7954 },
5042         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5043                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5044                 pbn_pericom_PI7C9X7952 },
5045         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5046                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5047                 pbn_pericom_PI7C9X7954 },
5048         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5049                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050                 pbn_pericom_PI7C9X7954 },
5051         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5052                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053                 pbn_pericom_PI7C9X7958 },
5054         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5055                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5056                 pbn_pericom_PI7C9X7958 },
5057         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5058                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5059                 pbn_pericom_PI7C9X7954 },
5060         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5061                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062                 pbn_pericom_PI7C9X7958 },
5063         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5064                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065                 pbn_pericom_PI7C9X7954 },
5066         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5067                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5068                 pbn_pericom_PI7C9X7958 },
5069         {       PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5070                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5071                 pbn_pericom_PI7C9X7954 },
5072         /*
5073          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5074          */
5075         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5076                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077                 pbn_b0_1_115200 },
5078         /*
5079          * ITE
5080          */
5081         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5082                 PCI_ANY_ID, PCI_ANY_ID,
5083                 0, 0,
5084                 pbn_b1_bt_1_115200 },
5085 
5086         /*
5087          * IntaShield IS-200
5088          */
5089         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5090                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
5091                 pbn_b2_2_115200 },
5092         /*
5093          * IntaShield IS-400
5094          */
5095         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5096                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5097                 pbn_b2_4_115200 },
5098         /*
5099          * BrainBoxes UC-260
5100          */
5101         {       PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5102                 PCI_ANY_ID, PCI_ANY_ID,
5103                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5104                 pbn_b2_4_115200 },
5105         {       PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5106                 PCI_ANY_ID, PCI_ANY_ID,
5107                  PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5108                 pbn_b2_4_115200 },
5109         /*
5110          * Perle PCI-RAS cards
5111          */
5112         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5113                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5114                 0, 0, pbn_b2_4_921600 },
5115         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5116                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5117                 0, 0, pbn_b2_8_921600 },
5118 
5119         /*
5120          * Mainpine series cards: Fairly standard layout but fools
5121          * parts of the autodetect in some cases and uses otherwise
5122          * unmatched communications subclasses in the PCI Express case
5123          */
5124 
5125         {       /* RockForceDUO */
5126                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5127                 PCI_VENDOR_ID_MAINPINE, 0x0200,
5128                 0, 0, pbn_b0_2_115200 },
5129         {       /* RockForceQUATRO */
5130                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5131                 PCI_VENDOR_ID_MAINPINE, 0x0300,
5132                 0, 0, pbn_b0_4_115200 },
5133         {       /* RockForceDUO+ */
5134                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5135                 PCI_VENDOR_ID_MAINPINE, 0x0400,
5136                 0, 0, pbn_b0_2_115200 },
5137         {       /* RockForceQUATRO+ */
5138                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5139                 PCI_VENDOR_ID_MAINPINE, 0x0500,
5140                 0, 0, pbn_b0_4_115200 },
5141         {       /* RockForce+ */
5142                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5143                 PCI_VENDOR_ID_MAINPINE, 0x0600,
5144                 0, 0, pbn_b0_2_115200 },
5145         {       /* RockForce+ */
5146                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5147                 PCI_VENDOR_ID_MAINPINE, 0x0700,
5148                 0, 0, pbn_b0_4_115200 },
5149         {       /* RockForceOCTO+ */
5150                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5151                 PCI_VENDOR_ID_MAINPINE, 0x0800,
5152                 0, 0, pbn_b0_8_115200 },
5153         {       /* RockForceDUO+ */
5154                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5155                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5156                 0, 0, pbn_b0_2_115200 },
5157         {       /* RockForceQUARTRO+ */
5158                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5159                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5160                 0, 0, pbn_b0_4_115200 },
5161         {       /* RockForceOCTO+ */
5162                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5163                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5164                 0, 0, pbn_b0_8_115200 },
5165         {       /* RockForceD1 */
5166                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5167                 PCI_VENDOR_ID_MAINPINE, 0x2000,
5168                 0, 0, pbn_b0_1_115200 },
5169         {       /* RockForceF1 */
5170                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5171                 PCI_VENDOR_ID_MAINPINE, 0x2100,
5172                 0, 0, pbn_b0_1_115200 },
5173         {       /* RockForceD2 */
5174                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5175                 PCI_VENDOR_ID_MAINPINE, 0x2200,
5176                 0, 0, pbn_b0_2_115200 },
5177         {       /* RockForceF2 */
5178                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5179                 PCI_VENDOR_ID_MAINPINE, 0x2300,
5180                 0, 0, pbn_b0_2_115200 },
5181         {       /* RockForceD4 */
5182                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5183                 PCI_VENDOR_ID_MAINPINE, 0x2400,
5184                 0, 0, pbn_b0_4_115200 },
5185         {       /* RockForceF4 */
5186                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5187                 PCI_VENDOR_ID_MAINPINE, 0x2500,
5188                 0, 0, pbn_b0_4_115200 },
5189         {       /* RockForceD8 */
5190                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5191                 PCI_VENDOR_ID_MAINPINE, 0x2600,
5192                 0, 0, pbn_b0_8_115200 },
5193         {       /* RockForceF8 */
5194                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5195                 PCI_VENDOR_ID_MAINPINE, 0x2700,
5196                 0, 0, pbn_b0_8_115200 },
5197         {       /* IQ Express D1 */
5198                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5199                 PCI_VENDOR_ID_MAINPINE, 0x3000,
5200                 0, 0, pbn_b0_1_115200 },
5201         {       /* IQ Express F1 */
5202                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5203                 PCI_VENDOR_ID_MAINPINE, 0x3100,
5204                 0, 0, pbn_b0_1_115200 },
5205         {       /* IQ Express D2 */
5206                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5207                 PCI_VENDOR_ID_MAINPINE, 0x3200,
5208                 0, 0, pbn_b0_2_115200 },
5209         {       /* IQ Express F2 */
5210                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5211                 PCI_VENDOR_ID_MAINPINE, 0x3300,
5212                 0, 0, pbn_b0_2_115200 },
5213         {       /* IQ Express D4 */
5214                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5215                 PCI_VENDOR_ID_MAINPINE, 0x3400,
5216                 0, 0, pbn_b0_4_115200 },
5217         {       /* IQ Express F4 */
5218                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5219                 PCI_VENDOR_ID_MAINPINE, 0x3500,
5220                 0, 0, pbn_b0_4_115200 },
5221         {       /* IQ Express D8 */
5222                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5223                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5224                 0, 0, pbn_b0_8_115200 },
5225         {       /* IQ Express F8 */
5226                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5227                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5228                 0, 0, pbn_b0_8_115200 },
5229 
5230 
5231         /*
5232          * PA Semi PA6T-1682M on-chip UART
5233          */
5234         {       PCI_VENDOR_ID_PASEMI, 0xa004,
5235                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5236                 pbn_pasemi_1682M },
5237 
5238         /*
5239          * National Instruments
5240          */
5241         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5242                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5243                 pbn_b1_16_115200 },
5244         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5245                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5246                 pbn_b1_8_115200 },
5247         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5248                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5249                 pbn_b1_bt_4_115200 },
5250         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5251                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5252                 pbn_b1_bt_2_115200 },
5253         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5255                 pbn_b1_bt_4_115200 },
5256         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5258                 pbn_b1_bt_2_115200 },
5259         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5261                 pbn_b1_16_115200 },
5262         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5264                 pbn_b1_8_115200 },
5265         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267                 pbn_b1_bt_4_115200 },
5268         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270                 pbn_b1_bt_2_115200 },
5271         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273                 pbn_b1_bt_4_115200 },
5274         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5275                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5276                 pbn_b1_bt_2_115200 },
5277         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279                 pbn_ni8430_2 },
5280         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282                 pbn_ni8430_2 },
5283         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285                 pbn_ni8430_4 },
5286         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288                 pbn_ni8430_4 },
5289         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5290                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291                 pbn_ni8430_8 },
5292         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5293                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294                 pbn_ni8430_8 },
5295         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5296                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297                 pbn_ni8430_16 },
5298         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5299                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300                 pbn_ni8430_16 },
5301         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5302                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303                 pbn_ni8430_2 },
5304         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5305                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306                 pbn_ni8430_2 },
5307         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5308                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309                 pbn_ni8430_4 },
5310         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5312                 pbn_ni8430_4 },
5313 
5314         /*
5315          * MOXA
5316          */
5317         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5319                 pbn_moxa8250_2p },
5320         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5322                 pbn_moxa8250_2p },
5323         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5325                 pbn_moxa8250_4p },
5326         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5328                 pbn_moxa8250_4p },
5329         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5331                 pbn_moxa8250_8p },
5332         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5334                 pbn_moxa8250_8p },
5335         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5337                 pbn_moxa8250_8p },
5338         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5340                 pbn_moxa8250_8p },
5341         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5342                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5343                 pbn_moxa8250_2p },
5344         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5346                 pbn_moxa8250_4p },
5347         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5349                 pbn_moxa8250_8p },
5350         {       PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5351                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5352                 pbn_moxa8250_8p },
5353 
5354         /*
5355         * ADDI-DATA GmbH communication cards <info@addi-data.com>
5356         */
5357         {       PCI_VENDOR_ID_ADDIDATA,
5358                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5359                 PCI_ANY_ID,
5360                 PCI_ANY_ID,
5361                 0,
5362                 0,
5363                 pbn_b0_4_115200 },
5364 
5365         {       PCI_VENDOR_ID_ADDIDATA,
5366                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5367                 PCI_ANY_ID,
5368                 PCI_ANY_ID,
5369                 0,
5370                 0,
5371                 pbn_b0_2_115200 },
5372 
5373         {       PCI_VENDOR_ID_ADDIDATA,
5374                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5375                 PCI_ANY_ID,
5376                 PCI_ANY_ID,
5377                 0,
5378                 0,
5379                 pbn_b0_1_115200 },
5380 
5381         {       PCI_VENDOR_ID_AMCC,
5382                 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5383                 PCI_ANY_ID,
5384                 PCI_ANY_ID,
5385                 0,
5386                 0,
5387                 pbn_b1_8_115200 },
5388 
5389         {       PCI_VENDOR_ID_ADDIDATA,
5390                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5391                 PCI_ANY_ID,
5392                 PCI_ANY_ID,
5393                 0,
5394                 0,
5395                 pbn_b0_4_115200 },
5396 
5397         {       PCI_VENDOR_ID_ADDIDATA,
5398                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5399                 PCI_ANY_ID,
5400                 PCI_ANY_ID,
5401                 0,
5402                 0,
5403                 pbn_b0_2_115200 },
5404 
5405         {       PCI_VENDOR_ID_ADDIDATA,
5406                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5407                 PCI_ANY_ID,
5408                 PCI_ANY_ID,
5409                 0,
5410                 0,
5411                 pbn_b0_1_115200 },
5412 
5413         {       PCI_VENDOR_ID_ADDIDATA,
5414                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5415                 PCI_ANY_ID,
5416                 PCI_ANY_ID,
5417                 0,
5418                 0,
5419                 pbn_b0_4_115200 },
5420 
5421         {       PCI_VENDOR_ID_ADDIDATA,
5422                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5423                 PCI_ANY_ID,
5424                 PCI_ANY_ID,
5425                 0,
5426                 0,
5427                 pbn_b0_2_115200 },
5428 
5429         {       PCI_VENDOR_ID_ADDIDATA,
5430                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5431                 PCI_ANY_ID,
5432                 PCI_ANY_ID,
5433                 0,
5434                 0,
5435                 pbn_b0_1_115200 },
5436 
5437         {       PCI_VENDOR_ID_ADDIDATA,
5438                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5439                 PCI_ANY_ID,
5440                 PCI_ANY_ID,
5441                 0,
5442                 0,
5443                 pbn_b0_8_115200 },
5444 
5445         {       PCI_VENDOR_ID_ADDIDATA,
5446                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5447                 PCI_ANY_ID,
5448                 PCI_ANY_ID,
5449                 0,
5450                 0,
5451                 pbn_ADDIDATA_PCIe_4_3906250 },
5452 
5453         {       PCI_VENDOR_ID_ADDIDATA,
5454                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5455                 PCI_ANY_ID,
5456                 PCI_ANY_ID,
5457                 0,
5458                 0,
5459                 pbn_ADDIDATA_PCIe_2_3906250 },
5460 
5461         {       PCI_VENDOR_ID_ADDIDATA,
5462                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5463                 PCI_ANY_ID,
5464                 PCI_ANY_ID,
5465                 0,
5466                 0,
5467                 pbn_ADDIDATA_PCIe_1_3906250 },
5468 
5469         {       PCI_VENDOR_ID_ADDIDATA,
5470                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5471                 PCI_ANY_ID,
5472                 PCI_ANY_ID,
5473                 0,
5474                 0,
5475                 pbn_ADDIDATA_PCIe_8_3906250 },
5476 
5477         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5478                 PCI_VENDOR_ID_IBM, 0x0299,
5479                 0, 0, pbn_b0_bt_2_115200 },
5480 
5481         /*
5482          * other NetMos 9835 devices are most likely handled by the
5483          * parport_serial driver, check drivers/parport/parport_serial.c
5484          * before adding them here.
5485          */
5486 
5487         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5488                 0xA000, 0x1000,
5489                 0, 0, pbn_b0_1_115200 },
5490 
5491         /* the 9901 is a rebranded 9912 */
5492         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5493                 0xA000, 0x1000,
5494                 0, 0, pbn_b0_1_115200 },
5495 
5496         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5497                 0xA000, 0x1000,
5498                 0, 0, pbn_b0_1_115200 },
5499 
5500         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5501                 0xA000, 0x1000,
5502                 0, 0, pbn_b0_1_115200 },
5503 
5504         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5505                 0xA000, 0x1000,
5506                 0, 0, pbn_b0_1_115200 },
5507 
5508         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5509                 0xA000, 0x3002,
5510                 0, 0, pbn_NETMOS9900_2s_115200 },
5511 
5512         /*
5513          * Best Connectivity and Rosewill PCI Multi I/O cards
5514          */
5515 
5516         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5517                 0xA000, 0x1000,
5518                 0, 0, pbn_b0_1_115200 },
5519 
5520         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5521                 0xA000, 0x3002,
5522                 0, 0, pbn_b0_bt_2_115200 },
5523 
5524         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5525                 0xA000, 0x3004,
5526                 0, 0, pbn_b0_bt_4_115200 },
5527         /* Intel CE4100 */
5528         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5529                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5530                 pbn_ce4100_1_115200 },
5531 
5532         /*
5533          * Cronyx Omega PCI
5534          */
5535         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5536                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5537                 pbn_omegapci },
5538 
5539         /*
5540          * Broadcom TruManage
5541          */
5542         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5543                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5544                 pbn_brcm_trumanage },
5545 
5546         /*
5547          * AgeStar as-prs2-009
5548          */
5549         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5550                 PCI_ANY_ID, PCI_ANY_ID,
5551                 0, 0, pbn_b0_bt_2_115200 },
5552 
5553         /*
5554          * WCH CH353 series devices: The 2S1P is handled by parport_serial
5555          * so not listed here.
5556          */
5557         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5558                 PCI_ANY_ID, PCI_ANY_ID,
5559                 0, 0, pbn_b0_bt_4_115200 },
5560 
5561         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5562                 PCI_ANY_ID, PCI_ANY_ID,
5563                 0, 0, pbn_b0_bt_2_115200 },
5564 
5565         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5566                 PCI_ANY_ID, PCI_ANY_ID,
5567                 0, 0, pbn_b0_bt_4_115200 },
5568 
5569         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5570                 PCI_ANY_ID, PCI_ANY_ID,
5571                 0, 0, pbn_wch382_2 },
5572 
5573         {       PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5574                 PCI_ANY_ID, PCI_ANY_ID,
5575                 0, 0, pbn_wch384_4 },
5576 
5577         /* Fintek PCI serial cards */
5578         { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5579         { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5580         { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5581         { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5582         { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5583         { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5584 
5585         /* MKS Tenta SCOM-080x serial cards */
5586         { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5587         { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5588 
5589         /* Amazon PCI serial device */
5590         { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5591 
5592         /*
5593          * These entries match devices with class COMMUNICATION_SERIAL,
5594          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5595          */
5596         {       PCI_ANY_ID, PCI_ANY_ID,
5597                 PCI_ANY_ID, PCI_ANY_ID,
5598                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5599                 0xffff00, pbn_default },
5600         {       PCI_ANY_ID, PCI_ANY_ID,
5601                 PCI_ANY_ID, PCI_ANY_ID,
5602                 PCI_CLASS_COMMUNICATION_MODEM << 8,
5603                 0xffff00, pbn_default },
5604         {       PCI_ANY_ID, PCI_ANY_ID,
5605                 PCI_ANY_ID, PCI_ANY_ID,
5606                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5607                 0xffff00, pbn_default },
5608         { 0, }
5609 };
5610 
5611 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5612                                                 pci_channel_state_t state)
5613 {
5614         struct serial_private *priv = pci_get_drvdata(dev);
5615 
5616         if (state == pci_channel_io_perm_failure)
5617                 return PCI_ERS_RESULT_DISCONNECT;
5618 
5619         if (priv)
5620                 pciserial_detach_ports(priv);
5621 
5622         pci_disable_device(dev);
5623 
5624         return PCI_ERS_RESULT_NEED_RESET;
5625 }
5626 
5627 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5628 {
5629         int rc;
5630 
5631         rc = pci_enable_device(dev);
5632 
5633         if (rc)
5634                 return PCI_ERS_RESULT_DISCONNECT;
5635 
5636         pci_restore_state(dev);
5637         pci_save_state(dev);
5638 
5639         return PCI_ERS_RESULT_RECOVERED;
5640 }
5641 
5642 static void serial8250_io_resume(struct pci_dev *dev)
5643 {
5644         struct serial_private *priv = pci_get_drvdata(dev);
5645         struct serial_private *new;
5646 
5647         if (!priv)
5648                 return;
5649 
5650         new = pciserial_init_ports(dev, priv->board);
5651         if (!IS_ERR(new)) {
5652                 pci_set_drvdata(dev, new);
5653                 kfree(priv);
5654         }
5655 }
5656 
5657 static const struct pci_error_handlers serial8250_err_handler = {
5658         .error_detected = serial8250_io_error_detected,
5659         .slot_reset = serial8250_io_slot_reset,
5660         .resume = serial8250_io_resume,
5661 };
5662 
5663 static struct pci_driver serial_pci_driver = {
5664         .name           = "serial",
5665         .probe          = pciserial_init_one,
5666         .remove         = pciserial_remove_one,
5667         .driver         = {
5668                 .pm     = &pciserial_pm_ops,
5669         },
5670         .id_table       = serial_pci_tbl,
5671         .err_handler    = &serial8250_err_handler,
5672 };
5673 
5674 module_pci_driver(serial_pci_driver);
5675 
5676 MODULE_LICENSE("GPL");
5677 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5678 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/8250/8250_pci.c

DEFINITIONS
