drivers/tty/serial/8250/8250

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This source file includes following definitions.
exar_pm
xr17v35x_get_divisor
xr17v35x_set_divisor
exar_shutdown
default_setup
pci_fastcom335_setup
pci_connect_tech_setup
pci_xr17c154_setup
setup_gpio
__xr17v35x_register_gpio
xr17v35x_register_gpio
generic_rs485_config
iot2040_rs485_config
iot2040_register_gpio
pci_xr17v35x_setup
pci_xr17v35x_exit
exar_misc_clear
exar_misc_handler
exar_pci_probe
exar_pci_remove
exar_suspend
exar_resume
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Probe module for 8250/16550-type Exar chips PCI serial ports.
   4  *
   5  *  Based on drivers/tty/serial/8250/8250_pci.c,
   6  *
   7  *  Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
   8  */
   9 #include <linux/acpi.h>
  10 #include <linux/dmi.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/property.h>
  16 #include <linux/serial_core.h>
  17 #include <linux/serial_reg.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/tty.h>
  21 #include <linux/8250_pci.h>
  22 #include <linux/delay.h>
  23 
  24 #include <asm/byteorder.h>
  25 
  26 #include "8250.h"
  27 
  28 #define PCI_DEVICE_ID_ACCES_COM_2S              0x1052
  29 #define PCI_DEVICE_ID_ACCES_COM_4S              0x105d
  30 #define PCI_DEVICE_ID_ACCES_COM_8S              0x106c
  31 #define PCI_DEVICE_ID_ACCES_COM232_8            0x10a8
  32 #define PCI_DEVICE_ID_ACCES_COM_2SM             0x10d2
  33 #define PCI_DEVICE_ID_ACCES_COM_4SM             0x10db
  34 #define PCI_DEVICE_ID_ACCES_COM_8SM             0x10ea
  35 
  36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335       0x0002
  37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335       0x0004
  38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335       0x000a
  39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335       0x000b
  40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE         0x0020
  41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE         0x0021
  42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE         0x0022
  43 #define PCI_DEVICE_ID_EXAR_XR17V4358            0x4358
  44 #define PCI_DEVICE_ID_EXAR_XR17V8358            0x8358
  45 
  46 #define UART_EXAR_INT0          0x80
  47 #define UART_EXAR_8XMODE        0x88    /* 8X sampling rate select */
  48 #define UART_EXAR_SLEEP         0x8b    /* Sleep mode */
  49 #define UART_EXAR_DVID          0x8d    /* Device identification */
  50 
  51 #define UART_EXAR_FCTR          0x08    /* Feature Control Register */
  52 #define UART_FCTR_EXAR_IRDA     0x10    /* IrDa data encode select */
  53 #define UART_FCTR_EXAR_485      0x20    /* Auto 485 half duplex dir ctl */
  54 #define UART_FCTR_EXAR_TRGA     0x00    /* FIFO trigger table A */
  55 #define UART_FCTR_EXAR_TRGB     0x60    /* FIFO trigger table B */
  56 #define UART_FCTR_EXAR_TRGC     0x80    /* FIFO trigger table C */
  57 #define UART_FCTR_EXAR_TRGD     0xc0    /* FIFO trigger table D programmable */
  58 
  59 #define UART_EXAR_TXTRG         0x0a    /* Tx FIFO trigger level write-only */
  60 #define UART_EXAR_RXTRG         0x0b    /* Rx FIFO trigger level write-only */
  61 
  62 #define UART_EXAR_MPIOINT_7_0   0x8f    /* MPIOINT[7:0] */
  63 #define UART_EXAR_MPIOLVL_7_0   0x90    /* MPIOLVL[7:0] */
  64 #define UART_EXAR_MPIO3T_7_0    0x91    /* MPIO3T[7:0] */
  65 #define UART_EXAR_MPIOINV_7_0   0x92    /* MPIOINV[7:0] */
  66 #define UART_EXAR_MPIOSEL_7_0   0x93    /* MPIOSEL[7:0] */
  67 #define UART_EXAR_MPIOOD_7_0    0x94    /* MPIOOD[7:0] */
  68 #define UART_EXAR_MPIOINT_15_8  0x95    /* MPIOINT[15:8] */
  69 #define UART_EXAR_MPIOLVL_15_8  0x96    /* MPIOLVL[15:8] */
  70 #define UART_EXAR_MPIO3T_15_8   0x97    /* MPIO3T[15:8] */
  71 #define UART_EXAR_MPIOINV_15_8  0x98    /* MPIOINV[15:8] */
  72 #define UART_EXAR_MPIOSEL_15_8  0x99    /* MPIOSEL[15:8] */
  73 #define UART_EXAR_MPIOOD_15_8   0x9a    /* MPIOOD[15:8] */
  74 
  75 #define UART_EXAR_RS485_DLY(x)  ((x) << 4)
  76 
  77 /*
  78  * IOT2040 MPIO wiring semantics:
  79  *
  80  * MPIO         Port    Function
  81  * ----         ----    --------
  82  * 0            2       Mode bit 0
  83  * 1            2       Mode bit 1
  84  * 2            2       Terminate bus
  85  * 3            -       <reserved>
  86  * 4            3       Mode bit 0
  87  * 5            3       Mode bit 1
  88  * 6            3       Terminate bus
  89  * 7            -       <reserved>
  90  * 8            2       Enable
  91  * 9            3       Enable
  92  * 10           -       Red LED
  93  * 11..15       -       <unused>
  94  */
  95 
  96 /* IOT2040 MPIOs 0..7 */
  97 #define IOT2040_UART_MODE_RS232         0x01
  98 #define IOT2040_UART_MODE_RS485         0x02
  99 #define IOT2040_UART_MODE_RS422         0x03
 100 #define IOT2040_UART_TERMINATE_BUS      0x04
 101 
 102 #define IOT2040_UART1_MASK              0x0f
 103 #define IOT2040_UART2_SHIFT             4
 104 
 105 #define IOT2040_UARTS_DEFAULT_MODE      0x11    /* both RS232 */
 106 #define IOT2040_UARTS_GPIO_LO_MODE      0x88    /* reserved pins as input */
 107 
 108 /* IOT2040 MPIOs 8..15 */
 109 #define IOT2040_UARTS_ENABLE            0x03
 110 #define IOT2040_UARTS_GPIO_HI_MODE      0xF8    /* enable & LED as outputs */
 111 
 112 struct exar8250;
 113 
 114 struct exar8250_platform {
 115         int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
 116         int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
 117 };
 118 
 119 /**
 120  * struct exar8250_board - board information
 121  * @num_ports: number of serial ports
 122  * @reg_shift: describes UART register mapping in PCI memory
 123  * @setup: quirk run at ->probe() stage
 124  * @exit: quirk run at ->remove() stage
 125  */
 126 struct exar8250_board {
 127         unsigned int num_ports;
 128         unsigned int reg_shift;
 129         int     (*setup)(struct exar8250 *, struct pci_dev *,
 130                          struct uart_8250_port *, int);
 131         void    (*exit)(struct pci_dev *pcidev);
 132 };
 133 
 134 struct exar8250 {
 135         unsigned int            nr;
 136         struct exar8250_board   *board;
 137         void __iomem            *virt;
 138         int                     line[0];
 139 };
 140 
 141 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
 142 {
 143         /*
 144          * Exar UARTs have a SLEEP register that enables or disables each UART
 145          * to enter sleep mode separately. On the XR17V35x the register
 146          * is accessible to each UART at the UART_EXAR_SLEEP offset, but
 147          * the UART channel may only write to the corresponding bit.
 148          */
 149         serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
 150 }
 151 
 152 /*
 153  * XR17V35x UARTs have an extra fractional divisor register (DLD)
 154  * Calculate divisor with extra 4-bit fractional portion
 155  */
 156 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
 157                                          unsigned int *frac)
 158 {
 159         unsigned int quot_16;
 160 
 161         quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
 162         *frac = quot_16 & 0x0f;
 163 
 164         return quot_16 >> 4;
 165 }
 166 
 167 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
 168                                  unsigned int quot, unsigned int quot_frac)
 169 {
 170         serial8250_do_set_divisor(p, baud, quot, quot_frac);
 171 
 172         /* Preserve bits not related to baudrate; DLD[7:4]. */
 173         quot_frac |= serial_port_in(p, 0x2) & 0xf0;
 174         serial_port_out(p, 0x2, quot_frac);
 175 }
 176 
 177 static void exar_shutdown(struct uart_port *port)
 178 {
 179         unsigned char lsr;
 180         bool tx_complete = 0;
 181         struct uart_8250_port *up = up_to_u8250p(port);
 182         struct circ_buf *xmit = &port->state->xmit;
 183         int i = 0;
 184 
 185         do {
 186                 lsr = serial_in(up, UART_LSR);
 187                 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
 188                         tx_complete = 1;
 189                 else
 190                         tx_complete = 0;
 191                 usleep_range(1000, 1100);
 192         } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
 193 
 194         serial8250_do_shutdown(port);
 195 }
 196 
 197 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 198                          int idx, unsigned int offset,
 199                          struct uart_8250_port *port)
 200 {
 201         const struct exar8250_board *board = priv->board;
 202         unsigned int bar = 0;
 203         unsigned char status;
 204 
 205         port->port.iotype = UPIO_MEM;
 206         port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
 207         port->port.membase = priv->virt + offset;
 208         port->port.regshift = board->reg_shift;
 209 
 210         /*
 211          * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
 212          * with when DLAB is set which will cause the device to incorrectly match
 213          * and assign port type to PORT_16650. The EFR for this UART is found
 214          * at offset 0x09. Instead check the Deice ID (DVID) register
 215          * for a 2, 4 or 8 port UART.
 216          */
 217         status = readb(port->port.membase + UART_EXAR_DVID);
 218         if (status == 0x82 || status == 0x84 || status == 0x88) {
 219                 port->port.type = PORT_XR17V35X;
 220 
 221                 port->port.get_divisor = xr17v35x_get_divisor;
 222                 port->port.set_divisor = xr17v35x_set_divisor;
 223         } else {
 224                 port->port.type = PORT_XR17D15X;
 225         }
 226 
 227         port->port.pm = exar_pm;
 228         port->port.shutdown = exar_shutdown;
 229 
 230         return 0;
 231 }
 232 
 233 static int
 234 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 235                      struct uart_8250_port *port, int idx)
 236 {
 237         unsigned int offset = idx * 0x200;
 238         unsigned int baud = 1843200;
 239         u8 __iomem *p;
 240         int err;
 241 
 242         port->port.uartclk = baud * 16;
 243 
 244         err = default_setup(priv, pcidev, idx, offset, port);
 245         if (err)
 246                 return err;
 247 
 248         p = port->port.membase;
 249 
 250         writeb(0x00, p + UART_EXAR_8XMODE);
 251         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
 252         writeb(32, p + UART_EXAR_TXTRG);
 253         writeb(32, p + UART_EXAR_RXTRG);
 254 
 255         /*
 256          * Setup Multipurpose Input/Output pins.
 257          */
 258         if (idx == 0) {
 259                 switch (pcidev->device) {
 260                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
 261                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
 262                         writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
 263                         writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
 264                         writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
 265                         break;
 266                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
 267                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
 268                         writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
 269                         writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
 270                         writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
 271                         break;
 272                 }
 273                 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
 274                 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
 275                 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
 276         }
 277 
 278         return 0;
 279 }
 280 
 281 static int
 282 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 283                        struct uart_8250_port *port, int idx)
 284 {
 285         unsigned int offset = idx * 0x200;
 286         unsigned int baud = 1843200;
 287 
 288         port->port.uartclk = baud * 16;
 289         return default_setup(priv, pcidev, idx, offset, port);
 290 }
 291 
 292 static int
 293 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 294                    struct uart_8250_port *port, int idx)
 295 {
 296         unsigned int offset = idx * 0x200;
 297         unsigned int baud = 921600;
 298 
 299         port->port.uartclk = baud * 16;
 300         return default_setup(priv, pcidev, idx, offset, port);
 301 }
 302 
 303 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
 304 {
 305         /*
 306          * The Commtech adapters required the MPIOs to be driven low. The Exar
 307          * devices will export them as GPIOs, so we pre-configure them safely
 308          * as inputs.
 309          */
 310         u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;
 311 
 312         writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
 313         writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
 314         writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
 315         writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
 316         writeb(dir,  p + UART_EXAR_MPIOSEL_7_0);
 317         writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
 318         writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
 319         writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
 320         writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
 321         writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
 322         writeb(dir,  p + UART_EXAR_MPIOSEL_15_8);
 323         writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
 324 }
 325 
 326 static void *
 327 __xr17v35x_register_gpio(struct pci_dev *pcidev,
 328                          const struct property_entry *properties)
 329 {
 330         struct platform_device *pdev;
 331 
 332         pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
 333         if (!pdev)
 334                 return NULL;
 335 
 336         pdev->dev.parent = &pcidev->dev;
 337         ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
 338 
 339         if (platform_device_add_properties(pdev, properties) < 0 ||
 340             platform_device_add(pdev) < 0) {
 341                 platform_device_put(pdev);
 342                 return NULL;
 343         }
 344 
 345         return pdev;
 346 }
 347 
 348 static const struct property_entry exar_gpio_properties[] = {
 349         PROPERTY_ENTRY_U32("exar,first-pin", 0),
 350         PROPERTY_ENTRY_U32("ngpios", 16),
 351         { }
 352 };
 353 
 354 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
 355                                   struct uart_8250_port *port)
 356 {
 357         if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
 358                 port->port.private_data =
 359                         __xr17v35x_register_gpio(pcidev, exar_gpio_properties);
 360 
 361         return 0;
 362 }
 363 
 364 static int generic_rs485_config(struct uart_port *port,
 365                                 struct serial_rs485 *rs485)
 366 {
 367         bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
 368         u8 __iomem *p = port->membase;
 369         u8 value;
 370 
 371         value = readb(p + UART_EXAR_FCTR);
 372         if (is_rs485)
 373                 value |= UART_FCTR_EXAR_485;
 374         else
 375                 value &= ~UART_FCTR_EXAR_485;
 376 
 377         writeb(value, p + UART_EXAR_FCTR);
 378 
 379         if (is_rs485)
 380                 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
 381 
 382         port->rs485 = *rs485;
 383 
 384         return 0;
 385 }
 386 
 387 static const struct exar8250_platform exar8250_default_platform = {
 388         .register_gpio = xr17v35x_register_gpio,
 389         .rs485_config = generic_rs485_config,
 390 };
 391 
 392 static int iot2040_rs485_config(struct uart_port *port,
 393                                 struct serial_rs485 *rs485)
 394 {
 395         bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
 396         u8 __iomem *p = port->membase;
 397         u8 mask = IOT2040_UART1_MASK;
 398         u8 mode, value;
 399 
 400         if (is_rs485) {
 401                 if (rs485->flags & SER_RS485_RX_DURING_TX)
 402                         mode = IOT2040_UART_MODE_RS422;
 403                 else
 404                         mode = IOT2040_UART_MODE_RS485;
 405 
 406                 if (rs485->flags & SER_RS485_TERMINATE_BUS)
 407                         mode |= IOT2040_UART_TERMINATE_BUS;
 408         } else {
 409                 mode = IOT2040_UART_MODE_RS232;
 410         }
 411 
 412         if (port->line == 3) {
 413                 mask <<= IOT2040_UART2_SHIFT;
 414                 mode <<= IOT2040_UART2_SHIFT;
 415         }
 416 
 417         value = readb(p + UART_EXAR_MPIOLVL_7_0);
 418         value &= ~mask;
 419         value |= mode;
 420         writeb(value, p + UART_EXAR_MPIOLVL_7_0);
 421 
 422         return generic_rs485_config(port, rs485);
 423 }
 424 
 425 static const struct property_entry iot2040_gpio_properties[] = {
 426         PROPERTY_ENTRY_U32("exar,first-pin", 10),
 427         PROPERTY_ENTRY_U32("ngpios", 1),
 428         { }
 429 };
 430 
 431 static int iot2040_register_gpio(struct pci_dev *pcidev,
 432                               struct uart_8250_port *port)
 433 {
 434         u8 __iomem *p = port->port.membase;
 435 
 436         writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
 437         writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
 438         writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
 439         writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
 440 
 441         port->port.private_data =
 442                 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
 443 
 444         return 0;
 445 }
 446 
 447 static const struct exar8250_platform iot2040_platform = {
 448         .rs485_config = iot2040_rs485_config,
 449         .register_gpio = iot2040_register_gpio,
 450 };
 451 
 452 /*
 453  * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
 454  * IOT2020 doesn't have. Therefore it is sufficient to match on the common
 455  * board name after the device was found.
 456  */
 457 static const struct dmi_system_id exar_platforms[] = {
 458         {
 459                 .matches = {
 460                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
 461                 },
 462                 .driver_data = (void *)&iot2040_platform,
 463         },
 464         {}
 465 };
 466 
 467 static int
 468 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 469                    struct uart_8250_port *port, int idx)
 470 {
 471         const struct exar8250_platform *platform;
 472         const struct dmi_system_id *dmi_match;
 473         unsigned int offset = idx * 0x400;
 474         unsigned int baud = 7812500;
 475         u8 __iomem *p;
 476         int ret;
 477 
 478         dmi_match = dmi_first_match(exar_platforms);
 479         if (dmi_match)
 480                 platform = dmi_match->driver_data;
 481         else
 482                 platform = &exar8250_default_platform;
 483 
 484         port->port.uartclk = baud * 16;
 485         port->port.rs485_config = platform->rs485_config;
 486 
 487         /*
 488          * Setup the UART clock for the devices on expansion slot to
 489          * half the clock speed of the main chip (which is 125MHz)
 490          */
 491         if (idx >= 8)
 492                 port->port.uartclk /= 2;
 493 
 494         ret = default_setup(priv, pcidev, idx, offset, port);
 495         if (ret)
 496                 return ret;
 497 
 498         p = port->port.membase;
 499 
 500         writeb(0x00, p + UART_EXAR_8XMODE);
 501         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
 502         writeb(128, p + UART_EXAR_TXTRG);
 503         writeb(128, p + UART_EXAR_RXTRG);
 504 
 505         if (idx == 0) {
 506                 /* Setup Multipurpose Input/Output pins. */
 507                 setup_gpio(pcidev, p);
 508 
 509                 ret = platform->register_gpio(pcidev, port);
 510         }
 511 
 512         return ret;
 513 }
 514 
 515 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
 516 {
 517         struct exar8250 *priv = pci_get_drvdata(pcidev);
 518         struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
 519         struct platform_device *pdev = port->port.private_data;
 520 
 521         platform_device_unregister(pdev);
 522         port->port.private_data = NULL;
 523 }
 524 
 525 static inline void exar_misc_clear(struct exar8250 *priv)
 526 {
 527         /* Clear all PCI interrupts by reading INT0. No effect on IIR */
 528         readb(priv->virt + UART_EXAR_INT0);
 529 
 530         /* Clear INT0 for Expansion Interface slave ports, too */
 531         if (priv->board->num_ports > 8)
 532                 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
 533 }
 534 
 535 /*
 536  * These Exar UARTs have an extra interrupt indicator that could fire for a
 537  * few interrupts that are not presented/cleared through IIR.  One of which is
 538  * a wakeup interrupt when coming out of sleep.  These interrupts are only
 539  * cleared by reading global INT0 or INT1 registers as interrupts are
 540  * associated with channel 0. The INT[3:0] registers _are_ accessible from each
 541  * channel's address space, but for the sake of bus efficiency we register a
 542  * dedicated handler at the PCI device level to handle them.
 543  */
 544 static irqreturn_t exar_misc_handler(int irq, void *data)
 545 {
 546         exar_misc_clear(data);
 547 
 548         return IRQ_HANDLED;
 549 }
 550 
 551 static int
 552 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
 553 {
 554         unsigned int nr_ports, i, bar = 0, maxnr;
 555         struct exar8250_board *board;
 556         struct uart_8250_port uart;
 557         struct exar8250 *priv;
 558         int rc;
 559 
 560         board = (struct exar8250_board *)ent->driver_data;
 561         if (!board)
 562                 return -EINVAL;
 563 
 564         rc = pcim_enable_device(pcidev);
 565         if (rc)
 566                 return rc;
 567 
 568         maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
 569 
 570         nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
 571 
 572         priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
 573         if (!priv)
 574                 return -ENOMEM;
 575 
 576         priv->board = board;
 577         priv->virt = pcim_iomap(pcidev, bar, 0);
 578         if (!priv->virt)
 579                 return -ENOMEM;
 580 
 581         pci_set_master(pcidev);
 582 
 583         rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
 584         if (rc < 0)
 585                 return rc;
 586 
 587         memset(&uart, 0, sizeof(uart));
 588         uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
 589         uart.port.irq = pci_irq_vector(pcidev, 0);
 590         uart.port.dev = &pcidev->dev;
 591 
 592         rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
 593                          IRQF_SHARED, "exar_uart", priv);
 594         if (rc)
 595                 return rc;
 596 
 597         /* Clear interrupts */
 598         exar_misc_clear(priv);
 599 
 600         for (i = 0; i < nr_ports && i < maxnr; i++) {
 601                 rc = board->setup(priv, pcidev, &uart, i);
 602                 if (rc) {
 603                         dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
 604                         break;
 605                 }
 606 
 607                 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
 608                         uart.port.iobase, uart.port.irq, uart.port.iotype);
 609 
 610                 priv->line[i] = serial8250_register_8250_port(&uart);
 611                 if (priv->line[i] < 0) {
 612                         dev_err(&pcidev->dev,
 613                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
 614                                 uart.port.iobase, uart.port.irq,
 615                                 uart.port.iotype, priv->line[i]);
 616                         break;
 617                 }
 618         }
 619         priv->nr = i;
 620         pci_set_drvdata(pcidev, priv);
 621         return 0;
 622 }
 623 
 624 static void exar_pci_remove(struct pci_dev *pcidev)
 625 {
 626         struct exar8250 *priv = pci_get_drvdata(pcidev);
 627         unsigned int i;
 628 
 629         for (i = 0; i < priv->nr; i++)
 630                 serial8250_unregister_port(priv->line[i]);
 631 
 632         if (priv->board->exit)
 633                 priv->board->exit(pcidev);
 634 }
 635 
 636 static int __maybe_unused exar_suspend(struct device *dev)
 637 {
 638         struct pci_dev *pcidev = to_pci_dev(dev);
 639         struct exar8250 *priv = pci_get_drvdata(pcidev);
 640         unsigned int i;
 641 
 642         for (i = 0; i < priv->nr; i++)
 643                 if (priv->line[i] >= 0)
 644                         serial8250_suspend_port(priv->line[i]);
 645 
 646         /* Ensure that every init quirk is properly torn down */
 647         if (priv->board->exit)
 648                 priv->board->exit(pcidev);
 649 
 650         return 0;
 651 }
 652 
 653 static int __maybe_unused exar_resume(struct device *dev)
 654 {
 655         struct exar8250 *priv = dev_get_drvdata(dev);
 656         unsigned int i;
 657 
 658         exar_misc_clear(priv);
 659 
 660         for (i = 0; i < priv->nr; i++)
 661                 if (priv->line[i] >= 0)
 662                         serial8250_resume_port(priv->line[i]);
 663 
 664         return 0;
 665 }
 666 
 667 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
 668 
 669 static const struct exar8250_board acces_com_2x = {
 670         .num_ports      = 2,
 671         .setup          = pci_xr17c154_setup,
 672 };
 673 
 674 static const struct exar8250_board acces_com_4x = {
 675         .num_ports      = 4,
 676         .setup          = pci_xr17c154_setup,
 677 };
 678 
 679 static const struct exar8250_board acces_com_8x = {
 680         .num_ports      = 8,
 681         .setup          = pci_xr17c154_setup,
 682 };
 683 
 684 
 685 static const struct exar8250_board pbn_fastcom335_2 = {
 686         .num_ports      = 2,
 687         .setup          = pci_fastcom335_setup,
 688 };
 689 
 690 static const struct exar8250_board pbn_fastcom335_4 = {
 691         .num_ports      = 4,
 692         .setup          = pci_fastcom335_setup,
 693 };
 694 
 695 static const struct exar8250_board pbn_fastcom335_8 = {
 696         .num_ports      = 8,
 697         .setup          = pci_fastcom335_setup,
 698 };
 699 
 700 static const struct exar8250_board pbn_connect = {
 701         .setup          = pci_connect_tech_setup,
 702 };
 703 
 704 static const struct exar8250_board pbn_exar_ibm_saturn = {
 705         .num_ports      = 1,
 706         .setup          = pci_xr17c154_setup,
 707 };
 708 
 709 static const struct exar8250_board pbn_exar_XR17C15x = {
 710         .setup          = pci_xr17c154_setup,
 711 };
 712 
 713 static const struct exar8250_board pbn_exar_XR17V35x = {
 714         .setup          = pci_xr17v35x_setup,
 715         .exit           = pci_xr17v35x_exit,
 716 };
 717 
 718 static const struct exar8250_board pbn_exar_XR17V4358 = {
 719         .num_ports      = 12,
 720         .setup          = pci_xr17v35x_setup,
 721         .exit           = pci_xr17v35x_exit,
 722 };
 723 
 724 static const struct exar8250_board pbn_exar_XR17V8358 = {
 725         .num_ports      = 16,
 726         .setup          = pci_xr17v35x_setup,
 727         .exit           = pci_xr17v35x_exit,
 728 };
 729 
 730 #define CONNECT_DEVICE(devid, sdevid, bd) {                             \
 731         PCI_DEVICE_SUB(                                                 \
 732                 PCI_VENDOR_ID_EXAR,                                     \
 733                 PCI_DEVICE_ID_EXAR_##devid,                             \
 734                 PCI_SUBVENDOR_ID_CONNECT_TECH,                          \
 735                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0,      \
 736                 (kernel_ulong_t)&bd                                     \
 737         }
 738 
 739 #define EXAR_DEVICE(vend, devid, bd) {                                  \
 740         PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd   \
 741         }
 742 
 743 #define IBM_DEVICE(devid, sdevid, bd) {                 \
 744         PCI_DEVICE_SUB(                                 \
 745                 PCI_VENDOR_ID_EXAR,                     \
 746                 PCI_DEVICE_ID_EXAR_##devid,             \
 747                 PCI_VENDOR_ID_IBM,                      \
 748                 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0,   \
 749                 (kernel_ulong_t)&bd                     \
 750         }
 751 
 752 static const struct pci_device_id exar_pci_tbl[] = {
 753         EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x),
 754         EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x),
 755         EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x),
 756         EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x),
 757         EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x),
 758         EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x),
 759         EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x),
 760 
 761 
 762         CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
 763         CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
 764         CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
 765         CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
 766         CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
 767         CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
 768         CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
 769         CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
 770         CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
 771         CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
 772         CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
 773         CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
 774 
 775         IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
 776 
 777         /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
 778         EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
 779         EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
 780         EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
 781 
 782         /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
 783         EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
 784         EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
 785         EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
 786         EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
 787         EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
 788         EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x),
 789         EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x),
 790         EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x),
 791 
 792         EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
 793         EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
 794         EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
 795         EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
 796         { 0, }
 797 };
 798 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
 799 
 800 static struct pci_driver exar_pci_driver = {
 801         .name           = "exar_serial",
 802         .probe          = exar_pci_probe,
 803         .remove         = exar_pci_remove,
 804         .driver         = {
 805                 .pm     = &exar_pci_pm,
 806         },
 807         .id_table       = exar_pci_tbl,
 808 };
 809 module_pci_driver(exar_pci_driver);
 810 
 811 MODULE_LICENSE("GPL");
 812 MODULE_DESCRIPTION("Exar Serial Driver");
 813 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
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root/drivers/tty/serial/8250/8250_exar.c

DEFINITIONS
