drivers/tty/serial/8250/8250

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This source file includes following definitions.
to_dw8250_data
dw8250_modify_msr
dw8250_force_idle
dw8250_check_lcr
dw8250_tx_wait_empty
dw8250_serial_out38x
dw8250_serial_out
dw8250_serial_in
dw8250_serial_inq
dw8250_serial_outq
dw8250_serial_out32
dw8250_serial_in32
dw8250_serial_out32be
dw8250_serial_in32be
dw8250_handle_irq
dw8250_do_pm
dw8250_set_termios
dw8250_set_ldisc
dw8250_fallback_dma_filter
dw8250_idma_filter
dw8250_quirks
dw8250_probe
dw8250_remove
dw8250_suspend
dw8250_resume
dw8250_runtime_suspend
dw8250_runtime_resume
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Synopsys DesignWare 8250 driver.
   4  *
   5  * Copyright 2011 Picochip, Jamie Iles.
   6  * Copyright 2013 Intel Corporation
   7  *
   8  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
   9  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  10  * raised, the LCR needs to be rewritten and the uart status register read.
  11  */
  12 #include <linux/delay.h>
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/serial_8250.h>
  17 #include <linux/serial_reg.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/acpi.h>
  24 #include <linux/clk.h>
  25 #include <linux/reset.h>
  26 #include <linux/pm_runtime.h>
  27 
  28 #include <asm/byteorder.h>
  29 
  30 #include "8250_dwlib.h"
  31 
  32 /* Offsets for the DesignWare specific registers */
  33 #define DW_UART_USR     0x1f /* UART Status Register */
  34 
  35 /* DesignWare specific register fields */
  36 #define DW_UART_MCR_SIRE                BIT(6)
  37 
  38 struct dw8250_data {
  39         struct dw8250_port_data data;
  40 
  41         u8                      usr_reg;
  42         int                     msr_mask_on;
  43         int                     msr_mask_off;
  44         struct clk              *clk;
  45         struct clk              *pclk;
  46         struct reset_control    *rst;
  47 
  48         unsigned int            skip_autocfg:1;
  49         unsigned int            uart_16550_compatible:1;
  50 };
  51 
  52 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
  53 {
  54         return container_of(data, struct dw8250_data, data);
  55 }
  56 
  57 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
  58 {
  59         struct dw8250_data *d = to_dw8250_data(p->private_data);
  60 
  61         /* Override any modem control signals if needed */
  62         if (offset == UART_MSR) {
  63                 value |= d->msr_mask_on;
  64                 value &= ~d->msr_mask_off;
  65         }
  66 
  67         return value;
  68 }
  69 
  70 static void dw8250_force_idle(struct uart_port *p)
  71 {
  72         struct uart_8250_port *up = up_to_u8250p(p);
  73 
  74         serial8250_clear_and_reinit_fifos(up);
  75         (void)p->serial_in(p, UART_RX);
  76 }
  77 
  78 static void dw8250_check_lcr(struct uart_port *p, int value)
  79 {
  80         void __iomem *offset = p->membase + (UART_LCR << p->regshift);
  81         int tries = 1000;
  82 
  83         /* Make sure LCR write wasn't ignored */
  84         while (tries--) {
  85                 unsigned int lcr = p->serial_in(p, UART_LCR);
  86 
  87                 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
  88                         return;
  89 
  90                 dw8250_force_idle(p);
  91 
  92 #ifdef CONFIG_64BIT
  93                 if (p->type == PORT_OCTEON)
  94                         __raw_writeq(value & 0xff, offset);
  95                 else
  96 #endif
  97                 if (p->iotype == UPIO_MEM32)
  98                         writel(value, offset);
  99                 else if (p->iotype == UPIO_MEM32BE)
 100                         iowrite32be(value, offset);
 101                 else
 102                         writeb(value, offset);
 103         }
 104         /*
 105          * FIXME: this deadlocks if port->lock is already held
 106          * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 107          */
 108 }
 109 
 110 /* Returns once the transmitter is empty or we run out of retries */
 111 static void dw8250_tx_wait_empty(struct uart_port *p)
 112 {
 113         unsigned int tries = 20000;
 114         unsigned int delay_threshold = tries - 1000;
 115         unsigned int lsr;
 116 
 117         while (tries--) {
 118                 lsr = readb (p->membase + (UART_LSR << p->regshift));
 119                 if (lsr & UART_LSR_TEMT)
 120                         break;
 121 
 122                 /* The device is first given a chance to empty without delay,
 123                  * to avoid slowdowns at high bitrates. If after 1000 tries
 124                  * the buffer has still not emptied, allow more time for low-
 125                  * speed links. */
 126                 if (tries < delay_threshold)
 127                         udelay (1);
 128         }
 129 }
 130 
 131 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
 132 {
 133         struct dw8250_data *d = to_dw8250_data(p->private_data);
 134 
 135         /* Allow the TX to drain before we reconfigure */
 136         if (offset == UART_LCR)
 137                 dw8250_tx_wait_empty(p);
 138 
 139         writeb(value, p->membase + (offset << p->regshift));
 140 
 141         if (offset == UART_LCR && !d->uart_16550_compatible)
 142                 dw8250_check_lcr(p, value);
 143 }
 144 
 145 
 146 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
 147 {
 148         struct dw8250_data *d = to_dw8250_data(p->private_data);
 149 
 150         writeb(value, p->membase + (offset << p->regshift));
 151 
 152         if (offset == UART_LCR && !d->uart_16550_compatible)
 153                 dw8250_check_lcr(p, value);
 154 }
 155 
 156 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
 157 {
 158         unsigned int value = readb(p->membase + (offset << p->regshift));
 159 
 160         return dw8250_modify_msr(p, offset, value);
 161 }
 162 
 163 #ifdef CONFIG_64BIT
 164 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
 165 {
 166         unsigned int value;
 167 
 168         value = (u8)__raw_readq(p->membase + (offset << p->regshift));
 169 
 170         return dw8250_modify_msr(p, offset, value);
 171 }
 172 
 173 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
 174 {
 175         struct dw8250_data *d = to_dw8250_data(p->private_data);
 176 
 177         value &= 0xff;
 178         __raw_writeq(value, p->membase + (offset << p->regshift));
 179         /* Read back to ensure register write ordering. */
 180         __raw_readq(p->membase + (UART_LCR << p->regshift));
 181 
 182         if (offset == UART_LCR && !d->uart_16550_compatible)
 183                 dw8250_check_lcr(p, value);
 184 }
 185 #endif /* CONFIG_64BIT */
 186 
 187 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 188 {
 189         struct dw8250_data *d = to_dw8250_data(p->private_data);
 190 
 191         writel(value, p->membase + (offset << p->regshift));
 192 
 193         if (offset == UART_LCR && !d->uart_16550_compatible)
 194                 dw8250_check_lcr(p, value);
 195 }
 196 
 197 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
 198 {
 199         unsigned int value = readl(p->membase + (offset << p->regshift));
 200 
 201         return dw8250_modify_msr(p, offset, value);
 202 }
 203 
 204 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
 205 {
 206         struct dw8250_data *d = to_dw8250_data(p->private_data);
 207 
 208         iowrite32be(value, p->membase + (offset << p->regshift));
 209 
 210         if (offset == UART_LCR && !d->uart_16550_compatible)
 211                 dw8250_check_lcr(p, value);
 212 }
 213 
 214 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
 215 {
 216        unsigned int value = ioread32be(p->membase + (offset << p->regshift));
 217 
 218        return dw8250_modify_msr(p, offset, value);
 219 }
 220 
 221 
 222 static int dw8250_handle_irq(struct uart_port *p)
 223 {
 224         struct uart_8250_port *up = up_to_u8250p(p);
 225         struct dw8250_data *d = to_dw8250_data(p->private_data);
 226         unsigned int iir = p->serial_in(p, UART_IIR);
 227         unsigned int status;
 228         unsigned long flags;
 229 
 230         /*
 231          * There are ways to get Designware-based UARTs into a state where
 232          * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
 233          * data available.  If we see such a case then we'll do a bogus
 234          * read.  If we don't do this then the "RX TIMEOUT" interrupt will
 235          * fire forever.
 236          *
 237          * This problem has only been observed so far when not in DMA mode
 238          * so we limit the workaround only to non-DMA mode.
 239          */
 240         if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
 241                 spin_lock_irqsave(&p->lock, flags);
 242                 status = p->serial_in(p, UART_LSR);
 243 
 244                 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
 245                         (void) p->serial_in(p, UART_RX);
 246 
 247                 spin_unlock_irqrestore(&p->lock, flags);
 248         }
 249 
 250         if (serial8250_handle_irq(p, iir))
 251                 return 1;
 252 
 253         if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 254                 /* Clear the USR */
 255                 (void)p->serial_in(p, d->usr_reg);
 256 
 257                 return 1;
 258         }
 259 
 260         return 0;
 261 }
 262 
 263 static void
 264 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 265 {
 266         if (!state)
 267                 pm_runtime_get_sync(port->dev);
 268 
 269         serial8250_do_pm(port, state, old);
 270 
 271         if (state)
 272                 pm_runtime_put_sync_suspend(port->dev);
 273 }
 274 
 275 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
 276                                struct ktermios *old)
 277 {
 278         unsigned int baud = tty_termios_baud_rate(termios);
 279         struct dw8250_data *d = to_dw8250_data(p->private_data);
 280         long rate;
 281         int ret;
 282 
 283         if (IS_ERR(d->clk))
 284                 goto out;
 285 
 286         clk_disable_unprepare(d->clk);
 287         rate = clk_round_rate(d->clk, baud * 16);
 288         if (rate < 0)
 289                 ret = rate;
 290         else if (rate == 0)
 291                 ret = -ENOENT;
 292         else
 293                 ret = clk_set_rate(d->clk, rate);
 294         clk_prepare_enable(d->clk);
 295 
 296         if (!ret)
 297                 p->uartclk = rate;
 298 
 299 out:
 300         p->status &= ~UPSTAT_AUTOCTS;
 301         if (termios->c_cflag & CRTSCTS)
 302                 p->status |= UPSTAT_AUTOCTS;
 303 
 304         serial8250_do_set_termios(p, termios, old);
 305 }
 306 
 307 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
 308 {
 309         struct uart_8250_port *up = up_to_u8250p(p);
 310         unsigned int mcr = p->serial_in(p, UART_MCR);
 311 
 312         if (up->capabilities & UART_CAP_IRDA) {
 313                 if (termios->c_line == N_IRDA)
 314                         mcr |= DW_UART_MCR_SIRE;
 315                 else
 316                         mcr &= ~DW_UART_MCR_SIRE;
 317 
 318                 p->serial_out(p, UART_MCR, mcr);
 319         }
 320         serial8250_do_set_ldisc(p, termios);
 321 }
 322 
 323 /*
 324  * dw8250_fallback_dma_filter will prevent the UART from getting just any free
 325  * channel on platforms that have DMA engines, but don't have any channels
 326  * assigned to the UART.
 327  *
 328  * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
 329  * core problem is fixed, this function is no longer needed.
 330  */
 331 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
 332 {
 333         return false;
 334 }
 335 
 336 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 337 {
 338         return param == chan->device->dev;
 339 }
 340 
 341 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 342 {
 343         if (p->dev->of_node) {
 344                 struct device_node *np = p->dev->of_node;
 345                 int id;
 346 
 347                 /* get index of serial line, if found in DT aliases */
 348                 id = of_alias_get_id(np, "serial");
 349                 if (id >= 0)
 350                         p->line = id;
 351 #ifdef CONFIG_64BIT
 352                 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
 353                         p->serial_in = dw8250_serial_inq;
 354                         p->serial_out = dw8250_serial_outq;
 355                         p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
 356                         p->type = PORT_OCTEON;
 357                         data->usr_reg = 0x27;
 358                         data->skip_autocfg = true;
 359                 }
 360 #endif
 361                 if (of_device_is_big_endian(p->dev->of_node)) {
 362                         p->iotype = UPIO_MEM32BE;
 363                         p->serial_in = dw8250_serial_in32be;
 364                         p->serial_out = dw8250_serial_out32be;
 365                 }
 366                 if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
 367                         p->serial_out = dw8250_serial_out38x;
 368 
 369         } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
 370                 p->iotype = UPIO_MEM32;
 371                 p->regshift = 2;
 372                 p->serial_in = dw8250_serial_in32;
 373                 data->uart_16550_compatible = true;
 374         }
 375 
 376         /* Platforms with iDMA 64-bit */
 377         if (platform_get_resource_byname(to_platform_device(p->dev),
 378                                          IORESOURCE_MEM, "lpss_priv")) {
 379                 data->data.dma.rx_param = p->dev->parent;
 380                 data->data.dma.tx_param = p->dev->parent;
 381                 data->data.dma.fn = dw8250_idma_filter;
 382         }
 383 }
 384 
 385 static int dw8250_probe(struct platform_device *pdev)
 386 {
 387         struct uart_8250_port uart = {}, *up = &uart;
 388         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 389         struct uart_port *p = &up->port;
 390         struct device *dev = &pdev->dev;
 391         struct dw8250_data *data;
 392         int irq;
 393         int err;
 394         u32 val;
 395 
 396         if (!regs) {
 397                 dev_err(dev, "no registers defined\n");
 398                 return -EINVAL;
 399         }
 400 
 401         irq = platform_get_irq(pdev, 0);
 402         if (irq < 0)
 403                 return irq;
 404 
 405         spin_lock_init(&p->lock);
 406         p->mapbase      = regs->start;
 407         p->irq          = irq;
 408         p->handle_irq   = dw8250_handle_irq;
 409         p->pm           = dw8250_do_pm;
 410         p->type         = PORT_8250;
 411         p->flags        = UPF_SHARE_IRQ | UPF_FIXED_PORT;
 412         p->dev          = dev;
 413         p->iotype       = UPIO_MEM;
 414         p->serial_in    = dw8250_serial_in;
 415         p->serial_out   = dw8250_serial_out;
 416         p->set_ldisc    = dw8250_set_ldisc;
 417         p->set_termios  = dw8250_set_termios;
 418 
 419         p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
 420         if (!p->membase)
 421                 return -ENOMEM;
 422 
 423         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 424         if (!data)
 425                 return -ENOMEM;
 426 
 427         data->data.dma.fn = dw8250_fallback_dma_filter;
 428         data->usr_reg = DW_UART_USR;
 429         p->private_data = &data->data;
 430 
 431         data->uart_16550_compatible = device_property_read_bool(dev,
 432                                                 "snps,uart-16550-compatible");
 433 
 434         err = device_property_read_u32(dev, "reg-shift", &val);
 435         if (!err)
 436                 p->regshift = val;
 437 
 438         err = device_property_read_u32(dev, "reg-io-width", &val);
 439         if (!err && val == 4) {
 440                 p->iotype = UPIO_MEM32;
 441                 p->serial_in = dw8250_serial_in32;
 442                 p->serial_out = dw8250_serial_out32;
 443         }
 444 
 445         if (device_property_read_bool(dev, "dcd-override")) {
 446                 /* Always report DCD as active */
 447                 data->msr_mask_on |= UART_MSR_DCD;
 448                 data->msr_mask_off |= UART_MSR_DDCD;
 449         }
 450 
 451         if (device_property_read_bool(dev, "dsr-override")) {
 452                 /* Always report DSR as active */
 453                 data->msr_mask_on |= UART_MSR_DSR;
 454                 data->msr_mask_off |= UART_MSR_DDSR;
 455         }
 456 
 457         if (device_property_read_bool(dev, "cts-override")) {
 458                 /* Always report CTS as active */
 459                 data->msr_mask_on |= UART_MSR_CTS;
 460                 data->msr_mask_off |= UART_MSR_DCTS;
 461         }
 462 
 463         if (device_property_read_bool(dev, "ri-override")) {
 464                 /* Always report Ring indicator as inactive */
 465                 data->msr_mask_off |= UART_MSR_RI;
 466                 data->msr_mask_off |= UART_MSR_TERI;
 467         }
 468 
 469         /* Always ask for fixed clock rate from a property. */
 470         device_property_read_u32(dev, "clock-frequency", &p->uartclk);
 471 
 472         /* If there is separate baudclk, get the rate from it. */
 473         data->clk = devm_clk_get(dev, "baudclk");
 474         if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
 475                 data->clk = devm_clk_get(dev, NULL);
 476         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
 477                 return -EPROBE_DEFER;
 478         if (!IS_ERR_OR_NULL(data->clk)) {
 479                 err = clk_prepare_enable(data->clk);
 480                 if (err)
 481                         dev_warn(dev, "could not enable optional baudclk: %d\n",
 482                                  err);
 483                 else
 484                         p->uartclk = clk_get_rate(data->clk);
 485         }
 486 
 487         /* If no clock rate is defined, fail. */
 488         if (!p->uartclk) {
 489                 dev_err(dev, "clock rate not defined\n");
 490                 err = -EINVAL;
 491                 goto err_clk;
 492         }
 493 
 494         data->pclk = devm_clk_get(dev, "apb_pclk");
 495         if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) {
 496                 err = -EPROBE_DEFER;
 497                 goto err_clk;
 498         }
 499         if (!IS_ERR(data->pclk)) {
 500                 err = clk_prepare_enable(data->pclk);
 501                 if (err) {
 502                         dev_err(dev, "could not enable apb_pclk\n");
 503                         goto err_clk;
 504                 }
 505         }
 506 
 507         data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
 508         if (IS_ERR(data->rst)) {
 509                 err = PTR_ERR(data->rst);
 510                 goto err_pclk;
 511         }
 512         reset_control_deassert(data->rst);
 513 
 514         dw8250_quirks(p, data);
 515 
 516         /* If the Busy Functionality is not implemented, don't handle it */
 517         if (data->uart_16550_compatible)
 518                 p->handle_irq = NULL;
 519 
 520         if (!data->skip_autocfg)
 521                 dw8250_setup_port(p);
 522 
 523         /* If we have a valid fifosize, try hooking up DMA */
 524         if (p->fifosize) {
 525                 data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
 526                 data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
 527                 up->dma = &data->data.dma;
 528         }
 529 
 530         data->data.line = serial8250_register_8250_port(up);
 531         if (data->data.line < 0) {
 532                 err = data->data.line;
 533                 goto err_reset;
 534         }
 535 
 536         platform_set_drvdata(pdev, data);
 537 
 538         pm_runtime_set_active(dev);
 539         pm_runtime_enable(dev);
 540 
 541         return 0;
 542 
 543 err_reset:
 544         reset_control_assert(data->rst);
 545 
 546 err_pclk:
 547         if (!IS_ERR(data->pclk))
 548                 clk_disable_unprepare(data->pclk);
 549 
 550 err_clk:
 551         if (!IS_ERR(data->clk))
 552                 clk_disable_unprepare(data->clk);
 553 
 554         return err;
 555 }
 556 
 557 static int dw8250_remove(struct platform_device *pdev)
 558 {
 559         struct dw8250_data *data = platform_get_drvdata(pdev);
 560         struct device *dev = &pdev->dev;
 561 
 562         pm_runtime_get_sync(dev);
 563 
 564         serial8250_unregister_port(data->data.line);
 565 
 566         reset_control_assert(data->rst);
 567 
 568         if (!IS_ERR(data->pclk))
 569                 clk_disable_unprepare(data->pclk);
 570 
 571         if (!IS_ERR(data->clk))
 572                 clk_disable_unprepare(data->clk);
 573 
 574         pm_runtime_disable(dev);
 575         pm_runtime_put_noidle(dev);
 576 
 577         return 0;
 578 }
 579 
 580 #ifdef CONFIG_PM_SLEEP
 581 static int dw8250_suspend(struct device *dev)
 582 {
 583         struct dw8250_data *data = dev_get_drvdata(dev);
 584 
 585         serial8250_suspend_port(data->data.line);
 586 
 587         return 0;
 588 }
 589 
 590 static int dw8250_resume(struct device *dev)
 591 {
 592         struct dw8250_data *data = dev_get_drvdata(dev);
 593 
 594         serial8250_resume_port(data->data.line);
 595 
 596         return 0;
 597 }
 598 #endif /* CONFIG_PM_SLEEP */
 599 
 600 #ifdef CONFIG_PM
 601 static int dw8250_runtime_suspend(struct device *dev)
 602 {
 603         struct dw8250_data *data = dev_get_drvdata(dev);
 604 
 605         if (!IS_ERR(data->clk))
 606                 clk_disable_unprepare(data->clk);
 607 
 608         if (!IS_ERR(data->pclk))
 609                 clk_disable_unprepare(data->pclk);
 610 
 611         return 0;
 612 }
 613 
 614 static int dw8250_runtime_resume(struct device *dev)
 615 {
 616         struct dw8250_data *data = dev_get_drvdata(dev);
 617 
 618         if (!IS_ERR(data->pclk))
 619                 clk_prepare_enable(data->pclk);
 620 
 621         if (!IS_ERR(data->clk))
 622                 clk_prepare_enable(data->clk);
 623 
 624         return 0;
 625 }
 626 #endif
 627 
 628 static const struct dev_pm_ops dw8250_pm_ops = {
 629         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 630         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 631 };
 632 
 633 static const struct of_device_id dw8250_of_match[] = {
 634         { .compatible = "snps,dw-apb-uart" },
 635         { .compatible = "cavium,octeon-3860-uart" },
 636         { .compatible = "marvell,armada-38x-uart" },
 637         { .compatible = "renesas,rzn1-uart" },
 638         { /* Sentinel */ }
 639 };
 640 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 641 
 642 static const struct acpi_device_id dw8250_acpi_match[] = {
 643         { "INT33C4", 0 },
 644         { "INT33C5", 0 },
 645         { "INT3434", 0 },
 646         { "INT3435", 0 },
 647         { "80860F0A", 0 },
 648         { "8086228A", 0 },
 649         { "APMC0D08", 0},
 650         { "AMD0020", 0 },
 651         { "AMDI0020", 0 },
 652         { "BRCM2032", 0 },
 653         { "HISI0031", 0 },
 654         { },
 655 };
 656 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 657 
 658 static struct platform_driver dw8250_platform_driver = {
 659         .driver = {
 660                 .name           = "dw-apb-uart",
 661                 .pm             = &dw8250_pm_ops,
 662                 .of_match_table = dw8250_of_match,
 663                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 664         },
 665         .probe                  = dw8250_probe,
 666         .remove                 = dw8250_remove,
 667 };
 668 
 669 module_platform_driver(dw8250_platform_driver);
 670 
 671 MODULE_AUTHOR("Jamie Iles");
 672 MODULE_LICENSE("GPL");
 673 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
 674 MODULE_ALIAS("platform:dw-apb-uart");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/8250/8250_dw.c

DEFINITIONS
