drivers/tty/serial/atmel

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This source file includes following definitions.
to_atmel_uart_port
atmel_uart_readl
atmel_uart_writel
atmel_uart_read_char
atmel_uart_write_char
atmel_uart_is_half_duplex
atmel_use_pdc_rx
atmel_use_pdc_tx
atmel_use_pdc_rx
atmel_use_pdc_tx
atmel_use_dma_tx
atmel_use_dma_rx
atmel_use_fifo
atmel_tasklet_schedule
atmel_config_rs485
atmel_calc_cd
atmel_calc_fidi
atmel_config_iso7816
atmel_tx_empty
atmel_set_mctrl
atmel_get_mctrl
atmel_stop_tx
atmel_start_tx
atmel_start_rx
atmel_stop_rx
atmel_enable_ms
atmel_disable_ms
atmel_break_ctl
atmel_buffer_rx_char
atmel_pdc_rxerr
atmel_rx_chars
atmel_tx_chars
atmel_complete_tx_dma
atmel_release_tx_dma
atmel_tx_dma
atmel_prepare_tx_dma
atmel_complete_rx_dma
atmel_release_rx_dma
atmel_rx_from_dma
atmel_prepare_rx_dma
atmel_uart_timer_callback
atmel_handle_receive
atmel_handle_transmit
atmel_handle_status
atmel_interrupt
atmel_release_tx_pdc
atmel_tx_pdc
atmel_prepare_tx_pdc
atmel_rx_from_ring
atmel_release_rx_pdc
atmel_rx_from_pdc
atmel_prepare_rx_pdc
atmel_tasklet_rx_func
atmel_tasklet_tx_func
atmel_init_property
atmel_set_ops
atmel_get_ip_name
atmel_startup
atmel_flush_buffer
atmel_shutdown
atmel_serial_pm
atmel_set_termios
atmel_set_ldisc
atmel_type
atmel_release_port
atmel_request_port
atmel_config_port
atmel_verify_port
atmel_poll_get_char
atmel_poll_put_char
atmel_init_port
atmel_console_putchar
atmel_console_write
atmel_console_get_options
atmel_console_setup
atmel_is_console_port
atmel_is_console_port
atmel_serial_clk_will_stop
atmel_serial_suspend
atmel_serial_resume
atmel_serial_probe_fifos
atmel_serial_probe
atmel_serial_remove
atmel_serial_init
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Driver for Atmel AT91 Serial ports
   4  *  Copyright (C) 2003 Rick Bronson
   5  *
   6  *  Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
   7  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   8  *
   9  *  DMA support added by Chip Coldwell.
  10  */
  11 #include <linux/tty.h>
  12 #include <linux/ioport.h>
  13 #include <linux/slab.h>
  14 #include <linux/init.h>
  15 #include <linux/serial.h>
  16 #include <linux/clk.h>
  17 #include <linux/console.h>
  18 #include <linux/sysrq.h>
  19 #include <linux/tty_flip.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/atmel_pdc.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/platform_data/atmel.h>
  29 #include <linux/timer.h>
  30 #include <linux/gpio.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/err.h>
  33 #include <linux/irq.h>
  34 #include <linux/suspend.h>
  35 #include <linux/mm.h>
  36 
  37 #include <asm/div64.h>
  38 #include <asm/io.h>
  39 #include <asm/ioctls.h>
  40 
  41 #define PDC_BUFFER_SIZE         512
  42 /* Revisit: We should calculate this based on the actual port settings */
  43 #define PDC_RX_TIMEOUT          (3 * 10)                /* 3 bytes */
  44 
  45 /* The minium number of data FIFOs should be able to contain */
  46 #define ATMEL_MIN_FIFO_SIZE     8
  47 /*
  48  * These two offsets are substracted from the RX FIFO size to define the RTS
  49  * high and low thresholds
  50  */
  51 #define ATMEL_RTS_HIGH_OFFSET   16
  52 #define ATMEL_RTS_LOW_OFFSET    20
  53 
  54 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  55 #define SUPPORT_SYSRQ
  56 #endif
  57 
  58 #include <linux/serial_core.h>
  59 
  60 #include "serial_mctrl_gpio.h"
  61 #include "atmel_serial.h"
  62 
  63 static void atmel_start_rx(struct uart_port *port);
  64 static void atmel_stop_rx(struct uart_port *port);
  65 
  66 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
  67 
  68 /* Use device name ttyAT, major 204 and minor 154-169.  This is necessary if we
  69  * should coexist with the 8250 driver, such as if we have an external 16C550
  70  * UART. */
  71 #define SERIAL_ATMEL_MAJOR      204
  72 #define MINOR_START             154
  73 #define ATMEL_DEVICENAME        "ttyAT"
  74 
  75 #else
  76 
  77 /* Use device name ttyS, major 4, minor 64-68.  This is the usual serial port
  78  * name, but it is legally reserved for the 8250 driver. */
  79 #define SERIAL_ATMEL_MAJOR      TTY_MAJOR
  80 #define MINOR_START             64
  81 #define ATMEL_DEVICENAME        "ttyS"
  82 
  83 #endif
  84 
  85 #define ATMEL_ISR_PASS_LIMIT    256
  86 
  87 struct atmel_dma_buffer {
  88         unsigned char   *buf;
  89         dma_addr_t      dma_addr;
  90         unsigned int    dma_size;
  91         unsigned int    ofs;
  92 };
  93 
  94 struct atmel_uart_char {
  95         u16             status;
  96         u16             ch;
  97 };
  98 
  99 /*
 100  * Be careful, the real size of the ring buffer is
 101  * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
 102  * can contain up to 1024 characters in PIO mode and up to 4096 characters in
 103  * DMA mode.
 104  */
 105 #define ATMEL_SERIAL_RINGSIZE 1024
 106 
 107 /*
 108  * at91: 6 USARTs and one DBGU port (SAM9260)
 109  * samx7: 3 USARTs and 5 UARTs
 110  */
 111 #define ATMEL_MAX_UART          8
 112 
 113 /*
 114  * We wrap our port structure around the generic uart_port.
 115  */
 116 struct atmel_uart_port {
 117         struct uart_port        uart;           /* uart */
 118         struct clk              *clk;           /* uart clock */
 119         int                     may_wakeup;     /* cached value of device_may_wakeup for times we need to disable it */
 120         u32                     backup_imr;     /* IMR saved during suspend */
 121         int                     break_active;   /* break being received */
 122 
 123         bool                    use_dma_rx;     /* enable DMA receiver */
 124         bool                    use_pdc_rx;     /* enable PDC receiver */
 125         short                   pdc_rx_idx;     /* current PDC RX buffer */
 126         struct atmel_dma_buffer pdc_rx[2];      /* PDC receier */
 127 
 128         bool                    use_dma_tx;     /* enable DMA transmitter */
 129         bool                    use_pdc_tx;     /* enable PDC transmitter */
 130         struct atmel_dma_buffer pdc_tx;         /* PDC transmitter */
 131 
 132         spinlock_t                      lock_tx;        /* port lock */
 133         spinlock_t                      lock_rx;        /* port lock */
 134         struct dma_chan                 *chan_tx;
 135         struct dma_chan                 *chan_rx;
 136         struct dma_async_tx_descriptor  *desc_tx;
 137         struct dma_async_tx_descriptor  *desc_rx;
 138         dma_cookie_t                    cookie_tx;
 139         dma_cookie_t                    cookie_rx;
 140         struct scatterlist              sg_tx;
 141         struct scatterlist              sg_rx;
 142         struct tasklet_struct   tasklet_rx;
 143         struct tasklet_struct   tasklet_tx;
 144         atomic_t                tasklet_shutdown;
 145         unsigned int            irq_status_prev;
 146         unsigned int            tx_len;
 147 
 148         struct circ_buf         rx_ring;
 149 
 150         struct mctrl_gpios      *gpios;
 151         u32                     backup_mode;    /* MR saved during iso7816 operations */
 152         u32                     backup_brgr;    /* BRGR saved during iso7816 operations */
 153         unsigned int            tx_done_mask;
 154         u32                     fifo_size;
 155         u32                     rts_high;
 156         u32                     rts_low;
 157         bool                    ms_irq_enabled;
 158         u32                     rtor;   /* address of receiver timeout register if it exists */
 159         bool                    has_frac_baudrate;
 160         bool                    has_hw_timer;
 161         struct timer_list       uart_timer;
 162 
 163         bool                    tx_stopped;
 164         bool                    suspended;
 165         unsigned int            pending;
 166         unsigned int            pending_status;
 167         spinlock_t              lock_suspended;
 168 
 169         bool                    hd_start_rx;    /* can start RX during half-duplex operation */
 170 
 171         /* ISO7816 */
 172         unsigned int            fidi_min;
 173         unsigned int            fidi_max;
 174 
 175 #ifdef CONFIG_PM
 176         struct {
 177                 u32             cr;
 178                 u32             mr;
 179                 u32             imr;
 180                 u32             brgr;
 181                 u32             rtor;
 182                 u32             ttgr;
 183                 u32             fmr;
 184                 u32             fimr;
 185         } cache;
 186 #endif
 187 
 188         int (*prepare_rx)(struct uart_port *port);
 189         int (*prepare_tx)(struct uart_port *port);
 190         void (*schedule_rx)(struct uart_port *port);
 191         void (*schedule_tx)(struct uart_port *port);
 192         void (*release_rx)(struct uart_port *port);
 193         void (*release_tx)(struct uart_port *port);
 194 };
 195 
 196 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
 197 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
 198 
 199 #ifdef SUPPORT_SYSRQ
 200 static struct console atmel_console;
 201 #endif
 202 
 203 #if defined(CONFIG_OF)
 204 static const struct of_device_id atmel_serial_dt_ids[] = {
 205         { .compatible = "atmel,at91rm9200-usart-serial" },
 206         { /* sentinel */ }
 207 };
 208 #endif
 209 
 210 static inline struct atmel_uart_port *
 211 to_atmel_uart_port(struct uart_port *uart)
 212 {
 213         return container_of(uart, struct atmel_uart_port, uart);
 214 }
 215 
 216 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
 217 {
 218         return __raw_readl(port->membase + reg);
 219 }
 220 
 221 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
 222 {
 223         __raw_writel(value, port->membase + reg);
 224 }
 225 
 226 static inline u8 atmel_uart_read_char(struct uart_port *port)
 227 {
 228         return __raw_readb(port->membase + ATMEL_US_RHR);
 229 }
 230 
 231 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
 232 {
 233         __raw_writeb(value, port->membase + ATMEL_US_THR);
 234 }
 235 
 236 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
 237 {
 238         return ((port->rs485.flags & SER_RS485_ENABLED) &&
 239                 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
 240                 (port->iso7816.flags & SER_ISO7816_ENABLED);
 241 }
 242 
 243 #ifdef CONFIG_SERIAL_ATMEL_PDC
 244 static bool atmel_use_pdc_rx(struct uart_port *port)
 245 {
 246         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 247 
 248         return atmel_port->use_pdc_rx;
 249 }
 250 
 251 static bool atmel_use_pdc_tx(struct uart_port *port)
 252 {
 253         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 254 
 255         return atmel_port->use_pdc_tx;
 256 }
 257 #else
 258 static bool atmel_use_pdc_rx(struct uart_port *port)
 259 {
 260         return false;
 261 }
 262 
 263 static bool atmel_use_pdc_tx(struct uart_port *port)
 264 {
 265         return false;
 266 }
 267 #endif
 268 
 269 static bool atmel_use_dma_tx(struct uart_port *port)
 270 {
 271         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 272 
 273         return atmel_port->use_dma_tx;
 274 }
 275 
 276 static bool atmel_use_dma_rx(struct uart_port *port)
 277 {
 278         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 279 
 280         return atmel_port->use_dma_rx;
 281 }
 282 
 283 static bool atmel_use_fifo(struct uart_port *port)
 284 {
 285         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 286 
 287         return atmel_port->fifo_size;
 288 }
 289 
 290 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
 291                                    struct tasklet_struct *t)
 292 {
 293         if (!atomic_read(&atmel_port->tasklet_shutdown))
 294                 tasklet_schedule(t);
 295 }
 296 
 297 /* Enable or disable the rs485 support */
 298 static int atmel_config_rs485(struct uart_port *port,
 299                               struct serial_rs485 *rs485conf)
 300 {
 301         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 302         unsigned int mode;
 303 
 304         /* Disable interrupts */
 305         atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
 306 
 307         mode = atmel_uart_readl(port, ATMEL_US_MR);
 308 
 309         /* Resetting serial mode to RS232 (0x0) */
 310         mode &= ~ATMEL_US_USMODE;
 311 
 312         port->rs485 = *rs485conf;
 313 
 314         if (rs485conf->flags & SER_RS485_ENABLED) {
 315                 dev_dbg(port->dev, "Setting UART to RS485\n");
 316                 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
 317                 atmel_uart_writel(port, ATMEL_US_TTGR,
 318                                   rs485conf->delay_rts_after_send);
 319                 mode |= ATMEL_US_USMODE_RS485;
 320         } else {
 321                 dev_dbg(port->dev, "Setting UART to RS232\n");
 322                 if (atmel_use_pdc_tx(port))
 323                         atmel_port->tx_done_mask = ATMEL_US_ENDTX |
 324                                 ATMEL_US_TXBUFE;
 325                 else
 326                         atmel_port->tx_done_mask = ATMEL_US_TXRDY;
 327         }
 328         atmel_uart_writel(port, ATMEL_US_MR, mode);
 329 
 330         /* Enable interrupts */
 331         atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
 332 
 333         return 0;
 334 }
 335 
 336 static unsigned int atmel_calc_cd(struct uart_port *port,
 337                                   struct serial_iso7816 *iso7816conf)
 338 {
 339         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 340         unsigned int cd;
 341         u64 mck_rate;
 342 
 343         mck_rate = (u64)clk_get_rate(atmel_port->clk);
 344         do_div(mck_rate, iso7816conf->clk);
 345         cd = mck_rate;
 346         return cd;
 347 }
 348 
 349 static unsigned int atmel_calc_fidi(struct uart_port *port,
 350                                     struct serial_iso7816 *iso7816conf)
 351 {
 352         u64 fidi = 0;
 353 
 354         if (iso7816conf->sc_fi && iso7816conf->sc_di) {
 355                 fidi = (u64)iso7816conf->sc_fi;
 356                 do_div(fidi, iso7816conf->sc_di);
 357         }
 358         return (u32)fidi;
 359 }
 360 
 361 /* Enable or disable the iso7816 support */
 362 /* Called with interrupts disabled */
 363 static int atmel_config_iso7816(struct uart_port *port,
 364                                 struct serial_iso7816 *iso7816conf)
 365 {
 366         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 367         unsigned int mode;
 368         unsigned int cd, fidi;
 369         int ret = 0;
 370 
 371         /* Disable interrupts */
 372         atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
 373 
 374         mode = atmel_uart_readl(port, ATMEL_US_MR);
 375 
 376         if (iso7816conf->flags & SER_ISO7816_ENABLED) {
 377                 mode &= ~ATMEL_US_USMODE;
 378 
 379                 if (iso7816conf->tg > 255) {
 380                         dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
 381                         memset(iso7816conf, 0, sizeof(struct serial_iso7816));
 382                         ret = -EINVAL;
 383                         goto err_out;
 384                 }
 385 
 386                 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
 387                     == SER_ISO7816_T(0)) {
 388                         mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
 389                 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
 390                            == SER_ISO7816_T(1)) {
 391                         mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
 392                 } else {
 393                         dev_err(port->dev, "ISO7816: Type not supported\n");
 394                         memset(iso7816conf, 0, sizeof(struct serial_iso7816));
 395                         ret = -EINVAL;
 396                         goto err_out;
 397                 }
 398 
 399                 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
 400 
 401                 /* select mck clock, and output  */
 402                 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
 403                 /* set parity for normal/inverse mode + max iterations */
 404                 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
 405 
 406                 cd = atmel_calc_cd(port, iso7816conf);
 407                 fidi = atmel_calc_fidi(port, iso7816conf);
 408                 if (fidi == 0) {
 409                         dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
 410                 } else if (fidi < atmel_port->fidi_min
 411                            || fidi > atmel_port->fidi_max) {
 412                         dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
 413                         memset(iso7816conf, 0, sizeof(struct serial_iso7816));
 414                         ret = -EINVAL;
 415                         goto err_out;
 416                 }
 417 
 418                 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
 419                         /* port not yet in iso7816 mode: store configuration */
 420                         atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
 421                         atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
 422                 }
 423 
 424                 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
 425                 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
 426                 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
 427 
 428                 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
 429                 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
 430         } else {
 431                 dev_dbg(port->dev, "Setting UART back to RS232\n");
 432                 /* back to last RS232 settings */
 433                 mode = atmel_port->backup_mode;
 434                 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
 435                 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
 436                 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
 437                 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
 438 
 439                 if (atmel_use_pdc_tx(port))
 440                         atmel_port->tx_done_mask = ATMEL_US_ENDTX |
 441                                                    ATMEL_US_TXBUFE;
 442                 else
 443                         atmel_port->tx_done_mask = ATMEL_US_TXRDY;
 444         }
 445 
 446         port->iso7816 = *iso7816conf;
 447 
 448         atmel_uart_writel(port, ATMEL_US_MR, mode);
 449 
 450 err_out:
 451         /* Enable interrupts */
 452         atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
 453 
 454         return ret;
 455 }
 456 
 457 /*
 458  * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
 459  */
 460 static u_int atmel_tx_empty(struct uart_port *port)
 461 {
 462         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 463 
 464         if (atmel_port->tx_stopped)
 465                 return TIOCSER_TEMT;
 466         return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
 467                 TIOCSER_TEMT :
 468                 0;
 469 }
 470 
 471 /*
 472  * Set state of the modem control output lines
 473  */
 474 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
 475 {
 476         unsigned int control = 0;
 477         unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
 478         unsigned int rts_paused, rts_ready;
 479         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 480 
 481         /* override mode to RS485 if needed, otherwise keep the current mode */
 482         if (port->rs485.flags & SER_RS485_ENABLED) {
 483                 atmel_uart_writel(port, ATMEL_US_TTGR,
 484                                   port->rs485.delay_rts_after_send);
 485                 mode &= ~ATMEL_US_USMODE;
 486                 mode |= ATMEL_US_USMODE_RS485;
 487         }
 488 
 489         /* set the RTS line state according to the mode */
 490         if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
 491                 /* force RTS line to high level */
 492                 rts_paused = ATMEL_US_RTSEN;
 493 
 494                 /* give the control of the RTS line back to the hardware */
 495                 rts_ready = ATMEL_US_RTSDIS;
 496         } else {
 497                 /* force RTS line to high level */
 498                 rts_paused = ATMEL_US_RTSDIS;
 499 
 500                 /* force RTS line to low level */
 501                 rts_ready = ATMEL_US_RTSEN;
 502         }
 503 
 504         if (mctrl & TIOCM_RTS)
 505                 control |= rts_ready;
 506         else
 507                 control |= rts_paused;
 508 
 509         if (mctrl & TIOCM_DTR)
 510                 control |= ATMEL_US_DTREN;
 511         else
 512                 control |= ATMEL_US_DTRDIS;
 513 
 514         atmel_uart_writel(port, ATMEL_US_CR, control);
 515 
 516         mctrl_gpio_set(atmel_port->gpios, mctrl);
 517 
 518         /* Local loopback mode? */
 519         mode &= ~ATMEL_US_CHMODE;
 520         if (mctrl & TIOCM_LOOP)
 521                 mode |= ATMEL_US_CHMODE_LOC_LOOP;
 522         else
 523                 mode |= ATMEL_US_CHMODE_NORMAL;
 524 
 525         atmel_uart_writel(port, ATMEL_US_MR, mode);
 526 }
 527 
 528 /*
 529  * Get state of the modem control input lines
 530  */
 531 static u_int atmel_get_mctrl(struct uart_port *port)
 532 {
 533         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 534         unsigned int ret = 0, status;
 535 
 536         status = atmel_uart_readl(port, ATMEL_US_CSR);
 537 
 538         /*
 539          * The control signals are active low.
 540          */
 541         if (!(status & ATMEL_US_DCD))
 542                 ret |= TIOCM_CD;
 543         if (!(status & ATMEL_US_CTS))
 544                 ret |= TIOCM_CTS;
 545         if (!(status & ATMEL_US_DSR))
 546                 ret |= TIOCM_DSR;
 547         if (!(status & ATMEL_US_RI))
 548                 ret |= TIOCM_RI;
 549 
 550         return mctrl_gpio_get(atmel_port->gpios, &ret);
 551 }
 552 
 553 /*
 554  * Stop transmitting.
 555  */
 556 static void atmel_stop_tx(struct uart_port *port)
 557 {
 558         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 559 
 560         if (atmel_use_pdc_tx(port)) {
 561                 /* disable PDC transmit */
 562                 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
 563         }
 564 
 565         /*
 566          * Disable the transmitter.
 567          * This is mandatory when DMA is used, otherwise the DMA buffer
 568          * is fully transmitted.
 569          */
 570         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
 571         atmel_port->tx_stopped = true;
 572 
 573         /* Disable interrupts */
 574         atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
 575 
 576         if (atmel_uart_is_half_duplex(port))
 577                 if (!atomic_read(&atmel_port->tasklet_shutdown))
 578                         atmel_start_rx(port);
 579 
 580 }
 581 
 582 /*
 583  * Start transmitting.
 584  */
 585 static void atmel_start_tx(struct uart_port *port)
 586 {
 587         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 588 
 589         if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
 590                                        & ATMEL_PDC_TXTEN))
 591                 /* The transmitter is already running.  Yes, we
 592                    really need this.*/
 593                 return;
 594 
 595         if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
 596                 if (atmel_uart_is_half_duplex(port))
 597                         atmel_stop_rx(port);
 598 
 599         if (atmel_use_pdc_tx(port))
 600                 /* re-enable PDC transmit */
 601                 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
 602 
 603         /* Enable interrupts */
 604         atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
 605 
 606         /* re-enable the transmitter */
 607         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
 608         atmel_port->tx_stopped = false;
 609 }
 610 
 611 /*
 612  * start receiving - port is in process of being opened.
 613  */
 614 static void atmel_start_rx(struct uart_port *port)
 615 {
 616         /* reset status and receiver */
 617         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
 618 
 619         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
 620 
 621         if (atmel_use_pdc_rx(port)) {
 622                 /* enable PDC controller */
 623                 atmel_uart_writel(port, ATMEL_US_IER,
 624                                   ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
 625                                   port->read_status_mask);
 626                 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
 627         } else {
 628                 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
 629         }
 630 }
 631 
 632 /*
 633  * Stop receiving - port is in process of being closed.
 634  */
 635 static void atmel_stop_rx(struct uart_port *port)
 636 {
 637         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
 638 
 639         if (atmel_use_pdc_rx(port)) {
 640                 /* disable PDC receive */
 641                 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
 642                 atmel_uart_writel(port, ATMEL_US_IDR,
 643                                   ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
 644                                   port->read_status_mask);
 645         } else {
 646                 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
 647         }
 648 }
 649 
 650 /*
 651  * Enable modem status interrupts
 652  */
 653 static void atmel_enable_ms(struct uart_port *port)
 654 {
 655         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 656         uint32_t ier = 0;
 657 
 658         /*
 659          * Interrupt should not be enabled twice
 660          */
 661         if (atmel_port->ms_irq_enabled)
 662                 return;
 663 
 664         atmel_port->ms_irq_enabled = true;
 665 
 666         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
 667                 ier |= ATMEL_US_CTSIC;
 668 
 669         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
 670                 ier |= ATMEL_US_DSRIC;
 671 
 672         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
 673                 ier |= ATMEL_US_RIIC;
 674 
 675         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
 676                 ier |= ATMEL_US_DCDIC;
 677 
 678         atmel_uart_writel(port, ATMEL_US_IER, ier);
 679 
 680         mctrl_gpio_enable_ms(atmel_port->gpios);
 681 }
 682 
 683 /*
 684  * Disable modem status interrupts
 685  */
 686 static void atmel_disable_ms(struct uart_port *port)
 687 {
 688         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 689         uint32_t idr = 0;
 690 
 691         /*
 692          * Interrupt should not be disabled twice
 693          */
 694         if (!atmel_port->ms_irq_enabled)
 695                 return;
 696 
 697         atmel_port->ms_irq_enabled = false;
 698 
 699         mctrl_gpio_disable_ms(atmel_port->gpios);
 700 
 701         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
 702                 idr |= ATMEL_US_CTSIC;
 703 
 704         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
 705                 idr |= ATMEL_US_DSRIC;
 706 
 707         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
 708                 idr |= ATMEL_US_RIIC;
 709 
 710         if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
 711                 idr |= ATMEL_US_DCDIC;
 712 
 713         atmel_uart_writel(port, ATMEL_US_IDR, idr);
 714 }
 715 
 716 /*
 717  * Control the transmission of a break signal
 718  */
 719 static void atmel_break_ctl(struct uart_port *port, int break_state)
 720 {
 721         if (break_state != 0)
 722                 /* start break */
 723                 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
 724         else
 725                 /* stop break */
 726                 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
 727 }
 728 
 729 /*
 730  * Stores the incoming character in the ring buffer
 731  */
 732 static void
 733 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
 734                      unsigned int ch)
 735 {
 736         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 737         struct circ_buf *ring = &atmel_port->rx_ring;
 738         struct atmel_uart_char *c;
 739 
 740         if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
 741                 /* Buffer overflow, ignore char */
 742                 return;
 743 
 744         c = &((struct atmel_uart_char *)ring->buf)[ring->head];
 745         c->status       = status;
 746         c->ch           = ch;
 747 
 748         /* Make sure the character is stored before we update head. */
 749         smp_wmb();
 750 
 751         ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
 752 }
 753 
 754 /*
 755  * Deal with parity, framing and overrun errors.
 756  */
 757 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
 758 {
 759         /* clear error */
 760         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
 761 
 762         if (status & ATMEL_US_RXBRK) {
 763                 /* ignore side-effect */
 764                 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
 765                 port->icount.brk++;
 766         }
 767         if (status & ATMEL_US_PARE)
 768                 port->icount.parity++;
 769         if (status & ATMEL_US_FRAME)
 770                 port->icount.frame++;
 771         if (status & ATMEL_US_OVRE)
 772                 port->icount.overrun++;
 773 }
 774 
 775 /*
 776  * Characters received (called from interrupt handler)
 777  */
 778 static void atmel_rx_chars(struct uart_port *port)
 779 {
 780         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 781         unsigned int status, ch;
 782 
 783         status = atmel_uart_readl(port, ATMEL_US_CSR);
 784         while (status & ATMEL_US_RXRDY) {
 785                 ch = atmel_uart_read_char(port);
 786 
 787                 /*
 788                  * note that the error handling code is
 789                  * out of the main execution path
 790                  */
 791                 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
 792                                        | ATMEL_US_OVRE | ATMEL_US_RXBRK)
 793                              || atmel_port->break_active)) {
 794 
 795                         /* clear error */
 796                         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
 797 
 798                         if (status & ATMEL_US_RXBRK
 799                             && !atmel_port->break_active) {
 800                                 atmel_port->break_active = 1;
 801                                 atmel_uart_writel(port, ATMEL_US_IER,
 802                                                   ATMEL_US_RXBRK);
 803                         } else {
 804                                 /*
 805                                  * This is either the end-of-break
 806                                  * condition or we've received at
 807                                  * least one character without RXBRK
 808                                  * being set. In both cases, the next
 809                                  * RXBRK will indicate start-of-break.
 810                                  */
 811                                 atmel_uart_writel(port, ATMEL_US_IDR,
 812                                                   ATMEL_US_RXBRK);
 813                                 status &= ~ATMEL_US_RXBRK;
 814                                 atmel_port->break_active = 0;
 815                         }
 816                 }
 817 
 818                 atmel_buffer_rx_char(port, status, ch);
 819                 status = atmel_uart_readl(port, ATMEL_US_CSR);
 820         }
 821 
 822         atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
 823 }
 824 
 825 /*
 826  * Transmit characters (called from tasklet with TXRDY interrupt
 827  * disabled)
 828  */
 829 static void atmel_tx_chars(struct uart_port *port)
 830 {
 831         struct circ_buf *xmit = &port->state->xmit;
 832         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 833 
 834         if (port->x_char &&
 835             (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
 836                 atmel_uart_write_char(port, port->x_char);
 837                 port->icount.tx++;
 838                 port->x_char = 0;
 839         }
 840         if (uart_circ_empty(xmit) || uart_tx_stopped(port))
 841                 return;
 842 
 843         while (atmel_uart_readl(port, ATMEL_US_CSR) &
 844                atmel_port->tx_done_mask) {
 845                 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
 846                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 847                 port->icount.tx++;
 848                 if (uart_circ_empty(xmit))
 849                         break;
 850         }
 851 
 852         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 853                 uart_write_wakeup(port);
 854 
 855         if (!uart_circ_empty(xmit))
 856                 /* Enable interrupts */
 857                 atmel_uart_writel(port, ATMEL_US_IER,
 858                                   atmel_port->tx_done_mask);
 859 }
 860 
 861 static void atmel_complete_tx_dma(void *arg)
 862 {
 863         struct atmel_uart_port *atmel_port = arg;
 864         struct uart_port *port = &atmel_port->uart;
 865         struct circ_buf *xmit = &port->state->xmit;
 866         struct dma_chan *chan = atmel_port->chan_tx;
 867         unsigned long flags;
 868 
 869         spin_lock_irqsave(&port->lock, flags);
 870 
 871         if (chan)
 872                 dmaengine_terminate_all(chan);
 873         xmit->tail += atmel_port->tx_len;
 874         xmit->tail &= UART_XMIT_SIZE - 1;
 875 
 876         port->icount.tx += atmel_port->tx_len;
 877 
 878         spin_lock_irq(&atmel_port->lock_tx);
 879         async_tx_ack(atmel_port->desc_tx);
 880         atmel_port->cookie_tx = -EINVAL;
 881         atmel_port->desc_tx = NULL;
 882         spin_unlock_irq(&atmel_port->lock_tx);
 883 
 884         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 885                 uart_write_wakeup(port);
 886 
 887         /*
 888          * xmit is a circular buffer so, if we have just send data from
 889          * xmit->tail to the end of xmit->buf, now we have to transmit the
 890          * remaining data from the beginning of xmit->buf to xmit->head.
 891          */
 892         if (!uart_circ_empty(xmit))
 893                 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
 894         else if (atmel_uart_is_half_duplex(port)) {
 895                 /*
 896                  * DMA done, re-enable TXEMPTY and signal that we can stop
 897                  * TX and start RX for RS485
 898                  */
 899                 atmel_port->hd_start_rx = true;
 900                 atmel_uart_writel(port, ATMEL_US_IER,
 901                                   atmel_port->tx_done_mask);
 902         }
 903 
 904         spin_unlock_irqrestore(&port->lock, flags);
 905 }
 906 
 907 static void atmel_release_tx_dma(struct uart_port *port)
 908 {
 909         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 910         struct dma_chan *chan = atmel_port->chan_tx;
 911 
 912         if (chan) {
 913                 dmaengine_terminate_all(chan);
 914                 dma_release_channel(chan);
 915                 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
 916                                 DMA_TO_DEVICE);
 917         }
 918 
 919         atmel_port->desc_tx = NULL;
 920         atmel_port->chan_tx = NULL;
 921         atmel_port->cookie_tx = -EINVAL;
 922 }
 923 
 924 /*
 925  * Called from tasklet with TXRDY interrupt is disabled.
 926  */
 927 static void atmel_tx_dma(struct uart_port *port)
 928 {
 929         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
 930         struct circ_buf *xmit = &port->state->xmit;
 931         struct dma_chan *chan = atmel_port->chan_tx;
 932         struct dma_async_tx_descriptor *desc;
 933         struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
 934         unsigned int tx_len, part1_len, part2_len, sg_len;
 935         dma_addr_t phys_addr;
 936 
 937         /* Make sure we have an idle channel */
 938         if (atmel_port->desc_tx != NULL)
 939                 return;
 940 
 941         if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
 942                 /*
 943                  * DMA is idle now.
 944                  * Port xmit buffer is already mapped,
 945                  * and it is one page... Just adjust
 946                  * offsets and lengths. Since it is a circular buffer,
 947                  * we have to transmit till the end, and then the rest.
 948                  * Take the port lock to get a
 949                  * consistent xmit buffer state.
 950                  */
 951                 tx_len = CIRC_CNT_TO_END(xmit->head,
 952                                          xmit->tail,
 953                                          UART_XMIT_SIZE);
 954 
 955                 if (atmel_port->fifo_size) {
 956                         /* multi data mode */
 957                         part1_len = (tx_len & ~0x3); /* DWORD access */
 958                         part2_len = (tx_len & 0x3); /* BYTE access */
 959                 } else {
 960                         /* single data (legacy) mode */
 961                         part1_len = 0;
 962                         part2_len = tx_len; /* BYTE access only */
 963                 }
 964 
 965                 sg_init_table(sgl, 2);
 966                 sg_len = 0;
 967                 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
 968                 if (part1_len) {
 969                         sg = &sgl[sg_len++];
 970                         sg_dma_address(sg) = phys_addr;
 971                         sg_dma_len(sg) = part1_len;
 972 
 973                         phys_addr += part1_len;
 974                 }
 975 
 976                 if (part2_len) {
 977                         sg = &sgl[sg_len++];
 978                         sg_dma_address(sg) = phys_addr;
 979                         sg_dma_len(sg) = part2_len;
 980                 }
 981 
 982                 /*
 983                  * save tx_len so atmel_complete_tx_dma() will increase
 984                  * xmit->tail correctly
 985                  */
 986                 atmel_port->tx_len = tx_len;
 987 
 988                 desc = dmaengine_prep_slave_sg(chan,
 989                                                sgl,
 990                                                sg_len,
 991                                                DMA_MEM_TO_DEV,
 992                                                DMA_PREP_INTERRUPT |
 993                                                DMA_CTRL_ACK);
 994                 if (!desc) {
 995                         dev_err(port->dev, "Failed to send via dma!\n");
 996                         return;
 997                 }
 998 
 999                 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
1000 
1001                 atmel_port->desc_tx = desc;
1002                 desc->callback = atmel_complete_tx_dma;
1003                 desc->callback_param = atmel_port;
1004                 atmel_port->cookie_tx = dmaengine_submit(desc);
1005         }
1006 
1007         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1008                 uart_write_wakeup(port);
1009 }
1010 
1011 static int atmel_prepare_tx_dma(struct uart_port *port)
1012 {
1013         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1014         struct device *mfd_dev = port->dev->parent;
1015         dma_cap_mask_t          mask;
1016         struct dma_slave_config config;
1017         int ret, nent;
1018 
1019         dma_cap_zero(mask);
1020         dma_cap_set(DMA_SLAVE, mask);
1021 
1022         atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1023         if (atmel_port->chan_tx == NULL)
1024                 goto chan_err;
1025         dev_info(port->dev, "using %s for tx DMA transfers\n",
1026                 dma_chan_name(atmel_port->chan_tx));
1027 
1028         spin_lock_init(&atmel_port->lock_tx);
1029         sg_init_table(&atmel_port->sg_tx, 1);
1030         /* UART circular tx buffer is an aligned page. */
1031         BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1032         sg_set_page(&atmel_port->sg_tx,
1033                         virt_to_page(port->state->xmit.buf),
1034                         UART_XMIT_SIZE,
1035                         offset_in_page(port->state->xmit.buf));
1036         nent = dma_map_sg(port->dev,
1037                                 &atmel_port->sg_tx,
1038                                 1,
1039                                 DMA_TO_DEVICE);
1040 
1041         if (!nent) {
1042                 dev_dbg(port->dev, "need to release resource of dma\n");
1043                 goto chan_err;
1044         } else {
1045                 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1046                         sg_dma_len(&atmel_port->sg_tx),
1047                         port->state->xmit.buf,
1048                         &sg_dma_address(&atmel_port->sg_tx));
1049         }
1050 
1051         /* Configure the slave DMA */
1052         memset(&config, 0, sizeof(config));
1053         config.direction = DMA_MEM_TO_DEV;
1054         config.dst_addr_width = (atmel_port->fifo_size) ?
1055                                 DMA_SLAVE_BUSWIDTH_4_BYTES :
1056                                 DMA_SLAVE_BUSWIDTH_1_BYTE;
1057         config.dst_addr = port->mapbase + ATMEL_US_THR;
1058         config.dst_maxburst = 1;
1059 
1060         ret = dmaengine_slave_config(atmel_port->chan_tx,
1061                                      &config);
1062         if (ret) {
1063                 dev_err(port->dev, "DMA tx slave configuration failed\n");
1064                 goto chan_err;
1065         }
1066 
1067         return 0;
1068 
1069 chan_err:
1070         dev_err(port->dev, "TX channel not available, switch to pio\n");
1071         atmel_port->use_dma_tx = 0;
1072         if (atmel_port->chan_tx)
1073                 atmel_release_tx_dma(port);
1074         return -EINVAL;
1075 }
1076 
1077 static void atmel_complete_rx_dma(void *arg)
1078 {
1079         struct uart_port *port = arg;
1080         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1081 
1082         atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1083 }
1084 
1085 static void atmel_release_rx_dma(struct uart_port *port)
1086 {
1087         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1088         struct dma_chan *chan = atmel_port->chan_rx;
1089 
1090         if (chan) {
1091                 dmaengine_terminate_all(chan);
1092                 dma_release_channel(chan);
1093                 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1094                                 DMA_FROM_DEVICE);
1095         }
1096 
1097         atmel_port->desc_rx = NULL;
1098         atmel_port->chan_rx = NULL;
1099         atmel_port->cookie_rx = -EINVAL;
1100 }
1101 
1102 static void atmel_rx_from_dma(struct uart_port *port)
1103 {
1104         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1105         struct tty_port *tport = &port->state->port;
1106         struct circ_buf *ring = &atmel_port->rx_ring;
1107         struct dma_chan *chan = atmel_port->chan_rx;
1108         struct dma_tx_state state;
1109         enum dma_status dmastat;
1110         size_t count;
1111 
1112 
1113         /* Reset the UART timeout early so that we don't miss one */
1114         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1115         dmastat = dmaengine_tx_status(chan,
1116                                 atmel_port->cookie_rx,
1117                                 &state);
1118         /* Restart a new tasklet if DMA status is error */
1119         if (dmastat == DMA_ERROR) {
1120                 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1121                 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1122                 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1123                 return;
1124         }
1125 
1126         /* CPU claims ownership of RX DMA buffer */
1127         dma_sync_sg_for_cpu(port->dev,
1128                             &atmel_port->sg_rx,
1129                             1,
1130                             DMA_FROM_DEVICE);
1131 
1132         /*
1133          * ring->head points to the end of data already written by the DMA.
1134          * ring->tail points to the beginning of data to be read by the
1135          * framework.
1136          * The current transfer size should not be larger than the dma buffer
1137          * length.
1138          */
1139         ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1140         BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1141         /*
1142          * At this point ring->head may point to the first byte right after the
1143          * last byte of the dma buffer:
1144          * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1145          *
1146          * However ring->tail must always points inside the dma buffer:
1147          * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1148          *
1149          * Since we use a ring buffer, we have to handle the case
1150          * where head is lower than tail. In such a case, we first read from
1151          * tail to the end of the buffer then reset tail.
1152          */
1153         if (ring->head < ring->tail) {
1154                 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1155 
1156                 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1157                 ring->tail = 0;
1158                 port->icount.rx += count;
1159         }
1160 
1161         /* Finally we read data from tail to head */
1162         if (ring->tail < ring->head) {
1163                 count = ring->head - ring->tail;
1164 
1165                 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1166                 /* Wrap ring->head if needed */
1167                 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1168                         ring->head = 0;
1169                 ring->tail = ring->head;
1170                 port->icount.rx += count;
1171         }
1172 
1173         /* USART retreives ownership of RX DMA buffer */
1174         dma_sync_sg_for_device(port->dev,
1175                                &atmel_port->sg_rx,
1176                                1,
1177                                DMA_FROM_DEVICE);
1178 
1179         /*
1180          * Drop the lock here since it might end up calling
1181          * uart_start(), which takes the lock.
1182          */
1183         spin_unlock(&port->lock);
1184         tty_flip_buffer_push(tport);
1185         spin_lock(&port->lock);
1186 
1187         atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1188 }
1189 
1190 static int atmel_prepare_rx_dma(struct uart_port *port)
1191 {
1192         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1193         struct device *mfd_dev = port->dev->parent;
1194         struct dma_async_tx_descriptor *desc;
1195         dma_cap_mask_t          mask;
1196         struct dma_slave_config config;
1197         struct circ_buf         *ring;
1198         int ret, nent;
1199 
1200         ring = &atmel_port->rx_ring;
1201 
1202         dma_cap_zero(mask);
1203         dma_cap_set(DMA_CYCLIC, mask);
1204 
1205         atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1206         if (atmel_port->chan_rx == NULL)
1207                 goto chan_err;
1208         dev_info(port->dev, "using %s for rx DMA transfers\n",
1209                 dma_chan_name(atmel_port->chan_rx));
1210 
1211         spin_lock_init(&atmel_port->lock_rx);
1212         sg_init_table(&atmel_port->sg_rx, 1);
1213         /* UART circular rx buffer is an aligned page. */
1214         BUG_ON(!PAGE_ALIGNED(ring->buf));
1215         sg_set_page(&atmel_port->sg_rx,
1216                     virt_to_page(ring->buf),
1217                     sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1218                     offset_in_page(ring->buf));
1219         nent = dma_map_sg(port->dev,
1220                           &atmel_port->sg_rx,
1221                           1,
1222                           DMA_FROM_DEVICE);
1223 
1224         if (!nent) {
1225                 dev_dbg(port->dev, "need to release resource of dma\n");
1226                 goto chan_err;
1227         } else {
1228                 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1229                         sg_dma_len(&atmel_port->sg_rx),
1230                         ring->buf,
1231                         &sg_dma_address(&atmel_port->sg_rx));
1232         }
1233 
1234         /* Configure the slave DMA */
1235         memset(&config, 0, sizeof(config));
1236         config.direction = DMA_DEV_TO_MEM;
1237         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1238         config.src_addr = port->mapbase + ATMEL_US_RHR;
1239         config.src_maxburst = 1;
1240 
1241         ret = dmaengine_slave_config(atmel_port->chan_rx,
1242                                      &config);
1243         if (ret) {
1244                 dev_err(port->dev, "DMA rx slave configuration failed\n");
1245                 goto chan_err;
1246         }
1247         /*
1248          * Prepare a cyclic dma transfer, assign 2 descriptors,
1249          * each one is half ring buffer size
1250          */
1251         desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1252                                          sg_dma_address(&atmel_port->sg_rx),
1253                                          sg_dma_len(&atmel_port->sg_rx),
1254                                          sg_dma_len(&atmel_port->sg_rx)/2,
1255                                          DMA_DEV_TO_MEM,
1256                                          DMA_PREP_INTERRUPT);
1257         if (!desc) {
1258                 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1259                 goto chan_err;
1260         }
1261         desc->callback = atmel_complete_rx_dma;
1262         desc->callback_param = port;
1263         atmel_port->desc_rx = desc;
1264         atmel_port->cookie_rx = dmaengine_submit(desc);
1265 
1266         return 0;
1267 
1268 chan_err:
1269         dev_err(port->dev, "RX channel not available, switch to pio\n");
1270         atmel_port->use_dma_rx = 0;
1271         if (atmel_port->chan_rx)
1272                 atmel_release_rx_dma(port);
1273         return -EINVAL;
1274 }
1275 
1276 static void atmel_uart_timer_callback(struct timer_list *t)
1277 {
1278         struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1279                                                         uart_timer);
1280         struct uart_port *port = &atmel_port->uart;
1281 
1282         if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1283                 tasklet_schedule(&atmel_port->tasklet_rx);
1284                 mod_timer(&atmel_port->uart_timer,
1285                           jiffies + uart_poll_timeout(port));
1286         }
1287 }
1288 
1289 /*
1290  * receive interrupt handler.
1291  */
1292 static void
1293 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1294 {
1295         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1296 
1297         if (atmel_use_pdc_rx(port)) {
1298                 /*
1299                  * PDC receive. Just schedule the tasklet and let it
1300                  * figure out the details.
1301                  *
1302                  * TODO: We're not handling error flags correctly at
1303                  * the moment.
1304                  */
1305                 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1306                         atmel_uart_writel(port, ATMEL_US_IDR,
1307                                           (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1308                         atmel_tasklet_schedule(atmel_port,
1309                                                &atmel_port->tasklet_rx);
1310                 }
1311 
1312                 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1313                                 ATMEL_US_FRAME | ATMEL_US_PARE))
1314                         atmel_pdc_rxerr(port, pending);
1315         }
1316 
1317         if (atmel_use_dma_rx(port)) {
1318                 if (pending & ATMEL_US_TIMEOUT) {
1319                         atmel_uart_writel(port, ATMEL_US_IDR,
1320                                           ATMEL_US_TIMEOUT);
1321                         atmel_tasklet_schedule(atmel_port,
1322                                                &atmel_port->tasklet_rx);
1323                 }
1324         }
1325 
1326         /* Interrupt receive */
1327         if (pending & ATMEL_US_RXRDY)
1328                 atmel_rx_chars(port);
1329         else if (pending & ATMEL_US_RXBRK) {
1330                 /*
1331                  * End of break detected. If it came along with a
1332                  * character, atmel_rx_chars will handle it.
1333                  */
1334                 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1335                 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1336                 atmel_port->break_active = 0;
1337         }
1338 }
1339 
1340 /*
1341  * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1342  */
1343 static void
1344 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1345 {
1346         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1347 
1348         if (pending & atmel_port->tx_done_mask) {
1349                 atmel_uart_writel(port, ATMEL_US_IDR,
1350                                   atmel_port->tx_done_mask);
1351 
1352                 /* Start RX if flag was set and FIFO is empty */
1353                 if (atmel_port->hd_start_rx) {
1354                         if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1355                                         & ATMEL_US_TXEMPTY))
1356                                 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1357 
1358                         atmel_port->hd_start_rx = false;
1359                         atmel_start_rx(port);
1360                 }
1361 
1362                 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1363         }
1364 }
1365 
1366 /*
1367  * status flags interrupt handler.
1368  */
1369 static void
1370 atmel_handle_status(struct uart_port *port, unsigned int pending,
1371                     unsigned int status)
1372 {
1373         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1374         unsigned int status_change;
1375 
1376         if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1377                                 | ATMEL_US_CTSIC)) {
1378                 status_change = status ^ atmel_port->irq_status_prev;
1379                 atmel_port->irq_status_prev = status;
1380 
1381                 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1382                                         | ATMEL_US_DCD | ATMEL_US_CTS)) {
1383                         /* TODO: All reads to CSR will clear these interrupts! */
1384                         if (status_change & ATMEL_US_RI)
1385                                 port->icount.rng++;
1386                         if (status_change & ATMEL_US_DSR)
1387                                 port->icount.dsr++;
1388                         if (status_change & ATMEL_US_DCD)
1389                                 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1390                         if (status_change & ATMEL_US_CTS)
1391                                 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1392 
1393                         wake_up_interruptible(&port->state->port.delta_msr_wait);
1394                 }
1395         }
1396 
1397         if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1398                 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1399 }
1400 
1401 /*
1402  * Interrupt handler
1403  */
1404 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1405 {
1406         struct uart_port *port = dev_id;
1407         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1408         unsigned int status, pending, mask, pass_counter = 0;
1409 
1410         spin_lock(&atmel_port->lock_suspended);
1411 
1412         do {
1413                 status = atmel_uart_readl(port, ATMEL_US_CSR);
1414                 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1415                 pending = status & mask;
1416                 if (!pending)
1417                         break;
1418 
1419                 if (atmel_port->suspended) {
1420                         atmel_port->pending |= pending;
1421                         atmel_port->pending_status = status;
1422                         atmel_uart_writel(port, ATMEL_US_IDR, mask);
1423                         pm_system_wakeup();
1424                         break;
1425                 }
1426 
1427                 atmel_handle_receive(port, pending);
1428                 atmel_handle_status(port, pending, status);
1429                 atmel_handle_transmit(port, pending);
1430         } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1431 
1432         spin_unlock(&atmel_port->lock_suspended);
1433 
1434         return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1435 }
1436 
1437 static void atmel_release_tx_pdc(struct uart_port *port)
1438 {
1439         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1440         struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1441 
1442         dma_unmap_single(port->dev,
1443                          pdc->dma_addr,
1444                          pdc->dma_size,
1445                          DMA_TO_DEVICE);
1446 }
1447 
1448 /*
1449  * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1450  */
1451 static void atmel_tx_pdc(struct uart_port *port)
1452 {
1453         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1454         struct circ_buf *xmit = &port->state->xmit;
1455         struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1456         int count;
1457 
1458         /* nothing left to transmit? */
1459         if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1460                 return;
1461 
1462         xmit->tail += pdc->ofs;
1463         xmit->tail &= UART_XMIT_SIZE - 1;
1464 
1465         port->icount.tx += pdc->ofs;
1466         pdc->ofs = 0;
1467 
1468         /* more to transmit - setup next transfer */
1469 
1470         /* disable PDC transmit */
1471         atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1472 
1473         if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1474                 dma_sync_single_for_device(port->dev,
1475                                            pdc->dma_addr,
1476                                            pdc->dma_size,
1477                                            DMA_TO_DEVICE);
1478 
1479                 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1480                 pdc->ofs = count;
1481 
1482                 atmel_uart_writel(port, ATMEL_PDC_TPR,
1483                                   pdc->dma_addr + xmit->tail);
1484                 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1485                 /* re-enable PDC transmit */
1486                 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1487                 /* Enable interrupts */
1488                 atmel_uart_writel(port, ATMEL_US_IER,
1489                                   atmel_port->tx_done_mask);
1490         } else {
1491                 if (atmel_uart_is_half_duplex(port)) {
1492                         /* DMA done, stop TX, start RX for RS485 */
1493                         atmel_start_rx(port);
1494                 }
1495         }
1496 
1497         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1498                 uart_write_wakeup(port);
1499 }
1500 
1501 static int atmel_prepare_tx_pdc(struct uart_port *port)
1502 {
1503         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1504         struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1505         struct circ_buf *xmit = &port->state->xmit;
1506 
1507         pdc->buf = xmit->buf;
1508         pdc->dma_addr = dma_map_single(port->dev,
1509                                         pdc->buf,
1510                                         UART_XMIT_SIZE,
1511                                         DMA_TO_DEVICE);
1512         pdc->dma_size = UART_XMIT_SIZE;
1513         pdc->ofs = 0;
1514 
1515         return 0;
1516 }
1517 
1518 static void atmel_rx_from_ring(struct uart_port *port)
1519 {
1520         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1521         struct circ_buf *ring = &atmel_port->rx_ring;
1522         unsigned int flg;
1523         unsigned int status;
1524 
1525         while (ring->head != ring->tail) {
1526                 struct atmel_uart_char c;
1527 
1528                 /* Make sure c is loaded after head. */
1529                 smp_rmb();
1530 
1531                 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1532 
1533                 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1534 
1535                 port->icount.rx++;
1536                 status = c.status;
1537                 flg = TTY_NORMAL;
1538 
1539                 /*
1540                  * note that the error handling code is
1541                  * out of the main execution path
1542                  */
1543                 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1544                                        | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1545                         if (status & ATMEL_US_RXBRK) {
1546                                 /* ignore side-effect */
1547                                 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1548 
1549                                 port->icount.brk++;
1550                                 if (uart_handle_break(port))
1551                                         continue;
1552                         }
1553                         if (status & ATMEL_US_PARE)
1554                                 port->icount.parity++;
1555                         if (status & ATMEL_US_FRAME)
1556                                 port->icount.frame++;
1557                         if (status & ATMEL_US_OVRE)
1558                                 port->icount.overrun++;
1559 
1560                         status &= port->read_status_mask;
1561 
1562                         if (status & ATMEL_US_RXBRK)
1563                                 flg = TTY_BREAK;
1564                         else if (status & ATMEL_US_PARE)
1565                                 flg = TTY_PARITY;
1566                         else if (status & ATMEL_US_FRAME)
1567                                 flg = TTY_FRAME;
1568                 }
1569 
1570 
1571                 if (uart_handle_sysrq_char(port, c.ch))
1572                         continue;
1573 
1574                 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1575         }
1576 
1577         /*
1578          * Drop the lock here since it might end up calling
1579          * uart_start(), which takes the lock.
1580          */
1581         spin_unlock(&port->lock);
1582         tty_flip_buffer_push(&port->state->port);
1583         spin_lock(&port->lock);
1584 }
1585 
1586 static void atmel_release_rx_pdc(struct uart_port *port)
1587 {
1588         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1589         int i;
1590 
1591         for (i = 0; i < 2; i++) {
1592                 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1593 
1594                 dma_unmap_single(port->dev,
1595                                  pdc->dma_addr,
1596                                  pdc->dma_size,
1597                                  DMA_FROM_DEVICE);
1598                 kfree(pdc->buf);
1599         }
1600 }
1601 
1602 static void atmel_rx_from_pdc(struct uart_port *port)
1603 {
1604         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1605         struct tty_port *tport = &port->state->port;
1606         struct atmel_dma_buffer *pdc;
1607         int rx_idx = atmel_port->pdc_rx_idx;
1608         unsigned int head;
1609         unsigned int tail;
1610         unsigned int count;
1611 
1612         do {
1613                 /* Reset the UART timeout early so that we don't miss one */
1614                 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1615 
1616                 pdc = &atmel_port->pdc_rx[rx_idx];
1617                 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1618                 tail = pdc->ofs;
1619 
1620                 /* If the PDC has switched buffers, RPR won't contain
1621                  * any address within the current buffer. Since head
1622                  * is unsigned, we just need a one-way comparison to
1623                  * find out.
1624                  *
1625                  * In this case, we just need to consume the entire
1626                  * buffer and resubmit it for DMA. This will clear the
1627                  * ENDRX bit as well, so that we can safely re-enable
1628                  * all interrupts below.
1629                  */
1630                 head = min(head, pdc->dma_size);
1631 
1632                 if (likely(head != tail)) {
1633                         dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1634                                         pdc->dma_size, DMA_FROM_DEVICE);
1635 
1636                         /*
1637                          * head will only wrap around when we recycle
1638                          * the DMA buffer, and when that happens, we
1639                          * explicitly set tail to 0. So head will
1640                          * always be greater than tail.
1641                          */
1642                         count = head - tail;
1643 
1644                         tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1645                                                 count);
1646 
1647                         dma_sync_single_for_device(port->dev, pdc->dma_addr,
1648                                         pdc->dma_size, DMA_FROM_DEVICE);
1649 
1650                         port->icount.rx += count;
1651                         pdc->ofs = head;
1652                 }
1653 
1654                 /*
1655                  * If the current buffer is full, we need to check if
1656                  * the next one contains any additional data.
1657                  */
1658                 if (head >= pdc->dma_size) {
1659                         pdc->ofs = 0;
1660                         atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1661                         atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1662 
1663                         rx_idx = !rx_idx;
1664                         atmel_port->pdc_rx_idx = rx_idx;
1665                 }
1666         } while (head >= pdc->dma_size);
1667 
1668         /*
1669          * Drop the lock here since it might end up calling
1670          * uart_start(), which takes the lock.
1671          */
1672         spin_unlock(&port->lock);
1673         tty_flip_buffer_push(tport);
1674         spin_lock(&port->lock);
1675 
1676         atmel_uart_writel(port, ATMEL_US_IER,
1677                           ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1678 }
1679 
1680 static int atmel_prepare_rx_pdc(struct uart_port *port)
1681 {
1682         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1683         int i;
1684 
1685         for (i = 0; i < 2; i++) {
1686                 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1687 
1688                 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1689                 if (pdc->buf == NULL) {
1690                         if (i != 0) {
1691                                 dma_unmap_single(port->dev,
1692                                         atmel_port->pdc_rx[0].dma_addr,
1693                                         PDC_BUFFER_SIZE,
1694                                         DMA_FROM_DEVICE);
1695                                 kfree(atmel_port->pdc_rx[0].buf);
1696                         }
1697                         atmel_port->use_pdc_rx = 0;
1698                         return -ENOMEM;
1699                 }
1700                 pdc->dma_addr = dma_map_single(port->dev,
1701                                                 pdc->buf,
1702                                                 PDC_BUFFER_SIZE,
1703                                                 DMA_FROM_DEVICE);
1704                 pdc->dma_size = PDC_BUFFER_SIZE;
1705                 pdc->ofs = 0;
1706         }
1707 
1708         atmel_port->pdc_rx_idx = 0;
1709 
1710         atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1711         atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1712 
1713         atmel_uart_writel(port, ATMEL_PDC_RNPR,
1714                           atmel_port->pdc_rx[1].dma_addr);
1715         atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1716 
1717         return 0;
1718 }
1719 
1720 /*
1721  * tasklet handling tty stuff outside the interrupt handler.
1722  */
1723 static void atmel_tasklet_rx_func(unsigned long data)
1724 {
1725         struct uart_port *port = (struct uart_port *)data;
1726         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1727 
1728         /* The interrupt handler does not take the lock */
1729         spin_lock(&port->lock);
1730         atmel_port->schedule_rx(port);
1731         spin_unlock(&port->lock);
1732 }
1733 
1734 static void atmel_tasklet_tx_func(unsigned long data)
1735 {
1736         struct uart_port *port = (struct uart_port *)data;
1737         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1738 
1739         /* The interrupt handler does not take the lock */
1740         spin_lock(&port->lock);
1741         atmel_port->schedule_tx(port);
1742         spin_unlock(&port->lock);
1743 }
1744 
1745 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1746                                 struct platform_device *pdev)
1747 {
1748         struct device_node *np = pdev->dev.of_node;
1749 
1750         /* DMA/PDC usage specification */
1751         if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1752                 if (of_property_read_bool(np, "dmas")) {
1753                         atmel_port->use_dma_rx  = true;
1754                         atmel_port->use_pdc_rx  = false;
1755                 } else {
1756                         atmel_port->use_dma_rx  = false;
1757                         atmel_port->use_pdc_rx  = true;
1758                 }
1759         } else {
1760                 atmel_port->use_dma_rx  = false;
1761                 atmel_port->use_pdc_rx  = false;
1762         }
1763 
1764         if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1765                 if (of_property_read_bool(np, "dmas")) {
1766                         atmel_port->use_dma_tx  = true;
1767                         atmel_port->use_pdc_tx  = false;
1768                 } else {
1769                         atmel_port->use_dma_tx  = false;
1770                         atmel_port->use_pdc_tx  = true;
1771                 }
1772         } else {
1773                 atmel_port->use_dma_tx  = false;
1774                 atmel_port->use_pdc_tx  = false;
1775         }
1776 }
1777 
1778 static void atmel_set_ops(struct uart_port *port)
1779 {
1780         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1781 
1782         if (atmel_use_dma_rx(port)) {
1783                 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1784                 atmel_port->schedule_rx = &atmel_rx_from_dma;
1785                 atmel_port->release_rx = &atmel_release_rx_dma;
1786         } else if (atmel_use_pdc_rx(port)) {
1787                 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1788                 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1789                 atmel_port->release_rx = &atmel_release_rx_pdc;
1790         } else {
1791                 atmel_port->prepare_rx = NULL;
1792                 atmel_port->schedule_rx = &atmel_rx_from_ring;
1793                 atmel_port->release_rx = NULL;
1794         }
1795 
1796         if (atmel_use_dma_tx(port)) {
1797                 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1798                 atmel_port->schedule_tx = &atmel_tx_dma;
1799                 atmel_port->release_tx = &atmel_release_tx_dma;
1800         } else if (atmel_use_pdc_tx(port)) {
1801                 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1802                 atmel_port->schedule_tx = &atmel_tx_pdc;
1803                 atmel_port->release_tx = &atmel_release_tx_pdc;
1804         } else {
1805                 atmel_port->prepare_tx = NULL;
1806                 atmel_port->schedule_tx = &atmel_tx_chars;
1807                 atmel_port->release_tx = NULL;
1808         }
1809 }
1810 
1811 /*
1812  * Get ip name usart or uart
1813  */
1814 static void atmel_get_ip_name(struct uart_port *port)
1815 {
1816         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1817         int name = atmel_uart_readl(port, ATMEL_US_NAME);
1818         u32 version;
1819         u32 usart, dbgu_uart, new_uart;
1820         /* ASCII decoding for IP version */
1821         usart = 0x55534152;     /* USAR(T) */
1822         dbgu_uart = 0x44424755; /* DBGU */
1823         new_uart = 0x55415254;  /* UART */
1824 
1825         /*
1826          * Only USART devices from at91sam9260 SOC implement fractional
1827          * baudrate. It is available for all asynchronous modes, with the
1828          * following restriction: the sampling clock's duty cycle is not
1829          * constant.
1830          */
1831         atmel_port->has_frac_baudrate = false;
1832         atmel_port->has_hw_timer = false;
1833 
1834         if (name == new_uart) {
1835                 dev_dbg(port->dev, "Uart with hw timer");
1836                 atmel_port->has_hw_timer = true;
1837                 atmel_port->rtor = ATMEL_UA_RTOR;
1838         } else if (name == usart) {
1839                 dev_dbg(port->dev, "Usart\n");
1840                 atmel_port->has_frac_baudrate = true;
1841                 atmel_port->has_hw_timer = true;
1842                 atmel_port->rtor = ATMEL_US_RTOR;
1843                 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1844                 switch (version) {
1845                 case 0x814:     /* sama5d2 */
1846                         /* fall through */
1847                 case 0x701:     /* sama5d4 */
1848                         atmel_port->fidi_min = 3;
1849                         atmel_port->fidi_max = 65535;
1850                         break;
1851                 case 0x502:     /* sam9x5, sama5d3 */
1852                         atmel_port->fidi_min = 3;
1853                         atmel_port->fidi_max = 2047;
1854                         break;
1855                 default:
1856                         atmel_port->fidi_min = 1;
1857                         atmel_port->fidi_max = 2047;
1858                 }
1859         } else if (name == dbgu_uart) {
1860                 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1861         } else {
1862                 /* fallback for older SoCs: use version field */
1863                 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1864                 switch (version) {
1865                 case 0x302:
1866                 case 0x10213:
1867                 case 0x10302:
1868                         dev_dbg(port->dev, "This version is usart\n");
1869                         atmel_port->has_frac_baudrate = true;
1870                         atmel_port->has_hw_timer = true;
1871                         atmel_port->rtor = ATMEL_US_RTOR;
1872                         break;
1873                 case 0x203:
1874                 case 0x10202:
1875                         dev_dbg(port->dev, "This version is uart\n");
1876                         break;
1877                 default:
1878                         dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1879                 }
1880         }
1881 }
1882 
1883 /*
1884  * Perform initialization and enable port for reception
1885  */
1886 static int atmel_startup(struct uart_port *port)
1887 {
1888         struct platform_device *pdev = to_platform_device(port->dev);
1889         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1890         int retval;
1891 
1892         /*
1893          * Ensure that no interrupts are enabled otherwise when
1894          * request_irq() is called we could get stuck trying to
1895          * handle an unexpected interrupt
1896          */
1897         atmel_uart_writel(port, ATMEL_US_IDR, -1);
1898         atmel_port->ms_irq_enabled = false;
1899 
1900         /*
1901          * Allocate the IRQ
1902          */
1903         retval = request_irq(port->irq, atmel_interrupt,
1904                              IRQF_SHARED | IRQF_COND_SUSPEND,
1905                              dev_name(&pdev->dev), port);
1906         if (retval) {
1907                 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1908                 return retval;
1909         }
1910 
1911         atomic_set(&atmel_port->tasklet_shutdown, 0);
1912         tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1913                         (unsigned long)port);
1914         tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1915                         (unsigned long)port);
1916 
1917         /*
1918          * Initialize DMA (if necessary)
1919          */
1920         atmel_init_property(atmel_port, pdev);
1921         atmel_set_ops(port);
1922 
1923         if (atmel_port->prepare_rx) {
1924                 retval = atmel_port->prepare_rx(port);
1925                 if (retval < 0)
1926                         atmel_set_ops(port);
1927         }
1928 
1929         if (atmel_port->prepare_tx) {
1930                 retval = atmel_port->prepare_tx(port);
1931                 if (retval < 0)
1932                         atmel_set_ops(port);
1933         }
1934 
1935         /*
1936          * Enable FIFO when available
1937          */
1938         if (atmel_port->fifo_size) {
1939                 unsigned int txrdym = ATMEL_US_ONE_DATA;
1940                 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1941                 unsigned int fmr;
1942 
1943                 atmel_uart_writel(port, ATMEL_US_CR,
1944                                   ATMEL_US_FIFOEN |
1945                                   ATMEL_US_RXFCLR |
1946                                   ATMEL_US_TXFLCLR);
1947 
1948                 if (atmel_use_dma_tx(port))
1949                         txrdym = ATMEL_US_FOUR_DATA;
1950 
1951                 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1952                 if (atmel_port->rts_high &&
1953                     atmel_port->rts_low)
1954                         fmr |=  ATMEL_US_FRTSC |
1955                                 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1956                                 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1957 
1958                 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1959         }
1960 
1961         /* Save current CSR for comparison in atmel_tasklet_func() */
1962         atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1963 
1964         /*
1965          * Finally, enable the serial port
1966          */
1967         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1968         /* enable xmit & rcvr */
1969         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1970         atmel_port->tx_stopped = false;
1971 
1972         timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1973 
1974         if (atmel_use_pdc_rx(port)) {
1975                 /* set UART timeout */
1976                 if (!atmel_port->has_hw_timer) {
1977                         mod_timer(&atmel_port->uart_timer,
1978                                         jiffies + uart_poll_timeout(port));
1979                 /* set USART timeout */
1980                 } else {
1981                         atmel_uart_writel(port, atmel_port->rtor,
1982                                           PDC_RX_TIMEOUT);
1983                         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1984 
1985                         atmel_uart_writel(port, ATMEL_US_IER,
1986                                           ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1987                 }
1988                 /* enable PDC controller */
1989                 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1990         } else if (atmel_use_dma_rx(port)) {
1991                 /* set UART timeout */
1992                 if (!atmel_port->has_hw_timer) {
1993                         mod_timer(&atmel_port->uart_timer,
1994                                         jiffies + uart_poll_timeout(port));
1995                 /* set USART timeout */
1996                 } else {
1997                         atmel_uart_writel(port, atmel_port->rtor,
1998                                           PDC_RX_TIMEOUT);
1999                         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
2000 
2001                         atmel_uart_writel(port, ATMEL_US_IER,
2002                                           ATMEL_US_TIMEOUT);
2003                 }
2004         } else {
2005                 /* enable receive only */
2006                 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2007         }
2008 
2009         return 0;
2010 }
2011 
2012 /*
2013  * Flush any TX data submitted for DMA. Called when the TX circular
2014  * buffer is reset.
2015  */
2016 static void atmel_flush_buffer(struct uart_port *port)
2017 {
2018         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2019 
2020         if (atmel_use_pdc_tx(port)) {
2021                 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2022                 atmel_port->pdc_tx.ofs = 0;
2023         }
2024         /*
2025          * in uart_flush_buffer(), the xmit circular buffer has just
2026          * been cleared, so we have to reset tx_len accordingly.
2027          */
2028         atmel_port->tx_len = 0;
2029 }
2030 
2031 /*
2032  * Disable the port
2033  */
2034 static void atmel_shutdown(struct uart_port *port)
2035 {
2036         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2037 
2038         /* Disable modem control lines interrupts */
2039         atmel_disable_ms(port);
2040 
2041         /* Disable interrupts at device level */
2042         atmel_uart_writel(port, ATMEL_US_IDR, -1);
2043 
2044         /* Prevent spurious interrupts from scheduling the tasklet */
2045         atomic_inc(&atmel_port->tasklet_shutdown);
2046 
2047         /*
2048          * Prevent any tasklets being scheduled during
2049          * cleanup
2050          */
2051         del_timer_sync(&atmel_port->uart_timer);
2052 
2053         /* Make sure that no interrupt is on the fly */
2054         synchronize_irq(port->irq);
2055 
2056         /*
2057          * Clear out any scheduled tasklets before
2058          * we destroy the buffers
2059          */
2060         tasklet_kill(&atmel_port->tasklet_rx);
2061         tasklet_kill(&atmel_port->tasklet_tx);
2062 
2063         /*
2064          * Ensure everything is stopped and
2065          * disable port and break condition.
2066          */
2067         atmel_stop_rx(port);
2068         atmel_stop_tx(port);
2069 
2070         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2071 
2072         /*
2073          * Shut-down the DMA.
2074          */
2075         if (atmel_port->release_rx)
2076                 atmel_port->release_rx(port);
2077         if (atmel_port->release_tx)
2078                 atmel_port->release_tx(port);
2079 
2080         /*
2081          * Reset ring buffer pointers
2082          */
2083         atmel_port->rx_ring.head = 0;
2084         atmel_port->rx_ring.tail = 0;
2085 
2086         /*
2087          * Free the interrupts
2088          */
2089         free_irq(port->irq, port);
2090 
2091         atmel_flush_buffer(port);
2092 }
2093 
2094 /*
2095  * Power / Clock management.
2096  */
2097 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2098                             unsigned int oldstate)
2099 {
2100         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2101 
2102         switch (state) {
2103         case 0:
2104                 /*
2105                  * Enable the peripheral clock for this serial port.
2106                  * This is called on uart_open() or a resume event.
2107                  */
2108                 clk_prepare_enable(atmel_port->clk);
2109 
2110                 /* re-enable interrupts if we disabled some on suspend */
2111                 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2112                 break;
2113         case 3:
2114                 /* Back up the interrupt mask and disable all interrupts */
2115                 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2116                 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2117 
2118                 /*
2119                  * Disable the peripheral clock for this serial port.
2120                  * This is called on uart_close() or a suspend event.
2121                  */
2122                 clk_disable_unprepare(atmel_port->clk);
2123                 break;
2124         default:
2125                 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2126         }
2127 }
2128 
2129 /*
2130  * Change the port parameters
2131  */
2132 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2133                               struct ktermios *old)
2134 {
2135         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2136         unsigned long flags;
2137         unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2138 
2139         /* save the current mode register */
2140         mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2141 
2142         /* reset the mode, clock divisor, parity, stop bits and data size */
2143         mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2144                   ATMEL_US_PAR | ATMEL_US_USMODE);
2145 
2146         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2147 
2148         /* byte size */
2149         switch (termios->c_cflag & CSIZE) {
2150         case CS5:
2151                 mode |= ATMEL_US_CHRL_5;
2152                 break;
2153         case CS6:
2154                 mode |= ATMEL_US_CHRL_6;
2155                 break;
2156         case CS7:
2157                 mode |= ATMEL_US_CHRL_7;
2158                 break;
2159         default:
2160                 mode |= ATMEL_US_CHRL_8;
2161                 break;
2162         }
2163 
2164         /* stop bits */
2165         if (termios->c_cflag & CSTOPB)
2166                 mode |= ATMEL_US_NBSTOP_2;
2167 
2168         /* parity */
2169         if (termios->c_cflag & PARENB) {
2170                 /* Mark or Space parity */
2171                 if (termios->c_cflag & CMSPAR) {
2172                         if (termios->c_cflag & PARODD)
2173                                 mode |= ATMEL_US_PAR_MARK;
2174                         else
2175                                 mode |= ATMEL_US_PAR_SPACE;
2176                 } else if (termios->c_cflag & PARODD)
2177                         mode |= ATMEL_US_PAR_ODD;
2178                 else
2179                         mode |= ATMEL_US_PAR_EVEN;
2180         } else
2181                 mode |= ATMEL_US_PAR_NONE;
2182 
2183         spin_lock_irqsave(&port->lock, flags);
2184 
2185         port->read_status_mask = ATMEL_US_OVRE;
2186         if (termios->c_iflag & INPCK)
2187                 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2188         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2189                 port->read_status_mask |= ATMEL_US_RXBRK;
2190 
2191         if (atmel_use_pdc_rx(port))
2192                 /* need to enable error interrupts */
2193                 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2194 
2195         /*
2196          * Characters to ignore
2197          */
2198         port->ignore_status_mask = 0;
2199         if (termios->c_iflag & IGNPAR)
2200                 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2201         if (termios->c_iflag & IGNBRK) {
2202                 port->ignore_status_mask |= ATMEL_US_RXBRK;
2203                 /*
2204                  * If we're ignoring parity and break indicators,
2205                  * ignore overruns too (for real raw support).
2206                  */
2207                 if (termios->c_iflag & IGNPAR)
2208                         port->ignore_status_mask |= ATMEL_US_OVRE;
2209         }
2210         /* TODO: Ignore all characters if CREAD is set.*/
2211 
2212         /* update the per-port timeout */
2213         uart_update_timeout(port, termios->c_cflag, baud);
2214 
2215         /*
2216          * save/disable interrupts. The tty layer will ensure that the
2217          * transmitter is empty if requested by the caller, so there's
2218          * no need to wait for it here.
2219          */
2220         imr = atmel_uart_readl(port, ATMEL_US_IMR);
2221         atmel_uart_writel(port, ATMEL_US_IDR, -1);
2222 
2223         /* disable receiver and transmitter */
2224         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2225         atmel_port->tx_stopped = true;
2226 
2227         /* mode */
2228         if (port->rs485.flags & SER_RS485_ENABLED) {
2229                 atmel_uart_writel(port, ATMEL_US_TTGR,
2230                                   port->rs485.delay_rts_after_send);
2231                 mode |= ATMEL_US_USMODE_RS485;
2232         } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2233                 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2234                 /* select mck clock, and output  */
2235                 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2236                 /* set max iterations */
2237                 mode |= ATMEL_US_MAX_ITER(3);
2238                 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2239                                 == SER_ISO7816_T(0))
2240                         mode |= ATMEL_US_USMODE_ISO7816_T0;
2241                 else
2242                         mode |= ATMEL_US_USMODE_ISO7816_T1;
2243         } else if (termios->c_cflag & CRTSCTS) {
2244                 /* RS232 with hardware handshake (RTS/CTS) */
2245                 if (atmel_use_fifo(port) &&
2246                     !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2247                         /*
2248                          * with ATMEL_US_USMODE_HWHS set, the controller will
2249                          * be able to drive the RTS pin high/low when the RX
2250                          * FIFO is above RXFTHRES/below RXFTHRES2.
2251                          * It will also disable the transmitter when the CTS
2252                          * pin is high.
2253                          * This mode is not activated if CTS pin is a GPIO
2254                          * because in this case, the transmitter is always
2255                          * disabled (there must be an internal pull-up
2256                          * responsible for this behaviour).
2257                          * If the RTS pin is a GPIO, the controller won't be
2258                          * able to drive it according to the FIFO thresholds,
2259                          * but it will be handled by the driver.
2260                          */
2261                         mode |= ATMEL_US_USMODE_HWHS;
2262                 } else {
2263                         /*
2264                          * For platforms without FIFO, the flow control is
2265                          * handled by the driver.
2266                          */
2267                         mode |= ATMEL_US_USMODE_NORMAL;
2268                 }
2269         } else {
2270                 /* RS232 without hadware handshake */
2271                 mode |= ATMEL_US_USMODE_NORMAL;
2272         }
2273 
2274         /*
2275          * Set the baud rate:
2276          * Fractional baudrate allows to setup output frequency more
2277          * accurately. This feature is enabled only when using normal mode.
2278          * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2279          * Currently, OVER is always set to 0 so we get
2280          * baudrate = selected clock / (16 * (CD + FP / 8))
2281          * then
2282          * 8 CD + FP = selected clock / (2 * baudrate)
2283          */
2284         if (atmel_port->has_frac_baudrate) {
2285                 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2286                 cd = div >> 3;
2287                 fp = div & ATMEL_US_FP_MASK;
2288         } else {
2289                 cd = uart_get_divisor(port, baud);
2290         }
2291 
2292         if (cd > 65535) {       /* BRGR is 16-bit, so switch to slower clock */
2293                 cd /= 8;
2294                 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2295         }
2296         quot = cd | fp << ATMEL_US_FP_OFFSET;
2297 
2298         if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2299                 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2300 
2301         /* set the mode, clock divisor, parity, stop bits and data size */
2302         atmel_uart_writel(port, ATMEL_US_MR, mode);
2303 
2304         /*
2305          * when switching the mode, set the RTS line state according to the
2306          * new mode, otherwise keep the former state
2307          */
2308         if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2309                 unsigned int rts_state;
2310 
2311                 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2312                         /* let the hardware control the RTS line */
2313                         rts_state = ATMEL_US_RTSDIS;
2314                 } else {
2315                         /* force RTS line to low level */
2316                         rts_state = ATMEL_US_RTSEN;
2317                 }
2318 
2319                 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2320         }
2321 
2322         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2323         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2324         atmel_port->tx_stopped = false;
2325 
2326         /* restore interrupts */
2327         atmel_uart_writel(port, ATMEL_US_IER, imr);
2328 
2329         /* CTS flow-control and modem-status interrupts */
2330         if (UART_ENABLE_MS(port, termios->c_cflag))
2331                 atmel_enable_ms(port);
2332         else
2333                 atmel_disable_ms(port);
2334 
2335         spin_unlock_irqrestore(&port->lock, flags);
2336 }
2337 
2338 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2339 {
2340         if (termios->c_line == N_PPS) {
2341                 port->flags |= UPF_HARDPPS_CD;
2342                 spin_lock_irq(&port->lock);
2343                 atmel_enable_ms(port);
2344                 spin_unlock_irq(&port->lock);
2345         } else {
2346                 port->flags &= ~UPF_HARDPPS_CD;
2347                 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2348                         spin_lock_irq(&port->lock);
2349                         atmel_disable_ms(port);
2350                         spin_unlock_irq(&port->lock);
2351                 }
2352         }
2353 }
2354 
2355 /*
2356  * Return string describing the specified port
2357  */
2358 static const char *atmel_type(struct uart_port *port)
2359 {
2360         return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2361 }
2362 
2363 /*
2364  * Release the memory region(s) being used by 'port'.
2365  */
2366 static void atmel_release_port(struct uart_port *port)
2367 {
2368         struct platform_device *mpdev = to_platform_device(port->dev->parent);
2369         int size = resource_size(mpdev->resource);
2370 
2371         release_mem_region(port->mapbase, size);
2372 
2373         if (port->flags & UPF_IOREMAP) {
2374                 iounmap(port->membase);
2375                 port->membase = NULL;
2376         }
2377 }
2378 
2379 /*
2380  * Request the memory region(s) being used by 'port'.
2381  */
2382 static int atmel_request_port(struct uart_port *port)
2383 {
2384         struct platform_device *mpdev = to_platform_device(port->dev->parent);
2385         int size = resource_size(mpdev->resource);
2386 
2387         if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2388                 return -EBUSY;
2389 
2390         if (port->flags & UPF_IOREMAP) {
2391                 port->membase = ioremap(port->mapbase, size);
2392                 if (port->membase == NULL) {
2393                         release_mem_region(port->mapbase, size);
2394                         return -ENOMEM;
2395                 }
2396         }
2397 
2398         return 0;
2399 }
2400 
2401 /*
2402  * Configure/autoconfigure the port.
2403  */
2404 static void atmel_config_port(struct uart_port *port, int flags)
2405 {
2406         if (flags & UART_CONFIG_TYPE) {
2407                 port->type = PORT_ATMEL;
2408                 atmel_request_port(port);
2409         }
2410 }
2411 
2412 /*
2413  * Verify the new serial_struct (for TIOCSSERIAL).
2414  */
2415 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2416 {
2417         int ret = 0;
2418         if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2419                 ret = -EINVAL;
2420         if (port->irq != ser->irq)
2421                 ret = -EINVAL;
2422         if (ser->io_type != SERIAL_IO_MEM)
2423                 ret = -EINVAL;
2424         if (port->uartclk / 16 != ser->baud_base)
2425                 ret = -EINVAL;
2426         if (port->mapbase != (unsigned long)ser->iomem_base)
2427                 ret = -EINVAL;
2428         if (port->iobase != ser->port)
2429                 ret = -EINVAL;
2430         if (ser->hub6 != 0)
2431                 ret = -EINVAL;
2432         return ret;
2433 }
2434 
2435 #ifdef CONFIG_CONSOLE_POLL
2436 static int atmel_poll_get_char(struct uart_port *port)
2437 {
2438         while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2439                 cpu_relax();
2440 
2441         return atmel_uart_read_char(port);
2442 }
2443 
2444 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2445 {
2446         while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2447                 cpu_relax();
2448 
2449         atmel_uart_write_char(port, ch);
2450 }
2451 #endif
2452 
2453 static const struct uart_ops atmel_pops = {
2454         .tx_empty       = atmel_tx_empty,
2455         .set_mctrl      = atmel_set_mctrl,
2456         .get_mctrl      = atmel_get_mctrl,
2457         .stop_tx        = atmel_stop_tx,
2458         .start_tx       = atmel_start_tx,
2459         .stop_rx        = atmel_stop_rx,
2460         .enable_ms      = atmel_enable_ms,
2461         .break_ctl      = atmel_break_ctl,
2462         .startup        = atmel_startup,
2463         .shutdown       = atmel_shutdown,
2464         .flush_buffer   = atmel_flush_buffer,
2465         .set_termios    = atmel_set_termios,
2466         .set_ldisc      = atmel_set_ldisc,
2467         .type           = atmel_type,
2468         .release_port   = atmel_release_port,
2469         .request_port   = atmel_request_port,
2470         .config_port    = atmel_config_port,
2471         .verify_port    = atmel_verify_port,
2472         .pm             = atmel_serial_pm,
2473 #ifdef CONFIG_CONSOLE_POLL
2474         .poll_get_char  = atmel_poll_get_char,
2475         .poll_put_char  = atmel_poll_put_char,
2476 #endif
2477 };
2478 
2479 /*
2480  * Configure the port from the platform device resource info.
2481  */
2482 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2483                                       struct platform_device *pdev)
2484 {
2485         int ret;
2486         struct uart_port *port = &atmel_port->uart;
2487         struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2488 
2489         atmel_init_property(atmel_port, pdev);
2490         atmel_set_ops(port);
2491 
2492         uart_get_rs485_mode(&mpdev->dev, &port->rs485);
2493 
2494         port->iotype            = UPIO_MEM;
2495         port->flags             = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2496         port->ops               = &atmel_pops;
2497         port->fifosize          = 1;
2498         port->dev               = &pdev->dev;
2499         port->mapbase           = mpdev->resource[0].start;
2500         port->irq               = mpdev->resource[1].start;
2501         port->rs485_config      = atmel_config_rs485;
2502         port->iso7816_config    = atmel_config_iso7816;
2503         port->membase           = NULL;
2504 
2505         memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2506 
2507         /* for console, the clock could already be configured */
2508         if (!atmel_port->clk) {
2509                 atmel_port->clk = clk_get(&mpdev->dev, "usart");
2510                 if (IS_ERR(atmel_port->clk)) {
2511                         ret = PTR_ERR(atmel_port->clk);
2512                         atmel_port->clk = NULL;
2513                         return ret;
2514                 }
2515                 ret = clk_prepare_enable(atmel_port->clk);
2516                 if (ret) {
2517                         clk_put(atmel_port->clk);
2518                         atmel_port->clk = NULL;
2519                         return ret;
2520                 }
2521                 port->uartclk = clk_get_rate(atmel_port->clk);
2522                 clk_disable_unprepare(atmel_port->clk);
2523                 /* only enable clock when USART is in use */
2524         }
2525 
2526         /*
2527          * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2528          * ENDTX|TXBUFE
2529          */
2530         if (port->rs485.flags & SER_RS485_ENABLED ||
2531             port->iso7816.flags & SER_ISO7816_ENABLED)
2532                 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2533         else if (atmel_use_pdc_tx(port)) {
2534                 port->fifosize = PDC_BUFFER_SIZE;
2535                 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2536         } else {
2537                 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2538         }
2539 
2540         return 0;
2541 }
2542 
2543 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2544 static void atmel_console_putchar(struct uart_port *port, int ch)
2545 {
2546         while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2547                 cpu_relax();
2548         atmel_uart_write_char(port, ch);
2549 }
2550 
2551 /*
2552  * Interrupts are disabled on entering
2553  */
2554 static void atmel_console_write(struct console *co, const char *s, u_int count)
2555 {
2556         struct uart_port *port = &atmel_ports[co->index].uart;
2557         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2558         unsigned int status, imr;
2559         unsigned int pdc_tx;
2560 
2561         /*
2562          * First, save IMR and then disable interrupts
2563          */
2564         imr = atmel_uart_readl(port, ATMEL_US_IMR);
2565         atmel_uart_writel(port, ATMEL_US_IDR,
2566                           ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2567 
2568         /* Store PDC transmit status and disable it */
2569         pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2570         atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2571 
2572         /* Make sure that tx path is actually able to send characters */
2573         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2574         atmel_port->tx_stopped = false;
2575 
2576         uart_console_write(port, s, count, atmel_console_putchar);
2577 
2578         /*
2579          * Finally, wait for transmitter to become empty
2580          * and restore IMR
2581          */
2582         do {
2583                 status = atmel_uart_readl(port, ATMEL_US_CSR);
2584         } while (!(status & ATMEL_US_TXRDY));
2585 
2586         /* Restore PDC transmit status */
2587         if (pdc_tx)
2588                 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2589 
2590         /* set interrupts back the way they were */
2591         atmel_uart_writel(port, ATMEL_US_IER, imr);
2592 }
2593 
2594 /*
2595  * If the port was already initialised (eg, by a boot loader),
2596  * try to determine the current setup.
2597  */
2598 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2599                                              int *parity, int *bits)
2600 {
2601         unsigned int mr, quot;
2602 
2603         /*
2604          * If the baud rate generator isn't running, the port wasn't
2605          * initialized by the boot loader.
2606          */
2607         quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2608         if (!quot)
2609                 return;
2610 
2611         mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2612         if (mr == ATMEL_US_CHRL_8)
2613                 *bits = 8;
2614         else
2615                 *bits = 7;
2616 
2617         mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2618         if (mr == ATMEL_US_PAR_EVEN)
2619                 *parity = 'e';
2620         else if (mr == ATMEL_US_PAR_ODD)
2621                 *parity = 'o';
2622 
2623         /*
2624          * The serial core only rounds down when matching this to a
2625          * supported baud rate. Make sure we don't end up slightly
2626          * lower than one of those, as it would make us fall through
2627          * to a much lower baud rate than we really want.
2628          */
2629         *baud = port->uartclk / (16 * (quot - 1));
2630 }
2631 
2632 static int __init atmel_console_setup(struct console *co, char *options)
2633 {
2634         int ret;
2635         struct uart_port *port = &atmel_ports[co->index].uart;
2636         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2637         int baud = 115200;
2638         int bits = 8;
2639         int parity = 'n';
2640         int flow = 'n';
2641 
2642         if (port->membase == NULL) {
2643                 /* Port not initialized yet - delay setup */
2644                 return -ENODEV;
2645         }
2646 
2647         ret = clk_prepare_enable(atmel_ports[co->index].clk);
2648         if (ret)
2649                 return ret;
2650 
2651         atmel_uart_writel(port, ATMEL_US_IDR, -1);
2652         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2653         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2654         atmel_port->tx_stopped = false;
2655 
2656         if (options)
2657                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2658         else
2659                 atmel_console_get_options(port, &baud, &parity, &bits);
2660 
2661         return uart_set_options(port, co, baud, parity, bits, flow);
2662 }
2663 
2664 static struct uart_driver atmel_uart;
2665 
2666 static struct console atmel_console = {
2667         .name           = ATMEL_DEVICENAME,
2668         .write          = atmel_console_write,
2669         .device         = uart_console_device,
2670         .setup          = atmel_console_setup,
2671         .flags          = CON_PRINTBUFFER,
2672         .index          = -1,
2673         .data           = &atmel_uart,
2674 };
2675 
2676 #define ATMEL_CONSOLE_DEVICE    (&atmel_console)
2677 
2678 static inline bool atmel_is_console_port(struct uart_port *port)
2679 {
2680         return port->cons && port->cons->index == port->line;
2681 }
2682 
2683 #else
2684 #define ATMEL_CONSOLE_DEVICE    NULL
2685 
2686 static inline bool atmel_is_console_port(struct uart_port *port)
2687 {
2688         return false;
2689 }
2690 #endif
2691 
2692 static struct uart_driver atmel_uart = {
2693         .owner          = THIS_MODULE,
2694         .driver_name    = "atmel_serial",
2695         .dev_name       = ATMEL_DEVICENAME,
2696         .major          = SERIAL_ATMEL_MAJOR,
2697         .minor          = MINOR_START,
2698         .nr             = ATMEL_MAX_UART,
2699         .cons           = ATMEL_CONSOLE_DEVICE,
2700 };
2701 
2702 #ifdef CONFIG_PM
2703 static bool atmel_serial_clk_will_stop(void)
2704 {
2705 #ifdef CONFIG_ARCH_AT91
2706         return at91_suspend_entering_slow_clock();
2707 #else
2708         return false;
2709 #endif
2710 }
2711 
2712 static int atmel_serial_suspend(struct platform_device *pdev,
2713                                 pm_message_t state)
2714 {
2715         struct uart_port *port = platform_get_drvdata(pdev);
2716         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2717 
2718         if (atmel_is_console_port(port) && console_suspend_enabled) {
2719                 /* Drain the TX shifter */
2720                 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2721                          ATMEL_US_TXEMPTY))
2722                         cpu_relax();
2723         }
2724 
2725         if (atmel_is_console_port(port) && !console_suspend_enabled) {
2726                 /* Cache register values as we won't get a full shutdown/startup
2727                  * cycle
2728                  */
2729                 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2730                 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2731                 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2732                 atmel_port->cache.rtor = atmel_uart_readl(port,
2733                                                           atmel_port->rtor);
2734                 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2735                 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2736                 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2737         }
2738 
2739         /* we can not wake up if we're running on slow clock */
2740         atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2741         if (atmel_serial_clk_will_stop()) {
2742                 unsigned long flags;
2743 
2744                 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2745                 atmel_port->suspended = true;
2746                 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2747                 device_set_wakeup_enable(&pdev->dev, 0);
2748         }
2749 
2750         uart_suspend_port(&atmel_uart, port);
2751 
2752         return 0;
2753 }
2754 
2755 static int atmel_serial_resume(struct platform_device *pdev)
2756 {
2757         struct uart_port *port = platform_get_drvdata(pdev);
2758         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2759         unsigned long flags;
2760 
2761         if (atmel_is_console_port(port) && !console_suspend_enabled) {
2762                 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2763                 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2764                 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2765                 atmel_uart_writel(port, atmel_port->rtor,
2766                                   atmel_port->cache.rtor);
2767                 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2768 
2769                 if (atmel_port->fifo_size) {
2770                         atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2771                                           ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2772                         atmel_uart_writel(port, ATMEL_US_FMR,
2773                                           atmel_port->cache.fmr);
2774                         atmel_uart_writel(port, ATMEL_US_FIER,
2775                                           atmel_port->cache.fimr);
2776                 }
2777                 atmel_start_rx(port);
2778         }
2779 
2780         spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2781         if (atmel_port->pending) {
2782                 atmel_handle_receive(port, atmel_port->pending);
2783                 atmel_handle_status(port, atmel_port->pending,
2784                                     atmel_port->pending_status);
2785                 atmel_handle_transmit(port, atmel_port->pending);
2786                 atmel_port->pending = 0;
2787         }
2788         atmel_port->suspended = false;
2789         spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2790 
2791         uart_resume_port(&atmel_uart, port);
2792         device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2793 
2794         return 0;
2795 }
2796 #else
2797 #define atmel_serial_suspend NULL
2798 #define atmel_serial_resume NULL
2799 #endif
2800 
2801 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2802                                      struct platform_device *pdev)
2803 {
2804         atmel_port->fifo_size = 0;
2805         atmel_port->rts_low = 0;
2806         atmel_port->rts_high = 0;
2807 
2808         if (of_property_read_u32(pdev->dev.of_node,
2809                                  "atmel,fifo-size",
2810                                  &atmel_port->fifo_size))
2811                 return;
2812 
2813         if (!atmel_port->fifo_size)
2814                 return;
2815 
2816         if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2817                 atmel_port->fifo_size = 0;
2818                 dev_err(&pdev->dev, "Invalid FIFO size\n");
2819                 return;
2820         }
2821 
2822         /*
2823          * 0 <= rts_low <= rts_high <= fifo_size
2824          * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2825          * to flush their internal TX FIFO, commonly up to 16 data, before
2826          * actually stopping to send new data. So we try to set the RTS High
2827          * Threshold to a reasonably high value respecting this 16 data
2828          * empirical rule when possible.
2829          */
2830         atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2831                                atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2832         atmel_port->rts_low  = max_t(int, atmel_port->fifo_size >> 2,
2833                                atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2834 
2835         dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2836                  atmel_port->fifo_size);
2837         dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2838                 atmel_port->rts_high);
2839         dev_dbg(&pdev->dev, "RTS Low Threshold  : %2u data\n",
2840                 atmel_port->rts_low);
2841 }
2842 
2843 static int atmel_serial_probe(struct platform_device *pdev)
2844 {
2845         struct atmel_uart_port *atmel_port;
2846         struct device_node *np = pdev->dev.parent->of_node;
2847         void *data;
2848         int ret;
2849         bool rs485_enabled;
2850 
2851         BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2852 
2853         /*
2854          * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2855          * as compatible string. This driver is probed by at91-usart mfd driver
2856          * which is just a wrapper over the atmel_serial driver and
2857          * spi-at91-usart driver. All attributes needed by this driver are
2858          * found in of_node of parent.
2859          */
2860         pdev->dev.of_node = np;
2861 
2862         ret = of_alias_get_id(np, "serial");
2863         if (ret < 0)
2864                 /* port id not found in platform data nor device-tree aliases:
2865                  * auto-enumerate it */
2866                 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2867 
2868         if (ret >= ATMEL_MAX_UART) {
2869                 ret = -ENODEV;
2870                 goto err;
2871         }
2872 
2873         if (test_and_set_bit(ret, atmel_ports_in_use)) {
2874                 /* port already in use */
2875                 ret = -EBUSY;
2876                 goto err;
2877         }
2878 
2879         atmel_port = &atmel_ports[ret];
2880         atmel_port->backup_imr = 0;
2881         atmel_port->uart.line = ret;
2882         atmel_serial_probe_fifos(atmel_port, pdev);
2883 
2884         atomic_set(&atmel_port->tasklet_shutdown, 0);
2885         spin_lock_init(&atmel_port->lock_suspended);
2886 
2887         ret = atmel_init_port(atmel_port, pdev);
2888         if (ret)
2889                 goto err_clear_bit;
2890 
2891         atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2892         if (IS_ERR(atmel_port->gpios)) {
2893                 ret = PTR_ERR(atmel_port->gpios);
2894                 goto err_clear_bit;
2895         }
2896 
2897         if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2898                 ret = -ENOMEM;
2899                 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2900                                      sizeof(struct atmel_uart_char),
2901                                      GFP_KERNEL);
2902                 if (!data)
2903                         goto err_alloc_ring;
2904                 atmel_port->rx_ring.buf = data;
2905         }
2906 
2907         rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2908 
2909         ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2910         if (ret)
2911                 goto err_add_port;
2912 
2913 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2914         if (atmel_is_console_port(&atmel_port->uart)
2915                         && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2916                 /*
2917                  * The serial core enabled the clock for us, so undo
2918                  * the clk_prepare_enable() in atmel_console_setup()
2919                  */
2920                 clk_disable_unprepare(atmel_port->clk);
2921         }
2922 #endif
2923 
2924         device_init_wakeup(&pdev->dev, 1);
2925         platform_set_drvdata(pdev, atmel_port);
2926 
2927         /*
2928          * The peripheral clock has been disabled by atmel_init_port():
2929          * enable it before accessing I/O registers
2930          */
2931         clk_prepare_enable(atmel_port->clk);
2932 
2933         if (rs485_enabled) {
2934                 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2935                                   ATMEL_US_USMODE_NORMAL);
2936                 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2937                                   ATMEL_US_RTSEN);
2938         }
2939 
2940         /*
2941          * Get port name of usart or uart
2942          */
2943         atmel_get_ip_name(&atmel_port->uart);
2944 
2945         /*
2946          * The peripheral clock can now safely be disabled till the port
2947          * is used
2948          */
2949         clk_disable_unprepare(atmel_port->clk);
2950 
2951         return 0;
2952 
2953 err_add_port:
2954         kfree(atmel_port->rx_ring.buf);
2955         atmel_port->rx_ring.buf = NULL;
2956 err_alloc_ring:
2957         if (!atmel_is_console_port(&atmel_port->uart)) {
2958                 clk_put(atmel_port->clk);
2959                 atmel_port->clk = NULL;
2960         }
2961 err_clear_bit:
2962         clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2963 err:
2964         return ret;
2965 }
2966 
2967 /*
2968  * Even if the driver is not modular, it makes sense to be able to
2969  * unbind a device: there can be many bound devices, and there are
2970  * situations where dynamic binding and unbinding can be useful.
2971  *
2972  * For example, a connected device can require a specific firmware update
2973  * protocol that needs bitbanging on IO lines, but use the regular serial
2974  * port in the normal case.
2975  */
2976 static int atmel_serial_remove(struct platform_device *pdev)
2977 {
2978         struct uart_port *port = platform_get_drvdata(pdev);
2979         struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2980         int ret = 0;
2981 
2982         tasklet_kill(&atmel_port->tasklet_rx);
2983         tasklet_kill(&atmel_port->tasklet_tx);
2984 
2985         device_init_wakeup(&pdev->dev, 0);
2986 
2987         ret = uart_remove_one_port(&atmel_uart, port);
2988 
2989         kfree(atmel_port->rx_ring.buf);
2990 
2991         /* "port" is allocated statically, so we shouldn't free it */
2992 
2993         clear_bit(port->line, atmel_ports_in_use);
2994 
2995         clk_put(atmel_port->clk);
2996         atmel_port->clk = NULL;
2997         pdev->dev.of_node = NULL;
2998 
2999         return ret;
3000 }
3001 
3002 static struct platform_driver atmel_serial_driver = {
3003         .probe          = atmel_serial_probe,
3004         .remove         = atmel_serial_remove,
3005         .suspend        = atmel_serial_suspend,
3006         .resume         = atmel_serial_resume,
3007         .driver         = {
3008                 .name                   = "atmel_usart_serial",
3009                 .of_match_table         = of_match_ptr(atmel_serial_dt_ids),
3010         },
3011 };
3012 
3013 static int __init atmel_serial_init(void)
3014 {
3015         int ret;
3016 
3017         ret = uart_register_driver(&atmel_uart);
3018         if (ret)
3019                 return ret;
3020 
3021         ret = platform_driver_register(&atmel_serial_driver);
3022         if (ret)
3023                 uart_unregister_driver(&atmel_uart);
3024 
3025         return ret;
3026 }
3027 device_initcall(atmel_serial_init);
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/atmel_serial.c

DEFINITIONS
