This source file includes following definitions.
- loopback_show
- loopback_store
- qcom_geni_serial_request_port
- qcom_geni_serial_config_port
- qcom_geni_serial_get_mctrl
- qcom_geni_serial_set_mctrl
- qcom_geni_serial_get_type
- get_port_from_line
- qcom_geni_serial_poll_bit
- qcom_geni_serial_setup_tx
- qcom_geni_serial_poll_tx_done
- qcom_geni_serial_abort_rx
- qcom_geni_serial_get_char
- qcom_geni_serial_poll_put_char
- qcom_geni_serial_wr_char
- __qcom_geni_serial_console_write
- qcom_geni_serial_console_write
- handle_rx_console
- handle_rx_console
- handle_rx_uart
- qcom_geni_serial_start_tx
- qcom_geni_serial_stop_tx
- qcom_geni_serial_start_rx
- qcom_geni_serial_stop_rx
- qcom_geni_serial_handle_rx
- qcom_geni_serial_handle_tx
- qcom_geni_serial_isr
- get_tx_fifo_size
- qcom_geni_serial_shutdown
- qcom_geni_serial_port_setup
- qcom_geni_serial_startup
- get_clk_cfg
- get_clk_div_rate
- qcom_geni_serial_set_termios
- qcom_geni_serial_tx_empty
- qcom_geni_console_setup
- qcom_geni_serial_earlycon_write
- qcom_geni_serial_earlycon_setup
- console_register
- console_unregister
- console_register
- console_unregister
- qcom_geni_serial_pm
- qcom_geni_serial_probe
- qcom_geni_serial_remove
- qcom_geni_serial_sys_suspend
- qcom_geni_serial_sys_resume
- qcom_geni_serial_init
- qcom_geni_serial_exit
1
2
3
4 #if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5 # define SUPPORT_SYSRQ
6 #endif
7
8 #include <linux/clk.h>
9 #include <linux/console.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/qcom-geni-se.h>
17 #include <linux/serial.h>
18 #include <linux/serial_core.h>
19 #include <linux/slab.h>
20 #include <linux/tty.h>
21 #include <linux/tty_flip.h>
22
23
24 #define SE_UART_LOOPBACK_CFG 0x22c
25 #define SE_UART_TX_TRANS_CFG 0x25c
26 #define SE_UART_TX_WORD_LEN 0x268
27 #define SE_UART_TX_STOP_BIT_LEN 0x26c
28 #define SE_UART_TX_TRANS_LEN 0x270
29 #define SE_UART_RX_TRANS_CFG 0x280
30 #define SE_UART_RX_WORD_LEN 0x28c
31 #define SE_UART_RX_STALE_CNT 0x294
32 #define SE_UART_TX_PARITY_CFG 0x2a4
33 #define SE_UART_RX_PARITY_CFG 0x2a8
34 #define SE_UART_MANUAL_RFR 0x2ac
35
36
37 #define UART_TX_PAR_EN BIT(0)
38 #define UART_CTS_MASK BIT(1)
39
40
41 #define TX_WORD_LEN_MSK GENMASK(9, 0)
42
43
44 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
45 #define TX_STOP_BIT_LEN_1 0
46 #define TX_STOP_BIT_LEN_1_5 1
47 #define TX_STOP_BIT_LEN_2 2
48
49
50 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
51
52
53 #define UART_RX_INS_STATUS_BIT BIT(2)
54 #define UART_RX_PAR_EN BIT(3)
55
56
57 #define RX_WORD_LEN_MASK GENMASK(9, 0)
58
59
60 #define RX_STALE_CNT GENMASK(23, 0)
61
62
63 #define PAR_CALC_EN BIT(0)
64 #define PAR_MODE_MSK GENMASK(2, 1)
65 #define PAR_MODE_SHFT 1
66 #define PAR_EVEN 0x00
67 #define PAR_ODD 0x01
68 #define PAR_SPACE 0x10
69 #define PAR_MARK 0x11
70
71
72 #define UART_MANUAL_RFR_EN BIT(31)
73 #define UART_RFR_NOT_READY BIT(1)
74 #define UART_RFR_READY BIT(0)
75
76
77 #define UART_START_TX 0x1
78 #define UART_START_BREAK 0x4
79 #define UART_STOP_BREAK 0x5
80
81 #define UART_START_READ 0x1
82 #define UART_PARAM 0x1
83
84 #define UART_OVERSAMPLING 32
85 #define STALE_TIMEOUT 16
86 #define DEFAULT_BITS_PER_CHAR 10
87 #define GENI_UART_CONS_PORTS 1
88 #define GENI_UART_PORTS 3
89 #define DEF_FIFO_DEPTH_WORDS 16
90 #define DEF_TX_WM 2
91 #define DEF_FIFO_WIDTH_BITS 32
92 #define UART_RX_WM 2
93 #define MAX_LOOPBACK_CFG 3
94
95 #ifdef CONFIG_CONSOLE_POLL
96 #define CONSOLE_RX_BYTES_PW 1
97 #else
98 #define CONSOLE_RX_BYTES_PW 4
99 #endif
100
101 struct qcom_geni_serial_port {
102 struct uart_port uport;
103 struct geni_se se;
104 char name[20];
105 u32 tx_fifo_depth;
106 u32 tx_fifo_width;
107 u32 rx_fifo_depth;
108 bool setup;
109 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
110 unsigned int baud;
111 unsigned int tx_bytes_pw;
112 unsigned int rx_bytes_pw;
113 u32 *rx_fifo;
114 u32 loopback;
115 bool brk;
116
117 unsigned int tx_remaining;
118 };
119
120 static const struct uart_ops qcom_geni_console_pops;
121 static const struct uart_ops qcom_geni_uart_pops;
122 static struct uart_driver qcom_geni_console_driver;
123 static struct uart_driver qcom_geni_uart_driver;
124 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
125 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
126 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
127 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
128 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
129
130 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
131 32000000, 48000000, 64000000, 80000000,
132 96000000, 100000000, 102400000,
133 112000000, 120000000, 128000000};
134
135 #define to_dev_port(ptr, member) \
136 container_of(ptr, struct qcom_geni_serial_port, member)
137
138 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
139 [0] = {
140 .uport = {
141 .iotype = UPIO_MEM,
142 .ops = &qcom_geni_uart_pops,
143 .flags = UPF_BOOT_AUTOCONF,
144 .line = 0,
145 },
146 },
147 [1] = {
148 .uport = {
149 .iotype = UPIO_MEM,
150 .ops = &qcom_geni_uart_pops,
151 .flags = UPF_BOOT_AUTOCONF,
152 .line = 1,
153 },
154 },
155 [2] = {
156 .uport = {
157 .iotype = UPIO_MEM,
158 .ops = &qcom_geni_uart_pops,
159 .flags = UPF_BOOT_AUTOCONF,
160 .line = 2,
161 },
162 },
163 };
164
165 static ssize_t loopback_show(struct device *dev,
166 struct device_attribute *attr, char *buf)
167 {
168 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
169
170 return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
171 }
172
173 static ssize_t loopback_store(struct device *dev,
174 struct device_attribute *attr, const char *buf,
175 size_t size)
176 {
177 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
178 u32 loopback;
179
180 if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
181 dev_err(dev, "Invalid input\n");
182 return -EINVAL;
183 }
184 port->loopback = loopback;
185 return size;
186 }
187 static DEVICE_ATTR_RW(loopback);
188
189 static struct qcom_geni_serial_port qcom_geni_console_port = {
190 .uport = {
191 .iotype = UPIO_MEM,
192 .ops = &qcom_geni_console_pops,
193 .flags = UPF_BOOT_AUTOCONF,
194 .line = 0,
195 },
196 };
197
198 static int qcom_geni_serial_request_port(struct uart_port *uport)
199 {
200 struct platform_device *pdev = to_platform_device(uport->dev);
201 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
202
203 uport->membase = devm_platform_ioremap_resource(pdev, 0);
204 if (IS_ERR(uport->membase))
205 return PTR_ERR(uport->membase);
206 port->se.base = uport->membase;
207 return 0;
208 }
209
210 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
211 {
212 if (cfg_flags & UART_CONFIG_TYPE) {
213 uport->type = PORT_MSM;
214 qcom_geni_serial_request_port(uport);
215 }
216 }
217
218 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
219 {
220 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
221 u32 geni_ios;
222
223 if (uart_console(uport)) {
224 mctrl |= TIOCM_CTS;
225 } else {
226 geni_ios = readl(uport->membase + SE_GENI_IOS);
227 if (!(geni_ios & IO2_DATA_IN))
228 mctrl |= TIOCM_CTS;
229 }
230
231 return mctrl;
232 }
233
234 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
235 unsigned int mctrl)
236 {
237 u32 uart_manual_rfr = 0;
238
239 if (uart_console(uport))
240 return;
241
242 if (!(mctrl & TIOCM_RTS))
243 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
244 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
245 }
246
247 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
248 {
249 return "MSM";
250 }
251
252 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
253 {
254 struct qcom_geni_serial_port *port;
255 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
256
257 if (line < 0 || line >= nr_ports)
258 return ERR_PTR(-ENXIO);
259
260 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
261 return port;
262 }
263
264 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
265 int offset, int field, bool set)
266 {
267 u32 reg;
268 struct qcom_geni_serial_port *port;
269 unsigned int baud;
270 unsigned int fifo_bits;
271 unsigned long timeout_us = 20000;
272
273 if (uport->private_data) {
274 port = to_dev_port(uport, uport);
275 baud = port->baud;
276 if (!baud)
277 baud = 115200;
278 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
279
280
281
282
283 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
284 }
285
286
287
288
289
290 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
291 while (timeout_us) {
292 reg = readl(uport->membase + offset);
293 if ((bool)(reg & field) == set)
294 return true;
295 udelay(10);
296 timeout_us -= 10;
297 }
298 return false;
299 }
300
301 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
302 {
303 u32 m_cmd;
304
305 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
306 m_cmd = UART_START_TX << M_OPCODE_SHFT;
307 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
308 }
309
310 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
311 {
312 int done;
313 u32 irq_clear = M_CMD_DONE_EN;
314
315 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
316 M_CMD_DONE_EN, true);
317 if (!done) {
318 writel(M_GENI_CMD_ABORT, uport->membase +
319 SE_GENI_M_CMD_CTRL_REG);
320 irq_clear |= M_CMD_ABORT_EN;
321 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
322 M_CMD_ABORT_EN, true);
323 }
324 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
325 }
326
327 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
328 {
329 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
330
331 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
332 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
333 S_GENI_CMD_ABORT, false);
334 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
335 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
336 }
337
338 #ifdef CONFIG_CONSOLE_POLL
339 static int qcom_geni_serial_get_char(struct uart_port *uport)
340 {
341 u32 rx_fifo;
342 u32 status;
343
344 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
345 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
346
347 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
348 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
349
350 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
351 if (!(status & RX_FIFO_WC_MSK))
352 return NO_POLL_CHAR;
353
354 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
355 return rx_fifo & 0xff;
356 }
357
358 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
359 unsigned char c)
360 {
361 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
362 qcom_geni_serial_setup_tx(uport, 1);
363 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
364 M_TX_FIFO_WATERMARK_EN, true));
365 writel(c, uport->membase + SE_GENI_TX_FIFOn);
366 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
367 qcom_geni_serial_poll_tx_done(uport);
368 }
369 #endif
370
371 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
372 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
373 {
374 writel(ch, uport->membase + SE_GENI_TX_FIFOn);
375 }
376
377 static void
378 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
379 unsigned int count)
380 {
381 int i;
382 u32 bytes_to_send = count;
383
384 for (i = 0; i < count; i++) {
385
386
387
388
389 if (s[i] == '\n')
390 bytes_to_send++;
391 }
392
393 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
394 qcom_geni_serial_setup_tx(uport, bytes_to_send);
395 for (i = 0; i < count; ) {
396 size_t chars_to_write = 0;
397 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
398
399
400
401
402
403
404
405 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
406 M_TX_FIFO_WATERMARK_EN, true))
407 break;
408 chars_to_write = min_t(size_t, count - i, avail / 2);
409 uart_console_write(uport, s + i, chars_to_write,
410 qcom_geni_serial_wr_char);
411 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
412 SE_GENI_M_IRQ_CLEAR);
413 i += chars_to_write;
414 }
415 qcom_geni_serial_poll_tx_done(uport);
416 }
417
418 static void qcom_geni_serial_console_write(struct console *co, const char *s,
419 unsigned int count)
420 {
421 struct uart_port *uport;
422 struct qcom_geni_serial_port *port;
423 bool locked = true;
424 unsigned long flags;
425 u32 geni_status;
426 u32 irq_en;
427
428 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
429
430 port = get_port_from_line(co->index, true);
431 if (IS_ERR(port))
432 return;
433
434 uport = &port->uport;
435 if (oops_in_progress)
436 locked = spin_trylock_irqsave(&uport->lock, flags);
437 else
438 spin_lock_irqsave(&uport->lock, flags);
439
440 geni_status = readl(uport->membase + SE_GENI_STATUS);
441
442
443 if (!locked) {
444 geni_se_cancel_m_cmd(&port->se);
445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
446 M_CMD_CANCEL_EN, true)) {
447 geni_se_abort_m_cmd(&port->se);
448 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
449 M_CMD_ABORT_EN, true);
450 writel(M_CMD_ABORT_EN, uport->membase +
451 SE_GENI_M_IRQ_CLEAR);
452 }
453 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
454 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
455
456
457
458
459 qcom_geni_serial_poll_tx_done(uport);
460
461 if (uart_circ_chars_pending(&uport->state->xmit)) {
462 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
463 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
464 uport->membase + SE_GENI_M_IRQ_EN);
465 }
466 }
467
468 __qcom_geni_serial_console_write(uport, s, count);
469
470 if (port->tx_remaining)
471 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
472
473 if (locked)
474 spin_unlock_irqrestore(&uport->lock, flags);
475 }
476
477 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
478 {
479 u32 i;
480 unsigned char buf[sizeof(u32)];
481 struct tty_port *tport;
482 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
483
484 tport = &uport->state->port;
485 for (i = 0; i < bytes; ) {
486 int c;
487 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
488
489 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
490 i += chunk;
491 if (drop)
492 continue;
493
494 for (c = 0; c < chunk; c++) {
495 int sysrq;
496
497 uport->icount.rx++;
498 if (port->brk && buf[c] == 0) {
499 port->brk = false;
500 if (uart_handle_break(uport))
501 continue;
502 }
503
504 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
505
506 if (!sysrq)
507 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
508 }
509 }
510 if (!drop)
511 tty_flip_buffer_push(tport);
512 return 0;
513 }
514 #else
515 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
516 {
517 return -EPERM;
518 }
519
520 #endif
521
522 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
523 {
524 unsigned char *buf;
525 struct tty_port *tport;
526 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
527 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
528 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
529 int ret;
530
531 tport = &uport->state->port;
532 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
533 if (drop)
534 return 0;
535
536 buf = (unsigned char *)port->rx_fifo;
537 ret = tty_insert_flip_string(tport, buf, bytes);
538 if (ret != bytes) {
539 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
540 __func__, ret, bytes);
541 WARN_ON_ONCE(1);
542 }
543 uport->icount.rx += ret;
544 tty_flip_buffer_push(tport);
545 return ret;
546 }
547
548 static void qcom_geni_serial_start_tx(struct uart_port *uport)
549 {
550 u32 irq_en;
551 u32 status;
552
553 status = readl(uport->membase + SE_GENI_STATUS);
554 if (status & M_GENI_CMD_ACTIVE)
555 return;
556
557 if (!qcom_geni_serial_tx_empty(uport))
558 return;
559
560 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
561 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
562
563 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
564 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
565 }
566
567 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
568 {
569 u32 irq_en;
570 u32 status;
571 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
572
573 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
574 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
575 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
576 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
577 status = readl(uport->membase + SE_GENI_STATUS);
578
579 if (!(status & M_GENI_CMD_ACTIVE))
580 return;
581
582 geni_se_cancel_m_cmd(&port->se);
583 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
584 M_CMD_CANCEL_EN, true)) {
585 geni_se_abort_m_cmd(&port->se);
586 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
587 M_CMD_ABORT_EN, true);
588 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
589 }
590 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
591 }
592
593 static void qcom_geni_serial_start_rx(struct uart_port *uport)
594 {
595 u32 irq_en;
596 u32 status;
597 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
598
599 status = readl(uport->membase + SE_GENI_STATUS);
600 if (status & S_GENI_CMD_ACTIVE)
601 qcom_geni_serial_stop_rx(uport);
602
603 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
604
605 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
606 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
607 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
608
609 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
610 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
611 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
612 }
613
614 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
615 {
616 u32 irq_en;
617 u32 status;
618 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
619 u32 s_irq_status;
620
621 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
622 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
623 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
624
625 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
626 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
627 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
628
629 status = readl(uport->membase + SE_GENI_STATUS);
630
631 if (!(status & S_GENI_CMD_ACTIVE))
632 return;
633
634 geni_se_cancel_s_cmd(&port->se);
635 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
636 S_CMD_CANCEL_EN, true);
637
638
639
640
641 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
642
643 if (s_irq_status & S_RX_FIFO_LAST_EN)
644 qcom_geni_serial_handle_rx(uport, true);
645 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
646
647 status = readl(uport->membase + SE_GENI_STATUS);
648 if (status & S_GENI_CMD_ACTIVE)
649 qcom_geni_serial_abort_rx(uport);
650 }
651
652 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
653 {
654 u32 status;
655 u32 word_cnt;
656 u32 last_word_byte_cnt;
657 u32 last_word_partial;
658 u32 total_bytes;
659 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
660
661 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
662 word_cnt = status & RX_FIFO_WC_MSK;
663 last_word_partial = status & RX_LAST;
664 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
665 RX_LAST_BYTE_VALID_SHFT;
666
667 if (!word_cnt)
668 return;
669 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
670 if (last_word_partial && last_word_byte_cnt)
671 total_bytes += last_word_byte_cnt;
672 else
673 total_bytes += port->rx_bytes_pw;
674 port->handle_rx(uport, total_bytes, drop);
675 }
676
677 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
678 bool active)
679 {
680 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
681 struct circ_buf *xmit = &uport->state->xmit;
682 size_t avail;
683 size_t remaining;
684 size_t pending;
685 int i;
686 u32 status;
687 u32 irq_en;
688 unsigned int chunk;
689 int tail;
690
691 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
692
693
694 if (active)
695 pending = port->tx_remaining;
696 else
697 pending = uart_circ_chars_pending(xmit);
698
699
700 if (!pending && !status && done) {
701 qcom_geni_serial_stop_tx(uport);
702 goto out_write_wakeup;
703 }
704
705 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
706 avail *= port->tx_bytes_pw;
707
708 tail = xmit->tail;
709 chunk = min(avail, pending);
710 if (!chunk)
711 goto out_write_wakeup;
712
713 if (!port->tx_remaining) {
714 qcom_geni_serial_setup_tx(uport, pending);
715 port->tx_remaining = pending;
716
717 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
718 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
719 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
720 uport->membase + SE_GENI_M_IRQ_EN);
721 }
722
723 remaining = chunk;
724 for (i = 0; i < chunk; ) {
725 unsigned int tx_bytes;
726 u8 buf[sizeof(u32)];
727 int c;
728
729 memset(buf, 0, ARRAY_SIZE(buf));
730 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
731
732 for (c = 0; c < tx_bytes ; c++) {
733 buf[c] = xmit->buf[tail++];
734 tail &= UART_XMIT_SIZE - 1;
735 }
736
737 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
738
739 i += tx_bytes;
740 uport->icount.tx += tx_bytes;
741 remaining -= tx_bytes;
742 port->tx_remaining -= tx_bytes;
743 }
744
745 xmit->tail = tail;
746
747
748
749
750
751
752 writel(M_TX_FIFO_WATERMARK_EN,
753 uport->membase + SE_GENI_M_IRQ_CLEAR);
754
755 out_write_wakeup:
756 if (!port->tx_remaining) {
757 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
758 if (irq_en & M_TX_FIFO_WATERMARK_EN)
759 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
760 uport->membase + SE_GENI_M_IRQ_EN);
761 }
762
763 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
764 uart_write_wakeup(uport);
765 }
766
767 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
768 {
769 u32 m_irq_en;
770 u32 m_irq_status;
771 u32 s_irq_status;
772 u32 geni_status;
773 struct uart_port *uport = dev;
774 unsigned long flags;
775 bool drop_rx = false;
776 struct tty_port *tport = &uport->state->port;
777 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
778
779 if (uport->suspended)
780 return IRQ_NONE;
781
782 spin_lock_irqsave(&uport->lock, flags);
783 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
784 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
785 geni_status = readl(uport->membase + SE_GENI_STATUS);
786 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
787 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
788 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
789
790 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
791 goto out_unlock;
792
793 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
794 uport->icount.overrun++;
795 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
796 }
797
798 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
799 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
800 geni_status & M_GENI_CMD_ACTIVE);
801
802 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
803 if (s_irq_status & S_GP_IRQ_0_EN)
804 uport->icount.parity++;
805 drop_rx = true;
806 } else if (s_irq_status & S_GP_IRQ_2_EN ||
807 s_irq_status & S_GP_IRQ_3_EN) {
808 uport->icount.brk++;
809 port->brk = true;
810 }
811
812 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
813 s_irq_status & S_RX_FIFO_LAST_EN)
814 qcom_geni_serial_handle_rx(uport, drop_rx);
815
816 out_unlock:
817 uart_unlock_and_check_sysrq(uport, flags);
818
819 return IRQ_HANDLED;
820 }
821
822 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
823 {
824 struct uart_port *uport;
825
826 uport = &port->uport;
827 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
828 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
829 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
830 uport->fifosize =
831 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
832 }
833
834
835 static void qcom_geni_serial_shutdown(struct uart_port *uport)
836 {
837 unsigned long flags;
838
839
840 if (uart_console(uport))
841 console_stop(uport->cons);
842
843 free_irq(uport->irq, uport);
844 spin_lock_irqsave(&uport->lock, flags);
845 qcom_geni_serial_stop_tx(uport);
846 qcom_geni_serial_stop_rx(uport);
847 spin_unlock_irqrestore(&uport->lock, flags);
848 }
849
850 static int qcom_geni_serial_port_setup(struct uart_port *uport)
851 {
852 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
853 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
854 u32 proto;
855
856 if (uart_console(uport)) {
857 port->tx_bytes_pw = 1;
858 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
859 } else {
860 port->tx_bytes_pw = 4;
861 port->rx_bytes_pw = 4;
862 }
863
864 proto = geni_se_read_proto(&port->se);
865 if (proto != GENI_SE_UART) {
866 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
867 return -ENXIO;
868 }
869
870 qcom_geni_serial_stop_rx(uport);
871
872 get_tx_fifo_size(port);
873
874 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
875
876
877
878
879 if (uart_console(uport))
880 qcom_geni_serial_poll_tx_done(uport);
881 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
882 false, true, false);
883 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
884 false, false, true);
885 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
886 geni_se_select_mode(&port->se, GENI_SE_FIFO);
887 if (!uart_console(uport)) {
888 port->rx_fifo = devm_kcalloc(uport->dev,
889 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
890 if (!port->rx_fifo)
891 return -ENOMEM;
892 }
893 port->setup = true;
894
895 return 0;
896 }
897
898 static int qcom_geni_serial_startup(struct uart_port *uport)
899 {
900 int ret;
901 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
902
903 scnprintf(port->name, sizeof(port->name),
904 "qcom_serial_%s%d",
905 (uart_console(uport) ? "console" : "uart"), uport->line);
906
907 if (!port->setup) {
908 ret = qcom_geni_serial_port_setup(uport);
909 if (ret)
910 return ret;
911 }
912
913 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
914 port->name, uport);
915 if (ret)
916 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
917 return ret;
918 }
919
920 static unsigned long get_clk_cfg(unsigned long clk_freq)
921 {
922 int i;
923
924 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
925 if (!(root_freq[i] % clk_freq))
926 return root_freq[i];
927 }
928 return 0;
929 }
930
931 static unsigned long get_clk_div_rate(unsigned int baud,
932 unsigned int sampling_rate, unsigned int *clk_div)
933 {
934 unsigned long ser_clk;
935 unsigned long desired_clk;
936
937 desired_clk = baud * sampling_rate;
938 ser_clk = get_clk_cfg(desired_clk);
939 if (!ser_clk) {
940 pr_err("%s: Can't find matching DFS entry for baud %d\n",
941 __func__, baud);
942 return ser_clk;
943 }
944
945 *clk_div = ser_clk / desired_clk;
946 return ser_clk;
947 }
948
949 static void qcom_geni_serial_set_termios(struct uart_port *uport,
950 struct ktermios *termios, struct ktermios *old)
951 {
952 unsigned int baud;
953 u32 bits_per_char;
954 u32 tx_trans_cfg;
955 u32 tx_parity_cfg;
956 u32 rx_trans_cfg;
957 u32 rx_parity_cfg;
958 u32 stop_bit_len;
959 unsigned int clk_div;
960 u32 ser_clk_cfg;
961 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
962 unsigned long clk_rate;
963 u32 ver, sampling_rate;
964
965 qcom_geni_serial_stop_rx(uport);
966
967 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
968 port->baud = baud;
969
970 sampling_rate = UART_OVERSAMPLING;
971
972 ver = geni_se_get_qup_hw_version(&port->se);
973 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
974 sampling_rate /= 2;
975
976 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
977 if (!clk_rate)
978 goto out_restart_rx;
979
980 uport->uartclk = clk_rate;
981 clk_set_rate(port->se.clk, clk_rate);
982 ser_clk_cfg = SER_CLK_EN;
983 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
984
985
986 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
987 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
988 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
989 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
990 if (termios->c_cflag & PARENB) {
991 tx_trans_cfg |= UART_TX_PAR_EN;
992 rx_trans_cfg |= UART_RX_PAR_EN;
993 tx_parity_cfg |= PAR_CALC_EN;
994 rx_parity_cfg |= PAR_CALC_EN;
995 if (termios->c_cflag & PARODD) {
996 tx_parity_cfg |= PAR_ODD;
997 rx_parity_cfg |= PAR_ODD;
998 } else if (termios->c_cflag & CMSPAR) {
999 tx_parity_cfg |= PAR_SPACE;
1000 rx_parity_cfg |= PAR_SPACE;
1001 } else {
1002 tx_parity_cfg |= PAR_EVEN;
1003 rx_parity_cfg |= PAR_EVEN;
1004 }
1005 } else {
1006 tx_trans_cfg &= ~UART_TX_PAR_EN;
1007 rx_trans_cfg &= ~UART_RX_PAR_EN;
1008 tx_parity_cfg &= ~PAR_CALC_EN;
1009 rx_parity_cfg &= ~PAR_CALC_EN;
1010 }
1011
1012
1013 switch (termios->c_cflag & CSIZE) {
1014 case CS5:
1015 bits_per_char = 5;
1016 break;
1017 case CS6:
1018 bits_per_char = 6;
1019 break;
1020 case CS7:
1021 bits_per_char = 7;
1022 break;
1023 case CS8:
1024 default:
1025 bits_per_char = 8;
1026 break;
1027 }
1028
1029
1030 if (termios->c_cflag & CSTOPB)
1031 stop_bit_len = TX_STOP_BIT_LEN_2;
1032 else
1033 stop_bit_len = TX_STOP_BIT_LEN_1;
1034
1035
1036 if (termios->c_cflag & CRTSCTS)
1037 tx_trans_cfg &= ~UART_CTS_MASK;
1038 else
1039 tx_trans_cfg |= UART_CTS_MASK;
1040
1041 if (baud)
1042 uart_update_timeout(uport, termios->c_cflag, baud);
1043
1044 if (!uart_console(uport))
1045 writel(port->loopback,
1046 uport->membase + SE_UART_LOOPBACK_CFG);
1047 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1048 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1049 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1050 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1051 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1052 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1053 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1054 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1055 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1056 out_restart_rx:
1057 qcom_geni_serial_start_rx(uport);
1058 }
1059
1060 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1061 {
1062 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1063 }
1064
1065 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1066 static int __init qcom_geni_console_setup(struct console *co, char *options)
1067 {
1068 struct uart_port *uport;
1069 struct qcom_geni_serial_port *port;
1070 int baud = 9600;
1071 int bits = 8;
1072 int parity = 'n';
1073 int flow = 'n';
1074 int ret;
1075
1076 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1077 return -ENXIO;
1078
1079 port = get_port_from_line(co->index, true);
1080 if (IS_ERR(port)) {
1081 pr_err("Invalid line %d\n", co->index);
1082 return PTR_ERR(port);
1083 }
1084
1085 uport = &port->uport;
1086
1087 if (unlikely(!uport->membase))
1088 return -ENXIO;
1089
1090 if (!port->setup) {
1091 ret = qcom_geni_serial_port_setup(uport);
1092 if (ret)
1093 return ret;
1094 }
1095
1096 if (options)
1097 uart_parse_options(options, &baud, &parity, &bits, &flow);
1098
1099 return uart_set_options(uport, co, baud, parity, bits, flow);
1100 }
1101
1102 static void qcom_geni_serial_earlycon_write(struct console *con,
1103 const char *s, unsigned int n)
1104 {
1105 struct earlycon_device *dev = con->data;
1106
1107 __qcom_geni_serial_console_write(&dev->port, s, n);
1108 }
1109
1110 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1111 const char *opt)
1112 {
1113 struct uart_port *uport = &dev->port;
1114 u32 tx_trans_cfg;
1115 u32 tx_parity_cfg = 0;
1116 u32 rx_trans_cfg = 0;
1117 u32 rx_parity_cfg = 0;
1118 u32 stop_bit_len = 0;
1119 u32 bits_per_char;
1120 struct geni_se se;
1121
1122 if (!uport->membase)
1123 return -EINVAL;
1124
1125 memset(&se, 0, sizeof(se));
1126 se.base = uport->membase;
1127 if (geni_se_read_proto(&se) != GENI_SE_UART)
1128 return -ENXIO;
1129
1130
1131
1132
1133 tx_trans_cfg = UART_CTS_MASK;
1134 bits_per_char = BITS_PER_BYTE;
1135
1136
1137
1138
1139
1140 qcom_geni_serial_poll_tx_done(uport);
1141 qcom_geni_serial_abort_rx(uport);
1142 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1143 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1144 geni_se_select_mode(&se, GENI_SE_FIFO);
1145
1146 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1147 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1148 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1149 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1150 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1151 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1152 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1153
1154 dev->con->write = qcom_geni_serial_earlycon_write;
1155 dev->con->setup = NULL;
1156 return 0;
1157 }
1158 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1159 qcom_geni_serial_earlycon_setup);
1160
1161 static int __init console_register(struct uart_driver *drv)
1162 {
1163 return uart_register_driver(drv);
1164 }
1165
1166 static void console_unregister(struct uart_driver *drv)
1167 {
1168 uart_unregister_driver(drv);
1169 }
1170
1171 static struct console cons_ops = {
1172 .name = "ttyMSM",
1173 .write = qcom_geni_serial_console_write,
1174 .device = uart_console_device,
1175 .setup = qcom_geni_console_setup,
1176 .flags = CON_PRINTBUFFER,
1177 .index = -1,
1178 .data = &qcom_geni_console_driver,
1179 };
1180
1181 static struct uart_driver qcom_geni_console_driver = {
1182 .owner = THIS_MODULE,
1183 .driver_name = "qcom_geni_console",
1184 .dev_name = "ttyMSM",
1185 .nr = GENI_UART_CONS_PORTS,
1186 .cons = &cons_ops,
1187 };
1188 #else
1189 static int console_register(struct uart_driver *drv)
1190 {
1191 return 0;
1192 }
1193
1194 static void console_unregister(struct uart_driver *drv)
1195 {
1196 }
1197 #endif
1198
1199 static struct uart_driver qcom_geni_uart_driver = {
1200 .owner = THIS_MODULE,
1201 .driver_name = "qcom_geni_uart",
1202 .dev_name = "ttyHS",
1203 .nr = GENI_UART_PORTS,
1204 };
1205
1206 static void qcom_geni_serial_pm(struct uart_port *uport,
1207 unsigned int new_state, unsigned int old_state)
1208 {
1209 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1210
1211
1212 if (old_state == UART_PM_STATE_UNDEFINED)
1213 old_state = UART_PM_STATE_OFF;
1214
1215 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1216 geni_se_resources_on(&port->se);
1217 else if (new_state == UART_PM_STATE_OFF &&
1218 old_state == UART_PM_STATE_ON)
1219 geni_se_resources_off(&port->se);
1220 }
1221
1222 static const struct uart_ops qcom_geni_console_pops = {
1223 .tx_empty = qcom_geni_serial_tx_empty,
1224 .stop_tx = qcom_geni_serial_stop_tx,
1225 .start_tx = qcom_geni_serial_start_tx,
1226 .stop_rx = qcom_geni_serial_stop_rx,
1227 .set_termios = qcom_geni_serial_set_termios,
1228 .startup = qcom_geni_serial_startup,
1229 .request_port = qcom_geni_serial_request_port,
1230 .config_port = qcom_geni_serial_config_port,
1231 .shutdown = qcom_geni_serial_shutdown,
1232 .type = qcom_geni_serial_get_type,
1233 .set_mctrl = qcom_geni_serial_set_mctrl,
1234 .get_mctrl = qcom_geni_serial_get_mctrl,
1235 #ifdef CONFIG_CONSOLE_POLL
1236 .poll_get_char = qcom_geni_serial_get_char,
1237 .poll_put_char = qcom_geni_serial_poll_put_char,
1238 #endif
1239 .pm = qcom_geni_serial_pm,
1240 };
1241
1242 static const struct uart_ops qcom_geni_uart_pops = {
1243 .tx_empty = qcom_geni_serial_tx_empty,
1244 .stop_tx = qcom_geni_serial_stop_tx,
1245 .start_tx = qcom_geni_serial_start_tx,
1246 .stop_rx = qcom_geni_serial_stop_rx,
1247 .set_termios = qcom_geni_serial_set_termios,
1248 .startup = qcom_geni_serial_startup,
1249 .request_port = qcom_geni_serial_request_port,
1250 .config_port = qcom_geni_serial_config_port,
1251 .shutdown = qcom_geni_serial_shutdown,
1252 .type = qcom_geni_serial_get_type,
1253 .set_mctrl = qcom_geni_serial_set_mctrl,
1254 .get_mctrl = qcom_geni_serial_get_mctrl,
1255 .pm = qcom_geni_serial_pm,
1256 };
1257
1258 static int qcom_geni_serial_probe(struct platform_device *pdev)
1259 {
1260 int ret = 0;
1261 int line = -1;
1262 struct qcom_geni_serial_port *port;
1263 struct uart_port *uport;
1264 struct resource *res;
1265 int irq;
1266 bool console = false;
1267 struct uart_driver *drv;
1268
1269 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1270 console = true;
1271
1272 if (console) {
1273 drv = &qcom_geni_console_driver;
1274 line = of_alias_get_id(pdev->dev.of_node, "serial");
1275 } else {
1276 drv = &qcom_geni_uart_driver;
1277 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1278 }
1279
1280 port = get_port_from_line(line, console);
1281 if (IS_ERR(port)) {
1282 dev_err(&pdev->dev, "Invalid line %d\n", line);
1283 return PTR_ERR(port);
1284 }
1285
1286 uport = &port->uport;
1287
1288 if (uport->private_data)
1289 return -ENODEV;
1290
1291 uport->dev = &pdev->dev;
1292 port->se.dev = &pdev->dev;
1293 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1294 port->se.clk = devm_clk_get(&pdev->dev, "se");
1295 if (IS_ERR(port->se.clk)) {
1296 ret = PTR_ERR(port->se.clk);
1297 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1298 return ret;
1299 }
1300
1301 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1302 if (!res)
1303 return -EINVAL;
1304 uport->mapbase = res->start;
1305
1306 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1307 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1308 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1309
1310 irq = platform_get_irq(pdev, 0);
1311 if (irq < 0)
1312 return irq;
1313 uport->irq = irq;
1314
1315 uport->private_data = drv;
1316 platform_set_drvdata(pdev, port);
1317 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1318 if (!console)
1319 device_create_file(uport->dev, &dev_attr_loopback);
1320 return uart_add_one_port(drv, uport);
1321 }
1322
1323 static int qcom_geni_serial_remove(struct platform_device *pdev)
1324 {
1325 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1326 struct uart_driver *drv = port->uport.private_data;
1327
1328 uart_remove_one_port(drv, &port->uport);
1329 return 0;
1330 }
1331
1332 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1333 {
1334 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1335 struct uart_port *uport = &port->uport;
1336
1337 return uart_suspend_port(uport->private_data, uport);
1338 }
1339
1340 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1341 {
1342 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1343 struct uart_port *uport = &port->uport;
1344
1345 return uart_resume_port(uport->private_data, uport);
1346 }
1347
1348 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1349 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1350 qcom_geni_serial_sys_resume)
1351 };
1352
1353 static const struct of_device_id qcom_geni_serial_match_table[] = {
1354 { .compatible = "qcom,geni-debug-uart", },
1355 { .compatible = "qcom,geni-uart", },
1356 {}
1357 };
1358 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1359
1360 static struct platform_driver qcom_geni_serial_platform_driver = {
1361 .remove = qcom_geni_serial_remove,
1362 .probe = qcom_geni_serial_probe,
1363 .driver = {
1364 .name = "qcom_geni_serial",
1365 .of_match_table = qcom_geni_serial_match_table,
1366 .pm = &qcom_geni_serial_pm_ops,
1367 },
1368 };
1369
1370 static int __init qcom_geni_serial_init(void)
1371 {
1372 int ret;
1373
1374 ret = console_register(&qcom_geni_console_driver);
1375 if (ret)
1376 return ret;
1377
1378 ret = uart_register_driver(&qcom_geni_uart_driver);
1379 if (ret) {
1380 console_unregister(&qcom_geni_console_driver);
1381 return ret;
1382 }
1383
1384 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1385 if (ret) {
1386 console_unregister(&qcom_geni_console_driver);
1387 uart_unregister_driver(&qcom_geni_uart_driver);
1388 }
1389 return ret;
1390 }
1391 module_init(qcom_geni_serial_init);
1392
1393 static void __exit qcom_geni_serial_exit(void)
1394 {
1395 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1396 console_unregister(&qcom_geni_console_driver);
1397 uart_unregister_driver(&qcom_geni_uart_driver);
1398 }
1399 module_exit(qcom_geni_serial_exit);
1400
1401 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1402 MODULE_LICENSE("GPL v2");