drivers/tty/serial/xilinx

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This source file includes following definitions.
cdns_uart_handle_rx
cdns_uart_handle_tx
cdns_uart_isr
cdns_uart_calc_baud_divs
cdns_uart_set_baud_rate
cdns_uart_clk_notifier_cb
cdns_uart_start_tx
cdns_uart_stop_tx
cdns_uart_stop_rx
cdns_uart_tx_empty
cdns_uart_break_ctl
cdns_uart_set_termios
cdns_uart_startup
cdns_uart_shutdown
cdns_uart_type
cdns_uart_verify_port
cdns_uart_request_port
cdns_uart_release_port
cdns_uart_config_port
cdns_uart_get_mctrl
cdns_uart_set_mctrl
cdns_uart_poll_get_char
cdns_uart_poll_put_char
cdns_uart_pm
cdns_uart_console_putchar
cdns_early_write
cdns_early_console_setup
cdns_uart_console_write
cdns_uart_console_setup
cdns_uart_suspend
cdns_uart_resume
cdns_runtime_suspend
cdns_runtime_resume
cdns_uart_probe
cdns_uart_remove
cdns_uart_init
cdns_uart_exit
   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cadence UART driver (found in Xilinx Zynq)
   4  *
   5  * 2011 - 2014 (C) Xilinx Inc.
   6  *
   7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
   8  * still shows in the naming of this file, the kconfig symbols and some symbols
   9  * in the code.
  10  */
  11 
  12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15 
  16 #include <linux/platform_device.h>
  17 #include <linux/serial.h>
  18 #include <linux/console.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/slab.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/clk.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/iopoll.h>
  30 
  31 #define CDNS_UART_TTY_NAME      "ttyPS"
  32 #define CDNS_UART_NAME          "xuartps"
  33 #define CDNS_UART_MAJOR         0       /* use dynamic node allocation */
  34 #define CDNS_UART_MINOR         0       /* works best with devtmpfs */
  35 #define CDNS_UART_NR_PORTS      16
  36 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
  37 #define CDNS_UART_REGISTER_SPACE        0x1000
  38 #define TX_TIMEOUT              500000
  39 
  40 /* Rx Trigger level */
  41 static int rx_trigger_level = 56;
  42 module_param(rx_trigger_level, uint, 0444);
  43 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
  44 
  45 /* Rx Timeout */
  46 static int rx_timeout = 10;
  47 module_param(rx_timeout, uint, 0444);
  48 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  49 
  50 /* Register offsets for the UART. */
  51 #define CDNS_UART_CR            0x00  /* Control Register */
  52 #define CDNS_UART_MR            0x04  /* Mode Register */
  53 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
  54 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
  55 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
  56 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
  57 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
  58 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
  59 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
  60 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
  61 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
  62 #define CDNS_UART_SR            0x2C  /* Channel Status */
  63 #define CDNS_UART_FIFO          0x30  /* FIFO */
  64 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
  65 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
  66 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
  67 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
  68 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
  69 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
  70 
  71 /* Control Register Bit Definitions */
  72 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
  73 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
  74 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
  75 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
  76 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
  77 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
  78 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
  79 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
  80 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
  81 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
  82 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
  83 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
  84 
  85 /*
  86  * Mode Register:
  87  * The mode register (MR) defines the mode of transfer as well as the data
  88  * format. If this register is modified during transmission or reception,
  89  * data validity cannot be guaranteed.
  90  */
  91 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
  92 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
  93 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
  94 #define CDNS_UART_MR_CHMODE_MASK        0x00000300  /* Mask for mode bits */
  95 
  96 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  97 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  98 
  99 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
 100 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
 101 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
 102 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
 103 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
 104 
 105 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
 106 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
 107 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
 108 
 109 /*
 110  * Interrupt Registers:
 111  * Interrupt control logic uses the interrupt enable register (IER) and the
 112  * interrupt disable register (IDR) to set the value of the bits in the
 113  * interrupt mask register (IMR). The IMR determines whether to pass an
 114  * interrupt to the interrupt status register (ISR).
 115  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 116  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 117  * Reading either IER or IDR returns 0x00.
 118  * All four registers have the same bit definitions.
 119  */
 120 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
 121 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
 122 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
 123 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
 124 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
 125 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
 126 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
 127 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
 128 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
 129 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
 130 #define CDNS_UART_IXR_RXMASK    0x000021e7 /* Valid RX bit mask */
 131 
 132         /*
 133          * Do not enable parity error interrupt for the following
 134          * reason: When parity error interrupt is enabled, each Rx
 135          * parity error always results in 2 events. The first one
 136          * being parity error interrupt and the second one with a
 137          * proper Rx interrupt with the incoming data.  Disabling
 138          * parity error interrupt ensures better handling of parity
 139          * error events. With this change, for a parity error case, we
 140          * get a Rx interrupt with parity error set in ISR register
 141          * and we still handle parity errors in the desired way.
 142          */
 143 
 144 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
 145                                  CDNS_UART_IXR_OVERRUN | \
 146                                  CDNS_UART_IXR_RXTRIG |  \
 147                                  CDNS_UART_IXR_TOUT)
 148 
 149 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
 150 #define CDNS_UART_IXR_BRK       0x00002000
 151 
 152 #define CDNS_UART_RXBS_SUPPORT BIT(1)
 153 /*
 154  * Modem Control register:
 155  * The read/write Modem Control register controls the interface with the modem
 156  * or data set, or a peripheral device emulating a modem.
 157  */
 158 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
 159 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
 160 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
 161 
 162 /*
 163  * Channel Status Register:
 164  * The channel status register (CSR) is provided to enable the control logic
 165  * to monitor the status of bits in the channel interrupt status register,
 166  * even if these are masked out by the interrupt mask register.
 167  */
 168 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
 169 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
 170 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
 171 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
 172 #define CDNS_UART_SR_TACTIVE    0x00000800 /* TX state machine active */
 173 
 174 /* baud dividers min/max values */
 175 #define CDNS_UART_BDIV_MIN      4
 176 #define CDNS_UART_BDIV_MAX      255
 177 #define CDNS_UART_CD_MAX        65535
 178 #define UART_AUTOSUSPEND_TIMEOUT        3000
 179 
 180 /**
 181  * struct cdns_uart - device data
 182  * @port:               Pointer to the UART port
 183  * @uartclk:            Reference clock
 184  * @pclk:               APB clock
 185  * @cdns_uart_driver:   Pointer to UART driver
 186  * @baud:               Current baud rate
 187  * @clk_rate_change_nb: Notifier block for clock changes
 188  * @quirks:             Flags for RXBS support.
 189  */
 190 struct cdns_uart {
 191         struct uart_port        *port;
 192         struct clk              *uartclk;
 193         struct clk              *pclk;
 194         struct uart_driver      *cdns_uart_driver;
 195         unsigned int            baud;
 196         struct notifier_block   clk_rate_change_nb;
 197         u32                     quirks;
 198         bool cts_override;
 199 };
 200 struct cdns_platform_data {
 201         u32 quirks;
 202 };
 203 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
 204                 clk_rate_change_nb)
 205 
 206 /**
 207  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 208  * @dev_id: Id of the UART port
 209  * @isrstatus: The interrupt status register value as read
 210  * Return: None
 211  */
 212 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
 213 {
 214         struct uart_port *port = (struct uart_port *)dev_id;
 215         struct cdns_uart *cdns_uart = port->private_data;
 216         unsigned int data;
 217         unsigned int rxbs_status = 0;
 218         unsigned int status_mask;
 219         unsigned int framerrprocessed = 0;
 220         char status = TTY_NORMAL;
 221         bool is_rxbs_support;
 222 
 223         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 224 
 225         while ((readl(port->membase + CDNS_UART_SR) &
 226                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
 227                 if (is_rxbs_support)
 228                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
 229                 data = readl(port->membase + CDNS_UART_FIFO);
 230                 port->icount.rx++;
 231                 /*
 232                  * There is no hardware break detection in Zynq, so we interpret
 233                  * framing error with all-zeros data as a break sequence.
 234                  * Most of the time, there's another non-zero byte at the
 235                  * end of the sequence.
 236                  */
 237                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
 238                         if (!data) {
 239                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
 240                                 framerrprocessed = 1;
 241                                 continue;
 242                         }
 243                 }
 244                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
 245                         port->icount.brk++;
 246                         status = TTY_BREAK;
 247                         if (uart_handle_break(port))
 248                                 continue;
 249                 }
 250 
 251                 isrstatus &= port->read_status_mask;
 252                 isrstatus &= ~port->ignore_status_mask;
 253                 status_mask = port->read_status_mask;
 254                 status_mask &= ~port->ignore_status_mask;
 255 
 256                 if (data &&
 257                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
 258                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
 259                         port->icount.brk++;
 260                         if (uart_handle_break(port))
 261                                 continue;
 262                 }
 263 
 264                 if (uart_handle_sysrq_char(port, data))
 265                         continue;
 266 
 267                 if (is_rxbs_support) {
 268                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
 269                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 270                                 port->icount.parity++;
 271                                 status = TTY_PARITY;
 272                         }
 273                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
 274                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 275                                 port->icount.frame++;
 276                                 status = TTY_FRAME;
 277                         }
 278                 } else {
 279                         if (isrstatus & CDNS_UART_IXR_PARITY) {
 280                                 port->icount.parity++;
 281                                 status = TTY_PARITY;
 282                         }
 283                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
 284                             !framerrprocessed) {
 285                                 port->icount.frame++;
 286                                 status = TTY_FRAME;
 287                         }
 288                 }
 289                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
 290                         port->icount.overrun++;
 291                         tty_insert_flip_char(&port->state->port, 0,
 292                                              TTY_OVERRUN);
 293                 }
 294                 tty_insert_flip_char(&port->state->port, data, status);
 295                 isrstatus = 0;
 296         }
 297         spin_unlock(&port->lock);
 298         tty_flip_buffer_push(&port->state->port);
 299         spin_lock(&port->lock);
 300 }
 301 
 302 /**
 303  * cdns_uart_handle_tx - Handle the bytes to be Txed.
 304  * @dev_id: Id of the UART port
 305  * Return: None
 306  */
 307 static void cdns_uart_handle_tx(void *dev_id)
 308 {
 309         struct uart_port *port = (struct uart_port *)dev_id;
 310         unsigned int numbytes;
 311 
 312         if (uart_circ_empty(&port->state->xmit)) {
 313                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
 314         } else {
 315                 numbytes = port->fifosize;
 316                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
 317                        !(readl(port->membase + CDNS_UART_SR) &
 318                                                 CDNS_UART_SR_TXFULL)) {
 319                         /*
 320                          * Get the data from the UART circular buffer
 321                          * and write it to the cdns_uart's TX_FIFO
 322                          * register.
 323                          */
 324                         writel(
 325                                 port->state->xmit.buf[port->state->xmit.tail],
 326                                         port->membase + CDNS_UART_FIFO);
 327 
 328                         port->icount.tx++;
 329 
 330                         /*
 331                          * Adjust the tail of the UART buffer and wrap
 332                          * the buffer if it reaches limit.
 333                          */
 334                         port->state->xmit.tail =
 335                                 (port->state->xmit.tail + 1) &
 336                                         (UART_XMIT_SIZE - 1);
 337 
 338                         numbytes--;
 339                 }
 340 
 341                 if (uart_circ_chars_pending(
 342                                 &port->state->xmit) < WAKEUP_CHARS)
 343                         uart_write_wakeup(port);
 344         }
 345 }
 346 
 347 /**
 348  * cdns_uart_isr - Interrupt handler
 349  * @irq: Irq number
 350  * @dev_id: Id of the port
 351  *
 352  * Return: IRQHANDLED
 353  */
 354 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
 355 {
 356         struct uart_port *port = (struct uart_port *)dev_id;
 357         unsigned int isrstatus;
 358 
 359         spin_lock(&port->lock);
 360 
 361         /* Read the interrupt status register to determine which
 362          * interrupt(s) is/are active and clear them.
 363          */
 364         isrstatus = readl(port->membase + CDNS_UART_ISR);
 365         writel(isrstatus, port->membase + CDNS_UART_ISR);
 366 
 367         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
 368                 cdns_uart_handle_tx(dev_id);
 369                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
 370         }
 371 
 372         /*
 373          * Skip RX processing if RX is disabled as RXEMPTY will never be set
 374          * as read bytes will not be removed from the FIFO.
 375          */
 376         if (isrstatus & CDNS_UART_IXR_RXMASK &&
 377             !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
 378                 cdns_uart_handle_rx(dev_id, isrstatus);
 379 
 380         spin_unlock(&port->lock);
 381         return IRQ_HANDLED;
 382 }
 383 
 384 /**
 385  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
 386  * @clk: UART module input clock
 387  * @baud: Desired baud rate
 388  * @rbdiv: BDIV value (return value)
 389  * @rcd: CD value (return value)
 390  * @div8: Value for clk_sel bit in mod (return value)
 391  * Return: baud rate, requested baud when possible, or actual baud when there
 392  *      was too much error, zero if no valid divisors are found.
 393  *
 394  * Formula to obtain baud rate is
 395  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
 396  *      input_clk = (Uart User Defined Clock or Apb Clock)
 397  *              depends on UCLKEN in MR Reg
 398  *      clk = input_clk or input_clk/8;
 399  *              depends on CLKS in MR reg
 400  *      CD and BDIV depends on values in
 401  *                      baud rate generate register
 402  *                      baud rate clock divisor register
 403  */
 404 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
 405                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
 406 {
 407         u32 cd, bdiv;
 408         unsigned int calc_baud;
 409         unsigned int bestbaud = 0;
 410         unsigned int bauderror;
 411         unsigned int besterror = ~0;
 412 
 413         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
 414                 *div8 = 1;
 415                 clk /= 8;
 416         } else {
 417                 *div8 = 0;
 418         }
 419 
 420         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
 421                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
 422                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
 423                         continue;
 424 
 425                 calc_baud = clk / (cd * (bdiv + 1));
 426 
 427                 if (baud > calc_baud)
 428                         bauderror = baud - calc_baud;
 429                 else
 430                         bauderror = calc_baud - baud;
 431 
 432                 if (besterror > bauderror) {
 433                         *rbdiv = bdiv;
 434                         *rcd = cd;
 435                         bestbaud = calc_baud;
 436                         besterror = bauderror;
 437                 }
 438         }
 439         /* use the values when percent error is acceptable */
 440         if (((besterror * 100) / baud) < 3)
 441                 bestbaud = baud;
 442 
 443         return bestbaud;
 444 }
 445 
 446 /**
 447  * cdns_uart_set_baud_rate - Calculate and set the baud rate
 448  * @port: Handle to the uart port structure
 449  * @baud: Baud rate to set
 450  * Return: baud rate, requested baud when possible, or actual baud when there
 451  *         was too much error, zero if no valid divisors are found.
 452  */
 453 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
 454                 unsigned int baud)
 455 {
 456         unsigned int calc_baud;
 457         u32 cd = 0, bdiv = 0;
 458         u32 mreg;
 459         int div8;
 460         struct cdns_uart *cdns_uart = port->private_data;
 461 
 462         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
 463                         &div8);
 464 
 465         /* Write new divisors to hardware */
 466         mreg = readl(port->membase + CDNS_UART_MR);
 467         if (div8)
 468                 mreg |= CDNS_UART_MR_CLKSEL;
 469         else
 470                 mreg &= ~CDNS_UART_MR_CLKSEL;
 471         writel(mreg, port->membase + CDNS_UART_MR);
 472         writel(cd, port->membase + CDNS_UART_BAUDGEN);
 473         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
 474         cdns_uart->baud = baud;
 475 
 476         return calc_baud;
 477 }
 478 
 479 #ifdef CONFIG_COMMON_CLK
 480 /**
 481  * cdns_uart_clk_notitifer_cb - Clock notifier callback
 482  * @nb:         Notifier block
 483  * @event:      Notify event
 484  * @data:       Notifier data
 485  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
 486  */
 487 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
 488                 unsigned long event, void *data)
 489 {
 490         u32 ctrl_reg;
 491         struct uart_port *port;
 492         int locked = 0;
 493         struct clk_notifier_data *ndata = data;
 494         unsigned long flags = 0;
 495         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
 496 
 497         port = cdns_uart->port;
 498         if (port->suspended)
 499                 return NOTIFY_OK;
 500 
 501         switch (event) {
 502         case PRE_RATE_CHANGE:
 503         {
 504                 u32 bdiv, cd;
 505                 int div8;
 506 
 507                 /*
 508                  * Find out if current baud-rate can be achieved with new clock
 509                  * frequency.
 510                  */
 511                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
 512                                         &bdiv, &cd, &div8)) {
 513                         dev_warn(port->dev, "clock rate change rejected\n");
 514                         return NOTIFY_BAD;
 515                 }
 516 
 517                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 518 
 519                 /* Disable the TX and RX to set baud rate */
 520                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 521                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 522                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 523 
 524                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 525 
 526                 return NOTIFY_OK;
 527         }
 528         case POST_RATE_CHANGE:
 529                 /*
 530                  * Set clk dividers to generate correct baud with new clock
 531                  * frequency.
 532                  */
 533 
 534                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 535 
 536                 locked = 1;
 537                 port->uartclk = ndata->new_rate;
 538 
 539                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
 540                                 cdns_uart->baud);
 541                 /* fall through */
 542         case ABORT_RATE_CHANGE:
 543                 if (!locked)
 544                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
 545 
 546                 /* Set TX/RX Reset */
 547                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 548                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 549                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 550 
 551                 while (readl(port->membase + CDNS_UART_CR) &
 552                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 553                         cpu_relax();
 554 
 555                 /*
 556                  * Clear the RX disable and TX disable bits and then set the TX
 557                  * enable bit and RX enable bit to enable the transmitter and
 558                  * receiver.
 559                  */
 560                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 561                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 562                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 563                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 564                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 565 
 566                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 567 
 568                 return NOTIFY_OK;
 569         default:
 570                 return NOTIFY_DONE;
 571         }
 572 }
 573 #endif
 574 
 575 /**
 576  * cdns_uart_start_tx -  Start transmitting bytes
 577  * @port: Handle to the uart port structure
 578  */
 579 static void cdns_uart_start_tx(struct uart_port *port)
 580 {
 581         unsigned int status;
 582 
 583         if (uart_tx_stopped(port))
 584                 return;
 585 
 586         /*
 587          * Set the TX enable bit and clear the TX disable bit to enable the
 588          * transmitter.
 589          */
 590         status = readl(port->membase + CDNS_UART_CR);
 591         status &= ~CDNS_UART_CR_TX_DIS;
 592         status |= CDNS_UART_CR_TX_EN;
 593         writel(status, port->membase + CDNS_UART_CR);
 594 
 595         if (uart_circ_empty(&port->state->xmit))
 596                 return;
 597 
 598         cdns_uart_handle_tx(port);
 599 
 600         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
 601         /* Enable the TX Empty interrupt */
 602         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
 603 }
 604 
 605 /**
 606  * cdns_uart_stop_tx - Stop TX
 607  * @port: Handle to the uart port structure
 608  */
 609 static void cdns_uart_stop_tx(struct uart_port *port)
 610 {
 611         unsigned int regval;
 612 
 613         regval = readl(port->membase + CDNS_UART_CR);
 614         regval |= CDNS_UART_CR_TX_DIS;
 615         /* Disable the transmitter */
 616         writel(regval, port->membase + CDNS_UART_CR);
 617 }
 618 
 619 /**
 620  * cdns_uart_stop_rx - Stop RX
 621  * @port: Handle to the uart port structure
 622  */
 623 static void cdns_uart_stop_rx(struct uart_port *port)
 624 {
 625         unsigned int regval;
 626 
 627         /* Disable RX IRQs */
 628         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
 629 
 630         /* Disable the receiver */
 631         regval = readl(port->membase + CDNS_UART_CR);
 632         regval |= CDNS_UART_CR_RX_DIS;
 633         writel(regval, port->membase + CDNS_UART_CR);
 634 }
 635 
 636 /**
 637  * cdns_uart_tx_empty -  Check whether TX is empty
 638  * @port: Handle to the uart port structure
 639  *
 640  * Return: TIOCSER_TEMT on success, 0 otherwise
 641  */
 642 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
 643 {
 644         unsigned int status;
 645 
 646         status = readl(port->membase + CDNS_UART_SR) &
 647                                 CDNS_UART_SR_TXEMPTY;
 648         return status ? TIOCSER_TEMT : 0;
 649 }
 650 
 651 /**
 652  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
 653  *                      transmitting char breaks
 654  * @port: Handle to the uart port structure
 655  * @ctl: Value based on which start or stop decision is taken
 656  */
 657 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
 658 {
 659         unsigned int status;
 660         unsigned long flags;
 661 
 662         spin_lock_irqsave(&port->lock, flags);
 663 
 664         status = readl(port->membase + CDNS_UART_CR);
 665 
 666         if (ctl == -1)
 667                 writel(CDNS_UART_CR_STARTBRK | status,
 668                                 port->membase + CDNS_UART_CR);
 669         else {
 670                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
 671                         writel(CDNS_UART_CR_STOPBRK | status,
 672                                         port->membase + CDNS_UART_CR);
 673         }
 674         spin_unlock_irqrestore(&port->lock, flags);
 675 }
 676 
 677 /**
 678  * cdns_uart_set_termios - termios operations, handling data length, parity,
 679  *                              stop bits, flow control, baud rate
 680  * @port: Handle to the uart port structure
 681  * @termios: Handle to the input termios structure
 682  * @old: Values of the previously saved termios structure
 683  */
 684 static void cdns_uart_set_termios(struct uart_port *port,
 685                                 struct ktermios *termios, struct ktermios *old)
 686 {
 687         unsigned int cval = 0;
 688         unsigned int baud, minbaud, maxbaud;
 689         unsigned long flags;
 690         unsigned int ctrl_reg, mode_reg, val;
 691         int err;
 692 
 693         /* Wait for the transmit FIFO to empty before making changes */
 694         if (!(readl(port->membase + CDNS_UART_CR) &
 695                                 CDNS_UART_CR_TX_DIS)) {
 696                 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
 697                                          val, (val & CDNS_UART_SR_TXEMPTY),
 698                                          1000, TX_TIMEOUT);
 699                 if (err) {
 700                         dev_err(port->dev, "timed out waiting for tx empty");
 701                         return;
 702                 }
 703         }
 704         spin_lock_irqsave(&port->lock, flags);
 705 
 706         /* Disable the TX and RX to set baud rate */
 707         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 708         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 709         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 710 
 711         /*
 712          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
 713          * min and max baud should be calculated here based on port->uartclk.
 714          * this way we get a valid baud and can safely call set_baud()
 715          */
 716         minbaud = port->uartclk /
 717                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
 718         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
 719         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
 720         baud = cdns_uart_set_baud_rate(port, baud);
 721         if (tty_termios_baud_rate(termios))
 722                 tty_termios_encode_baud_rate(termios, baud, baud);
 723 
 724         /* Update the per-port timeout. */
 725         uart_update_timeout(port, termios->c_cflag, baud);
 726 
 727         /* Set TX/RX Reset */
 728         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 729         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 730         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 731 
 732         while (readl(port->membase + CDNS_UART_CR) &
 733                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 734                 cpu_relax();
 735 
 736         /*
 737          * Clear the RX disable and TX disable bits and then set the TX enable
 738          * bit and RX enable bit to enable the transmitter and receiver.
 739          */
 740         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 741         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 742         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 743         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 744 
 745         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 746 
 747         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
 748                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
 749         port->ignore_status_mask = 0;
 750 
 751         if (termios->c_iflag & INPCK)
 752                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
 753                 CDNS_UART_IXR_FRAMING;
 754 
 755         if (termios->c_iflag & IGNPAR)
 756                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
 757                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 758 
 759         /* ignore all characters if CREAD is not set */
 760         if ((termios->c_cflag & CREAD) == 0)
 761                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
 762                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
 763                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 764 
 765         mode_reg = readl(port->membase + CDNS_UART_MR);
 766 
 767         /* Handling Data Size */
 768         switch (termios->c_cflag & CSIZE) {
 769         case CS6:
 770                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
 771                 break;
 772         case CS7:
 773                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
 774                 break;
 775         default:
 776         case CS8:
 777                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
 778                 termios->c_cflag &= ~CSIZE;
 779                 termios->c_cflag |= CS8;
 780                 break;
 781         }
 782 
 783         /* Handling Parity and Stop Bits length */
 784         if (termios->c_cflag & CSTOPB)
 785                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
 786         else
 787                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
 788 
 789         if (termios->c_cflag & PARENB) {
 790                 /* Mark or Space parity */
 791                 if (termios->c_cflag & CMSPAR) {
 792                         if (termios->c_cflag & PARODD)
 793                                 cval |= CDNS_UART_MR_PARITY_MARK;
 794                         else
 795                                 cval |= CDNS_UART_MR_PARITY_SPACE;
 796                 } else {
 797                         if (termios->c_cflag & PARODD)
 798                                 cval |= CDNS_UART_MR_PARITY_ODD;
 799                         else
 800                                 cval |= CDNS_UART_MR_PARITY_EVEN;
 801                 }
 802         } else {
 803                 cval |= CDNS_UART_MR_PARITY_NONE;
 804         }
 805         cval |= mode_reg & 1;
 806         writel(cval, port->membase + CDNS_UART_MR);
 807 
 808         spin_unlock_irqrestore(&port->lock, flags);
 809 }
 810 
 811 /**
 812  * cdns_uart_startup - Called when an application opens a cdns_uart port
 813  * @port: Handle to the uart port structure
 814  *
 815  * Return: 0 on success, negative errno otherwise
 816  */
 817 static int cdns_uart_startup(struct uart_port *port)
 818 {
 819         struct cdns_uart *cdns_uart = port->private_data;
 820         bool is_brk_support;
 821         int ret;
 822         unsigned long flags;
 823         unsigned int status = 0;
 824 
 825         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 826 
 827         spin_lock_irqsave(&port->lock, flags);
 828 
 829         /* Disable the TX and RX */
 830         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 831                         port->membase + CDNS_UART_CR);
 832 
 833         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
 834          * no break chars.
 835          */
 836         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
 837                         port->membase + CDNS_UART_CR);
 838 
 839         while (readl(port->membase + CDNS_UART_CR) &
 840                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 841                 cpu_relax();
 842 
 843         /*
 844          * Clear the RX disable bit and then set the RX enable bit to enable
 845          * the receiver.
 846          */
 847         status = readl(port->membase + CDNS_UART_CR);
 848         status &= ~CDNS_UART_CR_RX_DIS;
 849         status |= CDNS_UART_CR_RX_EN;
 850         writel(status, port->membase + CDNS_UART_CR);
 851 
 852         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
 853          * no parity.
 854          */
 855         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
 856                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
 857                 port->membase + CDNS_UART_MR);
 858 
 859         /*
 860          * Set the RX FIFO Trigger level to use most of the FIFO, but it
 861          * can be tuned with a module parameter
 862          */
 863         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
 864 
 865         /*
 866          * Receive Timeout register is enabled but it
 867          * can be tuned with a module parameter
 868          */
 869         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 870 
 871         /* Clear out any pending interrupts before enabling them */
 872         writel(readl(port->membase + CDNS_UART_ISR),
 873                         port->membase + CDNS_UART_ISR);
 874 
 875         spin_unlock_irqrestore(&port->lock, flags);
 876 
 877         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
 878         if (ret) {
 879                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
 880                         port->irq, ret);
 881                 return ret;
 882         }
 883 
 884         /* Set the Interrupt Registers with desired interrupts */
 885         if (is_brk_support)
 886                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
 887                                         port->membase + CDNS_UART_IER);
 888         else
 889                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
 890 
 891         return 0;
 892 }
 893 
 894 /**
 895  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
 896  * @port: Handle to the uart port structure
 897  */
 898 static void cdns_uart_shutdown(struct uart_port *port)
 899 {
 900         int status;
 901         unsigned long flags;
 902 
 903         spin_lock_irqsave(&port->lock, flags);
 904 
 905         /* Disable interrupts */
 906         status = readl(port->membase + CDNS_UART_IMR);
 907         writel(status, port->membase + CDNS_UART_IDR);
 908         writel(0xffffffff, port->membase + CDNS_UART_ISR);
 909 
 910         /* Disable the TX and RX */
 911         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 912                         port->membase + CDNS_UART_CR);
 913 
 914         spin_unlock_irqrestore(&port->lock, flags);
 915 
 916         free_irq(port->irq, port);
 917 }
 918 
 919 /**
 920  * cdns_uart_type - Set UART type to cdns_uart port
 921  * @port: Handle to the uart port structure
 922  *
 923  * Return: string on success, NULL otherwise
 924  */
 925 static const char *cdns_uart_type(struct uart_port *port)
 926 {
 927         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
 928 }
 929 
 930 /**
 931  * cdns_uart_verify_port - Verify the port params
 932  * @port: Handle to the uart port structure
 933  * @ser: Handle to the structure whose members are compared
 934  *
 935  * Return: 0 on success, negative errno otherwise.
 936  */
 937 static int cdns_uart_verify_port(struct uart_port *port,
 938                                         struct serial_struct *ser)
 939 {
 940         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
 941                 return -EINVAL;
 942         if (port->irq != ser->irq)
 943                 return -EINVAL;
 944         if (ser->io_type != UPIO_MEM)
 945                 return -EINVAL;
 946         if (port->iobase != ser->port)
 947                 return -EINVAL;
 948         if (ser->hub6 != 0)
 949                 return -EINVAL;
 950         return 0;
 951 }
 952 
 953 /**
 954  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 955  *                              called when the driver adds a cdns_uart port via
 956  *                              uart_add_one_port()
 957  * @port: Handle to the uart port structure
 958  *
 959  * Return: 0 on success, negative errno otherwise.
 960  */
 961 static int cdns_uart_request_port(struct uart_port *port)
 962 {
 963         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
 964                                          CDNS_UART_NAME)) {
 965                 return -ENOMEM;
 966         }
 967 
 968         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
 969         if (!port->membase) {
 970                 dev_err(port->dev, "Unable to map registers\n");
 971                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 972                 return -ENOMEM;
 973         }
 974         return 0;
 975 }
 976 
 977 /**
 978  * cdns_uart_release_port - Release UART port
 979  * @port: Handle to the uart port structure
 980  *
 981  * Release the memory region attached to a cdns_uart port. Called when the
 982  * driver removes a cdns_uart port via uart_remove_one_port().
 983  */
 984 static void cdns_uart_release_port(struct uart_port *port)
 985 {
 986         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 987         iounmap(port->membase);
 988         port->membase = NULL;
 989 }
 990 
 991 /**
 992  * cdns_uart_config_port - Configure UART port
 993  * @port: Handle to the uart port structure
 994  * @flags: If any
 995  */
 996 static void cdns_uart_config_port(struct uart_port *port, int flags)
 997 {
 998         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
 999                 port->type = PORT_XUARTPS;
1000 }
1001 
1002 /**
1003  * cdns_uart_get_mctrl - Get the modem control state
1004  * @port: Handle to the uart port structure
1005  *
1006  * Return: the modem control state
1007  */
1008 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1009 {
1010         struct cdns_uart *cdns_uart_data = port->private_data;
1011 
1012         if (cdns_uart_data->cts_override)
1013                 return 0;
1014 
1015         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1016 }
1017 
1018 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1019 {
1020         u32 val;
1021         u32 mode_reg;
1022         struct cdns_uart *cdns_uart_data = port->private_data;
1023 
1024         if (cdns_uart_data->cts_override)
1025                 return;
1026 
1027         val = readl(port->membase + CDNS_UART_MODEMCR);
1028         mode_reg = readl(port->membase + CDNS_UART_MR);
1029 
1030         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1031                  CDNS_UART_MODEMCR_FCM);
1032         mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1033 
1034         if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1035                 val |= CDNS_UART_MODEMCR_FCM;
1036         if (mctrl & TIOCM_LOOP)
1037                 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1038         else
1039                 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1040 
1041         writel(val, port->membase + CDNS_UART_MODEMCR);
1042         writel(mode_reg, port->membase + CDNS_UART_MR);
1043 }
1044 
1045 #ifdef CONFIG_CONSOLE_POLL
1046 static int cdns_uart_poll_get_char(struct uart_port *port)
1047 {
1048         int c;
1049         unsigned long flags;
1050 
1051         spin_lock_irqsave(&port->lock, flags);
1052 
1053         /* Check if FIFO is empty */
1054         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1055                 c = NO_POLL_CHAR;
1056         else /* Read a character */
1057                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1058 
1059         spin_unlock_irqrestore(&port->lock, flags);
1060 
1061         return c;
1062 }
1063 
1064 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1065 {
1066         unsigned long flags;
1067 
1068         spin_lock_irqsave(&port->lock, flags);
1069 
1070         /* Wait until FIFO is empty */
1071         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1072                 cpu_relax();
1073 
1074         /* Write a character */
1075         writel(c, port->membase + CDNS_UART_FIFO);
1076 
1077         /* Wait until FIFO is empty */
1078         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1079                 cpu_relax();
1080 
1081         spin_unlock_irqrestore(&port->lock, flags);
1082 }
1083 #endif
1084 
1085 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1086                    unsigned int oldstate)
1087 {
1088         switch (state) {
1089         case UART_PM_STATE_OFF:
1090                 pm_runtime_mark_last_busy(port->dev);
1091                 pm_runtime_put_autosuspend(port->dev);
1092                 break;
1093         default:
1094                 pm_runtime_get_sync(port->dev);
1095                 break;
1096         }
1097 }
1098 
1099 static const struct uart_ops cdns_uart_ops = {
1100         .set_mctrl      = cdns_uart_set_mctrl,
1101         .get_mctrl      = cdns_uart_get_mctrl,
1102         .start_tx       = cdns_uart_start_tx,
1103         .stop_tx        = cdns_uart_stop_tx,
1104         .stop_rx        = cdns_uart_stop_rx,
1105         .tx_empty       = cdns_uart_tx_empty,
1106         .break_ctl      = cdns_uart_break_ctl,
1107         .set_termios    = cdns_uart_set_termios,
1108         .startup        = cdns_uart_startup,
1109         .shutdown       = cdns_uart_shutdown,
1110         .pm             = cdns_uart_pm,
1111         .type           = cdns_uart_type,
1112         .verify_port    = cdns_uart_verify_port,
1113         .request_port   = cdns_uart_request_port,
1114         .release_port   = cdns_uart_release_port,
1115         .config_port    = cdns_uart_config_port,
1116 #ifdef CONFIG_CONSOLE_POLL
1117         .poll_get_char  = cdns_uart_poll_get_char,
1118         .poll_put_char  = cdns_uart_poll_put_char,
1119 #endif
1120 };
1121 
1122 static struct uart_driver cdns_uart_uart_driver;
1123 
1124 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1125 /**
1126  * cdns_uart_console_putchar - write the character to the FIFO buffer
1127  * @port: Handle to the uart port structure
1128  * @ch: Character to be written
1129  */
1130 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1131 {
1132         while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1133                 cpu_relax();
1134         writel(ch, port->membase + CDNS_UART_FIFO);
1135 }
1136 
1137 static void cdns_early_write(struct console *con, const char *s,
1138                                     unsigned n)
1139 {
1140         struct earlycon_device *dev = con->data;
1141 
1142         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1143 }
1144 
1145 static int __init cdns_early_console_setup(struct earlycon_device *device,
1146                                            const char *opt)
1147 {
1148         struct uart_port *port = &device->port;
1149 
1150         if (!port->membase)
1151                 return -ENODEV;
1152 
1153         /* initialise control register */
1154         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1155                port->membase + CDNS_UART_CR);
1156 
1157         /* only set baud if specified on command line - otherwise
1158          * assume it has been initialized by a boot loader.
1159          */
1160         if (port->uartclk && device->baud) {
1161                 u32 cd = 0, bdiv = 0;
1162                 u32 mr;
1163                 int div8;
1164 
1165                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1166                                          &bdiv, &cd, &div8);
1167                 mr = CDNS_UART_MR_PARITY_NONE;
1168                 if (div8)
1169                         mr |= CDNS_UART_MR_CLKSEL;
1170 
1171                 writel(mr,   port->membase + CDNS_UART_MR);
1172                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1173                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1174         }
1175 
1176         device->con->write = cdns_early_write;
1177 
1178         return 0;
1179 }
1180 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1181 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1182 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1183 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1184 
1185 
1186 /* Static pointer to console port */
1187 static struct uart_port *console_port;
1188 
1189 /**
1190  * cdns_uart_console_write - perform write operation
1191  * @co: Console handle
1192  * @s: Pointer to character array
1193  * @count: No of characters
1194  */
1195 static void cdns_uart_console_write(struct console *co, const char *s,
1196                                 unsigned int count)
1197 {
1198         struct uart_port *port = console_port;
1199         unsigned long flags = 0;
1200         unsigned int imr, ctrl;
1201         int locked = 1;
1202 
1203         if (port->sysrq)
1204                 locked = 0;
1205         else if (oops_in_progress)
1206                 locked = spin_trylock_irqsave(&port->lock, flags);
1207         else
1208                 spin_lock_irqsave(&port->lock, flags);
1209 
1210         /* save and disable interrupt */
1211         imr = readl(port->membase + CDNS_UART_IMR);
1212         writel(imr, port->membase + CDNS_UART_IDR);
1213 
1214         /*
1215          * Make sure that the tx part is enabled. Set the TX enable bit and
1216          * clear the TX disable bit to enable the transmitter.
1217          */
1218         ctrl = readl(port->membase + CDNS_UART_CR);
1219         ctrl &= ~CDNS_UART_CR_TX_DIS;
1220         ctrl |= CDNS_UART_CR_TX_EN;
1221         writel(ctrl, port->membase + CDNS_UART_CR);
1222 
1223         uart_console_write(port, s, count, cdns_uart_console_putchar);
1224         while ((readl(port->membase + CDNS_UART_SR) &
1225                         (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1226                         CDNS_UART_SR_TXEMPTY)
1227                 cpu_relax();
1228 
1229         /* restore interrupt state */
1230         writel(imr, port->membase + CDNS_UART_IER);
1231 
1232         if (locked)
1233                 spin_unlock_irqrestore(&port->lock, flags);
1234 }
1235 
1236 /**
1237  * cdns_uart_console_setup - Initialize the uart to default config
1238  * @co: Console handle
1239  * @options: Initial settings of uart
1240  *
1241  * Return: 0 on success, negative errno otherwise.
1242  */
1243 static int cdns_uart_console_setup(struct console *co, char *options)
1244 {
1245         struct uart_port *port = console_port;
1246 
1247         int baud = 9600;
1248         int bits = 8;
1249         int parity = 'n';
1250         int flow = 'n';
1251 
1252         if (!port->membase) {
1253                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1254                          co->index);
1255                 return -ENODEV;
1256         }
1257 
1258         if (options)
1259                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1260 
1261         return uart_set_options(port, co, baud, parity, bits, flow);
1262 }
1263 
1264 static struct console cdns_uart_console = {
1265         .name   = CDNS_UART_TTY_NAME,
1266         .write  = cdns_uart_console_write,
1267         .device = uart_console_device,
1268         .setup  = cdns_uart_console_setup,
1269         .flags  = CON_PRINTBUFFER,
1270         .index  = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1271         .data   = &cdns_uart_uart_driver,
1272 };
1273 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1274 
1275 #ifdef CONFIG_PM_SLEEP
1276 /**
1277  * cdns_uart_suspend - suspend event
1278  * @device: Pointer to the device structure
1279  *
1280  * Return: 0
1281  */
1282 static int cdns_uart_suspend(struct device *device)
1283 {
1284         struct uart_port *port = dev_get_drvdata(device);
1285         struct cdns_uart *cdns_uart = port->private_data;
1286         int may_wake;
1287 
1288         may_wake = device_may_wakeup(device);
1289 
1290         if (console_suspend_enabled && uart_console(port) && may_wake) {
1291                 unsigned long flags = 0;
1292 
1293                 spin_lock_irqsave(&port->lock, flags);
1294                 /* Empty the receive FIFO 1st before making changes */
1295                 while (!(readl(port->membase + CDNS_UART_SR) &
1296                                         CDNS_UART_SR_RXEMPTY))
1297                         readl(port->membase + CDNS_UART_FIFO);
1298                 /* set RX trigger level to 1 */
1299                 writel(1, port->membase + CDNS_UART_RXWM);
1300                 /* disable RX timeout interrups */
1301                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1302                 spin_unlock_irqrestore(&port->lock, flags);
1303         }
1304 
1305         /*
1306          * Call the API provided in serial_core.c file which handles
1307          * the suspend.
1308          */
1309         return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1310 }
1311 
1312 /**
1313  * cdns_uart_resume - Resume after a previous suspend
1314  * @device: Pointer to the device structure
1315  *
1316  * Return: 0
1317  */
1318 static int cdns_uart_resume(struct device *device)
1319 {
1320         struct uart_port *port = dev_get_drvdata(device);
1321         struct cdns_uart *cdns_uart = port->private_data;
1322         unsigned long flags = 0;
1323         u32 ctrl_reg;
1324         int may_wake;
1325 
1326         may_wake = device_may_wakeup(device);
1327 
1328         if (console_suspend_enabled && uart_console(port) && !may_wake) {
1329                 clk_enable(cdns_uart->pclk);
1330                 clk_enable(cdns_uart->uartclk);
1331 
1332                 spin_lock_irqsave(&port->lock, flags);
1333 
1334                 /* Set TX/RX Reset */
1335                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1336                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1337                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1338                 while (readl(port->membase + CDNS_UART_CR) &
1339                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1340                         cpu_relax();
1341 
1342                 /* restore rx timeout value */
1343                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1344                 /* Enable Tx/Rx */
1345                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1346                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1347                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1348                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1349 
1350                 clk_disable(cdns_uart->uartclk);
1351                 clk_disable(cdns_uart->pclk);
1352                 spin_unlock_irqrestore(&port->lock, flags);
1353         } else {
1354                 spin_lock_irqsave(&port->lock, flags);
1355                 /* restore original rx trigger level */
1356                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1357                 /* enable RX timeout interrupt */
1358                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1359                 spin_unlock_irqrestore(&port->lock, flags);
1360         }
1361 
1362         return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1363 }
1364 #endif /* ! CONFIG_PM_SLEEP */
1365 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1366 {
1367         struct uart_port *port = dev_get_drvdata(dev);
1368         struct cdns_uart *cdns_uart = port->private_data;
1369 
1370         clk_disable(cdns_uart->uartclk);
1371         clk_disable(cdns_uart->pclk);
1372         return 0;
1373 };
1374 
1375 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1376 {
1377         struct uart_port *port = dev_get_drvdata(dev);
1378         struct cdns_uart *cdns_uart = port->private_data;
1379 
1380         clk_enable(cdns_uart->pclk);
1381         clk_enable(cdns_uart->uartclk);
1382         return 0;
1383 };
1384 
1385 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1386         SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1387         SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1388                            cdns_runtime_resume, NULL)
1389 };
1390 
1391 static const struct cdns_platform_data zynqmp_uart_def = {
1392                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1393 
1394 /* Match table for of_platform binding */
1395 static const struct of_device_id cdns_uart_of_match[] = {
1396         { .compatible = "xlnx,xuartps", },
1397         { .compatible = "cdns,uart-r1p8", },
1398         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1399         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1400         {}
1401 };
1402 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1403 
1404 /* Temporary variable for storing number of instances */
1405 static int instances;
1406 
1407 /**
1408  * cdns_uart_probe - Platform driver probe
1409  * @pdev: Pointer to the platform device structure
1410  *
1411  * Return: 0 on success, negative errno otherwise
1412  */
1413 static int cdns_uart_probe(struct platform_device *pdev)
1414 {
1415         int rc, id, irq;
1416         struct uart_port *port;
1417         struct resource *res;
1418         struct cdns_uart *cdns_uart_data;
1419         const struct of_device_id *match;
1420 
1421         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1422                         GFP_KERNEL);
1423         if (!cdns_uart_data)
1424                 return -ENOMEM;
1425         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1426         if (!port)
1427                 return -ENOMEM;
1428 
1429         /* Look for a serialN alias */
1430         id = of_alias_get_id(pdev->dev.of_node, "serial");
1431         if (id < 0)
1432                 id = 0;
1433 
1434         if (id >= CDNS_UART_NR_PORTS) {
1435                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1436                 return -ENODEV;
1437         }
1438 
1439         if (!cdns_uart_uart_driver.state) {
1440                 cdns_uart_uart_driver.owner = THIS_MODULE;
1441                 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1442                 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1443                 cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1444                 cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1445                 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1446 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1447                 cdns_uart_uart_driver.cons = &cdns_uart_console;
1448                 cdns_uart_console.index = id;
1449 #endif
1450 
1451                 rc = uart_register_driver(&cdns_uart_uart_driver);
1452                 if (rc < 0) {
1453                         dev_err(&pdev->dev, "Failed to register driver\n");
1454                         return rc;
1455                 }
1456         }
1457 
1458         cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;
1459 
1460         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1461         if (match && match->data) {
1462                 const struct cdns_platform_data *data = match->data;
1463 
1464                 cdns_uart_data->quirks = data->quirks;
1465         }
1466 
1467         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1468         if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1469                 rc = PTR_ERR(cdns_uart_data->pclk);
1470                 goto err_out_unregister_driver;
1471         }
1472 
1473         if (IS_ERR(cdns_uart_data->pclk)) {
1474                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1475                 if (IS_ERR(cdns_uart_data->pclk)) {
1476                         rc = PTR_ERR(cdns_uart_data->pclk);
1477                         goto err_out_unregister_driver;
1478                 }
1479                 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1480         }
1481 
1482         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1483         if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1484                 rc = PTR_ERR(cdns_uart_data->uartclk);
1485                 goto err_out_unregister_driver;
1486         }
1487 
1488         if (IS_ERR(cdns_uart_data->uartclk)) {
1489                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1490                 if (IS_ERR(cdns_uart_data->uartclk)) {
1491                         rc = PTR_ERR(cdns_uart_data->uartclk);
1492                         goto err_out_unregister_driver;
1493                 }
1494                 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1495         }
1496 
1497         rc = clk_prepare_enable(cdns_uart_data->pclk);
1498         if (rc) {
1499                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1500                 goto err_out_unregister_driver;
1501         }
1502         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1503         if (rc) {
1504                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1505                 goto err_out_clk_dis_pclk;
1506         }
1507 
1508         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1509         if (!res) {
1510                 rc = -ENODEV;
1511                 goto err_out_clk_disable;
1512         }
1513 
1514         irq = platform_get_irq(pdev, 0);
1515         if (irq <= 0) {
1516                 rc = -ENXIO;
1517                 goto err_out_clk_disable;
1518         }
1519 
1520 #ifdef CONFIG_COMMON_CLK
1521         cdns_uart_data->clk_rate_change_nb.notifier_call =
1522                         cdns_uart_clk_notifier_cb;
1523         if (clk_notifier_register(cdns_uart_data->uartclk,
1524                                 &cdns_uart_data->clk_rate_change_nb))
1525                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1526 #endif
1527 
1528         /* At this point, we've got an empty uart_port struct, initialize it */
1529         spin_lock_init(&port->lock);
1530         port->type      = PORT_UNKNOWN;
1531         port->iotype    = UPIO_MEM32;
1532         port->flags     = UPF_BOOT_AUTOCONF;
1533         port->ops       = &cdns_uart_ops;
1534         port->fifosize  = CDNS_UART_FIFO_SIZE;
1535         port->line      = id;
1536 
1537         /*
1538          * Register the port.
1539          * This function also registers this device with the tty layer
1540          * and triggers invocation of the config_port() entry point.
1541          */
1542         port->mapbase = res->start;
1543         port->irq = irq;
1544         port->dev = &pdev->dev;
1545         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1546         port->private_data = cdns_uart_data;
1547         cdns_uart_data->port = port;
1548         platform_set_drvdata(pdev, port);
1549 
1550         pm_runtime_use_autosuspend(&pdev->dev);
1551         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1552         pm_runtime_set_active(&pdev->dev);
1553         pm_runtime_enable(&pdev->dev);
1554         device_init_wakeup(port->dev, true);
1555 
1556 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1557         /*
1558          * If console hasn't been found yet try to assign this port
1559          * because it is required to be assigned for console setup function.
1560          * If register_console() don't assign value, then console_port pointer
1561          * is cleanup.
1562          */
1563         if (!console_port)
1564                 console_port = port;
1565 #endif
1566 
1567         rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1568         if (rc) {
1569                 dev_err(&pdev->dev,
1570                         "uart_add_one_port() failed; err=%i\n", rc);
1571                 goto err_out_pm_disable;
1572         }
1573 
1574 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1575         /* This is not port which is used for console that's why clean it up */
1576         if (console_port == port &&
1577             !(cdns_uart_uart_driver.cons->flags & CON_ENABLED))
1578                 console_port = NULL;
1579 #endif
1580 
1581         cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1582                                                              "cts-override");
1583 
1584         instances++;
1585 
1586         return 0;
1587 
1588 err_out_pm_disable:
1589         pm_runtime_disable(&pdev->dev);
1590         pm_runtime_set_suspended(&pdev->dev);
1591         pm_runtime_dont_use_autosuspend(&pdev->dev);
1592 #ifdef CONFIG_COMMON_CLK
1593         clk_notifier_unregister(cdns_uart_data->uartclk,
1594                         &cdns_uart_data->clk_rate_change_nb);
1595 #endif
1596 err_out_clk_disable:
1597         clk_disable_unprepare(cdns_uart_data->uartclk);
1598 err_out_clk_dis_pclk:
1599         clk_disable_unprepare(cdns_uart_data->pclk);
1600 err_out_unregister_driver:
1601         if (!instances)
1602                 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1603         return rc;
1604 }
1605 
1606 /**
1607  * cdns_uart_remove - called when the platform driver is unregistered
1608  * @pdev: Pointer to the platform device structure
1609  *
1610  * Return: 0 on success, negative errno otherwise
1611  */
1612 static int cdns_uart_remove(struct platform_device *pdev)
1613 {
1614         struct uart_port *port = platform_get_drvdata(pdev);
1615         struct cdns_uart *cdns_uart_data = port->private_data;
1616         int rc;
1617 
1618         /* Remove the cdns_uart port from the serial core */
1619 #ifdef CONFIG_COMMON_CLK
1620         clk_notifier_unregister(cdns_uart_data->uartclk,
1621                         &cdns_uart_data->clk_rate_change_nb);
1622 #endif
1623         rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1624         port->mapbase = 0;
1625         clk_disable_unprepare(cdns_uart_data->uartclk);
1626         clk_disable_unprepare(cdns_uart_data->pclk);
1627         pm_runtime_disable(&pdev->dev);
1628         pm_runtime_set_suspended(&pdev->dev);
1629         pm_runtime_dont_use_autosuspend(&pdev->dev);
1630         device_init_wakeup(&pdev->dev, false);
1631 
1632 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1633         if (console_port == port)
1634                 console_port = NULL;
1635 #endif
1636 
1637         if (!--instances)
1638                 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1639         return rc;
1640 }
1641 
1642 static struct platform_driver cdns_uart_platform_driver = {
1643         .probe   = cdns_uart_probe,
1644         .remove  = cdns_uart_remove,
1645         .driver  = {
1646                 .name = CDNS_UART_NAME,
1647                 .of_match_table = cdns_uart_of_match,
1648                 .pm = &cdns_uart_dev_pm_ops,
1649                 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1650                 },
1651 };
1652 
1653 static int __init cdns_uart_init(void)
1654 {
1655         /* Register the platform driver */
1656         return platform_driver_register(&cdns_uart_platform_driver);
1657 }
1658 
1659 static void __exit cdns_uart_exit(void)
1660 {
1661         /* Unregister the platform driver */
1662         platform_driver_unregister(&cdns_uart_platform_driver);
1663 }
1664 
1665 arch_initcall(cdns_uart_init);
1666 module_exit(cdns_uart_exit);
1667 
1668 MODULE_DESCRIPTION("Driver for Cadence UART");
1669 MODULE_AUTHOR("Xilinx Inc.");
1670 MODULE_LICENSE("GPL");
/* [<][>][^][v][top][bottom][index][help] */
root/drivers/tty/serial/xilinx_uartps.c

DEFINITIONS
