This source file includes following definitions.
- to_sci_port
- sci_serial_in
- sci_serial_out
- sci_port_enable
- sci_port_disable
- port_rx_irq_mask
- sci_start_tx
- sci_stop_tx
- sci_start_rx
- sci_stop_rx
- sci_clear_SCxSR
- sci_poll_get_char
- sci_poll_put_char
- sci_init_pins
- sci_txfill
- sci_txroom
- sci_rxfill
- sci_transmit_chars
- sci_receive_chars
- sci_handle_errors
- sci_handle_fifo_overrun
- sci_handle_breaks
- scif_set_rtrg
- scif_rtrg_enabled
- rx_fifo_timer_fn
- rx_fifo_trigger_show
- rx_fifo_trigger_store
- rx_fifo_timeout_show
- rx_fifo_timeout_store
- sci_dma_tx_complete
- sci_dma_rx_push
- sci_dma_rx_find_active
- sci_dma_rx_chan_invalidate
- sci_dma_rx_release
- start_hrtimer_us
- sci_dma_rx_reenable_irq
- sci_dma_rx_complete
- sci_dma_tx_release
- sci_dma_rx_submit
- sci_dma_tx_work_fn
- sci_dma_rx_timer_fn
- sci_request_dma_chan
- sci_request_dma
- sci_free_dma
- sci_flush_buffer
- sci_request_dma
- sci_free_dma
- sci_rx_interrupt
- sci_tx_interrupt
- sci_br_interrupt
- sci_er_interrupt
- sci_mpxed_interrupt
- sci_request_irq
- sci_free_irq
- sci_tx_empty
- sci_set_rts
- sci_get_cts
- sci_set_mctrl
- sci_get_mctrl
- sci_enable_ms
- sci_break_ctl
- sci_startup
- sci_shutdown
- sci_sck_calc
- sci_brg_calc
- sci_scbrr_calc
- sci_reset
- sci_set_termios
- sci_pm
- sci_type
- sci_remap_port
- sci_release_port
- sci_request_port
- sci_config_port
- sci_verify_port
- sci_init_clocks
- sci_probe_regmap
- sci_init_single
- sci_cleanup_single
- serial_console_putchar
- serial_console_write
- serial_console_setup
- sci_probe_earlyprintk
- sci_probe_earlyprintk
- sci_remove
- sci_parse_dt
- sci_probe_single
- sci_probe
- sci_suspend
- sci_resume
- sci_init
- sci_exit
- early_console_setup
- sci_early_console_setup
- scif_early_console_setup
- rzscifa_early_console_setup
- scifa_early_console_setup
- scifb_early_console_setup
- hscif_early_console_setup
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 #define SUPPORT_SYSRQ
20 #endif
21
22 #undef DEBUG
23
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
39 #include <linux/mm.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
54
55 #ifdef CONFIG_SUPERH
56 #include <asm/sh_bios.h>
57 #endif
58
59 #include "serial_mctrl_gpio.h"
60 #include "sh-sci.h"
61
62
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS,
73 };
74
75 #define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
81 enum SCI_CLKS {
82 SCI_FCK,
83 SCI_SCK,
84 SCI_BRG_INT,
85 SCI_SCIF_CLK,
86 SCI_NUM_CLKS
87 };
88
89
90 #define SCI_SR(x) BIT((x) - 1)
91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
97 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
98 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100
101 #define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
105 struct plat_sci_reg {
106 u8 offset, size;
107 };
108
109 struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
117 };
118
119 struct sci_port {
120 struct uart_port port;
121
122
123 const struct sci_port_params *params;
124 const struct plat_sci_port *cfg;
125 unsigned int sampling_rate_mask;
126 resource_size_t reg_size;
127 struct mctrl_gpios *gpios;
128
129
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
132
133 int irqs[SCIx_NR_IRQS];
134 char *irqstr[SCIx_NR_IRQS];
135
136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
138
139 #ifdef CONFIG_SERIAL_SH_SCI_DMA
140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
147 struct scatterlist sg_rx[2];
148 void *rx_buf[2];
149 size_t buf_len_rx;
150 struct work_struct work_tx;
151 struct hrtimer rx_timer;
152 unsigned int rx_timeout;
153 #endif
154 unsigned int rx_frame;
155 int rx_trigger;
156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
158 u16 hscif_tot;
159
160 bool has_rtscts;
161 bool autorts;
162 };
163
164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165
166 static struct sci_port sci_ports[SCI_NPORTS];
167 static unsigned long sci_ports_in_use;
168 static struct uart_driver sci_uart_driver;
169
170 static inline struct sci_port *
171 to_sci_port(struct uart_port *uart)
172 {
173 return container_of(uart, struct sci_port, port);
174 }
175
176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
177
178
179
180
181 [SCIx_SCI_REGTYPE] = {
182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 },
197
198
199
200
201 [SCIx_IRDA_REGTYPE] = {
202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 },
219
220
221
222
223 [SCIx_SCIFA_REGTYPE] = {
224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 },
243
244
245
246
247 [SCIx_SCIFB_REGTYPE] = {
248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 },
268
269
270
271
272
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
292 },
293
294
295
296
297
298
299
300 [SCIx_RZ_SCIFA_REGTYPE] = {
301 .regs = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
312 },
313 .fifosize = 16,
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
319 },
320
321
322
323
324 [SCIx_SH3_SCIF_REGTYPE] = {
325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
335 .fifosize = 16,
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
341 },
342
343
344
345
346 [SCIx_SH4_SCIF_REGTYPE] = {
347 .regs = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
358 },
359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
365 },
366
367
368
369
370
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
372 .regs = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
385 },
386 .fifosize = 16,
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
392 },
393
394
395
396
397 [SCIx_HSCIF_REGTYPE] = {
398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
414 },
415 .fifosize = 128,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
421 },
422
423
424
425
426
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
428 .regs = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
438 },
439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
445 },
446
447
448
449
450
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 },
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
472 },
473
474
475
476
477
478 [SCIx_SH7705_SCIF_REGTYPE] = {
479 .regs = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
488 },
489 .fifosize = 64,
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
495 },
496 };
497
498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
499
500
501
502
503
504
505
506 static unsigned int sci_serial_in(struct uart_port *p, int offset)
507 {
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
509
510 if (reg->size == 8)
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
514 else
515 WARN(1, "Invalid register access\n");
516
517 return 0;
518 }
519
520 static void sci_serial_out(struct uart_port *p, int offset, int value)
521 {
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
523
524 if (reg->size == 8)
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
528 else
529 WARN(1, "Invalid register access\n");
530 }
531
532 static void sci_port_enable(struct sci_port *sci_port)
533 {
534 unsigned int i;
535
536 if (!sci_port->port.dev)
537 return;
538
539 pm_runtime_get_sync(sci_port->port.dev);
540
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
544 }
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
546 }
547
548 static void sci_port_disable(struct sci_port *sci_port)
549 {
550 unsigned int i;
551
552 if (!sci_port->port.dev)
553 return;
554
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
557
558 pm_runtime_put_sync(sci_port->port.dev);
559 }
560
561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 {
563
564
565
566
567
568
569
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 }
572
573 static void sci_start_tx(struct uart_port *port)
574 {
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594 #endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601 }
602
603 static void sci_stop_tx(struct uart_port *port)
604 {
605 unsigned short ctrl;
606
607
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616 }
617
618 static void sci_start_rx(struct uart_port *port)
619 {
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628 }
629
630 static void sci_stop_rx(struct uart_port *port)
631 {
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642 }
643
644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645 {
646 if (port->type == PORT_SCI) {
647
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650
651
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658 }
659
660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
662
663 #ifdef CONFIG_CONSOLE_POLL
664 static int sci_poll_get_char(struct uart_port *port)
665 {
666 unsigned short status;
667 int c;
668
669 do {
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
673 continue;
674 }
675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
680
681 c = serial_port_in(port, SCxRDR);
682
683
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
686
687 return c;
688 }
689 #endif
690
691 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
692 {
693 unsigned short status;
694
695 do {
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
698
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
701 }
702 #endif
703
704
705 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
706 {
707 struct sci_port *s = to_sci_port(port);
708
709
710
711
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
715 }
716
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 data = serial_port_in(port, SCPDR);
719 u16 ctrl = serial_port_in(port, SCPCR);
720
721
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
723 if (to_sci_port(port)->has_rtscts) {
724
725 if (!(port->mctrl & TIOCM_RTS)) {
726 ctrl |= SCPCR_RTSC;
727 data |= SCPDR_RTSD;
728 } else if (!s->autorts) {
729 ctrl |= SCPCR_RTSC;
730 data &= ~SCPDR_RTSD;
731 } else {
732
733 ctrl &= ~SCPCR_RTSC;
734 }
735
736 ctrl &= ~SCPCR_CTSC;
737 }
738 serial_port_out(port, SCPDR, data);
739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
741 u16 status = serial_port_in(port, SCSPTR);
742
743
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
749
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
752 }
753 }
754
755 static int sci_txfill(struct uart_port *port)
756 {
757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
759 const struct plat_sci_reg *reg;
760
761 reg = sci_getreg(port, SCTFDR);
762 if (reg->size)
763 return serial_port_in(port, SCTFDR) & fifo_mask;
764
765 reg = sci_getreg(port, SCFDR);
766 if (reg->size)
767 return serial_port_in(port, SCFDR) >> 8;
768
769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
770 }
771
772 static int sci_txroom(struct uart_port *port)
773 {
774 return port->fifosize - sci_txfill(port);
775 }
776
777 static int sci_rxfill(struct uart_port *port)
778 {
779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
781 const struct plat_sci_reg *reg;
782
783 reg = sci_getreg(port, SCRFDR);
784 if (reg->size)
785 return serial_port_in(port, SCRFDR) & fifo_mask;
786
787 reg = sci_getreg(port, SCFDR);
788 if (reg->size)
789 return serial_port_in(port, SCFDR) & fifo_mask;
790
791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
792 }
793
794
795
796
797
798 static void sci_transmit_chars(struct uart_port *port)
799 {
800 struct circ_buf *xmit = &port->state->xmit;
801 unsigned int stopped = uart_tx_stopped(port);
802 unsigned short status;
803 unsigned short ctrl;
804 int count;
805
806 status = serial_port_in(port, SCxSR);
807 if (!(status & SCxSR_TDxE(port))) {
808 ctrl = serial_port_in(port, SCSCR);
809 if (uart_circ_empty(xmit))
810 ctrl &= ~SCSCR_TIE;
811 else
812 ctrl |= SCSCR_TIE;
813 serial_port_out(port, SCSCR, ctrl);
814 return;
815 }
816
817 count = sci_txroom(port);
818
819 do {
820 unsigned char c;
821
822 if (port->x_char) {
823 c = port->x_char;
824 port->x_char = 0;
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
828 } else {
829 break;
830 }
831
832 serial_port_out(port, SCxTDR, c);
833
834 port->icount.tx++;
835 } while (--count > 0);
836
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
838
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit))
842 sci_stop_tx(port);
843
844 }
845
846
847 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
848
849 static void sci_receive_chars(struct uart_port *port)
850 {
851 struct tty_port *tport = &port->state->port;
852 int i, count, copied = 0;
853 unsigned short status;
854 unsigned char flag;
855
856 status = serial_port_in(port, SCxSR);
857 if (!(status & SCxSR_RDxF(port)))
858 return;
859
860 while (1) {
861
862 count = tty_buffer_request_room(tport, sci_rxfill(port));
863
864
865 if (count == 0)
866 break;
867
868 if (port->type == PORT_SCI) {
869 char c = serial_port_in(port, SCxRDR);
870 if (uart_handle_sysrq_char(port, c))
871 count = 0;
872 else
873 tty_insert_flip_char(tport, c, TTY_NORMAL);
874 } else {
875 for (i = 0; i < count; i++) {
876 char c;
877
878 if (port->type == PORT_SCIF ||
879 port->type == PORT_HSCIF) {
880 status = serial_port_in(port, SCxSR);
881 c = serial_port_in(port, SCxRDR);
882 } else {
883 c = serial_port_in(port, SCxRDR);
884 status = serial_port_in(port, SCxSR);
885 }
886 if (uart_handle_sysrq_char(port, c)) {
887 count--; i--;
888 continue;
889 }
890
891
892 if (status & SCxSR_FER(port)) {
893 flag = TTY_FRAME;
894 port->icount.frame++;
895 dev_notice(port->dev, "frame error\n");
896 } else if (status & SCxSR_PER(port)) {
897 flag = TTY_PARITY;
898 port->icount.parity++;
899 dev_notice(port->dev, "parity error\n");
900 } else
901 flag = TTY_NORMAL;
902
903 tty_insert_flip_char(tport, c, flag);
904 }
905 }
906
907 serial_port_in(port, SCxSR);
908 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
909
910 copied += count;
911 port->icount.rx += count;
912 }
913
914 if (copied) {
915
916 tty_flip_buffer_push(tport);
917 } else {
918
919 serial_port_in(port, SCxRDR);
920 serial_port_in(port, SCxSR);
921 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
922 }
923 }
924
925 static int sci_handle_errors(struct uart_port *port)
926 {
927 int copied = 0;
928 unsigned short status = serial_port_in(port, SCxSR);
929 struct tty_port *tport = &port->state->port;
930 struct sci_port *s = to_sci_port(port);
931
932
933 if (status & s->params->overrun_mask) {
934 port->icount.overrun++;
935
936
937 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
938 copied++;
939
940 dev_notice(port->dev, "overrun error\n");
941 }
942
943 if (status & SCxSR_FER(port)) {
944
945 port->icount.frame++;
946
947 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
948 copied++;
949
950 dev_notice(port->dev, "frame error\n");
951 }
952
953 if (status & SCxSR_PER(port)) {
954
955 port->icount.parity++;
956
957 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
958 copied++;
959
960 dev_notice(port->dev, "parity error\n");
961 }
962
963 if (copied)
964 tty_flip_buffer_push(tport);
965
966 return copied;
967 }
968
969 static int sci_handle_fifo_overrun(struct uart_port *port)
970 {
971 struct tty_port *tport = &port->state->port;
972 struct sci_port *s = to_sci_port(port);
973 const struct plat_sci_reg *reg;
974 int copied = 0;
975 u16 status;
976
977 reg = sci_getreg(port, s->params->overrun_reg);
978 if (!reg->size)
979 return 0;
980
981 status = serial_port_in(port, s->params->overrun_reg);
982 if (status & s->params->overrun_mask) {
983 status &= ~s->params->overrun_mask;
984 serial_port_out(port, s->params->overrun_reg, status);
985
986 port->icount.overrun++;
987
988 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
989 tty_flip_buffer_push(tport);
990
991 dev_dbg(port->dev, "overrun error\n");
992 copied++;
993 }
994
995 return copied;
996 }
997
998 static int sci_handle_breaks(struct uart_port *port)
999 {
1000 int copied = 0;
1001 unsigned short status = serial_port_in(port, SCxSR);
1002 struct tty_port *tport = &port->state->port;
1003
1004 if (uart_handle_break(port))
1005 return 0;
1006
1007 if (status & SCxSR_BRK(port)) {
1008 port->icount.brk++;
1009
1010
1011 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1012 copied++;
1013
1014 dev_dbg(port->dev, "BREAK detected\n");
1015 }
1016
1017 if (copied)
1018 tty_flip_buffer_push(tport);
1019
1020 copied += sci_handle_fifo_overrun(port);
1021
1022 return copied;
1023 }
1024
1025 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1026 {
1027 unsigned int bits;
1028
1029 if (rx_trig < 1)
1030 rx_trig = 1;
1031 if (rx_trig >= port->fifosize)
1032 rx_trig = port->fifosize;
1033
1034
1035 if (sci_getreg(port, HSRTRGR)->size) {
1036 serial_port_out(port, HSRTRGR, rx_trig);
1037 return rx_trig;
1038 }
1039
1040 switch (port->type) {
1041 case PORT_SCIF:
1042 if (rx_trig < 4) {
1043 bits = 0;
1044 rx_trig = 1;
1045 } else if (rx_trig < 8) {
1046 bits = SCFCR_RTRG0;
1047 rx_trig = 4;
1048 } else if (rx_trig < 14) {
1049 bits = SCFCR_RTRG1;
1050 rx_trig = 8;
1051 } else {
1052 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1053 rx_trig = 14;
1054 }
1055 break;
1056 case PORT_SCIFA:
1057 case PORT_SCIFB:
1058 if (rx_trig < 16) {
1059 bits = 0;
1060 rx_trig = 1;
1061 } else if (rx_trig < 32) {
1062 bits = SCFCR_RTRG0;
1063 rx_trig = 16;
1064 } else if (rx_trig < 48) {
1065 bits = SCFCR_RTRG1;
1066 rx_trig = 32;
1067 } else {
1068 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1069 rx_trig = 48;
1070 }
1071 break;
1072 default:
1073 WARN(1, "unknown FIFO configuration");
1074 return 1;
1075 }
1076
1077 serial_port_out(port, SCFCR,
1078 (serial_port_in(port, SCFCR) &
1079 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1080
1081 return rx_trig;
1082 }
1083
1084 static int scif_rtrg_enabled(struct uart_port *port)
1085 {
1086 if (sci_getreg(port, HSRTRGR)->size)
1087 return serial_port_in(port, HSRTRGR) != 0;
1088 else
1089 return (serial_port_in(port, SCFCR) &
1090 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1091 }
1092
1093 static void rx_fifo_timer_fn(struct timer_list *t)
1094 {
1095 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1096 struct uart_port *port = &s->port;
1097
1098 dev_dbg(port->dev, "Rx timed out\n");
1099 scif_set_rtrg(port, 1);
1100 }
1101
1102 static ssize_t rx_fifo_trigger_show(struct device *dev,
1103 struct device_attribute *attr, char *buf)
1104 {
1105 struct uart_port *port = dev_get_drvdata(dev);
1106 struct sci_port *sci = to_sci_port(port);
1107
1108 return sprintf(buf, "%d\n", sci->rx_trigger);
1109 }
1110
1111 static ssize_t rx_fifo_trigger_store(struct device *dev,
1112 struct device_attribute *attr,
1113 const char *buf, size_t count)
1114 {
1115 struct uart_port *port = dev_get_drvdata(dev);
1116 struct sci_port *sci = to_sci_port(port);
1117 int ret;
1118 long r;
1119
1120 ret = kstrtol(buf, 0, &r);
1121 if (ret)
1122 return ret;
1123
1124 sci->rx_trigger = scif_set_rtrg(port, r);
1125 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1126 scif_set_rtrg(port, 1);
1127
1128 return count;
1129 }
1130
1131 static DEVICE_ATTR_RW(rx_fifo_trigger);
1132
1133 static ssize_t rx_fifo_timeout_show(struct device *dev,
1134 struct device_attribute *attr,
1135 char *buf)
1136 {
1137 struct uart_port *port = dev_get_drvdata(dev);
1138 struct sci_port *sci = to_sci_port(port);
1139 int v;
1140
1141 if (port->type == PORT_HSCIF)
1142 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1143 else
1144 v = sci->rx_fifo_timeout;
1145
1146 return sprintf(buf, "%d\n", v);
1147 }
1148
1149 static ssize_t rx_fifo_timeout_store(struct device *dev,
1150 struct device_attribute *attr,
1151 const char *buf,
1152 size_t count)
1153 {
1154 struct uart_port *port = dev_get_drvdata(dev);
1155 struct sci_port *sci = to_sci_port(port);
1156 int ret;
1157 long r;
1158
1159 ret = kstrtol(buf, 0, &r);
1160 if (ret)
1161 return ret;
1162
1163 if (port->type == PORT_HSCIF) {
1164 if (r < 0 || r > 3)
1165 return -EINVAL;
1166 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1167 } else {
1168 sci->rx_fifo_timeout = r;
1169 scif_set_rtrg(port, 1);
1170 if (r > 0)
1171 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1172 }
1173
1174 return count;
1175 }
1176
1177 static DEVICE_ATTR_RW(rx_fifo_timeout);
1178
1179
1180 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1181 static void sci_dma_tx_complete(void *arg)
1182 {
1183 struct sci_port *s = arg;
1184 struct uart_port *port = &s->port;
1185 struct circ_buf *xmit = &port->state->xmit;
1186 unsigned long flags;
1187
1188 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1189
1190 spin_lock_irqsave(&port->lock, flags);
1191
1192 xmit->tail += s->tx_dma_len;
1193 xmit->tail &= UART_XMIT_SIZE - 1;
1194
1195 port->icount.tx += s->tx_dma_len;
1196
1197 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1198 uart_write_wakeup(port);
1199
1200 if (!uart_circ_empty(xmit)) {
1201 s->cookie_tx = 0;
1202 schedule_work(&s->work_tx);
1203 } else {
1204 s->cookie_tx = -EINVAL;
1205 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1206 u16 ctrl = serial_port_in(port, SCSCR);
1207 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1208 }
1209 }
1210
1211 spin_unlock_irqrestore(&port->lock, flags);
1212 }
1213
1214
1215 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1216 {
1217 struct uart_port *port = &s->port;
1218 struct tty_port *tport = &port->state->port;
1219 int copied;
1220
1221 copied = tty_insert_flip_string(tport, buf, count);
1222 if (copied < count)
1223 port->icount.buf_overrun++;
1224
1225 port->icount.rx += copied;
1226
1227 return copied;
1228 }
1229
1230 static int sci_dma_rx_find_active(struct sci_port *s)
1231 {
1232 unsigned int i;
1233
1234 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1235 if (s->active_rx == s->cookie_rx[i])
1236 return i;
1237
1238 return -1;
1239 }
1240
1241 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1242 {
1243 unsigned int i;
1244
1245 s->chan_rx = NULL;
1246 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1247 s->cookie_rx[i] = -EINVAL;
1248 s->active_rx = 0;
1249 }
1250
1251 static void sci_dma_rx_release(struct sci_port *s)
1252 {
1253 struct dma_chan *chan = s->chan_rx_saved;
1254
1255 s->chan_rx_saved = NULL;
1256 sci_dma_rx_chan_invalidate(s);
1257 dmaengine_terminate_sync(chan);
1258 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1259 sg_dma_address(&s->sg_rx[0]));
1260 dma_release_channel(chan);
1261 }
1262
1263 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1264 {
1265 long sec = usec / 1000000;
1266 long nsec = (usec % 1000000) * 1000;
1267 ktime_t t = ktime_set(sec, nsec);
1268
1269 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1270 }
1271
1272 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1273 {
1274 struct uart_port *port = &s->port;
1275 u16 scr;
1276
1277
1278 scr = serial_port_in(port, SCSCR);
1279 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1280 scr &= ~SCSCR_RDRQE;
1281 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1282 }
1283 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1284 }
1285
1286 static void sci_dma_rx_complete(void *arg)
1287 {
1288 struct sci_port *s = arg;
1289 struct dma_chan *chan = s->chan_rx;
1290 struct uart_port *port = &s->port;
1291 struct dma_async_tx_descriptor *desc;
1292 unsigned long flags;
1293 int active, count = 0;
1294
1295 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1296 s->active_rx);
1297
1298 spin_lock_irqsave(&port->lock, flags);
1299
1300 active = sci_dma_rx_find_active(s);
1301 if (active >= 0)
1302 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1303
1304 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1305
1306 if (count)
1307 tty_flip_buffer_push(&port->state->port);
1308
1309 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1310 DMA_DEV_TO_MEM,
1311 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1312 if (!desc)
1313 goto fail;
1314
1315 desc->callback = sci_dma_rx_complete;
1316 desc->callback_param = s;
1317 s->cookie_rx[active] = dmaengine_submit(desc);
1318 if (dma_submit_error(s->cookie_rx[active]))
1319 goto fail;
1320
1321 s->active_rx = s->cookie_rx[!active];
1322
1323 dma_async_issue_pending(chan);
1324
1325 spin_unlock_irqrestore(&port->lock, flags);
1326 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1327 __func__, s->cookie_rx[active], active, s->active_rx);
1328 return;
1329
1330 fail:
1331 spin_unlock_irqrestore(&port->lock, flags);
1332 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1333
1334 spin_lock_irqsave(&port->lock, flags);
1335 dmaengine_terminate_async(chan);
1336 sci_dma_rx_chan_invalidate(s);
1337 sci_dma_rx_reenable_irq(s);
1338 spin_unlock_irqrestore(&port->lock, flags);
1339 }
1340
1341 static void sci_dma_tx_release(struct sci_port *s)
1342 {
1343 struct dma_chan *chan = s->chan_tx_saved;
1344
1345 cancel_work_sync(&s->work_tx);
1346 s->chan_tx_saved = s->chan_tx = NULL;
1347 s->cookie_tx = -EINVAL;
1348 dmaengine_terminate_sync(chan);
1349 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1350 DMA_TO_DEVICE);
1351 dma_release_channel(chan);
1352 }
1353
1354 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1355 {
1356 struct dma_chan *chan = s->chan_rx;
1357 struct uart_port *port = &s->port;
1358 unsigned long flags;
1359 int i;
1360
1361 for (i = 0; i < 2; i++) {
1362 struct scatterlist *sg = &s->sg_rx[i];
1363 struct dma_async_tx_descriptor *desc;
1364
1365 desc = dmaengine_prep_slave_sg(chan,
1366 sg, 1, DMA_DEV_TO_MEM,
1367 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1368 if (!desc)
1369 goto fail;
1370
1371 desc->callback = sci_dma_rx_complete;
1372 desc->callback_param = s;
1373 s->cookie_rx[i] = dmaengine_submit(desc);
1374 if (dma_submit_error(s->cookie_rx[i]))
1375 goto fail;
1376
1377 }
1378
1379 s->active_rx = s->cookie_rx[0];
1380
1381 dma_async_issue_pending(chan);
1382 return 0;
1383
1384 fail:
1385
1386 if (!port_lock_held)
1387 spin_lock_irqsave(&port->lock, flags);
1388 if (i)
1389 dmaengine_terminate_async(chan);
1390 sci_dma_rx_chan_invalidate(s);
1391 sci_start_rx(port);
1392 if (!port_lock_held)
1393 spin_unlock_irqrestore(&port->lock, flags);
1394 return -EAGAIN;
1395 }
1396
1397 static void sci_dma_tx_work_fn(struct work_struct *work)
1398 {
1399 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1400 struct dma_async_tx_descriptor *desc;
1401 struct dma_chan *chan = s->chan_tx;
1402 struct uart_port *port = &s->port;
1403 struct circ_buf *xmit = &port->state->xmit;
1404 unsigned long flags;
1405 dma_addr_t buf;
1406 int head, tail;
1407
1408
1409
1410
1411
1412
1413
1414
1415 spin_lock_irq(&port->lock);
1416 head = xmit->head;
1417 tail = xmit->tail;
1418 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1419 s->tx_dma_len = min_t(unsigned int,
1420 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1421 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1422 if (!s->tx_dma_len) {
1423
1424 spin_unlock_irq(&port->lock);
1425 return;
1426 }
1427
1428 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1429 DMA_MEM_TO_DEV,
1430 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1431 if (!desc) {
1432 spin_unlock_irq(&port->lock);
1433 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1434 goto switch_to_pio;
1435 }
1436
1437 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1438 DMA_TO_DEVICE);
1439
1440 desc->callback = sci_dma_tx_complete;
1441 desc->callback_param = s;
1442 s->cookie_tx = dmaengine_submit(desc);
1443 if (dma_submit_error(s->cookie_tx)) {
1444 spin_unlock_irq(&port->lock);
1445 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1446 goto switch_to_pio;
1447 }
1448
1449 spin_unlock_irq(&port->lock);
1450 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1451 __func__, xmit->buf, tail, head, s->cookie_tx);
1452
1453 dma_async_issue_pending(chan);
1454 return;
1455
1456 switch_to_pio:
1457 spin_lock_irqsave(&port->lock, flags);
1458 s->chan_tx = NULL;
1459 sci_start_tx(port);
1460 spin_unlock_irqrestore(&port->lock, flags);
1461 return;
1462 }
1463
1464 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1465 {
1466 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1467 struct dma_chan *chan = s->chan_rx;
1468 struct uart_port *port = &s->port;
1469 struct dma_tx_state state;
1470 enum dma_status status;
1471 unsigned long flags;
1472 unsigned int read;
1473 int active, count;
1474
1475 dev_dbg(port->dev, "DMA Rx timed out\n");
1476
1477 spin_lock_irqsave(&port->lock, flags);
1478
1479 active = sci_dma_rx_find_active(s);
1480 if (active < 0) {
1481 spin_unlock_irqrestore(&port->lock, flags);
1482 return HRTIMER_NORESTART;
1483 }
1484
1485 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1486 if (status == DMA_COMPLETE) {
1487 spin_unlock_irqrestore(&port->lock, flags);
1488 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1489 s->active_rx, active);
1490
1491
1492 return HRTIMER_NORESTART;
1493 }
1494
1495 dmaengine_pause(chan);
1496
1497
1498
1499
1500
1501
1502
1503 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1504 if (status == DMA_COMPLETE) {
1505 spin_unlock_irqrestore(&port->lock, flags);
1506 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1507 return HRTIMER_NORESTART;
1508 }
1509
1510
1511 dmaengine_terminate_async(s->chan_rx);
1512 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1513
1514 if (read) {
1515 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1516 if (count)
1517 tty_flip_buffer_push(&port->state->port);
1518 }
1519
1520 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1521 sci_dma_rx_submit(s, true);
1522
1523 sci_dma_rx_reenable_irq(s);
1524
1525 spin_unlock_irqrestore(&port->lock, flags);
1526
1527 return HRTIMER_NORESTART;
1528 }
1529
1530 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1531 enum dma_transfer_direction dir)
1532 {
1533 struct dma_chan *chan;
1534 struct dma_slave_config cfg;
1535 int ret;
1536
1537 chan = dma_request_slave_channel(port->dev,
1538 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1539 if (!chan) {
1540 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1541 return NULL;
1542 }
1543
1544 memset(&cfg, 0, sizeof(cfg));
1545 cfg.direction = dir;
1546 if (dir == DMA_MEM_TO_DEV) {
1547 cfg.dst_addr = port->mapbase +
1548 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1549 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1550 } else {
1551 cfg.src_addr = port->mapbase +
1552 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1553 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1554 }
1555
1556 ret = dmaengine_slave_config(chan, &cfg);
1557 if (ret) {
1558 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1559 dma_release_channel(chan);
1560 return NULL;
1561 }
1562
1563 return chan;
1564 }
1565
1566 static void sci_request_dma(struct uart_port *port)
1567 {
1568 struct sci_port *s = to_sci_port(port);
1569 struct dma_chan *chan;
1570
1571 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1572
1573
1574
1575
1576
1577 if (uart_console(port))
1578 return;
1579
1580 if (!port->dev->of_node)
1581 return;
1582
1583 s->cookie_tx = -EINVAL;
1584
1585
1586
1587
1588
1589 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1590 return;
1591
1592 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1593 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1594 if (chan) {
1595
1596 s->tx_dma_addr = dma_map_single(chan->device->dev,
1597 port->state->xmit.buf,
1598 UART_XMIT_SIZE,
1599 DMA_TO_DEVICE);
1600 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1601 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1602 dma_release_channel(chan);
1603 } else {
1604 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1605 __func__, UART_XMIT_SIZE,
1606 port->state->xmit.buf, &s->tx_dma_addr);
1607
1608 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1609 s->chan_tx_saved = s->chan_tx = chan;
1610 }
1611 }
1612
1613 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1614 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1615 if (chan) {
1616 unsigned int i;
1617 dma_addr_t dma;
1618 void *buf;
1619
1620 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1621 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1622 &dma, GFP_KERNEL);
1623 if (!buf) {
1624 dev_warn(port->dev,
1625 "Failed to allocate Rx dma buffer, using PIO\n");
1626 dma_release_channel(chan);
1627 return;
1628 }
1629
1630 for (i = 0; i < 2; i++) {
1631 struct scatterlist *sg = &s->sg_rx[i];
1632
1633 sg_init_table(sg, 1);
1634 s->rx_buf[i] = buf;
1635 sg_dma_address(sg) = dma;
1636 sg_dma_len(sg) = s->buf_len_rx;
1637
1638 buf += s->buf_len_rx;
1639 dma += s->buf_len_rx;
1640 }
1641
1642 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1643 s->rx_timer.function = sci_dma_rx_timer_fn;
1644
1645 s->chan_rx_saved = s->chan_rx = chan;
1646
1647 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1648 sci_dma_rx_submit(s, false);
1649 }
1650 }
1651
1652 static void sci_free_dma(struct uart_port *port)
1653 {
1654 struct sci_port *s = to_sci_port(port);
1655
1656 if (s->chan_tx_saved)
1657 sci_dma_tx_release(s);
1658 if (s->chan_rx_saved)
1659 sci_dma_rx_release(s);
1660 }
1661
1662 static void sci_flush_buffer(struct uart_port *port)
1663 {
1664 struct sci_port *s = to_sci_port(port);
1665
1666
1667
1668
1669
1670
1671 s->tx_dma_len = 0;
1672 if (s->chan_tx) {
1673 dmaengine_terminate_async(s->chan_tx);
1674 s->cookie_tx = -EINVAL;
1675 }
1676 }
1677 #else
1678 static inline void sci_request_dma(struct uart_port *port)
1679 {
1680 }
1681
1682 static inline void sci_free_dma(struct uart_port *port)
1683 {
1684 }
1685
1686 #define sci_flush_buffer NULL
1687 #endif
1688
1689 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1690 {
1691 struct uart_port *port = ptr;
1692 struct sci_port *s = to_sci_port(port);
1693
1694 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1695 if (s->chan_rx) {
1696 u16 scr = serial_port_in(port, SCSCR);
1697 u16 ssr = serial_port_in(port, SCxSR);
1698
1699
1700 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1701 disable_irq_nosync(irq);
1702 scr |= SCSCR_RDRQE;
1703 } else {
1704 if (sci_dma_rx_submit(s, false) < 0)
1705 goto handle_pio;
1706
1707 scr &= ~SCSCR_RIE;
1708 }
1709 serial_port_out(port, SCSCR, scr);
1710
1711 serial_port_out(port, SCxSR,
1712 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1713 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1714 jiffies, s->rx_timeout);
1715 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1716
1717 return IRQ_HANDLED;
1718 }
1719
1720 handle_pio:
1721 #endif
1722
1723 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1724 if (!scif_rtrg_enabled(port))
1725 scif_set_rtrg(port, s->rx_trigger);
1726
1727 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1728 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1729 }
1730
1731
1732
1733
1734
1735 sci_receive_chars(port);
1736
1737 return IRQ_HANDLED;
1738 }
1739
1740 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1741 {
1742 struct uart_port *port = ptr;
1743 unsigned long flags;
1744
1745 spin_lock_irqsave(&port->lock, flags);
1746 sci_transmit_chars(port);
1747 spin_unlock_irqrestore(&port->lock, flags);
1748
1749 return IRQ_HANDLED;
1750 }
1751
1752 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1753 {
1754 struct uart_port *port = ptr;
1755
1756
1757 sci_handle_breaks(port);
1758 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1759
1760 return IRQ_HANDLED;
1761 }
1762
1763 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1764 {
1765 struct uart_port *port = ptr;
1766 struct sci_port *s = to_sci_port(port);
1767
1768 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1769
1770 unsigned short ssr_status = serial_port_in(port, SCxSR);
1771
1772
1773 if (ssr_status & SCxSR_BRK(port))
1774 sci_br_interrupt(irq, ptr);
1775
1776
1777 if (!(ssr_status & SCxSR_ERRORS(port)))
1778 return IRQ_HANDLED;
1779 }
1780
1781
1782 if (port->type == PORT_SCI) {
1783 if (sci_handle_errors(port)) {
1784
1785 serial_port_in(port, SCxSR);
1786 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1787 }
1788 } else {
1789 sci_handle_fifo_overrun(port);
1790 if (!s->chan_rx)
1791 sci_receive_chars(port);
1792 }
1793
1794 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1795
1796
1797 if (!s->chan_tx)
1798 sci_tx_interrupt(irq, ptr);
1799
1800 return IRQ_HANDLED;
1801 }
1802
1803 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1804 {
1805 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1806 struct uart_port *port = ptr;
1807 struct sci_port *s = to_sci_port(port);
1808 irqreturn_t ret = IRQ_NONE;
1809
1810 ssr_status = serial_port_in(port, SCxSR);
1811 scr_status = serial_port_in(port, SCSCR);
1812 if (s->params->overrun_reg == SCxSR)
1813 orer_status = ssr_status;
1814 else if (sci_getreg(port, s->params->overrun_reg)->size)
1815 orer_status = serial_port_in(port, s->params->overrun_reg);
1816
1817 err_enabled = scr_status & port_rx_irq_mask(port);
1818
1819
1820 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1821 !s->chan_tx)
1822 ret = sci_tx_interrupt(irq, ptr);
1823
1824
1825
1826
1827
1828 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1829 (scr_status & SCSCR_RIE))
1830 ret = sci_rx_interrupt(irq, ptr);
1831
1832
1833 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1834 ret = sci_er_interrupt(irq, ptr);
1835
1836
1837 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1838 ret = sci_br_interrupt(irq, ptr);
1839
1840
1841 if (orer_status & s->params->overrun_mask) {
1842 sci_handle_fifo_overrun(port);
1843 ret = IRQ_HANDLED;
1844 }
1845
1846 return ret;
1847 }
1848
1849 static const struct sci_irq_desc {
1850 const char *desc;
1851 irq_handler_t handler;
1852 } sci_irq_desc[] = {
1853
1854
1855
1856 [SCIx_ERI_IRQ] = {
1857 .desc = "rx err",
1858 .handler = sci_er_interrupt,
1859 },
1860
1861 [SCIx_RXI_IRQ] = {
1862 .desc = "rx full",
1863 .handler = sci_rx_interrupt,
1864 },
1865
1866 [SCIx_TXI_IRQ] = {
1867 .desc = "tx empty",
1868 .handler = sci_tx_interrupt,
1869 },
1870
1871 [SCIx_BRI_IRQ] = {
1872 .desc = "break",
1873 .handler = sci_br_interrupt,
1874 },
1875
1876 [SCIx_DRI_IRQ] = {
1877 .desc = "rx ready",
1878 .handler = sci_rx_interrupt,
1879 },
1880
1881 [SCIx_TEI_IRQ] = {
1882 .desc = "tx end",
1883 .handler = sci_tx_interrupt,
1884 },
1885
1886
1887
1888
1889 [SCIx_MUX_IRQ] = {
1890 .desc = "mux",
1891 .handler = sci_mpxed_interrupt,
1892 },
1893 };
1894
1895 static int sci_request_irq(struct sci_port *port)
1896 {
1897 struct uart_port *up = &port->port;
1898 int i, j, w, ret = 0;
1899
1900 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1901 const struct sci_irq_desc *desc;
1902 int irq;
1903
1904
1905 for (w = 0; w < i; w++)
1906 if (port->irqs[w] == port->irqs[i])
1907 w = i + 1;
1908 if (w > i)
1909 continue;
1910
1911 if (SCIx_IRQ_IS_MUXED(port)) {
1912 i = SCIx_MUX_IRQ;
1913 irq = up->irq;
1914 } else {
1915 irq = port->irqs[i];
1916
1917
1918
1919
1920
1921 if (unlikely(irq < 0))
1922 continue;
1923 }
1924
1925 desc = sci_irq_desc + i;
1926 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1927 dev_name(up->dev), desc->desc);
1928 if (!port->irqstr[j]) {
1929 ret = -ENOMEM;
1930 goto out_nomem;
1931 }
1932
1933 ret = request_irq(irq, desc->handler, up->irqflags,
1934 port->irqstr[j], port);
1935 if (unlikely(ret)) {
1936 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1937 goto out_noirq;
1938 }
1939 }
1940
1941 return 0;
1942
1943 out_noirq:
1944 while (--i >= 0)
1945 free_irq(port->irqs[i], port);
1946
1947 out_nomem:
1948 while (--j >= 0)
1949 kfree(port->irqstr[j]);
1950
1951 return ret;
1952 }
1953
1954 static void sci_free_irq(struct sci_port *port)
1955 {
1956 int i, j;
1957
1958
1959
1960
1961
1962 for (i = 0; i < SCIx_NR_IRQS; i++) {
1963 int irq = port->irqs[i];
1964
1965
1966
1967
1968
1969 if (unlikely(irq < 0))
1970 continue;
1971
1972
1973 for (j = 0; j < i; j++)
1974 if (port->irqs[j] == irq)
1975 j = i + 1;
1976 if (j > i)
1977 continue;
1978
1979 free_irq(port->irqs[i], port);
1980 kfree(port->irqstr[i]);
1981
1982 if (SCIx_IRQ_IS_MUXED(port)) {
1983
1984 return;
1985 }
1986 }
1987 }
1988
1989 static unsigned int sci_tx_empty(struct uart_port *port)
1990 {
1991 unsigned short status = serial_port_in(port, SCxSR);
1992 unsigned short in_tx_fifo = sci_txfill(port);
1993
1994 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1995 }
1996
1997 static void sci_set_rts(struct uart_port *port, bool state)
1998 {
1999 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2000 u16 data = serial_port_in(port, SCPDR);
2001
2002
2003 if (state)
2004 data &= ~SCPDR_RTSD;
2005 else
2006 data |= SCPDR_RTSD;
2007 serial_port_out(port, SCPDR, data);
2008
2009
2010 serial_port_out(port, SCPCR,
2011 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2012 } else if (sci_getreg(port, SCSPTR)->size) {
2013 u16 ctrl = serial_port_in(port, SCSPTR);
2014
2015
2016 if (state)
2017 ctrl &= ~SCSPTR_RTSDT;
2018 else
2019 ctrl |= SCSPTR_RTSDT;
2020 serial_port_out(port, SCSPTR, ctrl);
2021 }
2022 }
2023
2024 static bool sci_get_cts(struct uart_port *port)
2025 {
2026 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2027
2028 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2029 } else if (sci_getreg(port, SCSPTR)->size) {
2030
2031 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2032 }
2033
2034 return true;
2035 }
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2050 {
2051 struct sci_port *s = to_sci_port(port);
2052
2053 if (mctrl & TIOCM_LOOP) {
2054 const struct plat_sci_reg *reg;
2055
2056
2057
2058
2059 reg = sci_getreg(port, SCFCR);
2060 if (reg->size)
2061 serial_port_out(port, SCFCR,
2062 serial_port_in(port, SCFCR) |
2063 SCFCR_LOOP);
2064 }
2065
2066 mctrl_gpio_set(s->gpios, mctrl);
2067
2068 if (!s->has_rtscts)
2069 return;
2070
2071 if (!(mctrl & TIOCM_RTS)) {
2072
2073 serial_port_out(port, SCFCR,
2074 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2075
2076
2077 sci_set_rts(port, 0);
2078 } else if (s->autorts) {
2079 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2080
2081 serial_port_out(port, SCPCR,
2082 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2083 }
2084
2085
2086 serial_port_out(port, SCFCR,
2087 serial_port_in(port, SCFCR) | SCFCR_MCE);
2088 } else {
2089
2090 sci_set_rts(port, 1);
2091 }
2092 }
2093
2094 static unsigned int sci_get_mctrl(struct uart_port *port)
2095 {
2096 struct sci_port *s = to_sci_port(port);
2097 struct mctrl_gpios *gpios = s->gpios;
2098 unsigned int mctrl = 0;
2099
2100 mctrl_gpio_get(gpios, &mctrl);
2101
2102
2103
2104
2105
2106 if (s->autorts) {
2107 if (sci_get_cts(port))
2108 mctrl |= TIOCM_CTS;
2109 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2110 mctrl |= TIOCM_CTS;
2111 }
2112 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2113 mctrl |= TIOCM_DSR;
2114 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2115 mctrl |= TIOCM_CAR;
2116
2117 return mctrl;
2118 }
2119
2120 static void sci_enable_ms(struct uart_port *port)
2121 {
2122 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2123 }
2124
2125 static void sci_break_ctl(struct uart_port *port, int break_state)
2126 {
2127 unsigned short scscr, scsptr;
2128 unsigned long flags;
2129
2130
2131 if (!sci_getreg(port, SCSPTR)->size) {
2132
2133
2134
2135
2136 return;
2137 }
2138
2139 spin_lock_irqsave(&port->lock, flags);
2140 scsptr = serial_port_in(port, SCSPTR);
2141 scscr = serial_port_in(port, SCSCR);
2142
2143 if (break_state == -1) {
2144 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2145 scscr &= ~SCSCR_TE;
2146 } else {
2147 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2148 scscr |= SCSCR_TE;
2149 }
2150
2151 serial_port_out(port, SCSPTR, scsptr);
2152 serial_port_out(port, SCSCR, scscr);
2153 spin_unlock_irqrestore(&port->lock, flags);
2154 }
2155
2156 static int sci_startup(struct uart_port *port)
2157 {
2158 struct sci_port *s = to_sci_port(port);
2159 int ret;
2160
2161 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2162
2163 sci_request_dma(port);
2164
2165 ret = sci_request_irq(s);
2166 if (unlikely(ret < 0)) {
2167 sci_free_dma(port);
2168 return ret;
2169 }
2170
2171 return 0;
2172 }
2173
2174 static void sci_shutdown(struct uart_port *port)
2175 {
2176 struct sci_port *s = to_sci_port(port);
2177 unsigned long flags;
2178 u16 scr;
2179
2180 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2181
2182 s->autorts = false;
2183 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2184
2185 spin_lock_irqsave(&port->lock, flags);
2186 sci_stop_rx(port);
2187 sci_stop_tx(port);
2188
2189
2190
2191
2192 scr = serial_port_in(port, SCSCR);
2193 serial_port_out(port, SCSCR, scr &
2194 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2195 spin_unlock_irqrestore(&port->lock, flags);
2196
2197 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2198 if (s->chan_rx_saved) {
2199 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2200 port->line);
2201 hrtimer_cancel(&s->rx_timer);
2202 }
2203 #endif
2204
2205 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2206 del_timer_sync(&s->rx_fifo_timer);
2207 sci_free_irq(s);
2208 sci_free_dma(port);
2209 }
2210
2211 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2212 unsigned int *srr)
2213 {
2214 unsigned long freq = s->clk_rates[SCI_SCK];
2215 int err, min_err = INT_MAX;
2216 unsigned int sr;
2217
2218 if (s->port.type != PORT_HSCIF)
2219 freq *= 2;
2220
2221 for_each_sr(sr, s) {
2222 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2223 if (abs(err) >= abs(min_err))
2224 continue;
2225
2226 min_err = err;
2227 *srr = sr - 1;
2228
2229 if (!err)
2230 break;
2231 }
2232
2233 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2234 *srr + 1);
2235 return min_err;
2236 }
2237
2238 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2239 unsigned long freq, unsigned int *dlr,
2240 unsigned int *srr)
2241 {
2242 int err, min_err = INT_MAX;
2243 unsigned int sr, dl;
2244
2245 if (s->port.type != PORT_HSCIF)
2246 freq *= 2;
2247
2248 for_each_sr(sr, s) {
2249 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2250 dl = clamp(dl, 1U, 65535U);
2251
2252 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2253 if (abs(err) >= abs(min_err))
2254 continue;
2255
2256 min_err = err;
2257 *dlr = dl;
2258 *srr = sr - 1;
2259
2260 if (!err)
2261 break;
2262 }
2263
2264 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2265 min_err, *dlr, *srr + 1);
2266 return min_err;
2267 }
2268
2269
2270 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2271 unsigned int *brr, unsigned int *srr,
2272 unsigned int *cks)
2273 {
2274 unsigned long freq = s->clk_rates[SCI_FCK];
2275 unsigned int sr, br, prediv, scrate, c;
2276 int err, min_err = INT_MAX;
2277
2278 if (s->port.type != PORT_HSCIF)
2279 freq *= 2;
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296 for_each_sr(sr, s) {
2297 for (c = 0; c <= 3; c++) {
2298
2299 prediv = sr * (1 << (2 * c + 1));
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310 if (bps > UINT_MAX / prediv)
2311 break;
2312
2313 scrate = prediv * bps;
2314 br = DIV_ROUND_CLOSEST(freq, scrate);
2315 br = clamp(br, 1U, 256U);
2316
2317 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2318 if (abs(err) >= abs(min_err))
2319 continue;
2320
2321 min_err = err;
2322 *brr = br - 1;
2323 *srr = sr - 1;
2324 *cks = c;
2325
2326 if (!err)
2327 goto found;
2328 }
2329 }
2330
2331 found:
2332 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2333 min_err, *brr, *srr + 1, *cks);
2334 return min_err;
2335 }
2336
2337 static void sci_reset(struct uart_port *port)
2338 {
2339 const struct plat_sci_reg *reg;
2340 unsigned int status;
2341 struct sci_port *s = to_sci_port(port);
2342
2343 serial_port_out(port, SCSCR, s->hscif_tot);
2344
2345 reg = sci_getreg(port, SCFCR);
2346 if (reg->size)
2347 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2348
2349 sci_clear_SCxSR(port,
2350 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2351 SCxSR_BREAK_CLEAR(port));
2352 if (sci_getreg(port, SCLSR)->size) {
2353 status = serial_port_in(port, SCLSR);
2354 status &= ~(SCLSR_TO | SCLSR_ORER);
2355 serial_port_out(port, SCLSR, status);
2356 }
2357
2358 if (s->rx_trigger > 1) {
2359 if (s->rx_fifo_timeout) {
2360 scif_set_rtrg(port, 1);
2361 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2362 } else {
2363 if (port->type == PORT_SCIFA ||
2364 port->type == PORT_SCIFB)
2365 scif_set_rtrg(port, 1);
2366 else
2367 scif_set_rtrg(port, s->rx_trigger);
2368 }
2369 }
2370 }
2371
2372 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2373 struct ktermios *old)
2374 {
2375 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2376 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2377 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2378 struct sci_port *s = to_sci_port(port);
2379 const struct plat_sci_reg *reg;
2380 int min_err = INT_MAX, err;
2381 unsigned long max_freq = 0;
2382 int best_clk = -1;
2383 unsigned long flags;
2384
2385 if ((termios->c_cflag & CSIZE) == CS7)
2386 smr_val |= SCSMR_CHR;
2387 if (termios->c_cflag & PARENB)
2388 smr_val |= SCSMR_PE;
2389 if (termios->c_cflag & PARODD)
2390 smr_val |= SCSMR_PE | SCSMR_ODD;
2391 if (termios->c_cflag & CSTOPB)
2392 smr_val |= SCSMR_STOP;
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402 if (!port->uartclk) {
2403 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2404 goto done;
2405 }
2406
2407 for (i = 0; i < SCI_NUM_CLKS; i++)
2408 max_freq = max(max_freq, s->clk_rates[i]);
2409
2410 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2411 if (!baud)
2412 goto done;
2413
2414
2415
2416
2417
2418
2419
2420 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2421 port->type != PORT_SCIFB) {
2422 err = sci_sck_calc(s, baud, &srr1);
2423 if (abs(err) < abs(min_err)) {
2424 best_clk = SCI_SCK;
2425 scr_val = SCSCR_CKE1;
2426 sccks = SCCKS_CKS;
2427 min_err = err;
2428 srr = srr1;
2429 if (!err)
2430 goto done;
2431 }
2432 }
2433
2434
2435 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2436 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2437 &srr1);
2438 if (abs(err) < abs(min_err)) {
2439 best_clk = SCI_SCIF_CLK;
2440 scr_val = SCSCR_CKE1;
2441 sccks = 0;
2442 min_err = err;
2443 dl = dl1;
2444 srr = srr1;
2445 if (!err)
2446 goto done;
2447 }
2448 }
2449
2450
2451 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2452 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2453 &srr1);
2454 if (abs(err) < abs(min_err)) {
2455 best_clk = SCI_BRG_INT;
2456 scr_val = SCSCR_CKE1;
2457 sccks = SCCKS_XIN;
2458 min_err = err;
2459 dl = dl1;
2460 srr = srr1;
2461 if (!min_err)
2462 goto done;
2463 }
2464 }
2465
2466
2467 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2468 if (abs(err) < abs(min_err)) {
2469 best_clk = SCI_FCK;
2470 scr_val = 0;
2471 min_err = err;
2472 brr = brr1;
2473 srr = srr1;
2474 cks = cks1;
2475 }
2476
2477 done:
2478 if (best_clk >= 0)
2479 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2480 s->clks[best_clk], baud, min_err);
2481
2482 sci_port_enable(s);
2483
2484
2485
2486
2487
2488 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2489 serial_port_out(port, SCDL, dl);
2490 serial_port_out(port, SCCKS, sccks);
2491 }
2492
2493 spin_lock_irqsave(&port->lock, flags);
2494
2495 sci_reset(port);
2496
2497 uart_update_timeout(port, termios->c_cflag, baud);
2498
2499
2500 switch (termios->c_cflag & CSIZE) {
2501 case CS5:
2502 bits = 7;
2503 break;
2504 case CS6:
2505 bits = 8;
2506 break;
2507 case CS7:
2508 bits = 9;
2509 break;
2510 default:
2511 bits = 10;
2512 break;
2513 }
2514
2515 if (termios->c_cflag & CSTOPB)
2516 bits++;
2517 if (termios->c_cflag & PARENB)
2518 bits++;
2519
2520 if (best_clk >= 0) {
2521 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2522 switch (srr + 1) {
2523 case 5: smr_val |= SCSMR_SRC_5; break;
2524 case 7: smr_val |= SCSMR_SRC_7; break;
2525 case 11: smr_val |= SCSMR_SRC_11; break;
2526 case 13: smr_val |= SCSMR_SRC_13; break;
2527 case 16: smr_val |= SCSMR_SRC_16; break;
2528 case 17: smr_val |= SCSMR_SRC_17; break;
2529 case 19: smr_val |= SCSMR_SRC_19; break;
2530 case 27: smr_val |= SCSMR_SRC_27; break;
2531 }
2532 smr_val |= cks;
2533 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2534 serial_port_out(port, SCSMR, smr_val);
2535 serial_port_out(port, SCBRR, brr);
2536 if (sci_getreg(port, HSSRR)->size) {
2537 unsigned int hssrr = srr | HSCIF_SRE;
2538
2539
2540
2541 int last_stop = bits * 2 - 1;
2542 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2543 (int)(srr + 1),
2544 2 * (int)baud);
2545
2546 if (abs(deviation) >= 2) {
2547
2548
2549
2550
2551 int shift = clamp(deviation / 2, -8, 7);
2552
2553 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2554 HSCIF_SRHP_MASK;
2555 hssrr |= HSCIF_SRDE;
2556 }
2557 serial_port_out(port, HSSRR, hssrr);
2558 }
2559
2560
2561 udelay((1000000 + (baud - 1)) / baud);
2562 } else {
2563
2564 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2565 smr_val |= serial_port_in(port, SCSMR) &
2566 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2567 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2568 serial_port_out(port, SCSMR, smr_val);
2569 }
2570
2571 sci_init_pins(port, termios->c_cflag);
2572
2573 port->status &= ~UPSTAT_AUTOCTS;
2574 s->autorts = false;
2575 reg = sci_getreg(port, SCFCR);
2576 if (reg->size) {
2577 unsigned short ctrl = serial_port_in(port, SCFCR);
2578
2579 if ((port->flags & UPF_HARD_FLOW) &&
2580 (termios->c_cflag & CRTSCTS)) {
2581
2582 port->status |= UPSTAT_AUTOCTS;
2583
2584 s->autorts = true;
2585 }
2586
2587
2588
2589
2590
2591
2592 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2593
2594 serial_port_out(port, SCFCR, ctrl);
2595 }
2596 if (port->flags & UPF_HARD_FLOW) {
2597
2598 sci_set_mctrl(port, port->mctrl);
2599 }
2600
2601 scr_val |= SCSCR_RE | SCSCR_TE |
2602 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2603 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2604 if ((srr + 1 == 5) &&
2605 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2606
2607
2608
2609
2610
2611
2612 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2613 }
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625 s->rx_frame = (10000 * bits) / (baud / 100);
2626 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2627 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2628 if (s->rx_timeout < 20)
2629 s->rx_timeout = 20;
2630 #endif
2631
2632 if ((termios->c_cflag & CREAD) != 0)
2633 sci_start_rx(port);
2634
2635 spin_unlock_irqrestore(&port->lock, flags);
2636
2637 sci_port_disable(s);
2638
2639 if (UART_ENABLE_MS(port, termios->c_cflag))
2640 sci_enable_ms(port);
2641 }
2642
2643 static void sci_pm(struct uart_port *port, unsigned int state,
2644 unsigned int oldstate)
2645 {
2646 struct sci_port *sci_port = to_sci_port(port);
2647
2648 switch (state) {
2649 case UART_PM_STATE_OFF:
2650 sci_port_disable(sci_port);
2651 break;
2652 default:
2653 sci_port_enable(sci_port);
2654 break;
2655 }
2656 }
2657
2658 static const char *sci_type(struct uart_port *port)
2659 {
2660 switch (port->type) {
2661 case PORT_IRDA:
2662 return "irda";
2663 case PORT_SCI:
2664 return "sci";
2665 case PORT_SCIF:
2666 return "scif";
2667 case PORT_SCIFA:
2668 return "scifa";
2669 case PORT_SCIFB:
2670 return "scifb";
2671 case PORT_HSCIF:
2672 return "hscif";
2673 }
2674
2675 return NULL;
2676 }
2677
2678 static int sci_remap_port(struct uart_port *port)
2679 {
2680 struct sci_port *sport = to_sci_port(port);
2681
2682
2683
2684
2685 if (port->membase)
2686 return 0;
2687
2688 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2689 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2690 if (unlikely(!port->membase)) {
2691 dev_err(port->dev, "can't remap port#%d\n", port->line);
2692 return -ENXIO;
2693 }
2694 } else {
2695
2696
2697
2698
2699
2700 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2701 }
2702
2703 return 0;
2704 }
2705
2706 static void sci_release_port(struct uart_port *port)
2707 {
2708 struct sci_port *sport = to_sci_port(port);
2709
2710 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2711 iounmap(port->membase);
2712 port->membase = NULL;
2713 }
2714
2715 release_mem_region(port->mapbase, sport->reg_size);
2716 }
2717
2718 static int sci_request_port(struct uart_port *port)
2719 {
2720 struct resource *res;
2721 struct sci_port *sport = to_sci_port(port);
2722 int ret;
2723
2724 res = request_mem_region(port->mapbase, sport->reg_size,
2725 dev_name(port->dev));
2726 if (unlikely(res == NULL)) {
2727 dev_err(port->dev, "request_mem_region failed.");
2728 return -EBUSY;
2729 }
2730
2731 ret = sci_remap_port(port);
2732 if (unlikely(ret != 0)) {
2733 release_resource(res);
2734 return ret;
2735 }
2736
2737 return 0;
2738 }
2739
2740 static void sci_config_port(struct uart_port *port, int flags)
2741 {
2742 if (flags & UART_CONFIG_TYPE) {
2743 struct sci_port *sport = to_sci_port(port);
2744
2745 port->type = sport->cfg->type;
2746 sci_request_port(port);
2747 }
2748 }
2749
2750 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2751 {
2752 if (ser->baud_base < 2400)
2753
2754 return -EINVAL;
2755
2756 return 0;
2757 }
2758
2759 static const struct uart_ops sci_uart_ops = {
2760 .tx_empty = sci_tx_empty,
2761 .set_mctrl = sci_set_mctrl,
2762 .get_mctrl = sci_get_mctrl,
2763 .start_tx = sci_start_tx,
2764 .stop_tx = sci_stop_tx,
2765 .stop_rx = sci_stop_rx,
2766 .enable_ms = sci_enable_ms,
2767 .break_ctl = sci_break_ctl,
2768 .startup = sci_startup,
2769 .shutdown = sci_shutdown,
2770 .flush_buffer = sci_flush_buffer,
2771 .set_termios = sci_set_termios,
2772 .pm = sci_pm,
2773 .type = sci_type,
2774 .release_port = sci_release_port,
2775 .request_port = sci_request_port,
2776 .config_port = sci_config_port,
2777 .verify_port = sci_verify_port,
2778 #ifdef CONFIG_CONSOLE_POLL
2779 .poll_get_char = sci_poll_get_char,
2780 .poll_put_char = sci_poll_put_char,
2781 #endif
2782 };
2783
2784 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2785 {
2786 const char *clk_names[] = {
2787 [SCI_FCK] = "fck",
2788 [SCI_SCK] = "sck",
2789 [SCI_BRG_INT] = "brg_int",
2790 [SCI_SCIF_CLK] = "scif_clk",
2791 };
2792 struct clk *clk;
2793 unsigned int i;
2794
2795 if (sci_port->cfg->type == PORT_HSCIF)
2796 clk_names[SCI_SCK] = "hsck";
2797
2798 for (i = 0; i < SCI_NUM_CLKS; i++) {
2799 clk = devm_clk_get(dev, clk_names[i]);
2800 if (PTR_ERR(clk) == -EPROBE_DEFER)
2801 return -EPROBE_DEFER;
2802
2803 if (IS_ERR(clk) && i == SCI_FCK) {
2804
2805
2806
2807
2808 clk = devm_clk_get(dev, "sci_ick");
2809 if (PTR_ERR(clk) == -EPROBE_DEFER)
2810 return -EPROBE_DEFER;
2811
2812 if (!IS_ERR(clk))
2813 goto found;
2814
2815
2816
2817
2818
2819
2820 clk = devm_clk_get(dev, "peripheral_clk");
2821 if (!IS_ERR(clk))
2822 goto found;
2823
2824 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2825 PTR_ERR(clk));
2826 return PTR_ERR(clk);
2827 }
2828
2829 found:
2830 if (IS_ERR(clk))
2831 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2832 PTR_ERR(clk));
2833 else
2834 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2835 clk, clk_get_rate(clk));
2836 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2837 }
2838 return 0;
2839 }
2840
2841 static const struct sci_port_params *
2842 sci_probe_regmap(const struct plat_sci_port *cfg)
2843 {
2844 unsigned int regtype;
2845
2846 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2847 return &sci_port_params[cfg->regtype];
2848
2849 switch (cfg->type) {
2850 case PORT_SCI:
2851 regtype = SCIx_SCI_REGTYPE;
2852 break;
2853 case PORT_IRDA:
2854 regtype = SCIx_IRDA_REGTYPE;
2855 break;
2856 case PORT_SCIFA:
2857 regtype = SCIx_SCIFA_REGTYPE;
2858 break;
2859 case PORT_SCIFB:
2860 regtype = SCIx_SCIFB_REGTYPE;
2861 break;
2862 case PORT_SCIF:
2863
2864
2865
2866
2867
2868
2869 regtype = SCIx_SH4_SCIF_REGTYPE;
2870 break;
2871 case PORT_HSCIF:
2872 regtype = SCIx_HSCIF_REGTYPE;
2873 break;
2874 default:
2875 pr_err("Can't probe register map for given port\n");
2876 return NULL;
2877 }
2878
2879 return &sci_port_params[regtype];
2880 }
2881
2882 static int sci_init_single(struct platform_device *dev,
2883 struct sci_port *sci_port, unsigned int index,
2884 const struct plat_sci_port *p, bool early)
2885 {
2886 struct uart_port *port = &sci_port->port;
2887 const struct resource *res;
2888 unsigned int i;
2889 int ret;
2890
2891 sci_port->cfg = p;
2892
2893 port->ops = &sci_uart_ops;
2894 port->iotype = UPIO_MEM;
2895 port->line = index;
2896
2897 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2898 if (res == NULL)
2899 return -ENOMEM;
2900
2901 port->mapbase = res->start;
2902 sci_port->reg_size = resource_size(res);
2903
2904 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2905 if (i)
2906 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2907 else
2908 sci_port->irqs[i] = platform_get_irq(dev, i);
2909 }
2910
2911
2912
2913
2914
2915
2916
2917
2918 if (sci_port->irqs[0] < 0)
2919 return -ENXIO;
2920
2921 if (sci_port->irqs[1] < 0)
2922 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2923 sci_port->irqs[i] = sci_port->irqs[0];
2924
2925 sci_port->params = sci_probe_regmap(p);
2926 if (unlikely(sci_port->params == NULL))
2927 return -EINVAL;
2928
2929 switch (p->type) {
2930 case PORT_SCIFB:
2931 sci_port->rx_trigger = 48;
2932 break;
2933 case PORT_HSCIF:
2934 sci_port->rx_trigger = 64;
2935 break;
2936 case PORT_SCIFA:
2937 sci_port->rx_trigger = 32;
2938 break;
2939 case PORT_SCIF:
2940 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2941
2942 sci_port->rx_trigger = 1;
2943 else
2944 sci_port->rx_trigger = 8;
2945 break;
2946 default:
2947 sci_port->rx_trigger = 1;
2948 break;
2949 }
2950
2951 sci_port->rx_fifo_timeout = 0;
2952 sci_port->hscif_tot = 0;
2953
2954
2955
2956
2957
2958 sci_port->sampling_rate_mask = p->sampling_rate
2959 ? SCI_SR(p->sampling_rate)
2960 : sci_port->params->sampling_rate_mask;
2961
2962 if (!early) {
2963 ret = sci_init_clocks(sci_port, &dev->dev);
2964 if (ret < 0)
2965 return ret;
2966
2967 port->dev = &dev->dev;
2968
2969 pm_runtime_enable(&dev->dev);
2970 }
2971
2972 port->type = p->type;
2973 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2974 port->fifosize = sci_port->params->fifosize;
2975
2976 if (port->type == PORT_SCI) {
2977 if (sci_port->reg_size >= 0x20)
2978 port->regshift = 2;
2979 else
2980 port->regshift = 1;
2981 }
2982
2983
2984
2985
2986
2987
2988
2989
2990 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2991 port->irqflags = 0;
2992
2993 port->serial_in = sci_serial_in;
2994 port->serial_out = sci_serial_out;
2995
2996 return 0;
2997 }
2998
2999 static void sci_cleanup_single(struct sci_port *port)
3000 {
3001 pm_runtime_disable(port->port.dev);
3002 }
3003
3004 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3005 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3006 static void serial_console_putchar(struct uart_port *port, int ch)
3007 {
3008 sci_poll_put_char(port, ch);
3009 }
3010
3011
3012
3013
3014
3015 static void serial_console_write(struct console *co, const char *s,
3016 unsigned count)
3017 {
3018 struct sci_port *sci_port = &sci_ports[co->index];
3019 struct uart_port *port = &sci_port->port;
3020 unsigned short bits, ctrl, ctrl_temp;
3021 unsigned long flags;
3022 int locked = 1;
3023
3024 #if defined(SUPPORT_SYSRQ)
3025 if (port->sysrq)
3026 locked = 0;
3027 else
3028 #endif
3029 if (oops_in_progress)
3030 locked = spin_trylock_irqsave(&port->lock, flags);
3031 else
3032 spin_lock_irqsave(&port->lock, flags);
3033
3034
3035 ctrl = serial_port_in(port, SCSCR);
3036 ctrl_temp = SCSCR_RE | SCSCR_TE |
3037 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3038 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3039 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3040
3041 uart_console_write(port, s, count, serial_console_putchar);
3042
3043
3044 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3045 while ((serial_port_in(port, SCxSR) & bits) != bits)
3046 cpu_relax();
3047
3048
3049 serial_port_out(port, SCSCR, ctrl);
3050
3051 if (locked)
3052 spin_unlock_irqrestore(&port->lock, flags);
3053 }
3054
3055 static int serial_console_setup(struct console *co, char *options)
3056 {
3057 struct sci_port *sci_port;
3058 struct uart_port *port;
3059 int baud = 115200;
3060 int bits = 8;
3061 int parity = 'n';
3062 int flow = 'n';
3063 int ret;
3064
3065
3066
3067
3068 if (co->index < 0 || co->index >= SCI_NPORTS)
3069 return -ENODEV;
3070
3071 sci_port = &sci_ports[co->index];
3072 port = &sci_port->port;
3073
3074
3075
3076
3077 if (!port->ops)
3078 return -ENODEV;
3079
3080 ret = sci_remap_port(port);
3081 if (unlikely(ret != 0))
3082 return ret;
3083
3084 if (options)
3085 uart_parse_options(options, &baud, &parity, &bits, &flow);
3086
3087 return uart_set_options(port, co, baud, parity, bits, flow);
3088 }
3089
3090 static struct console serial_console = {
3091 .name = "ttySC",
3092 .device = uart_console_device,
3093 .write = serial_console_write,
3094 .setup = serial_console_setup,
3095 .flags = CON_PRINTBUFFER,
3096 .index = -1,
3097 .data = &sci_uart_driver,
3098 };
3099
3100 static struct console early_serial_console = {
3101 .name = "early_ttySC",
3102 .write = serial_console_write,
3103 .flags = CON_PRINTBUFFER,
3104 .index = -1,
3105 };
3106
3107 static char early_serial_buf[32];
3108
3109 static int sci_probe_earlyprintk(struct platform_device *pdev)
3110 {
3111 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3112
3113 if (early_serial_console.data)
3114 return -EEXIST;
3115
3116 early_serial_console.index = pdev->id;
3117
3118 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3119
3120 serial_console_setup(&early_serial_console, early_serial_buf);
3121
3122 if (!strstr(early_serial_buf, "keep"))
3123 early_serial_console.flags |= CON_BOOT;
3124
3125 register_console(&early_serial_console);
3126 return 0;
3127 }
3128
3129 #define SCI_CONSOLE (&serial_console)
3130
3131 #else
3132 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3133 {
3134 return -EINVAL;
3135 }
3136
3137 #define SCI_CONSOLE NULL
3138
3139 #endif
3140
3141 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3142
3143 static DEFINE_MUTEX(sci_uart_registration_lock);
3144 static struct uart_driver sci_uart_driver = {
3145 .owner = THIS_MODULE,
3146 .driver_name = "sci",
3147 .dev_name = "ttySC",
3148 .major = SCI_MAJOR,
3149 .minor = SCI_MINOR_START,
3150 .nr = SCI_NPORTS,
3151 .cons = SCI_CONSOLE,
3152 };
3153
3154 static int sci_remove(struct platform_device *dev)
3155 {
3156 struct sci_port *port = platform_get_drvdata(dev);
3157 unsigned int type = port->port.type;
3158
3159 sci_ports_in_use &= ~BIT(port->port.line);
3160 uart_remove_one_port(&sci_uart_driver, &port->port);
3161
3162 sci_cleanup_single(port);
3163
3164 if (port->port.fifosize > 1)
3165 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3166 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3167 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3168
3169 return 0;
3170 }
3171
3172
3173 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3174 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3175 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3176
3177 static const struct of_device_id of_sci_match[] = {
3178
3179 {
3180 .compatible = "renesas,scif-r7s72100",
3181 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3182 },
3183 {
3184 .compatible = "renesas,scif-r7s9210",
3185 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3186 },
3187
3188 {
3189 .compatible = "renesas,rcar-gen1-scif",
3190 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3191 }, {
3192 .compatible = "renesas,rcar-gen2-scif",
3193 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3194 }, {
3195 .compatible = "renesas,rcar-gen3-scif",
3196 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3197 },
3198
3199 {
3200 .compatible = "renesas,scif",
3201 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3202 }, {
3203 .compatible = "renesas,scifa",
3204 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3205 }, {
3206 .compatible = "renesas,scifb",
3207 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3208 }, {
3209 .compatible = "renesas,hscif",
3210 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3211 }, {
3212 .compatible = "renesas,sci",
3213 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3214 }, {
3215
3216 },
3217 };
3218 MODULE_DEVICE_TABLE(of, of_sci_match);
3219
3220 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3221 unsigned int *dev_id)
3222 {
3223 struct device_node *np = pdev->dev.of_node;
3224 struct plat_sci_port *p;
3225 struct sci_port *sp;
3226 const void *data;
3227 int id;
3228
3229 if (!IS_ENABLED(CONFIG_OF) || !np)
3230 return NULL;
3231
3232 data = of_device_get_match_data(&pdev->dev);
3233
3234 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3235 if (!p)
3236 return NULL;
3237
3238
3239 id = of_alias_get_id(np, "serial");
3240 if (id < 0 && ~sci_ports_in_use)
3241 id = ffz(sci_ports_in_use);
3242 if (id < 0) {
3243 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3244 return NULL;
3245 }
3246 if (id >= ARRAY_SIZE(sci_ports)) {
3247 dev_err(&pdev->dev, "serial%d out of range\n", id);
3248 return NULL;
3249 }
3250
3251 sp = &sci_ports[id];
3252 *dev_id = id;
3253
3254 p->type = SCI_OF_TYPE(data);
3255 p->regtype = SCI_OF_REGTYPE(data);
3256
3257 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3258
3259 return p;
3260 }
3261
3262 static int sci_probe_single(struct platform_device *dev,
3263 unsigned int index,
3264 struct plat_sci_port *p,
3265 struct sci_port *sciport)
3266 {
3267 int ret;
3268
3269
3270 if (unlikely(index >= SCI_NPORTS)) {
3271 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3272 index+1, SCI_NPORTS);
3273 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3274 return -EINVAL;
3275 }
3276 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3277 if (sci_ports_in_use & BIT(index))
3278 return -EBUSY;
3279
3280 mutex_lock(&sci_uart_registration_lock);
3281 if (!sci_uart_driver.state) {
3282 ret = uart_register_driver(&sci_uart_driver);
3283 if (ret) {
3284 mutex_unlock(&sci_uart_registration_lock);
3285 return ret;
3286 }
3287 }
3288 mutex_unlock(&sci_uart_registration_lock);
3289
3290 ret = sci_init_single(dev, sciport, index, p, false);
3291 if (ret)
3292 return ret;
3293
3294 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3295 if (IS_ERR(sciport->gpios))
3296 return PTR_ERR(sciport->gpios);
3297
3298 if (sciport->has_rtscts) {
3299 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3300 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3301 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3302 return -EINVAL;
3303 }
3304 sciport->port.flags |= UPF_HARD_FLOW;
3305 }
3306
3307 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3308 if (ret) {
3309 sci_cleanup_single(sciport);
3310 return ret;
3311 }
3312
3313 return 0;
3314 }
3315
3316 static int sci_probe(struct platform_device *dev)
3317 {
3318 struct plat_sci_port *p;
3319 struct sci_port *sp;
3320 unsigned int dev_id;
3321 int ret;
3322
3323
3324
3325
3326
3327
3328 if (is_early_platform_device(dev))
3329 return sci_probe_earlyprintk(dev);
3330
3331 if (dev->dev.of_node) {
3332 p = sci_parse_dt(dev, &dev_id);
3333 if (p == NULL)
3334 return -EINVAL;
3335 } else {
3336 p = dev->dev.platform_data;
3337 if (p == NULL) {
3338 dev_err(&dev->dev, "no platform data supplied\n");
3339 return -EINVAL;
3340 }
3341
3342 dev_id = dev->id;
3343 }
3344
3345 sp = &sci_ports[dev_id];
3346 platform_set_drvdata(dev, sp);
3347
3348 ret = sci_probe_single(dev, dev_id, p, sp);
3349 if (ret)
3350 return ret;
3351
3352 if (sp->port.fifosize > 1) {
3353 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3354 if (ret)
3355 return ret;
3356 }
3357 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3358 sp->port.type == PORT_HSCIF) {
3359 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3360 if (ret) {
3361 if (sp->port.fifosize > 1) {
3362 device_remove_file(&dev->dev,
3363 &dev_attr_rx_fifo_trigger);
3364 }
3365 return ret;
3366 }
3367 }
3368
3369 #ifdef CONFIG_SH_STANDARD_BIOS
3370 sh_bios_gdb_detach();
3371 #endif
3372
3373 sci_ports_in_use |= BIT(dev_id);
3374 return 0;
3375 }
3376
3377 static __maybe_unused int sci_suspend(struct device *dev)
3378 {
3379 struct sci_port *sport = dev_get_drvdata(dev);
3380
3381 if (sport)
3382 uart_suspend_port(&sci_uart_driver, &sport->port);
3383
3384 return 0;
3385 }
3386
3387 static __maybe_unused int sci_resume(struct device *dev)
3388 {
3389 struct sci_port *sport = dev_get_drvdata(dev);
3390
3391 if (sport)
3392 uart_resume_port(&sci_uart_driver, &sport->port);
3393
3394 return 0;
3395 }
3396
3397 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3398
3399 static struct platform_driver sci_driver = {
3400 .probe = sci_probe,
3401 .remove = sci_remove,
3402 .driver = {
3403 .name = "sh-sci",
3404 .pm = &sci_dev_pm_ops,
3405 .of_match_table = of_match_ptr(of_sci_match),
3406 },
3407 };
3408
3409 static int __init sci_init(void)
3410 {
3411 pr_info("%s\n", banner);
3412
3413 return platform_driver_register(&sci_driver);
3414 }
3415
3416 static void __exit sci_exit(void)
3417 {
3418 platform_driver_unregister(&sci_driver);
3419
3420 if (sci_uart_driver.state)
3421 uart_unregister_driver(&sci_uart_driver);
3422 }
3423
3424 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3425 early_platform_init_buffer("earlyprintk", &sci_driver,
3426 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3427 #endif
3428 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3429 static struct plat_sci_port port_cfg __initdata;
3430
3431 static int __init early_console_setup(struct earlycon_device *device,
3432 int type)
3433 {
3434 if (!device->port.membase)
3435 return -ENODEV;
3436
3437 device->port.serial_in = sci_serial_in;
3438 device->port.serial_out = sci_serial_out;
3439 device->port.type = type;
3440 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3441 port_cfg.type = type;
3442 sci_ports[0].cfg = &port_cfg;
3443 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3444 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3445 sci_serial_out(&sci_ports[0].port, SCSCR,
3446 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3447
3448 device->con->write = serial_console_write;
3449 return 0;
3450 }
3451 static int __init sci_early_console_setup(struct earlycon_device *device,
3452 const char *opt)
3453 {
3454 return early_console_setup(device, PORT_SCI);
3455 }
3456 static int __init scif_early_console_setup(struct earlycon_device *device,
3457 const char *opt)
3458 {
3459 return early_console_setup(device, PORT_SCIF);
3460 }
3461 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3462 const char *opt)
3463 {
3464 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3465 return early_console_setup(device, PORT_SCIF);
3466 }
3467 static int __init scifa_early_console_setup(struct earlycon_device *device,
3468 const char *opt)
3469 {
3470 return early_console_setup(device, PORT_SCIFA);
3471 }
3472 static int __init scifb_early_console_setup(struct earlycon_device *device,
3473 const char *opt)
3474 {
3475 return early_console_setup(device, PORT_SCIFB);
3476 }
3477 static int __init hscif_early_console_setup(struct earlycon_device *device,
3478 const char *opt)
3479 {
3480 return early_console_setup(device, PORT_HSCIF);
3481 }
3482
3483 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3484 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3485 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3486 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3487 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3488 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3489 #endif
3490
3491 module_init(sci_init);
3492 module_exit(sci_exit);
3493
3494 MODULE_LICENSE("GPL");
3495 MODULE_ALIAS("platform:sh-sci");
3496 MODULE_AUTHOR("Paul Mundt");
3497 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");