1
2 #ifndef _SUNZILOG_H
3 #define _SUNZILOG_H
4
5 struct zilog_channel {
6 volatile unsigned char control;
7 volatile unsigned char __pad1;
8 volatile unsigned char data;
9 volatile unsigned char __pad2;
10 };
11
12 struct zilog_layout {
13 struct zilog_channel channelB;
14 struct zilog_channel channelA;
15 };
16
17 #define NUM_ZSREGS 17
18 #define R7p 16
19
20
21
22
23 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
25
26
27
28 #define FLAG 0x7e
29
30
31 #define R0 0
32 #define R1 1
33 #define R2 2
34 #define R3 3
35 #define R4 4
36 #define R5 5
37 #define R6 6
38 #define R7 7
39 #define R8 8
40 #define R9 9
41 #define R10 10
42 #define R11 11
43 #define R12 12
44 #define R13 13
45 #define R14 14
46 #define R15 15
47
48 #define NULLCODE 0
49 #define POINT_HIGH 0x8
50 #define RES_EXT_INT 0x10
51 #define SEND_ABORT 0x18
52 #define RES_RxINT_FC 0x20
53 #define RES_Tx_P 0x28
54 #define ERR_RES 0x30
55 #define RES_H_IUS 0x38
56
57 #define RES_Rx_CRC 0x40
58 #define RES_Tx_CRC 0x80
59 #define RES_EOM_L 0xC0
60
61
62
63 #define EXT_INT_ENAB 0x1
64 #define TxINT_ENAB 0x2
65 #define PAR_SPEC 0x4
66
67 #define RxINT_DISAB 0
68 #define RxINT_FCERR 0x8
69 #define INT_ALL_Rx 0x10
70 #define INT_ERR_Rx 0x18
71 #define RxINT_MASK 0x18
72
73 #define WT_RDY_RT 0x20
74 #define WT_FN_RDYFN 0x40
75 #define WT_RDY_ENAB 0x80
76
77
78
79
80
81 #define RxENAB 0x1
82 #define SYNC_L_INH 0x2
83 #define ADD_SM 0x4
84 #define RxCRC_ENAB 0x8
85 #define ENT_HM 0x10
86 #define AUTO_ENAB 0x20
87 #define Rx5 0x0
88 #define Rx7 0x40
89 #define Rx6 0x80
90 #define Rx8 0xc0
91 #define RxN_MASK 0xc0
92
93
94
95 #define PAR_ENAB 0x1
96 #define PAR_EVEN 0x2
97
98 #define SYNC_ENAB 0
99 #define SB1 0x4
100 #define SB15 0x8
101 #define SB2 0xc
102
103 #define MONSYNC 0
104 #define BISYNC 0x10
105 #define SDLC 0x20
106 #define EXTSYNC 0x30
107
108 #define X1CLK 0x0
109 #define X16CLK 0x40
110 #define X32CLK 0x80
111 #define X64CLK 0xC0
112 #define XCLK_MASK 0xC0
113
114
115
116 #define TxCRC_ENAB 0x1
117 #define RTS 0x2
118 #define SDLC_CRC 0x4
119 #define TxENAB 0x8
120 #define SND_BRK 0x10
121 #define Tx5 0x0
122 #define Tx7 0x20
123 #define Tx6 0x40
124 #define Tx8 0x60
125 #define TxN_MASK 0x60
126 #define DTR 0x80
127
128
129
130
131
132
133 #define AUTO_TxFLAG 1
134 #define AUTO_EOM_RST 2
135 #define AUTOnRTS 4
136 #define RxFIFO_LVL 8
137 #define nDTRnREQ 0x10
138 #define TxFIFO_LVL 0x20
139 #define EXT_RD_EN 0x40
140
141
142
143
144 #define VIS 1
145 #define NV 2
146 #define DLC 4
147 #define MIE 8
148 #define STATHI 0x10
149 #define SWIACK 0x20
150 #define NORESET 0
151 #define CHRB 0x40
152 #define CHRA 0x80
153 #define FHWRES 0xc0
154
155
156 #define BIT6 1
157 #define LOOPMODE 2
158 #define ABUNDER 4
159 #define MARKIDLE 8
160 #define GAOP 0x10
161 #define NRZ 0
162 #define NRZI 0x20
163 #define FM1 0x40
164 #define FM0 0x60
165 #define CRCPS 0x80
166
167
168 #define TRxCXT 0
169 #define TRxCTC 1
170 #define TRxCBR 2
171 #define TRxCDP 3
172 #define TRxCOI 4
173 #define TCRTxCP 0
174 #define TCTRxCP 8
175 #define TCBR 0x10
176 #define TCDPLL 0x18
177 #define RCRTxCP 0
178 #define RCTRxCP 0x20
179 #define RCBR 0x40
180 #define RCDPLL 0x60
181 #define RTxCX 0x80
182
183
184
185
186
187
188 #define BRENAB 1
189 #define BRSRC 2
190 #define DTRREQ 4
191 #define AUTOECHO 8
192 #define LOOPBAK 0x10
193 #define SEARCH 0x20
194 #define RMC 0x40
195 #define DISDPLL 0x60
196 #define SSBR 0x80
197 #define SSRTxC 0xa0
198 #define SFMM 0xc0
199 #define SNRZI 0xe0
200
201
202 #define WR7pEN 1
203 #define ZCIE 2
204 #define FIFOEN 4
205 #define DCDIE 8
206 #define SYNCIE 0x10
207 #define CTSIE 0x20
208 #define TxUIE 0x40
209 #define BRKIE 0x80
210
211
212
213 #define Rx_CH_AV 0x1
214 #define ZCOUNT 0x2
215 #define Tx_BUF_EMP 0x4
216 #define DCD 0x8
217 #define SYNC 0x10
218 #define CTS 0x20
219 #define TxEOM 0x40
220 #define BRK_ABRT 0x80
221
222
223 #define ALL_SNT 0x1
224
225 #define RES3 0x8
226 #define RES4 0x4
227 #define RES5 0xc
228 #define RES6 0x2
229 #define RES7 0xa
230 #define RES8 0x6
231 #define RES18 0xe
232 #define RES28 0x0
233
234 #define PAR_ERR 0x10
235 #define Rx_OVR 0x20
236 #define CRC_ERR 0x40
237 #define END_FR 0x80
238
239
240 #define CHB_Tx_EMPTY 0x00
241 #define CHB_EXT_STAT 0x02
242 #define CHB_Rx_AVAIL 0x04
243 #define CHB_SPECIAL 0x06
244 #define CHA_Tx_EMPTY 0x08
245 #define CHA_EXT_STAT 0x0a
246 #define CHA_Rx_AVAIL 0x0c
247 #define CHA_SPECIAL 0x0e
248 #define STATUS_MASK 0x0e
249
250
251 #define CHBEXT 0x1
252 #define CHBTxIP 0x2
253 #define CHBRxIP 0x4
254 #define CHAEXT 0x8
255 #define CHATxIP 0x10
256 #define CHARxIP 0x20
257
258
259
260
261
262
263
264
265 #define ONLOOP 2
266 #define LOOPSEND 0x10
267 #define CLK2MIS 0x40
268 #define CLK1MIS 0x80
269
270
271
272
273
274
275
276
277 #define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \
278 udelay(5); } while(0)
279
280 #define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \
281 udelay(5); } while(0)
282
283 #define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \
284 udelay(2); \
285 sbus_readb(&channel->data); \
286 udelay(2); \
287 sbus_readb(&channel->data); \
288 udelay(2); } while(0)
289
290 #endif